WO2021237497A1 - 磁性随机存储器、数据读写方法及电子设备 - Google Patents

磁性随机存储器、数据读写方法及电子设备 Download PDF

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WO2021237497A1
WO2021237497A1 PCT/CN2020/092515 CN2020092515W WO2021237497A1 WO 2021237497 A1 WO2021237497 A1 WO 2021237497A1 CN 2020092515 W CN2020092515 W CN 2020092515W WO 2021237497 A1 WO2021237497 A1 WO 2021237497A1
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memory
line
memory cell
random access
voltage control
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PCT/CN2020/092515
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English (en)
French (fr)
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李文静
叶力
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华为技术有限公司
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Priority to CN202080092161.1A priority Critical patent/CN114930455A/zh
Priority to PCT/CN2020/092515 priority patent/WO2021237497A1/zh
Priority to EP20938336.3A priority patent/EP4145449A4/en
Publication of WO2021237497A1 publication Critical patent/WO2021237497A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods

Definitions

  • the embodiments of the present application relate to the field of storage technology, and in particular, to a magnetic random access memory and an electronic device.
  • MRAM magnetic random access memory
  • the core memory cell of MRAM is MTJ, and its core structure includes a free layer, a tunneling layer and a pinned layer.
  • the direction of the magnetic moment of the pinned layer is fixed, and the direction of the free layer can be changed; write data in the MTJ
  • you can write different data by changing the direction of the magnetic moment of the free layer (that is, controlling the parallel or anti-parallel arrangement of the magnetic moments of the MTJ free layer and the pinned layer); when reading data from the MTJ, you can determine the MTJ High and low resistance state to achieve.
  • the storage array of MRAM is usually two-dimensional (2D).
  • 2D two-dimensional
  • the size and spacing of MTJ are generally reduced to increase the number of memory cells per unit area.
  • this method can increase the storage density of MRAM to a certain extent, when the size of MTJ is reduced to To a certain extent, the thermal stability of the MTJ will decrease, resulting in a decrease in the reliability of stored data.
  • the embodiments of the present application provide a magnetic random access memory, a data reading and writing method of the magnetic random access memory, and electronic equipment to improve the storage density of the magnetic random access memory.
  • the first aspect of the embodiments of the present application provides a magnetic random access memory.
  • the magnetic random access memory includes a plurality of structural units and a plurality of voltage control lines.
  • the planes on which each structural unit is located are parallel to each other.
  • a plane is vertical; each structural unit includes a plurality of parallel storage strings, where each storage string is composed of a multilayer storage structure stacked in sequence, and each storage structure includes one vertical to the voltage control line
  • the memory cell is a magnetic tunnel junction. One end of the magnetic tunnel junction is connected to one of the multiple voltage control lines.
  • the memory cell The other end of the SOT is connected to the SOT electrode line of the layer, and all the SOT electrode lines in each storage string are connected in series by metal wires.
  • each magnetic tunnel junction includes a free layer, a barrier layer and a reference layer stacked in sequence, the free layer is connected to the SOT electrode line, and the reference layer is connected to the voltage control line.
  • the storage array is three-dimensional (3 dimensions, 3D), compared with the 2D array in the prior art, this solution can pass through the vertical direction under the premise of ensuring the thermal stability of the storage unit.
  • the stacking of storage units increases the surface storage density, thereby increasing the storage density of the magnetic random access memory.
  • the SOT electrode line corresponding to a memory cell in each layer of the multi-layer memory structure in the vertical direction is connected in series to form a memory string through a metal wire, thus writing to the magnetic random access memory
  • a bit line can be used to simultaneously apply corresponding read and write currents to multiple SOT electrode lines corresponding to the positions in the multi-layer storage structure, thereby reducing the bit line wiring in the peripheral circuit plane Space, with fewer bit lines to achieve addressing and access to the multi-layer storage structure in the magnetic random access memory.
  • each memory string in the magnetic random access memory further includes a transistor, and the drain/source of the transistor is connected to the first end of the memory string; the magnetic random access memory relies on multiple first bit lines And multiple word lines to connect multiple memory strings; wherein, the multiple first bit lines and the multiple word lines are parallel to each other and perpendicular to the multiple voltage control lines, and are the second ends of all memory strings belonging to the same structural unit The same first bit line is connected, and the gates of transistors in all memory strings belonging to the same structural unit are connected to the same word line.
  • the magnetic random access memory further includes a plurality of second bit lines; the second bit lines and the voltage control lines are parallel to each other; in a memory string, one end of the memory string is connected to the first bit line, which is connected with The other end of the transistor is connected to the second bit line.
  • the transistors of the memory string belonging to the same structural unit can be turned on by applying a gate bias voltage on a word line, and then by applying different voltages on the corresponding first bit line and the second bit line, All SOT electrode wires corresponding to a memory string have read and write currents passing through them.
  • the magnetic random access memory further includes a plurality of third bit lines; the third bit line is used to connect a plurality of voltage control lines, wherein each third bit line is used to connect and control through a metal wire All voltage control lines corresponding to one layer of the multi-layer storage structure.
  • a third bit line is used to connect the voltage control line corresponding to a layer of storage structure, so when data is written to or read from the magnetic random access memory, a third bit can be used
  • the line realizes that the corresponding voltage is applied to multiple voltage control lines corresponding to a layer of storage structure at the same time, thereby reducing the wiring space of the bit line in the peripheral circuit plane; and then by applying different voltages to different third bit lines to select a memory string A corresponding voltage is applied to one of the memory cells.
  • the SOT electrode lines are stacked in sequence; the series connection is as follows: the first end of the SOT electrode line of the Nth layer of storage structure is connected to the first end of the SOT electrode line of the N+1th layer of storage structure through a metal wire. At one end, the second end of the SOT electrode line of the N+1th layer storage structure is connected to the second end of the SOT electrode line of the N+2th layer storage structure.
  • the SOT electrode lines are stacked in sequence; the series connection method is that the first end of the SOT electrode line of the Nth layer of storage structure is connected to the second end of the SOT electrode line of the N+1th layer of storage structure through a metal wire.
  • writing data and reading data can be implemented in the following manner: when writing data to the magnetic random access memory, first pass the corresponding structural unit of the storage unit to be written The word line applies a gate bias voltage to the transistor in the memory string to which the memory cell to be written belongs; then applies a write voltage to the first bit line corresponding to the memory string, and the second bit line corresponding to the memory string is grounded , In this way, it is equivalent to selecting the memory string where the memory cell is located, so that the SOT electrode lines corresponding to the multiple memory cells on the memory string have write current; because in a memory string, each memory cell is in a different layer, Different layers correspond to different voltage control lines.
  • applying a bias voltage on the third bit line corresponding to the voltage control line connected to the memory cell to be written can be based on spin-orbit torque (SOT)
  • SOT spin-orbit torque
  • VCMA voltage-controlled magnetic anisotropy
  • a second aspect of the embodiments of the present application provides a method for writing data to a random access memory, including:
  • the magnetic random access memory includes multiple structural units, multiple voltage control lines, multiple first bit lines, multiple second bit lines, and multiple word lines.
  • the voltage control line is parallel to the second bit line, and the first bit line Parallel to the word line, the voltage control line is perpendicular to the first bit line;
  • the planes where the multiple structural units are located are parallel and each structural unit includes multiple parallel strings;
  • each string includes multiple layers of memory stacked in sequence Structure and a transistor, each layer of storage structure includes a spin-orbit torque SOT electrode line and a memory cell arranged on the SOT electrode line;
  • the memory cell may be a magnetic tunnel junction, one end is connected to the voltage control line, The other end is connected to the SOT electrode line, and the SOT electrode line and the voltage control line are perpendicular to each other and all SOT electrode lines in each memory string are connected in series by metal wires; at the same time, each structural unit shares a first bit line and one Word line, the first end of all memory strings in each structural unit is connected to the same first bit line
  • the two bit lines are grounded; in this way, the memory string to which the memory cell to be written belongs is selected, so that the SOT electrode line in the memory string has a write current, and then the voltage control line connected to the memory cell to be written is applied to the memory cell Bias voltage, so that the memory cell to be written is selected, and then data is written to the memory cell to be written according to the write voltage and the bias voltage.
  • a third aspect of the embodiments of the present application provides a method for writing data to a random access memory, including:
  • the magnetic random access memory includes multiple structural units, multiple voltage control lines, multiple first bit lines, multiple second bit lines, and multiple word lines.
  • the voltage control line is parallel to the second bit line, and the first bit line Parallel to the word line, the voltage control line is perpendicular to the first bit line;
  • the planes where the multiple structural units are located are parallel and each structural unit includes multiple parallel strings;
  • each string includes multiple layers of memory stacked in sequence Structure and a transistor, each layer of storage structure includes a spin-orbit torque SOT electrode line and a memory cell arranged on the SOT electrode line;
  • the memory cell may be a magnetic tunnel junction, one end is connected to the voltage control line, The other end is connected to the SOT electrode line, and the SOT electrode line and the voltage control line are perpendicular to each other and all SOT electrode lines in each memory string are connected in series by metal wires; at the same time, each structural unit shares a first bit line and one Word line, the first end of all memory strings in each structural unit is connected to the same first bit line
  • a fourth aspect of the embodiments of the present application provides a method for reading data from a random access memory, including:
  • the magnetic random access memory includes multiple structural units, multiple voltage control lines, multiple first bit lines, multiple second bit lines, and multiple word lines.
  • the voltage control line is parallel to the second bit line, and the first bit line Parallel to the word line, the voltage control line is perpendicular to the first bit line;
  • the planes where the multiple structural units are located are parallel and each structural unit includes multiple parallel strings;
  • each string includes multiple layers of memory stacked in sequence Structure and a transistor, each layer of storage structure includes a spin-orbit torque SOT electrode line and a memory cell arranged on the SOT electrode line;
  • the memory cell may be a magnetic tunnel junction, one end is connected to the voltage control line, The other end is connected to the SOT electrode line, and the SOT electrode line and the voltage control line are perpendicular to each other and all SOT electrode lines in each memory string are connected in series by metal wires; at the same time, each structural unit shares a first bit line and one Word line, the first end of all memory strings in each structural unit is connected to the same first bit line
  • the fifth aspect of the embodiments of the present application provides an electronic device, which includes a processor and the magnetic random access memory provided in the first aspect and any possible design thereof coupled with the processor.
  • the processor may call a software program stored in the magnetic random access memory to execute a corresponding method to realize the corresponding function of the electronic device.
  • FIG. 1 is a structural block diagram of a magnetic random access memory provided in an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a magnetic random access memory provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a connection of a storage string provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the connection of another storage string provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of another magnetic random access memory provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of an MTJ provided by an embodiment of the application.
  • FIG. 7 is a structural block diagram of an electronic device provided by an embodiment of the application.
  • the embodiments of the present application provide a magnetic random access memory and an electronic device, which are used to increase the storage density of the magnetic random access memory and improve the stability of the storage unit.
  • the embodiments of the present application can be applied to the magnetic random access memory shown in FIG. 1.
  • the magnetic random access memory includes a control circuit and at least one storage circuit.
  • each storage circuit is used for writing and reading data.
  • the control circuit is used to control the process of writing and reading data from the storage circuit, for example, when writing data, select the storage unit to write data, apply the corresponding voltage and pass the corresponding current to realize the selected storage unit Write data in the middle, for example, select the memory cell to be read when reading the data, and read the data from the selected memory cell by applying the corresponding voltage and passing the corresponding current.
  • each storage circuit includes multiple storage units.
  • the storage unit is the smallest unit with data storage and reading and writing functions in the magnetic random access memory. It can be used to store a minimum unit of information, that is, 1-bit data (for example, 0 or 1) , which is a binary bit.
  • the random access memory includes a plurality of storage units 201, which are sequentially stacked in a three-dimensional space; includes a plurality of structural units 202 and a plurality of voltage control lines 203
  • the multiple structural units 202 and the multiple voltage control lines 203 can be regarded as the storage circuit in FIG. 1.
  • each structural unit 202 includes a plurality of storage strings 204, and the plurality of storage strings 204 are parallel to each other; each storage string 204 is composed of a multilayer storage structure stacked in sequence, and each storage structure includes one and a voltage control
  • the memory cell 201 is a magnetic tunnel junction. One end of the magnetic tunnel junction is connected to the SOT electrode line of the layer. All SOT electrode wires in the string are connected in series by metal wires.
  • the voltage control line 203 and the memory cell 201 have a one-to-one correspondence, that is, each memory cell 201 has a corresponding voltage control line 203 for applying voltage to the memory cell 201 .
  • the multiple voltage control lines 203 are parallel to each other; the planes on which the multiple structural units 202 are located are parallel to each other, and the plane on which each structural unit 202 is located is perpendicular to the multiple voltage control lines 203.
  • the xyz coordinate system is shown in the magnetic random access memory shown in FIG. 2.
  • the voltage control lines 203 are arranged in parallel along the x-axis; the plane where each structural unit 202 is located is perpendicular to the x-axis; in each memory string 204, the multi-layer memory structure is sequentially arranged along the z-axis. Stacked, and the electrical level lines corresponding to each layer of the storage structure are arranged along the y-axis, and may be perpendicular to the voltage control line 203.
  • the storage unit 201 is the smallest unit with data storage and reading and writing functions in the magnetic random access memory, and can be used to store a minimum unit of information, that is, 1-bit data (for example, 0 or 1), that is, a binary bit. Through multiple storage units 201, multiple binary bit data can be stored.
  • one storage unit 201 includes one MTJ for storing one binary bit.
  • Each MTJ may include a free layer, a tunneling layer, and a pinned layer that are sequentially stacked along the positive z-axis direction. Among them, the direction of the magnetic moment of the pinned layer is fixed, and the direction of the magnetic moment of the free layer can be changed when data is written.
  • the tunneling layer Used to produce tunnel magnetoresistance effect.
  • the free layer is connected to the electrode line, and the pinning layer is connected to the voltage control line. That is, the free layer is close to the electrode line connected to the MTJ, the pinning layer is the farthest from the electrode line, and the tunneling layer is located between the free layer and the reference layer.
  • the magnetic moment directions of the free layer and the pinned layer can be in the xy plane, and can be perpendicular On the xy plane, or at a certain angle of inclination to the xy plane.
  • the magnetic moment directions of the free layer and the pinned layer are not specifically limited, as long as the magnetic moment directions of the free layer and the pinned layer are arranged in parallel or anti-parallel.
  • each memory string 204 all SOT electrode lines are connected in series by metal wires.
  • connection modes which are not specifically limited; for example, the following two series connection modes may be included:
  • FIG. 3 is a schematic diagram of the connection of a serial storage string 204 provided by an embodiment of this application.
  • a memory string 204 a plurality of memory cells 201 are sequentially stacked along the z-axis direction.
  • Each memory cell 201 includes a magnetic tunnel junction, which is arranged on a SOT electrode line. When metal wires are used, they will be stacked in sequence.
  • the first end of the SOT electrode line of the N-th layer of storage structure can be connected to the first end of the SOT electrode line of the N+1th layer of storage structure, and then the N+1th layer of storage structure
  • the second end of the SOT electrode line is connected to the second end of the SOT electrode line of the N+2th layer memory structure; exemplary, as shown in FIG. 3, the SOT electrode line can be divided into a left end and a right end, that is, the first layer
  • the left end of the second layer is connected to the left end of the second layer
  • the right end of the second layer is connected to the right end of the third layer
  • the left end of the third layer is connected to the left end of the fourth layer.
  • FIG. 4 is a schematic diagram of the connection of another memory string 204 provided in an embodiment of this application.
  • a memory string 204 a plurality of memory cells 201 are still stacked in sequence along the z-axis direction.
  • the memory cells 201 in the memory string 204 can be arranged in sequence along the positive direction of the Z axis, or they can be staggered with each other.
  • the electrode lines are connected in series, the first end of the SOT electrode line of the Nth layer of storage structure can be connected to the second end of the SOT electrode line of the N+1th layer of storage structure. For example, as shown in FIG.
  • the following describes how to control the storage unit 201 and how to write data to the storage unit 201 or read data stored in the storage unit 201 according to the structural framework shown in FIG. 2.
  • each memory string 204 can also be connected in series with a transistor to control the storage
  • the turn-on and turn-off of the string 204 can be directly connected to the SOT electrode line corresponding to the first-layer storage structure of the storage string 204, or can be connected to the SOT electrode line corresponding to the uppermost storage structure of the storage string 204, SOT The electrode line can be connected to the source of the transistor or the drain of the transistor, which is not specifically limited.
  • the magnetic random access memory also includes a plurality of different bit lines.
  • the connection between the plurality of memory strings 204 and the bit lines is as follows: along the z-axis direction, the uppermost end of the memory string 204 is connected to the first bit line, and the transistor at the lower end of the memory string 204 is connected to the first bit line.
  • Two bit lines that is, by applying different voltages to the first bit line and the second bit line to provide current to all SOT electrode lines in a memory string 204; the gate of the transistor is connected to the word line, and the transistor can be supplied to the transistor through the word line.
  • a gate bias voltage is applied to the gate of, and the transistor of the storage string 204 is controlled to be turned on and off.
  • a plurality of voltage control lines 203 are parallel to the x-axis, and one memory cell 201 of one layer in a row of memory strings 204 arranged in sequence along the x-axis direction is correspondingly connected to one Voltage control line 203; and the third bit line 501 is connected to all voltage control lines 203 of a whole layer of memory structure, that is, when a voltage is applied through a third bit line 501, the voltage control line corresponding to a whole layer of memory cell 201 203 will be applied with voltage.
  • the multiple first bit lines 502 are parallel to the y-axis, and the memory string 204 of each structural unit 202 is connected to the same first bit line 502, and the multiple word lines 503 are also parallel to the y-axis.
  • the gates of the transistors in the memory string 204 are connected to the same word line 503, that is, when a gate bias voltage is applied through a word line 503, all the transistors in a structural unit 202 will be turned on.
  • a plurality of second bit lines 504 are parallel to the voltage control line 203 and perpendicular to the plane where the structural unit 202 is located.
  • the gates/drains of the transistors in a row of memory strings 204 arranged in sequence along the x-axis direction correspond to one second bit. Line 504.
  • the first bit line includes bl u1 , bl u2 and bl u3
  • the second bit line includes bl d1 , bl d2 and bl d3 in sequence
  • the word lines WL 1 , WL 2 and WL 3 and the third bit lines BL 1 , BL 2 and BL 3 ;
  • the magnetic random access memory can arrange multiple storage strings 204 in any direction, and the number is not limited.
  • the magnetic random access memory uses the SOT effect and the VCMA effect when writing data, and uses the tunnel magneto resistance (TMR) effect when reading data.
  • TMR tunnel magneto resistance
  • the principle of the SOT effect is: passing a current in the electrode line will generate a spin-polarized current that diffuses upward (that is, in the positive direction of the z-axis) and enters the free layer of the MTJ.
  • the current reaches a certain value (critical switching current density)
  • critical switching current density critical switching current density
  • the magnetic moment of the free layer is reversed under the action of the spin-orbit interaction torque to realize data writing.
  • Changing the direction of the current in the electrode wire changes the polarization direction of the spin current, and the direction of the magnetic moment reversal of the free layer is also changed accordingly to realize the writing of different data.
  • the principle of the VCMA effect is: applying a bias voltage across the MTJ can change the charge density at the interface between the MTJ free layer and the tunneling layer, thereby changing the vertical anisotropy and coercivity of the free layer, thereby reducing the critical switching current density of the MTJ .
  • a current is passed into the electrode line, and the magnetic moment in the free layer is reversed under the combined action of the SOT effect and the VCMA effect to realize data writing. This method can significantly reduce the power consumption of data writing.
  • the electrode wires can be made of heavy metal materials or other materials that can generate spin current.
  • the electrode wires can also be called SOT electrode wires.
  • the structure of the MTJ in the magnetic random access memory shown in FIG. 2 may be as shown in FIG. 6. It can be seen from FIG. 6 that the free layer of the MTJ is connected to the electrode line, and the pinned layer of the MTJ is connected to the voltage control line 203. Applying a voltage or passing a current to the voltage control line 203 through a voltage source or a current source, and passing a current to the SOT electrode line can make the voltage on the voltage control line 203 and the voltage on the SOT electrode line have a voltage difference. The difference is the bias voltage applied across the MTJ.
  • the voltage control line 203 when writing data to the magnetic random access memory, the voltage control line 203 independently performs selective operations on the MTJ connected to it.
  • the first bias voltage is applied to the control line 203 to reduce the critical switching current density of the memory cell to be written.
  • a second bias voltage is applied to the voltage control line 203 connected to the non-write memory cell to increase (or not change) the critical switching current density of the non-write memory cell.
  • the write current is applied to the electrode line connected to the memory cell to be written (currents in different directions can be applied to write different data), resulting in self-diffusion upward (that is, in the positive direction of the z-axis).
  • the swirling flow enters the free layer of the MTJ, so that data can be written in the memory cell to be written.
  • the principle of the TMR effect is: when the magnetic moments of the free layer and the pinned layer of the MTJ are arranged in parallel, the MTJ is in a low-resistance state; when the magnetic moments of the free layer and the pinned layer are arranged anti-parallel (that is, parallel and opposite in direction), MTJ is a high resistance state.
  • the high and low resistances represent two different data states, such as 0 or 1. Different data can be read according to whether the MTJ is in the high-impedance state or the low-impedance state.
  • the electrode line connected to the memory cell to be read is used to provide a ground loop for the memory cell 201, and when the memory cell to be read is connected A read voltage or read current is applied to the voltage control line 203, and the data information carried by the memory cell to be read is obtained through a read circuit connected to the voltage control line 203 (for example, the amplifier SA on the third bit line).
  • the MTJ corresponding to the voltage control line 203 connected to the amplifier is in a high-impedance state or a low-impedance state, and then it can be determined whether the data stored in the MTJ is 0 or is 1.
  • the MTJ may have high resistance characteristics, such as MTJ.
  • the resistance value of MTJ is not less than 100K ⁇ , so that the resistance value of MTJ is much greater than the resistance value of the electrode line, which can effectively prevent the writing current from flowing through the MTJ and reduce the impact of the sneak path.
  • the magnetic moment directions of the free layer and the pinned layer are arranged in parallel or anti-parallel.
  • the direction of the magnetic moment of the free layer and the pinned layer may be in the xy plane, may be perpendicular to the xy plane, or have a certain inclined angle with the xy plane.
  • the magnetic moment directions of the free layer and the pinned layer are not specifically limited, as long as the magnetic moment directions of the free layer and the pinned layer are arranged in parallel or anti-parallel.
  • the process of passing current on the SOT electrode line can be controlled by the first bit line 502 and the second bit line 504.
  • the bit line 502 is directly connected to the upper end of the memory string 204, and the second bit line 504 is connected to one end of the transistor in the memory string 204. It can be connected to the source of the transistor or the drain of the transistor. Make a limit.
  • the turn-on and turn-off of the transistor is controlled by the word line 503.
  • a gate bias voltage is applied to the transistor on the corresponding word line 503 to turn the transistor on, and the first bit line 502 and the second bit line corresponding to the memory string 204 are turned on. Different voltages are applied to 504, that is, the target memory string can be selected, and a write current can be applied to the SOT electrode line of the target memory string.
  • the magnetic random access memory shown in FIG. 5 when writing data to the memory cell to be written, first determine the structural unit 202 to which the memory cell to be written belongs; then pass the word line 503 corresponding to the structural unit 202 Apply a gate bias voltage, so that all the transistors of the memory string 204 in a structural unit 202 are turned on; optionally, the remaining word lines 503 are not applied with a gate bias voltage, which is equivalent to selecting the Write to the structural unit 202 where the storage unit is located.
  • the write voltage can be applied through the first bit line 502 corresponding to the structural unit 202, and then the second bit line 504 corresponding to the memory string 204 where the memory cell to be written is located is determined, and the The second bit line 504 is grounded; the write voltage is applied to the remaining second bit line 504, so that the memory string 204 where the memory cell to be written is located is the only memory string with one end connected to the write voltage and the other end grounded, that is,
  • the SOT electrode line in the memory string 204 has a write current, which is equivalent to selecting the memory string where the memory cell to be written is located.
  • a plurality of third bit lines 501 can be used to apply a bias voltage to the voltage control line 203 of each layer.
  • the first bias voltage and the second bias voltage are different from each other. equal.
  • the first bias voltage is used to reduce the critical switching current density of the memory cell to be written
  • the second bias voltage is used to increase (or not change) the critical switching current density of the non-write memory cell.
  • the values of the first bias voltage and the second bias voltage are different, and the specific values of the first bias voltage and the second bias voltage may be determined according to the specific structure and material parameters of the memory cell 201. In other words, when the voltage control line 203 applies the first bias voltage, data can be written to the memory cell 201 connected to the voltage control line 203; when the voltage control line 203 applies the second bias voltage, it cannot be The memory cell 201 connected to the line 203 writes data.
  • the difference between the first bias voltage and the voltage of the electrode line is negative, and the difference between the second bias voltage and the voltage of the electrode line is positive or zero; or, the first bias voltage and the electrode
  • the difference between the line voltage is a positive value, and the difference between the second bias voltage and the electrode line voltage is a negative value or zero.
  • the memory cell to be written completes the writing of data through the applied writing current and the first bias voltage.
  • the first bit line 502 corresponding to the structural unit 202 can be grounded, and then the second bit line 504 corresponding to the memory string 204 where the memory cell to be written is located is determined, and the second bit line 504 is passed through the second bit line 504.
  • the bit line 504 applies a write voltage; optionally, the remaining second bit line 504 can be grounded, so that it can also be ensured that the memory string 204 where the memory cell to be written is located is the only end connected to the write voltage, and the other end is grounded That is, the SOT electrode line in the memory string 204 has a reverse write current, which is equivalent to selecting the memory string where the memory cell to be written is located; and then determine the third corresponding to the memory cell 201 to be written
  • the bit line 501 applies a first bias voltage to the third bit line 501 to complete the writing of different data.
  • the SOT electrode lines in the memory string are connected in series in various ways, if the SOT electrode lines in the memory string 204 are connected in series as shown in FIG.
  • the control method is also different; for example, If the first-level memory cell wants to write data "1", you can choose to apply the write voltage through the first bit line and connect the second bit line to the ground. If the second-level memory cell wants to write data "1", you can Select to apply the write voltage through the second bit line, and ground the first bit line.
  • the above-mentioned process of applying voltage or passing current on the first bit line 502, the second bit line 504, the word line 503 and the voltage control line 203 can be performed by the magnetic random access memory.
  • the level control circuit configured in the control is performed, and the level control circuit is used to provide the required voltage or current for the first bit line 502, the second bit line 504, the word line 503, and the voltage control line 203.
  • the process of applying a voltage or passing a current on the voltage control line 203 can also be controlled by the level control circuit, which is used to provide the voltage control line 203 with The required voltage or current.
  • the magnetic random access memory may also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding memory cell through the word line and the bit line when writing or reading data.
  • the above-mentioned level control circuit can be based on the row address.
  • the selection of the decoding circuit and the column address decoding circuit determines the voltage or current that needs to be applied to the first bit line, the second bit line and the word line, and realizes the selection of one or a few of the row address decoding circuit and the column address decoding circuit.
  • Each storage unit performs read and write operations.
  • the level control circuit, the row address decoding circuit, and the column address decoding circuit can be collectively referred to as a control circuit.
  • the data stored in all storage units in a certain storage string can be read at one time.
  • the reading of data in the memory cell utilizes the TMR effect.
  • the word lines respectively apply gate bias voltages to the transistors, so that the transistors are turned on; each of the multiple voltage control lines is used to apply reads to the correspondingly connected memory cells Voltage or reading current, and receiving feedback information of the correspondingly connected storage unit, the feedback information is used to indicate the data stored in the correspondingly connected storage unit.
  • the feedback information of the memory cell can be the current, capacitance and other information of the memory cell.
  • the read voltage applied to each voltage control line is the same
  • the feedback current or capacitance is different
  • the feedback information of the storage cell can be the voltage, capacitance, etc. of the storage cell Information
  • the magnetic random access memory may further include a plurality of amplifiers respectively connected to the plurality of third bit lines in a one-to-one correspondence, and each amplifier of the plurality of amplifiers is used to read the feedback information received by the correspondingly connected voltage control line.
  • each amplifier and its peripheral circuits together form a readout loop for receiving feedback information of the storage unit corresponding to the voltage control line connected to the amplifier, so as to read the data in the storage unit.
  • each amplifier can determine whether the memory cell is in a high-impedance state or a low-impedance state by comparing the feedback information (such as voltage, current, capacitance, charge and discharge time) of the memory cell with a reference value, and then determine the Data stored in the storage unit.
  • the feedback information such as voltage, current, capacitance, charge and discharge time
  • the data of all the storage cells 201 on a storage string 204 are read at one time; an example is: first, the word line corresponding to the structural unit 202 to which the storage string to be read belongs needs to be determined 503. Then, through the word line 503, a gate bias voltage is applied to the transistors in the memory string to be read, so that the transistors of the memory string 204 are turned on, which is equivalent to selecting the structural unit where the memory string 204 is located. Apply a read voltage on all the first bit lines 402 and all the third bit lines 501, and ground the second bit line 504 corresponding to the memory string to be read. At the same time, all the second bit lines 504 need to be connected to the ground.
  • each storage string includes a multi-layer storage structure, which can realize 3D stacking of the storage structure and improve the storage density of the magnetic random access memory.
  • the writing of the memory cell can utilize the SOT effect and the VCMA effect, that is, apply a bias voltage on the voltage control line connected to the magnetic tunnel junction, and use the VCMA effect to change the criticality of the magnetic tunnel junction.
  • the current density is reversed, and current is passed through the electrode line connected to the magnetic tunnel junction at the same time, and the magnetic moment in the free layer is reversed by using the SOT effect to realize data writing.
  • an embodiment of the present application also provides a data writing method for a magnetic random access memory, including:
  • the magnetic random access memory includes a plurality of structural units, the planes on which the multiple structural units are located are parallel, and each structural unit of the multiple structural units includes a mutual A plurality of parallel storage strings, each of the plurality of storage strings includes a multilayer storage structure stacked in sequence, and each storage structure of the multilayer storage structure includes a spin-orbit torque SOT electrode line and A memory cell arranged on the SOT electrode line;
  • the memory cell includes a magnetic tunnel junction, one end of the memory cell is connected to a voltage control line, and the other end of the memory cell is connected to the SOT electrode line,
  • the SOT electrode line is perpendicular to the voltage control line; all SOT electrode lines in each storage string are connected in series by metal wires;
  • the structural unit includes a word line and a first bit line, the word line and the first bit line are both perpendicular to the voltage control line, and the plurality of memory strings in each structural unit Respectively connected to the word line and the first bit line;
  • write data to the memory cell to be written According to the write voltage and the bias voltage, write data to the memory cell to be written.
  • an embodiment of the present application also provides another data writing method for a magnetic random access memory, including:
  • the magnetic random access memory includes a plurality of structural units, the planes on which the multiple structural units are located are parallel, and each structural unit of the multiple structural units includes a mutual A plurality of parallel storage strings, each of the plurality of storage strings includes a multilayer storage structure stacked in sequence, and each storage structure of the multilayer storage structure includes a spin-orbit torque SOT electrode line and A memory cell arranged on the SOT electrode line;
  • the memory cell includes a magnetic tunnel junction, one end of the memory cell is connected to a voltage control line, and the other end of the memory cell is connected to the SOT electrode line,
  • the SOT electrode line is perpendicular to the voltage control line; all SOT electrode lines in each storage string are connected in series by metal wires;
  • the write voltage is applied to the memory cell to be written through the second bit line corresponding to the memory string to which the memory cell to be written belongs; wherein, the second bit line is parallel to the voltage control line, and the second bit line is parallel to the voltage control line.
  • the bit line is connected to the transistor in the memory string;
  • write data to the memory cell to be written According to the write voltage and the bias voltage, write data to the memory cell to be written.
  • an embodiment of the present application also provides a data reading method of a magnetic random access memory, including:
  • the magnetic random access memory includes a plurality of structural units, the planes on which the multiple structural units are located are parallel, and each structural unit of the multiple structural units includes A plurality of memory strings parallel to each other, each of the plurality of memory strings includes a multilayer memory structure stacked in sequence, and each memory structure of the multilayer memory structure includes a spin-orbit moment SOT electrode line And a memory cell disposed on the SOT electrode line; the memory cell includes a magnetic tunnel junction, one end of the memory cell is connected to a voltage control line, and the other end of the memory cell is connected to the SOT electrode line , The SOT electrode line is perpendicular to the voltage control line; all the SOT electrode lines in each storage string are connected in series by metal wires;
  • a gate bias voltage is applied to the transistors in the memory string to be read through the word line corresponding to the target structure unit; wherein each structure unit includes a word line and a first bit line, and The word line and the first bit line are both perpendicular to the voltage control line, and the multiple memory strings in each structural unit are respectively connected to the word line and the first bit line;
  • the second bit line corresponding to the transistor in the memory string to be read is grounded, and the other second bit lines are used to apply a read voltage; wherein the second bit line is parallel to the voltage control line, so The second bit line is connected to the transistor in the memory string;
  • the data corresponding to the memory string to be read is determined according to the read voltage or current received on the third bit line.
  • the embodiments of the present application also provide an electronic device.
  • the electronic device includes a processor 701 and a magnetic random access memory 702 coupled with the processor.
  • the magnetic random access memory 702 may be the magnetic random access memory shown in FIG. 5.
  • the processor 701 may call a software program stored in the magnetic random access memory 702 to execute a corresponding method to realize the corresponding function of the electronic device.

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Abstract

一种磁性随机存储器，用于提高磁性随机存储器的存储密度。包括多个结构单元（202）以及多条电压控制线（203），多条电压控制线（203）平行，多个结构单元（202）所在的平面平行，且所述多个结构单元（202）中的每个结构单元（202）所在的平面与所述多条电压控制线（203）垂直；其中，多个结构单元（202）中的每个结构单元（202）都包括相互平行的多个存储串（204），每个存储串（204）都包括依次堆叠的多层存储结构，每层存储结构包括一条与所述多条电压线控制线（203）垂直的自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元（201）；存储单元（201）包括一个磁性隧道结，存储单元（201）的一端与多条电压控制线（203）中的一条电压控制线（203）连接，存储单元（201）的另一端与SOT电极线连接；每个存储串（204）中的所有SOT电极线之间通过金属导线串联连接。

Description

磁性随机存储器、数据读写方法及电子设备 技术领域
本申请实施例涉及存储技术领域，尤其涉及一种磁性随机存储器及电子设备。
背景技术
信息技术的发展对存储介质的容量、速度、功耗和稳定性等提出了更高要求，相比于传统的半导体存储技术，以磁性隧道结(magnetic tunnel junction，MTJ)为存储单元的磁性随机存储器(magnetic random access memory，MRAM)由于同时具有很多优异的特性如：存储数据的非易失性，读写速度快，无限次的擦写寿命，较低的读写功耗等，被认为是未来很有应用前景的一种存储技术。
MRAM的核心存储单元为MTJ，其核心结构包括自由层、隧穿层和钉扎层，其中，钉扎层的磁矩方向固定，自由层的磁矩方向可以发生改变；在MTJ中写入数据时，可以通过改变自由层的磁矩方向(即控制MTJ自由层和钉扎层的磁矩平行排列或反平行排列)写入不同的数据；从MTJ中读取数据时，可以通过判断MTJ的高低阻态来实现。
现有技术中，MRAM的存储阵列通常是二维(2 dimensions，2D)的。为了提高MRAM的存储密度，一般是通过不断缩小MTJ的尺寸和间距，从而增加单位面积内的存储单元个数这种方式虽然可以在一定程度上提高MRAM的存储密度，但是当MTJ的尺寸缩小到一定程度时，MTJ的热稳定性就会下降，导致存储数据的可靠性降低。
因此，亟需一种MRAM的存储阵列方案，以提高MRAM的存储密度。
发明内容
本申请实施例提供了一种磁性随机存储器、磁性随机存储器的数据读写方法及电子设备，用以提高磁性随机存储器的存储密度。
本申请实施例的第一方面提供一种磁性随机存储器，该磁性随机存储器包括多个结构单元以及多条电压控制线，每一个结构单元所在的平面都相互平行，并且所有的电压控制线与每一个平面都垂直；每个结构单元都包括了多个相互平行的存储串，其中，每个存储串都是由依次堆叠的多层存储结构构成的，每层存储结构包括一条与电压控制线垂直的自旋轨道力矩SOT电极线以及设置在SOT电极线上的一个存储单元，该存储单元为一个磁性隧道结，磁性隧道结的一端与多条电压控制线中的一条电压控制线连接，存储单元的另一端和该层的SOT电极线连接，每一个存储串中所有SOT电极线之间通过金属导线串联连接。
其中，每个磁性隧道结包括依次堆叠的自由层、势垒层和参考层，自由层与SOT电极线连接，参考层与电压控制线连接。
采用第一方面提供的磁性随机存储器，由于存储阵列是三维(3 dimensions，3D)的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。此外，由于在该磁性随机存储器中，通过金属导线将垂直方向上多层存储结构中每一层的一个存储单元对应的SOT电极线串联连接构成一个存储串，因而在向磁性随机存储器中写入数据或者从磁性随机存储器中读取数据时，可以通过一个位线实现同时向多层存储结构中位置对应的多 个SOT电极线施加相应读写电流，从而减少位线在外围电路平面的排线空间，通过较少的位线实现对磁性随机存储器中多层存储结构的寻址和访问。
在一种可能的设计中，该磁性随机存储器中的每一个存储串还包括一个晶体管，晶体管的漏极/源极与该存储串的第一端连接；磁性随机存储器靠多条第一位线和多条字线来连接多个存储串；其中，多条第一位线和所述多条字线相互平行并且与多条电压控制线垂直，属于同一结构单元的所有存储串的第二端连接同一条第一位线，属于同一结构单元的所有存储串中的晶体管的栅级连接同一条字线。
在一种可能的设计中，该磁性随机存储器还包括多条第二位线；第二位线与电压控制线相互平行；在一个存储串中，存储串的一端接第一位线，连接有晶体管的另一端与第二位线连接。
采用上述设计，可以通过在一条字线上施加栅极偏置电压使得属于同一结构单元的存储串的晶体管导通，进而通过在对应的第一位线和第二位线上施加不同的电压使得一个存储串对应的所有SOT电极线上有读写电流通过。
在一种可能的设计中，该磁性随机存储器还包括多条第三位线；第三位线用于连接多条电压控制线，其中，每一条第三位线用于通过金属导线连接和控制多层存储结构中的一层存储结构所对应的所有电压控制线。
采用上述设计，通过一条第三位线将一层存储结构对应的电压控制线连接起来，因而在向磁性随机存储器中写入数据或者从磁性随机存储器中读取数据时，可以通过一个第三位线实现同时向一层存储结构对应的多个电压控制线施加相应电压，从而减少位线在外围电路平面的排线空间；进而通过对不同第三位线施加不同的电压来选择对一个存储串中的一个存储单元施加相应电压。
在一种可能的设计中，对每一个存储串的所有SOT电极线进行串联的连接方式可以有多种，下面以其中两种为例进行说明：
第一种
在每个存储串中，SOT电极线依次堆叠；其串联方式为，其中，第N层存储结构的SOT电极线的第一端通过金属导线连接第N+1层存储结构的SOT电极线的第一端，第N+1层存储结构的SOT电极线的第二端连接第N+2层存储结构的SOT电极线的第二端。
第二种
每个存储串中，SOT电极线依次堆叠；其串联方式为，第N层存储结构的SOT电极线的第一端通过金属导线连接第N+1层存储结构的SOT电极线的第二端。
在第一方面提供的磁性随机存储器中，写入数据和读取数据可以通过以下的方式实现：在向所述磁性随机存储器写入数据时，先通过待写入存储单元所属的结构单元对应的字线向该待写入存储单元所属的存储串中的晶体管施加栅极偏置电压；然后向该存储串对应的第一位线施加写入电压，将该存储串对应的第二位线接地，这样，就相当于选中了存储单元所在的存储串，使得存储串上的多个存储单元对应的SOT电极线都有写入电流；由于一个存储串内，每个存储单元都在不同层，而不同层对应不同的电压控制线，因此，在待写入存储单元连接的电压控制线对应的第三位线上施加偏置电压，就可以根据自旋轨道力矩 (spin-orbit torque，SOT)效应和电压调控磁各向异性(voltage-controlled magnetic anisotropy，VCMA)原理写入相应的数据。在向所述磁性随机存储器写入不同数据时，也可以将待写入存储单元所属的存储串对应的第一位线接地，第二位线施加写入电压，从而选中存储单元所在的存储串，使得存储串上的多个存储单元对应的SOT电极线上都有反向写入电流；然后在待写入存储单元连接的电压控制线对应的第三位线上施加偏置电压，写入不同的数据。
在上述方案中，可以通过在字线上施加不同栅极偏置电压使得仅待写入存储单元所属的结构单元中的所有晶体管导通，其他结构单元中的晶体管非导通。进而通过在第一位线和第二位线上施加不同的电压使得仅待写入存储单元所属的存储串的SOT电极线上有写电流通过。同时，在待写入存储单元所连接的电压控制线对应的第三位线上施加写入偏置电压，其他第三位线施加非写入偏置电压，在写电流和电压的共同作用下仅待写入单元完成信息写入而其他存储单元信息不变。
在向所述磁性随机存储器读取数据时，一次性读取一个存储串上所有存储单元的数据，首先确定待读取存储串所属的结构单元对应的字线，然后通过该字线对待读取存储串中的晶体管施加栅极偏置电压，使得该存储串的晶体管导通，然后在该待读取存储串所属的结构单元对应的第一位线上施加读取电压，将该待读取存储串对应的第二位线接地，同时在其他所有的第一位线和第二位线上施加读取电压，在所有第三位线上施加读取电压，一次性读取一整个存储串上的数据。
本申请实施例的第二方面提供一种随机存储器的数据写入方法，包括：
磁性随机存储器包括多个结构单元、多条电压控制线、多条第一位线、多条第二位线和多条字线，其中，电压控制线与第二位线平行，第一位线与字线平行，电压控制线和第一位线垂直；多个结构单元所在的平面平行并且每个结构单元都包括相互平行的多个存储串；每个存储串都包括依次堆叠的多层存储结构和一个晶体管，每层存储结构又包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；该存储单元可以是一个磁性隧道结，一端与电压控制线连接，另一端与SOT电极线连接，而SOT电极线与电压控制线互相垂直并且每个存储串中的所有SOT电极线之间通过金属导线串联连接；同时每一个结构单元共用一条第一位线和一条字线，每个结构单元中所有存储串的第一端连接同一条第一位线，所有存储串的晶体管的栅级连接同一条字线，存储串的第二端连接晶体管的第一端，晶体管的第二端连接第二位线。
当向待写入存储单元写入数据时，先确定待写入存储单元所属的结构单元；然后通过该结构单元对应的字线向待写入存储单元所属的存储串中的晶体管施加栅极偏置电压，这样将使得一整个结构单元的存储串导通，然后通过该结构单元对应的第一位线向存储单元施加写入电压，并且将待写入存储单元所属的存储串所对应的第二位线接地；这样即选中了待写入存储单元所属的存储串，使得该存储串中的SOT电极线有了写入电流，然后通过待写入存储单元连接的电压控制线向存储单元施加偏置电压，这样就选中了待写入存储单元，然后根据写入电压和偏置电压，向待写入存储单元写入数据。
本申请实施例的第三方面提供一种随机存储器的数据写入方法，包括：
磁性随机存储器包括多个结构单元、多条电压控制线、多条第一位线、多条第二位线和多条字线，其中，电压控制线与第二位线平行，第一位线与字线平行，电压控制线和第一位线垂直；多个结构单元所在的平面平行并且每个结构单元都包括相互平行的多个存储串；每个存储串都包括依次堆叠的多层存储结构和一个晶体管，每层存储结构又包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；该存储单元可以是一个磁性隧道结，一端与电压控制线连接，另一端与SOT电极线连接，而SOT电极线与电压控制线互相垂直并且每个存储串中的所有SOT电极线之间通过金属导线串联连接；同时每一个结构单元共用一条第一位线和一条字线，每个结构单元中所有存储串的第一端连接同一条第一位线，所有存储串的晶体管的栅级连接同一条字线，存储串的第二端连接晶体管的第一端，晶体管的第二端连接第二位线。
当向待写入存储单元写入数据时，先确定待写入存储单元所属的结构单元；然后通过该结构单元对应的字线向待写入存储单元所属的存储串中的晶体管施加栅极偏置电压，这样将使得一整个结构单元的存储串导通，然后向该待写入存储单元所属存储串所对应的第二位线施加写入电压，将该结构单元对应的第一位线接地，这样即选中了待写入存储单元所属的存储串，使得该存储串中的SOT电极线有了写入电流，然后通过待写入存储单元连接的电压控制线向存储单元施加偏置电压，这样就选中了待写入存储单元，然后根据写入电压和偏置电压，向待写入存储单元写入数据。
本申请实施例的第四方面提供一种随机存储器的数据读取方法，包括：
磁性随机存储器包括多个结构单元、多条电压控制线、多条第一位线、多条第二位线和多条字线，其中，电压控制线与第二位线平行，第一位线与字线平行，电压控制线和第一位线垂直；多个结构单元所在的平面平行并且每个结构单元都包括相互平行的多个存储串；每个存储串都包括依次堆叠的多层存储结构和一个晶体管，每层存储结构又包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；该存储单元可以是一个磁性隧道结，一端与电压控制线连接，另一端与SOT电极线连接，而SOT电极线与电压控制线互相垂直并且每个存储串中的所有SOT电极线之间通过金属导线串联连接；同时每一个结构单元共用一条第一位线和一条字线，每个结构单元中所有存储串的第一端连接同一条第一位线，所有存储串的晶体管的栅级连接同一条字线，存储串的第二端连接晶体管的第一端，晶体管的第二端连接第二位线。
当向随机存储器读取数据时，首先需要确定待读取存储串对应的目标结构单元；然后通过目标结构单元对应的字线，向待读取存储串中的晶体管施加栅极偏置电压；即使得目标结构单元中的存储串都导通，然后在电压控制线和第一位线均施加读取电压；最后将待读取存储串中所述晶体管对应连接的第二位线接地，其他第二位线上施加读取电压，然后根据读取电流确定待读取存储串所对应的数据。
本申请实施例第五方面提供一种电子设备，该电子设备包括处理器以及与处理器耦合的、第一方面及其任一可能的设计中提供的磁性随机存储器。
具体地，处理器可以调用磁性随机存储器中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
附图说明
图1为本申请实施例中提供的一种磁性随机存储器的结构框图；
图2为本申请实施例提供的一种磁性随机存储器的结构示意图；
图3为本申请实施例提供的一种存储串的连接示意图；
图4为本申请实施例提供的另一种存储串的连接示意图；
图5为本申请实施例提供的另一种磁性随机存储器的结构示意图；
图6为本申请实施例提供的一种MTJ的结构示意图；
图7为本申请实施例提供的一种电子设备的结构框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
本申请实施例提供一种磁性随机存储器及电子设备，用以提高磁性随机存储器的存储密度、提升存储单元的稳定性。
下面，对本申请实施例的应用场景加以简单介绍。
本申请实施例可以应用于图1所示的磁性随机存储器。该磁性随机存储器包括控制电路以及至少一个存储电路。
具体地，每个存储电路用于写入和读取数据。控制电路用于对存储电路写入和读取数据的过程进行控制，比如，在写入数据时选择要写入数据的存储单元、通过施加相应电压和通入相应电流以实现在选择的存储单元中写入数据，再比如，在读取数据时选择要读取的存储单元，通过施加相应电压和通入相应电流以实现从选择的存储单元中读取数据。
其中，每个存储电路中包括多个存储单元，存储单元是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。
下面将结合附图对本申请实施例作进一步地详细描述。
需要说明的是，本申请中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
参见图2，为本申请实施例提供的一种磁性随机存储器的结构示意图，该随机存储器包括多个存储单元201，在三维空间内依次堆叠；包括多个结构单元202和多条电压控制线203，多个结构单元202以及多个电压控制线203可以视为图1中的存储电路。
其中，每一个结构单元202中包括多个存储串204，多个存储串204相互平行；每一个存储串204都是由依次堆叠的多层存储结构构成的，每层存储结构包括一条与电压控制线203垂直的自旋轨道力矩SOT电极线以及设置在SOT电极线上的一个存储单元201，该存储单元201为一个磁性隧道结，磁性隧道结的一端与该层的SOT电极线连接，一个存储串中所有SOT电极线之间通过金属导线串联连接。
在磁性随机存储器中，电压控制线203与存储单元201是一一对应的，也就是说，每个存储单元201均有与之对应的一个电压控制线203，用于向该存储单元201施加电压。
可选地，多个电压控制线203相互平行；多个结构单元202所在的平面相互平行，且每个结构单元202所在的平面与多个电压控制线203垂直。
需要说明的是，本申请实施例中，多个电压控制线203平行的概念并不是严格意义上的平行，在磁性随机存储器的制备过程中，由于制备工艺和制备设备的影响，可能存在多个电压控制线203并非严格平行的情况，这种情况是由于具体制备流程导致的，并不能说明多个电压控制线203不严格平行的情况超脱本申请的保护范围。此外，对于平面平行和垂直这两种位置关系也有类似理解，此处不再赘述。
为了方便描述，图2所示的磁性随机存储器中示出了xyz坐标系。其中，在磁性随机存储器中，电压控制线203沿x轴平行排列；每个结构单元202所在的平面均与x轴垂直；在每个存储串204中，多层存储结构沿着z轴方向依次堆叠，且每层存储结构对应的电级线沿y轴排列，可以与电压控制线203垂直。
应理解，存储单元201是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。通过多个存储单元201，可以实现多个二进制位数据的存储。具体地，本申请实施例中，一个存储单元201中包括一个MTJ，用于存储一个二进制位。每个MTJ可以包括沿z轴正方向依次堆叠的自由层、隧穿层和钉扎层。其中，钉扎层的磁矩方向固定，自由层的磁矩方向可以在数据写入时发生改变，自由层与钉扎层的磁矩呈平行或反平行排列时对应不同的数据，隧穿层用于产生隧道磁电阻效应。具体地，本申请中，自由层与电极线连接，钉扎层与电压控制线连接。也就是说，自由层靠近与MTJ连接的电极线，钉扎层与该电极线距离最远，隧穿层位于自由层和参考层之间。
具体地，本申请实施例中，对于自由层和钉扎层的磁矩方向平行排列或反平行排列，可以有如下理解：自由层和钉扎层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和钉扎层的磁矩方向不做具体限定，只要自由层和钉扎层的磁矩方向平行排列或反平行排列即可。
具体的，在每个存储串204中，所有SOT电极线之间通过金属导线串联连接，连接的方式可以有多种，具体不做限定；示例性的，可以包括下面两种串联方式：
参见图3，为本申请实施例提供的一种串联存储串204的连接示意图。在一个存储串204中，多个存储单元201沿z轴方向依次堆叠，每个存储单元201都包括一个磁性隧道结，该磁性隧道结设置在一条SOT电极线上，当使用金属导线将依次堆叠的SOT电极线进行串联时，可以将第N层存储结构的SOT电极线的第一端和第N+1层存储结构的SOT电极线的第一端相连，然后将第N+1层存储结构的SOT电极线的第二端与第N+2层存储结构的SOT电极线的第二端相连；示例性的，如图3所示，SOT电极线可以分为左端和右端，即第一层的左端与第二层的左端连接，第二层的右端与第三层的右端连接，第三层的左端与第四层的左端连接，按照该顺序依次连接多层的SOT电极线；可以理解的，当通过金属导线给存储串的SOT电极线通入电流时，相邻两层磁性隧道结对应的SOT电极线中电流流向是不同的。
参见图4，为本申请实施例提供的另一种存储串204的连接示意图。一个存储串204 中，多个存储单元201仍然沿z轴方向依次堆叠，存储串204中的存储单元201可以沿Z轴正方向依次排列，也可以相互错开，当使用金属导线将依次堆叠的SOT电极线进行串联时，可以将第N层存储结构的SOT电极线的第一端与第N+1层存储结构的SOT电极线的第二端相连，示例性的，如图3B所示，第一层SOT电极线的右端连接第二层SOT电极线的左端，第二层SOT电极线的右端连接第三层SOT电极线的左端，依次首尾相连；可以理解的，当通过金属导线给存储串的SOT电极线通入电流时，每一层磁性隧道结对应的SOT电极线中电流流向是相同的。
下面将根据图2所示的结构框架，来介绍如何对存储单元201进行控制以及如何向存储单元201写入数据或者读取存储单元201存储的数据。
磁性随机存储器是根据不同的位线来选择特定的存储单元201并写入或者读取数据的，在图2所示的结构示意图中，每一个存储串204还可以串联一个晶体管，用于控制存储串204的导通和关断，示例性的，可以直接与存储串204的第一层存储结构对应的SOT电极线连接，也可以与存储串204最上层存储结构对应的SOT电极线连接，SOT电极线可以连接晶体管的源极，也可以连接晶体管的漏极，具体不做限定。
磁性随机存储器还包括多条不同的位线，多个存储串204与位线的连接方式为：沿z轴方向，存储串204的最上端连接第一位线，存储串204下端的晶体管连接第二位线，即可以通过向第一位线和第二位线施加不同的电压来向一个存储串204中的所有SOT电极线提供电流；晶体管的栅级连接字线，通过字线可以向晶体管的栅级施加栅极偏置电压，控制存储串204的晶体管的导通和关断。
示例性的，如图5所示，在磁性随机存储器中，多条电压控制线203与x轴平行，沿着x轴方向依次排列的一行存储串204中的一层的存储单元201对应连接一条电压控制线203；而第三位线501则连接一整层存储结构的所有电压控制线203，即当通过一条第三位线501施加电压时，一整层的存储单元201对应的电压控制线203都将被施加电压。
而多条第一位线502与y轴平行，其中，每一个结构单元202的存储串204连接同一条第一位线502，多条字线503也与y轴平行，每一个结构单元202的存储串204中的晶体管栅级连接同一条字线503，即当通过一条字线503施加栅极偏置电压时，一个结构单元202内的所有晶体管都将导通。
多条第二位线504与电压控制线203平行，与结构单元202所在的平面垂直，沿着x轴方向依次排列的一行存储串204中的晶体管的栅极/漏极对应连接一条第二位线504。
此外，需要说明的是，在图4所示的磁性随机存储器中，为了示意简便，仅示出了x轴方向依次排列的三个存储串204和y轴方向依次排列的三个存储串204，因此，第一位线包括bl u1、bl u2和bl u3，第二位线依次包括bl d1、bl d2和bl d3，字线WL 1、WL 2和WL 3，第三位线BL 1、BL 2和BL 3；磁性随机存储器可以沿任意方向排列多个存储串204，对数量不进行限定。
(一)磁性随机存储器的数据写入：
本申请实施例提供的磁性随机存储器在写入数据时利用了SOT效应和VCMA效应，在读取数据时利用了隧穿磁电阻(tunnel magneto resistance，TMR)效应。
SOT效应的原理是：在电极线中通入电流，将会产生向上(即向z轴正方向)扩散的自旋极化电流，进入MTJ的自由层中。当电流达到一定值(临界翻转电流密度)时，在自旋轨道相互作用力矩作用下，自由层的磁矩发生翻转，实现数据的写入。改变电极线中电流的方向，自旋流的极化方向发生改变，自由层的磁矩翻转方向也相应改变，实现不同数据的写入。VCMA效应的原理是：在MTJ两端施加偏置电压可以改变MTJ自由层与隧穿层的界面电荷密度，从而改变自由层的垂直各向异性和矫顽力，进而降低MTJ的临界翻转电流密度。利用VCMA效应降低MTJ临界翻转电流密度的同时，在电极线中通入电流，在SOT效应和VCMA效应的共同作用下使得自由层中的磁矩发生翻转，实现数据的写入，这种写入方式可以显著降低数据写入的功耗。
实际应用中，电极线可以由重金属材料制成，或者由其他可以产生自旋流的材料制成，电极线也可以称为SOT电极线。
示例性地，图2所示的磁性随机存储器中的MTJ的结构可以如图6所示。从图6中可以看出，MTJ的自由层与电极线连接，MTJ的钉扎层与电压控制线203连接。通过电压源或电流源向电压控制线203施加电压或通入电流，以及向SOT电极线中通入电流，可以使得电压控制线203上的电压与SOT电极线上的电压存在电压差，该电压差即为在MTJ两端施加的偏置电压。
具体地，应用在本申请实施例中，在向磁性随机存储器写入数据时，由电压控制线203独立地对其连接的MTJ进行选择性操作，例如可以在待写入存储单元所连接的电压控制线203上施加第一偏置电压，降低待写入存储单元的临界翻转电流密度。在非写入存储单元所连接的电压控制线203上施加第二偏置电压，提高(或不改变)非写入存储单元的临界翻转电流密度。与此同时，在待写入存储单元所连接的电极线中通入写入电流(通入不同方向的电流，可以写入不同的数据)，产生向上(即向z轴正方向)扩散的自旋流进入MTJ的自由层中，从而实现在待写入存储单元写入数据。
TMR效应的原理是：当MTJ的自由层和钉扎层的磁矩平行排列时，MTJ为低电阻态；当自由层和钉扎层的磁矩反平行排列(即平行且方向相反)时，MTJ为高电阻态。高低电阻代表了两种不同的数据状态，例如0或1；根据MTJ为高阻态或低阻态可以读取出不同的数据。
具体地，应用在本申请实施例中，在从磁性随机存储器读取数据时，待读取存储单元所连接的电极线用于为存储单元201提供接地回路，在待读取存储单元所连接的电压控制线203上施加读取电压或读取电流，并通过与电压控制线203连接的读出回路(例如第三位线上的放大器SA)获取待读取存储单元携带的数据信息。
示例性地，通过放大器比较读出回路中的读电流，可以判断该放大器所连接的电压控制线203对应的MTJ为高阻态或低阻态，进而判断该MTJ中存储的数据为0还是为1。
为了避免在写入数据时，电极线上的电流流经MTJ，形成潜行通路(sneak path)，对写入数据的准确性产生影响，本申请实施例中，MTJ可以具有高电阻特性，例如MTJ的电阻值不低于100KΩ，使得MTJ的电阻值远大于电极线的电阻值，这样可以有效避免写入电流流经MTJ，降低sneak path的影响。
此外，在图2所示的磁性随机存储器中，自由层和钉扎层的磁矩方向平行排列或反平行排列。具体地，自由层和钉扎层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和钉扎层的磁矩方向不做具体限定，只要自由层和钉扎层的磁矩方向平行排列或反平行排列即可。
基于如前所述的磁性随机存储器的结构框架，当向存储单元201写入数据时，在SOT电极线上通入电流的过程可以由第一位线502和第二位线504控制，第一位线502直接与存储串204的上端相连，第二位线504则与存储串204中的晶体管的一端相连，其可以是与晶体管的源极相连，也可以与晶体管的漏极相连，具体不做限定。晶体管的导通和关断由字线503控制，在对应的字线503上向晶体管施加栅极偏置电压使得晶体管导通，并且在存储串204对应的第一位线502和第二位线504上施加不同的电压，即可以选中目标存储串，实现向目标存储串的SOT电极线上施加写电流。
具体的，在图5所示的磁性随机存储器中，在向待写入存储单元写入数据时，先确定待写入存储单元所属的结构单元202；然后通过该结构单元202对应的字线503施加栅极偏置电压，这样，则使得一个结构单元202中所有的存储串204的晶体管都导通；可选的，剩余的字线503不施加栅极偏置电压，这样相当于选中了待写入存储单元所在的结构单元202。
可以理解的，在一种方式中，可以通过该结构单元202对应的第一位线502施加写入电压，然后确定待写入存储单元所在的存储串204对应的第二位线504，将该第二位线504接地；向剩余的第二位线504施加写入电压，这样，待写入存储单元所在的存储串204为唯一的一端接写入电压，另一端接地的存储串，即使得该存储串204中的SOT电极线有了写入电流，相当于选中了待写入存储单元所在的存储串。
当选中待写入存储单元所在的存储串204后，可以通过多条第三位线501来对每一层的电压控制线203施加偏置电压，可选的，先确定待写入存储单元对应的第三位线501，然后在该第三位线501上施加第一偏置电压，在其他第三位线501上施加第二偏置电压，第一偏置电压与第二偏置电压不相等。
其中，第一偏置电压用于降低待写入存储单元的临界翻转电流密度，第二偏置电压用于提高(或不改变)非写入存储单元的临界翻转电流密度。第一偏置电压和第二偏置电压的值不相同，第一偏置电压和第二偏置电压的具体数值可以根据存储单元201的具体结构和材料参数确定。也就是说，当电压控制线203施加第一偏置电压时，可以实现向电压控制线203连接的存储单元201写入数据；当电压控制线203施加第二偏置电压时，无法向电压控制线203连接的存储单元201写入数据。
在一个具体的示例中，第一偏置电压与电极线的电压之差为负值，第二偏置电压与电极线的电压之差为正值或零；或者，第一偏置电压与电极线的电压之差为正值，第二偏置电压与电极线的电压之差为负值或零。
待写入存储单元通过施加的写入电流和第一偏置电压，完成数据的写入。
可以理解的，在另一种方式中，可以将该结构单元202对应的第一位线502接地，然后确定待写入存储单元所在的存储串204对应的第二位线504，通过该第二位线504施加 写入电压；可选的，可以将剩余的第二位线504接地，这样，也可以保证待写入存储单元所在的存储串204为唯一的一端接写入电压，另一端接地的存储串，即使得该存储串204中的SOT电极线有了反向写入电流，相当于选中了待写入存储单元所在的存储串；然后再确定待写入存储单元201对应的第三位线501，向该第三位线501施加第一偏置电压，完成不同数据的写入。
由于存储串中SOT电极线串联的方式多样，若存储串204中SOT电极线串联的方式如图3所示，可以得知当通过第一位线502和第二位线504为该存储串204提供写入电压时，相邻两层存储单元对应的SOT电极线中写入电流的流向不同，因此若相邻两层存储单元写入同一个数据时，其控制方式也不同；示例性的，若第一层存储单元要写入数据“1”，则可以选择通过第一位线施加写入电压，将第二位线接地，若第二层存储单元要写入数据“1”，则可以选择通过第二位线施加写入电压，将第一位线接地。
实际应用中，在向磁性随机存储器写入数据时，上述在第一位线502、第二位线504、字线503和电压控制线203上施加电压或通入电流的过程可以由磁性随机存储器中配置的电平控制电路进行控制，该电平控制电路用于为第一位线502、第二位线504、字线503和电压控制线203提供所需的电压或电流。同样地，在从磁性随机存储器读取数据时，在电压控制线203上施加电压或通入电流的过程也可以由该电平控制电路控制，该电平控制电路用于为电压控制线203提供所需的电压或电流。
此外，磁性随机存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线和位线选择对应的存储单元，上述电平控制电路可以根据行地址解码电路和列地址解码电路的选择来判断需要在第一位线、第二位线和字线上施加的电压或电流，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元进行读写操作。
其中，电平控制电路、行地址解码电路和列地址解码电路可以统称为控制电路。
(二)磁性随机存储器的数据读取：
在从磁性随机存储器读取数据时，可以一次性读取某个存储串中所有存储单元存储的数据。
存储单元中数据的读取利用TMR效应。在从磁性随机存储器读取数据时，字线分别向晶体管施加栅极偏置电压，使得晶体管导通；多个电压控制线中的每个电压控制线用于向对应连接的存储单元施加读取电压或读取电流，以及接收对应连接的存储单元的反馈信息，该反馈信息用于指示对应连接的存储单元中存储的数据。
其中，每个电压控制线向对应连接的存储单元施加读取电压时，存储单元的反馈信息可以是存储单元的电流、电容量等信息，在每个电压控制线施加的读取电压相同的情况下，存储单元处于不同阻态时，反馈的电流或电容量不同；每个电压控制线向对应连接的存储单元施加读取电流时，存储单元的反馈信息可以是存储单元的电压、电容量等信息，在每个电压控制线施加的读取电流相同的情况下，存储单元处于不同阻态时，反馈的电压或电容量不同。
此外，磁性随机存储器中还可以包括分别与多个第三位线一一对应连接的多个放大器， 多个放大器中的每个放大器用于读取对应连接的电压控制线所接收的反馈信息。
其中，每个放大器及其外围电路等共同组成读出回路，用于接收放大器所连接的电压控制线对应的存储单元的反馈信息，从而读取存储单元中的数据。
具体地，每个放大器可以通过将存储单元的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元处于高阻态还是低阻态，进而确定该存储单元中存储的数据。
在向所述磁性随机存储器读取数据时，一次性读取一个存储串204上所有存储单元201的数据；一种示例为：首先需要确定待读取存储串所属的结构单元202对应的字线503，然后通过该字线503对待读取存储串中的晶体管施加栅极偏置电压，使得该存储串204的晶体管导通，这样相当于选中了该存储串204所在的结构单元。在所有的第一位线402和所有第三位线501上施加读取电压，将该待读取存储串对应的第二位线504接地，同时还需要在其他的第二位线504上全部施加读取电压，这样就保证只有待读取存储串的存储单元MTJ两端有电压差，相当于选中了该待读取存储串，最后通过与第三位线一一对应的放大器接收的反馈信息来判断待读取存储串中各层存储单元对应的高低组态，从而实现一整个存储串数据的读出。
采用本申请实施例提供的磁性随机存储器，每个存储串包括多层存储结构，可以实现存储结构的3D堆叠，提高磁性随机存储器的存储密度。采用本申请实施例提供的磁性随机存储器，存储单元的写入可以利用SOT效应和VCMA效应，即在与磁性隧道结连接的电压控制线上施加偏置电压，利用VCMA效应改变磁性隧道结的临界翻转电流密度，同时在与磁性隧道结连接的电极线上通入电流，利用SOT效应使得自由层中的磁矩发生翻转，实现数据的写入。
基于同一发明构思，本申请实施例还提供一种磁性随机存储器的数据写入方法，包括：
确定待写入存储单元所属的结构单元；其中，所述磁性随机存储器包括多个结构单元，所述多个结构单元所在的平面平行，所述多个结构单元中的每个结构单元都包括相互平行的多个存储串，所述多个存储串中的每个存储串都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；所述存储单元包括一个磁性隧道结，所述存储单元的一端与电压控制线连接，所述存储单元的另一端与所述SOT电极线连接，所述SOT电极线与所述电压控制线垂直；所述每个存储串中的所有SOT电极线之间通过金属导线串联连接；
通过所述结构单元对应的字线向所述待写入存储单元所属存储串中的晶体管施加栅极偏置电压并通过所述结构单元对应的第一位线向所述存储单元施加写入电压，其中，所述结构单元包含一条字线和一条第一位线，所述字线和所述第一位线均与所述电压控制线垂直，所述每个结构单元中的多个存储串分别与所述字线和所述第一位线连接；
将所述待写入存储单元所属存储串对应的第二位线接地；其中，所述第二位线与所述电压控制线平行，所述第二位线与所述存储串中的晶体管连接；
通过所述待写入存储单元连接的电压控制线向所述存储单元施加偏置电压；
根据所述写入电压和所述偏置电压，向所述待写入存储单元写入数据。
基于同一发明构思，本申请实施例还提供另一种磁性随机存储器的数据写入方法，包括：
确定待写入存储单元所属的结构单元；其中，所述磁性随机存储器包括多个结构单元，所述多个结构单元所在的平面平行，所述多个结构单元中的每个结构单元都包括相互平行的多个存储串，所述多个存储串中的每个存储串都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；所述存储单元包括一个磁性隧道结，所述存储单元的一端与电压控制线连接，所述存储单元的另一端与所述SOT电极线连接，所述SOT电极线与所述电压控制线垂直；所述每个存储串中的所有SOT电极线之间通过金属导线串联连接；
通过所述结构单元对应的字线向所述待写入存储单元所属存储串中的晶体管施加栅极偏置电压并将所述结构单元对应的第一位线接地，其中，所述结构单元包含一条字线和一条第一位线，所述字线和所述第一位线均与所述电压控制线垂直，所述每个结构单元中的多个存储串分别与所述字线和所述第一位线连接；
通过所述待写入存储单元所属存储串对应的第二位线向所述待写入存储单元施加写入电压；其中，所述第二位线与所述电压控制线平行，所述第二位线与所述存储串中的晶体管连接；
通过所述待写入存储单元连接的电压控制线向所述存储单元施加偏置电压；
根据所述写入电压和所述偏置电压，向所述待写入存储单元写入数据。
基于同一发明构思，本申请实施例还提供一种磁性随机存储器的数据读取方法，包括：
确定待读取存储串对应的目标结构单元；其中，所述磁性随机存储器包括多个结构单元，所述多个结构单元所在的平面平行，所述多个结构单元中的每个结构单元都包括相互平行的多个存储串，所述多个存储串中的每个存储串都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；所述存储单元包括一个磁性隧道结，所述存储单元的一端与电压控制线连接，所述存储单元的另一端与所述SOT电极线连接，所述SOT电极线与所述电压控制线垂直；所述每个存储串中的所有SOT电极线之间通过金属导线串联连接；
通过所述目标结构单元对应的字线，向所述待读取存储串中的晶体管施加栅极偏置电压；其中，所述每个结构单元包含一条字线和一条第一位线，所述字线和所述第一位线均与所述电压控制线垂直，所述每个结构单元中的多个存储串分别与所述字线和所述第一位线连接；
在所述电压控制线和所述第一位线均施加读取电压；
将所述待读取存储串中所述晶体管对应的第二位线接地，其他所述第二位线用于施加读取电压；其中所述第二位线与所述电压控制线平行，所述第二位线与所述存储串中的晶体管连接；
根据所述第三位线上接收的读取电压或电流确定所述待读取存储串所对应的数据。
基于同一发明构思，本申请实施例还提供一种电子设备。参见图7，该电子设备包括处理器701以及与处理器耦合的磁性随机存储器702，磁性随机存储器702可以是图5所 示的磁性随机存储器。
具体地，处理器701可以调用磁性随机存储器702中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种磁性随机存储器，其特征在于，包括多个结构单元以及多条电压控制线，所述多条电压控制线平行，所述多个结构单元所在的平面平行，且所述多个结构单元中的每个结构单元所在的平面与所述多条电压控制线垂直；
    其中，所述多个结构单元中的每个结构单元都包括相互平行的多个存储串，所述多个存储串中的每个存储串都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构包括一条与所述多条电压线控制线垂直的自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；所述存储单元包括一个磁性隧道结，所述存储单元的一端与所述多条电压控制线中的一条电压控制线连接，所述存储单元的另一端与所述SOT电极线连接；所述每个存储串中的所有SOT电极线之间通过金属导线串联连接。
  2. 如权利要求1所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多条第一位线和多条字线，所述多条第一位线和所述多条字线平行且与所述多条电压控制线垂直；
    所述多个存储串中的每个存储串还包括晶体管，所述存储串的第一端与所述晶体管的第一端相连；其中，属于同一结构单元的所有存储串的第二端连接所述多条第一位线中的同一条第一位线，属于同一结构单元的所有晶体管的栅级连接所述多条字线中的同一条字线。
  3. 如权利要求2所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多条第二位线；所述多条第二位线与所述多条电压控制线平行；所述晶体管的第二端与所述多条第二位线的一个第二位线连接。
  4. 如权利要求1至3所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多条第三位线；所述多条第三位线中的每一条第三位线用于通过金属导线连接和控制所述多层存储结构中的一层存储结构所对应的电压控制线。
  5. 如权利要求1至4所述的磁性随机存储器，其特征在于，在所述多个存储串中的每个存储串中，所述SOT电极线依次堆叠；其中，所述多层存储结构中的第N层存储结构的SOT电极线的第一端通过金属导线连接所述多层存储结构中的第N+1层存储结构的SOT电极线的第一端，所述第N+1层存储结构的SOT电极线的第二端连接所述多层存储结构中的第N+2层存储结构的SOT电极线的第二端。
  6. 如权利要求1至4所述的磁性随机存储器，其特征在于，在所述多个存储串中的每个存储串中，所述SOT电极线依次堆叠；其中，所述多层存储结构中的第N层存储结构的SOT电极线的第一端通过金属导线连接所述多层存储结构中的第N+1层存储结构的SOT电极线的第二端。
  7. 如权利要求5或6所述的磁性随机存储器，其特征在于，在向所述磁性随机存储器写入数据时，所述待写入存储单元所属的结构单元对应的字线用于向所述待写入存储单元所属的存储串中的晶体管施加栅极偏置电压；所述待写入存储单元所属的存储串连接的第一位线用于施加写入电压，所述待写入存储单元所属的存储串连接的第二位线接地；所述待写入存储单元连接的电压控制线对应连通的第三位线用于施加偏置电压。
  8. 如权利要求5或6所述的磁性随机存储器，其特征在于，在向所述磁性随机存储器写入数据时，所述待写入存储单元所属的结构单元对应的字线用于向所述待写入存储单元所属的存储串中的晶体管施加栅极偏置电压；所述待写入存储单元所属的存储串连接的第一位线接地，所述待写入存储单元所属的存储串连接的第二位线用于施加写入电压；所述待写入存储单元连接的电压控制线对应连通的第三位线用于施加偏置电压。
  9. 如权利要求6、7或8所述的磁性随机存储器，其特征在于，在从所述磁性随机存储器读取数据时，待读取存储串所属的结构单元对应的字线用于向所述待读取存储串中的晶体管施加栅极偏置电压；所述磁性随机存储器中的所述多条第三位线和所述多条第一位线都用于施加读取电压；所述待读取存储串中所述晶体管对应连接的第二位线接地，其他所述第二位线用于施加读取电压。
  10. 如权利要求1至9任一项所述的磁性随机存储器，其特征在于，每个所述磁性隧道结包括依次堆叠的自由层、势垒层和参考层，所述自由层与所述SOT电极线连接，所述参考层与所述电压控制线连接。
  11. 如权利要求4所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多个放大器SA；
    所述多个放大器SA与所述多条第三位线一一对应连接，所述多个放大器中的每个放大器用于读取对应连接的第三位线所接收的信号。
  12. 一种磁性随机存储器的数据写入方法，其特征在于，所述方法包括：
    确定待写入存储单元所属的结构单元；其中，所述磁性随机存储器包括多个结构单元，所述多个结构单元所在的平面平行，所述多个结构单元中的每个结构单元都包括相互平行的多个存储串，所述多个存储串中的每个存储串都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；所述存储单元包括一个磁性隧道结，所述存储单元的一端与电压控制线连接，所述存储单元的另一端与所述SOT电极线连接，所述SOT电极线与所述电压控制线垂直；所述每个存储串中的所有SOT电极线之间通过金属导线串联连接；
    通过所述结构单元对应的字线向所述待写入存储单元所属存储串中的晶体管施加栅极偏置电压并通过所述结构单元对应的第一位线向所述存储单元施加写入电压，其中，所述结构单元包含一条字线和一条第一位线，所述字线和所述第一位线均与所述电压控制线垂直，所述每个结构单元中的多个存储串分别与所述字线和所述第一位线连接；
    将所述待写入存储单元所属存储串对应的第二位线接地，并其他所述第二位线施加写入电压；其中，所述第二位线与所述电压控制线平行，所述第二位线与所述存储串中的晶体管连接；
    通过所述待写入存储单元连接的电压控制线向所述存储单元施加偏置电压；
    根据所述写入电压和所述偏置电压，向所述待写入存储单元写入数据。
  13. 一种磁性随机存储器的数据写入方法，其特征在于，所述方法包括：
    确定待写入存储单元所属的结构单元；其中，所述磁性随机存储器包括多个结构单元，所述多个结构单元所在的平面平行，所述多个结构单元中的每个结构单元都包括相互平行 的多个存储串，所述多个存储串中的每个存储串都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；所述存储单元包括一个磁性隧道结，所述存储单元的一端与电压控制线连接，所述存储单元的另一端与所述SOT电极线连接，所述SOT电极线与所述电压控制线垂直；所述每个存储串中的所有SOT电极线之间通过金属导线串联连接；
    通过所述结构单元对应的字线向所述待写入存储单元所属存储串中的晶体管施加栅极偏置电压并将所述结构单元对应的第一位线接地，其中，所述结构单元包含一条字线和一条第一位线，所述字线和所述第一位线均与所述电压控制线垂直，所述每个结构单元中的多个存储串分别与所述字线和所述第一位线连接；
    通过所述待写入存储单元所属存储串对应的第二位线向所述待写入存储单元施加写入电压，并将其他所述第二位线接地；其中，所述第二位线与所述电压控制线平行，所述第二位线与所述存储串中的晶体管连接；
    通过所述待写入存储单元连接的电压控制线向所述存储单元施加偏置电压；
    根据所述写入电压和所述偏置电压，向所述待写入存储单元写入数据。
  14. 一种磁性随机存储器的数据读取方法，其特征在于，所述方法包括：
    确定待读取存储串对应的目标结构单元；其中，所述磁性随机存储器包括多个结构单元，所述多个结构单元所在的平面平行，所述多个结构单元中的每个结构单元都包括相互平行的多个存储串，所述多个存储串中的每个存储串都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构包括一条自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的一个存储单元；所述存储单元包括一个磁性隧道结，所述存储单元的一端与电压控制线连接，所述存储单元的另一端与所述SOT电极线连接，所述SOT电极线与所述电压控制线垂直；所述每个存储串中的所有SOT电极线之间通过金属导线串联连接；
    通过所述目标结构单元对应的字线，向所述待读取存储串中的晶体管施加栅极偏置电压；其中，所述每个结构单元包含一条字线和一条第一位线，所述字线和所述第一位线均与所述电压控制线垂直，所述每个结构单元中的多个存储串分别与所述字线和所述第一位线连接；
    在所述电压控制线和所述第一位线均施加读取电压；
    将所述待读取存储串中所述晶体管对应的第二位线接地，其他所述第二位线用于施加读取电压；其中所述第二位线与所述电压控制线平行，所述第二位线与所述存储串中的晶体管连接；
    根据所述读取电压或读取电流确定所述待读取存储串所对应的数据。
  15. 一种电子设备，其特征在于，包括处理器，以及与所述处理器耦合的、如权利要求1至11任一项所述的磁性随机存储器。
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