WO2023023878A1 - 一种磁性随机存储器及电子设备 - Google Patents

一种磁性随机存储器及电子设备 Download PDF

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Publication number
WO2023023878A1
WO2023023878A1 PCT/CN2021/113927 CN2021113927W WO2023023878A1 WO 2023023878 A1 WO2023023878 A1 WO 2023023878A1 CN 2021113927 W CN2021113927 W CN 2021113927W WO 2023023878 A1 WO2023023878 A1 WO 2023023878A1
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lines
bit line
unit
line
random access
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PCT/CN2021/113927
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English (en)
French (fr)
Inventor
李文静
叶力
金国栋
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华为技术有限公司
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Priority to CN202180098309.7A priority Critical patent/CN117321975A/zh
Priority to PCT/CN2021/113927 priority patent/WO2023023878A1/zh
Publication of WO2023023878A1 publication Critical patent/WO2023023878A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters

Definitions

  • the embodiments of the present application relate to the field of storage technologies, and in particular, to a magnetic random access memory and electronic equipment.
  • MRAM magnetic random Magnetic random access memory
  • the core structure of the MTJ includes a free layer, a tunneling layer, and a pinning layer; wherein, the direction of the magnetic moment of the pinning layer is fixed, and the direction of the magnetic moment of the free layer can be changed; when writing data to the MTJ, the free layer can be changed The direction of the magnetic moment (that is, the parallel arrangement or antiparallel arrangement of the magnetic moment of the MTJ free layer and the pinned layer is controlled) to write different data.
  • the data can be read by judging the high and low resistance states of the MTJ.
  • the writing method of MRAM is usually a spin transfer torque type (STT-MRAM) writing method.
  • STT-MRAM spin transfer torque type
  • the spin-orbit torque type (SOT-MRAM) writing method uses pure spin current to flip the magnetic moment of the free layer, and there is no charge flow Through the tunneling layer of MTJ, thus effectively avoiding the breakdown problem of MTJ, it has received extensive attention and research.
  • the embodiments of the present application provide a magnetic random access memory, a method for reading and writing data of the magnetic random access memory, and an electronic device, which are used to provide a new data reading and writing method of the magnetic random access memory, and to increase the storage density of the magnetic random access memory.
  • the first aspect of the embodiments of the present application provides a magnetic random access memory, including:
  • the magnetic random access memory includes a plurality of structural units and a plurality of auxiliary current lines, the planes of each structural unit are parallel to each other, and all auxiliary current lines are perpendicular to each plane; each structural unit includes sequentially stacked
  • a multi-layer storage structure in each layer of the storage structure, includes a plurality of storage units, and the storage units are all arranged on the spin-orbit torque SOT electrode lines, wherein all the SOT electrode lines are perpendicular to the plurality of auxiliary current lines , each storage unit includes a magnetic tunnel junction, one end of the storage unit is connected to one of the plurality of auxiliary current lines, and the other end is connected to the SOT electrode line.
  • each magnetic tunnel junction includes a free layer, a barrier layer and a reference layer stacked in sequence, the free layer is connected to the SOT electrode line, and the reference layer is connected to the auxiliary current line.
  • the current in the auxiliary current line can be used to provide a magnetic field for the magnetic tunnel junction, and the write current in the SOT electrode line can be used to complete the orientation reversal of the magnetic moment of the free layer and control the memory cell write input accurate data information; at the same time, because the storage array is three-dimensional (3dimensions, 3D), compared with the 2D array in the prior art, this solution can ensure the thermal stability of the storage unit through the storage unit in the vertical direction.
  • the stacking increases the areal storage density, thereby improving the storage density of the magnetic random access memory.
  • the MRAM further includes a plurality of first bit lines and a plurality of second bit lines, and both the first bit lines and the second bit lines are perpendicular to the plurality of auxiliary current lines; specifically, the first The bit line can be connected to one end of all auxiliary current lines corresponding to one layer of storage structure, and the second bit line is connected to the other end of all auxiliary current lines of one layer of storage structure.
  • the first bit line and the second bit line can be used to provide current or voltage for the auxiliary current line corresponding to the entire layer of storage structure, thereby reducing the wiring space of the bit line in the peripheral circuit plane, and through fewer bit lines Lines implement addressing and access to the multi-layer storage structure in the magnetic random access memory.
  • Each structural unit in the magnetic random access memory is composed of multiple operating units parallel to each other.
  • each operating unit includes multiple layers of memory cells stacked in sequence, and each layer includes a SOT electrode line and a set In the storage unit on the electrode line, in each operation unit, the SOT electrode lines of all layers are connected in parallel through metal wires.
  • the metal wire connects the SOT electrode lines corresponding to a memory cell of each layer in the vertical direction in parallel to form an operation unit, when writing data into the magnetic random access memory or reading data from the magnetic random access memory , the bit line can be used to simultaneously apply read and write currents to multiple SOT electrode lines corresponding to the positions in the multi-layer memory structure, thereby reducing the wiring space of the bit line in the peripheral circuit plane, and achieving magnetic randomness through fewer bit lines Addressing and accessing of multi-level storage structures in memory.
  • the current flow on a plurality of SOT electrode lines can be controlled through the third bit line and the fourth bit line
  • each structural unit in the plurality of structural units includes a third bit line and the fourth bit line, the third bit line and the fourth bit line are perpendicular to a plurality of auxiliary current lines in spatial distribution; wherein, the third bit line is used to connect and control all operating units in each structural unit through metal wires
  • the first terminal of the fourth bit line is used to connect and control the second terminal of all operating units in each structural unit through metal wires.
  • each operation unit may also include a transistor, which may be connected to one terminal of the operation unit as a control switch of the operation unit; specifically, the first terminal of the transistor and the second terminal of the operation unit One end is connected, and the other end of the transistor is connected to the third bit line.
  • the second end of the transistor corresponding to all operation units in the same structural unit is connected to the same third bit line;
  • the magnetic random access memory may also include A plurality of word lines, the plurality of word lines are parallel to the plurality of auxiliary current lines, and the gate of the transistor can be connected to one of the plurality of word lines.
  • the transistors of multiple operation units can be turned on by applying a gate bias voltage on one word line, and then by applying different voltages on the corresponding third and fourth bit lines, one operation unit can be turned on. All corresponding SOT electrode lines have read and write currents passing through them.
  • writing data and reading data can be realized in the following ways:
  • the third bit line corresponding to the structural unit to which the memory unit to be written can also be grounded, and the fourth bit line corresponding to the structural unit to which the memory unit to be written belongs can be applied Write the voltage, so as to select the operation unit where the storage unit is located, so that there is a reverse write current on the SOT electrode lines corresponding to the multiple storage units on the operation unit, and write different data.
  • the direction of the current on the SOT electrode line may not be changed, but the direction of the bias current on the auxiliary current line may be changed through the first bit line and the second bit line , and different data can also be written.
  • Each structural unit in the magnetic random access memory is composed of multiple operating units parallel to each other.
  • each operating unit includes multiple layers of memory cells stacked in sequence, and each layer includes a SOT electrode line and is arranged on the For the storage unit on the electrode line, in each operation unit, the SOT electrode lines of all layers are connected in series through metal wires.
  • the SOT electrode lines corresponding to a memory cell of each layer in the vertical direction are connected in series through metal wires to form an operation unit, so when writing data into the magnetic random access memory or reading data from the magnetic random access memory
  • the read and write current can be applied to multiple SOT electrode lines corresponding to the positions in the multi-layer memory structure through the bit line, thereby reducing the wiring space of the bit line in the peripheral circuit plane, and realizing the magnetic control through fewer bit lines. Addressing and accessing of multi-level storage structures in random access memory.
  • the magnetic random access memory also includes a plurality of fifth bit lines and sixth bit lines, and the fifth bit lines and sixth bit lines are parallel to the plurality of auxiliary current lines; wherein, each operation unit It also includes a transistor, and the drain/source of the transistor is connected to the second terminal of the operation unit; in the magnetic random access memory, the first terminals of all operation units are connected to the sixth bit line, and one terminal including the transistor is connected to the sixth bit line. A fifth bit line of the plurality of fifth bit lines is connected.
  • the presence or absence of the read and write current on the SOT electrode line in the operation unit can be controlled by applying different voltages on different fifth bit lines, thereby realizing addressing and addressing of multiple operation units in the magnetic random access memory. access.
  • the MRAM connects multiple operation units by the fifth bit line, the sixth bit line and multiple word lines; wherein, the multiple word lines are parallel to each other and perpendicular to the multiple auxiliary current lines, Gates of transistors in all operation units belonging to the same structural unit are connected to the same word line.
  • the SOT electrode lines are stacked sequentially; the series connection method is that the first end of the SOT electrode line of the memory unit on the Nth layer is connected to the SOT electrode line of the memory unit on the N+1 layer through a metal wire. The first end, the second end of the SOT electrode line of the N+1th memory cell is connected to the second end of the SOT electrode line of the N+2th memory cell.
  • the SOT electrode lines are stacked sequentially; the series connection method is that the first end of the SOT electrode line of the memory unit on the Nth layer is connected to the SOT electrode line of the memory unit on the N+1 layer through a metal wire second end.
  • writing data and reading data can be realized in the following ways:
  • the sixth bit line can also be grounded, and the write voltage can be applied to the fifth bit line corresponding to the operation unit, so as to select the operation unit where the storage unit is located, so that the multiple operation units on the operation unit There is a reverse write current on the SOT electrode lines corresponding to each memory cell, and different data are written.
  • the current direction on the SOT electrode line may not be changed, but the bias current on the auxiliary current line may be changed through the first bit line and the second bit line, It is also possible to write different data.
  • each magnetic tunnel junction includes a free layer, a barrier layer and a reference layer stacked in sequence, wherein the free layer is connected to the SOT electrode line, and the reference layer is connected to the auxiliary current line; the free layer and The magnetic moment direction of the reference layer is vertical magnetization, and the resistance value of the magnetic tunnel junction is not less than 100K ⁇ .
  • the MRAM further includes a plurality of sense amplifiers SA; the plurality of amplifiers SA are connected to the plurality of first bit lines in one-to-one correspondence, and each amplifier in the plurality of amplifiers is used to read the correspondingly connected The signal received by the first bit line.
  • the second aspect of the embodiment of the present application provides a method for writing data into a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, wherein the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the plane where each structural unit of the multiple structural units is located is parallel to the multiple
  • the auxiliary current lines are all vertical, and each structural unit includes a plurality of operating units parallel to each other, and each operating unit in the plurality of operating units includes a multi-layer storage structure stacked in sequence, and each layer of the multi-layer storage structure has a storage structure It includes a spin-orbit torque SOT electrode line perpendicular to the auxiliary current line and a storage unit arranged on the SOT electrode line; the storage unit includes a magnetic tunnel junction, and one end of the storage unit is connected to one of the plurality of auxiliary current lines. The other end of the storage unit is connected with the SOT electrode lines, and all the SOT electrode lines in each storage unit are connected in parallel through metal wires.
  • Each structural unit in the plurality of structural units includes a third bit line and a fourth bit line; the third bit line and the fourth bit line are perpendicular to a plurality of auxiliary current lines; the third bit line connects each structure through a metal wire The first terminals of all operating units in the unit, and the fourth bit line are connected and controlled by metal wires to the second terminals of all operating units in each structural unit.
  • the magnetic random access memory also includes a plurality of word lines, the word lines are parallel to a plurality of auxiliary current lines, the first end of the transistor is connected to the first end of the operation unit; the second end of the transistor corresponding to all operation units belonging to the same structural unit The terminals are connected to the same third bit line among the plurality of third bit lines.
  • the third aspect of the embodiment of the present application provides another method for writing data into a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, wherein the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the plane where each structural unit of the multiple structural units is located is parallel to the multiple
  • the auxiliary current line is vertical, and the auxiliary current line passes a bias current that generates a magnetic field when writing data to the MRAM; each structural unit includes multiple operating units parallel to each other, and each operating unit in the multiple operating units
  • Each unit includes a multilayer storage structure stacked in sequence, and each storage structure of the multilayer storage structure includes a spin-orbit torque SOT electrode line perpendicular to a plurality of auxiliary current lines and a storage unit arranged on the SOT electrode line;
  • the memory cell includes a magnetic tunnel junction, one end of the memory cell is connected to one of the plurality of auxiliary current lines, the other end of the memory cell is connected to the SOT electrode line, and all the SOT electrode lines in each memory cell pass through metal wires connected in series.
  • the magnetic random access memory also includes a plurality of fifth bit lines and sixth bit lines, and the plurality of fifth bit lines and sixth bit lines are parallel to a plurality of auxiliary current lines; the first end of each operation unit is connected to the sixth bit line; The bit line is connected, and the second end of each operation unit is connected to a fifth bit line among the plurality of fifth bit lines.
  • each structural unit in the plurality of structural units also includes a word line, and the word line is perpendicular to a plurality of auxiliary current lines; the first end of each operating unit is connected to the sixth bit line, and the second end of each operating unit The terminal is connected to the first terminal of the transistor, and the second terminal of the transistor is connected to a fifth bit line among the plurality of fifth bit lines.
  • a write voltage can be applied to the sixth bit line, and the fifth bit line corresponding to the operation unit to which the memory cell to be written is connected is grounded, so that there is an opposite voltage on the SOT electrode line of the memory cell to be written. Write current, and then write different data according to the opposite write current and bias current.
  • the fourth aspect of the embodiment of the present application provides a data reading method of a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the plane where each structural unit of the multiple structural units is located is parallel to the multiple auxiliary current lines.
  • the lines are vertical, and the auxiliary current line has a bias current that generates a magnetic field when writing data to the MRAM; each structural unit includes multiple operating units parallel to each other, and each of the multiple operating units has a Including a stacked multi-layer storage structure, each storage structure of the multi-layer storage structure includes a spin-orbit torque SOT electrode line perpendicular to the auxiliary current line and a memory cell arranged on the SOT electrode line; the memory cell includes a In the magnetic tunnel junction, one end of the storage unit is connected to one of the plurality of auxiliary current lines, the other end of the storage unit is connected to the SOT electrode line, and all the SOT electrode lines in each storage unit are connected in parallel through metal wires.
  • each structural unit in the plurality of structural units includes a third bit line and a fourth bit line, and the third bit line and the fourth bit line are perpendicular to a plurality of auxiliary current lines;
  • the third bit line connects each The first ends of all the operation units in each structural unit, the fourth bit line connects and controls the second ends of all the operation units in each structural unit through metal wires;
  • the magnetic random access memory also includes a plurality of word lines, a plurality of word lines The word lines are parallel to the plurality of auxiliary current lines.
  • the fifth aspect of the embodiment of the present application provides another method for reading data from a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the plane where each structural unit of the multiple structural units is located is parallel to the multiple auxiliary current lines.
  • the lines are vertical, and the auxiliary current line has a bias current that generates a magnetic field when writing data to the MRAM; each structural unit includes multiple operating units parallel to each other, and each of the multiple operating units has a It includes a multi-layer storage structure stacked in sequence, and each storage structure of the multi-layer storage structure includes a spin-orbit torque SOT electrode line perpendicular to a plurality of auxiliary current lines and a storage unit arranged on the SOT electrode line; the storage unit includes A magnetic tunnel junction, one end of the storage unit is connected to one of the plurality of auxiliary current lines, the other end of the storage unit is connected to the SOT electrode line, and all the SOT electrode lines in each storage unit are connected in series through metal wires;
  • the magnetic random access memory also includes a plurality of fifth bit lines and sixth bit lines, the plurality of fifth bit lines and sixth bit lines are parallel to the plurality of auxiliary current lines, each of the plurality of operation units includes a transistor, The first end of each operation unit is connected to the sixth bit line, the second end of each operation unit is connected to the first end of the transistor, and the second end of the transistor is connected to one of the fifth bit lines. bit line.
  • the sixth aspect of the embodiment of the present application provides a storage and calculation device, the storage and calculation device includes a magnetic memory and a controller. Store data and calculate data under the control of the controller.
  • the controller can call the software program stored in the magnetic random access memory to execute the corresponding method and realize the corresponding function of the storage and calculation device.
  • FIG. 1 is a structural block diagram of a magnetic random access memory provided in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of an MTJ provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a magnetic random access memory provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another magnetic random access memory provided by an embodiment of the present application.
  • Fig. 5 is a schematic diagram of the connection of an operation unit provided by the embodiment of the present application.
  • Fig. 6 is a schematic diagram of connection of another operating unit provided by the embodiment of the present application.
  • FIG. 7 is a structural block diagram of an access device provided by an embodiment of the present application.
  • Embodiments of the present application provide a magnetic random access memory and electronic equipment, which are used to write information into an MRAM by using an auxiliary current line, while increasing the storage density of the magnetic random access memory and improving the stability of a storage unit.
  • the embodiment of the present application may be applied to the magnetic random access memory shown in FIG. 1 .
  • the MRAM includes a control circuit and at least one storage circuit.
  • each memory circuit is used for writing and reading data.
  • the control circuit is used to control the process of writing and reading data in the storage circuit, for example, when writing data, select the storage unit to be written in data, apply the corresponding voltage and pass the corresponding current to achieve the selected storage unit
  • Writing data in, for another example, when reading data, select the memory cell to be read, and read data from the selected memory cell by applying a corresponding voltage and passing a corresponding current.
  • each storage circuit includes a plurality of storage units, the storage unit is the smallest unit with data storage and read-write functions in the magnetic random access memory, and can be used to store a minimum information unit, that is, 1-bit data (such as 0 or 1) , that is, a binary bit.
  • the MRAM provided by the present application utilizes the spin-orbit torque (SOT) effect when writing data, and utilizes the tunnel magneto resistance (TMR) effect when reading data.
  • SOT spin-orbit torque
  • TMR tunnel magneto resistance
  • the principle of the SOT effect is: passing a current in the electrode line will generate an upward (perpendicular magnetization) diffused spin-polarized current and enter the free layer of the MTJ.
  • the current reaches a certain value (critical switching current density)
  • critical switching current density under the action of the spin-orbit interaction torque, the magnetic moment of the free layer is flipped to realize data writing. If the direction of the current in the electrode line is changed, the polarization direction of the spin current will change, and the magnetic moment reversal direction of the free layer will also change accordingly, so that different data (0 or 1) can be written.
  • the polarity of the free layer magnetic moment reversal is uncertain, that is, writing 0 or 1 is uncertain. Therefore, while applying a write current in the SOT electrode line, and then apply a magnetic field in the direction of the write current to the MTJ, the symmetry can be broken and the deterministic reversal of the magnetic moment of the free layer can be realized; the magnetic field can not only realize the determination of the free layer It can also reduce the write current density required for free layer flipping.
  • the interlayer coupling field of the MTJ thin film can be used instead of the external magnetic field to realize the determination of the free layer.
  • the interlayer coupling is a property of magnetic materials
  • FIG. 2 shows a schematic diagram of information writing of a single MTJ device in a magnetic random access memory.
  • the structure shown in FIG. 2 exists in the storage circuit shown in FIG. 1. It can be seen from FIG. 2 that the free layer is connected to the SOT electrode line 201 , and the pinning layer of the MTJ is connected to the auxiliary current line 202 .
  • the MTJ includes a free layer, a tunneling layer and a pinning layer stacked in sequence along the vertical direction.
  • the magnetic moment direction of the pinned layer is fixed, and the magnetic moment direction of the free layer can be changed when data is written.
  • the magnetic moments of the free layer and the pinned layer are arranged in parallel or antiparallel, they correspond to different data. Used to produce the tunnel magnetoresistance effect.
  • the auxiliary current line 202 is perpendicular to the SOT electrode line 201, the auxiliary current line 202 is a common metal wire, and the SOT electrode line is a material with a large spin Hall effect. In practical applications, the SOT electrode line can be made of a heavy metal material. , or made of other materials that can generate spin currents.
  • the current I1 is passed into the auxiliary current line 202. According to the magnetic effect of the current, the current I1 will generate a magnetic field in the MTJ below, and the direction of the magnetic field is parallel to the current I2 in the SOT electrode line.
  • This magnetic field replaces the external magnetic field required by the MTJ; In this way, under the joint action of the spin-polarized electrons generated by the current I2 and the magnetic field generated by the current I1, the direction of the magnetic moment of the free layer will be reversed, and the deterministic writing of information will be completed. By changing the current direction of the current I1 or I2, the flipping direction of the free layer is changed, so that different information can be written.
  • the SOT writing method provided by the present invention can effectively avoid the loss of MTJ performance caused by the introduction of an external magnetic field, and can write certain information (0 or 1) into the MTJ.
  • the principle of the TMR effect is: when the magnetic moments of the free layer and the pinned layer of the MTJ are arranged in parallel, the MTJ is in a low resistance state; when the magnetic moments of the free layer and the pinned layer are arranged antiparallel (that is, parallel and opposite in direction), The MTJ is in a high resistance state.
  • High and low resistance represent two different data states, such as 0 or 1; different data can be read according to whether the MTJ is in a high resistance state or a low resistance state.
  • the present invention also proposes a new three-dimensional (3dimensions, 3D) MRAM array structure and corresponding operation method, which can realize the operation of the 3D MRAM array by controlling the current in the SOT electrode line and the auxiliary current line. Address selection and read and write operations.
  • FIG. 3 is a structural schematic diagram of a magnetic random access memory provided by an embodiment of the present application.
  • the magnetic random access memory includes a plurality of storage units 301, which are sequentially stacked in three-dimensional space; the magnetic random access memory includes a plurality of structural units 302 and a plurality of The auxiliary current line 303 ; the plurality of structural units 302 and the plurality of auxiliary current lines can be regarded as the storage circuit in FIG. 1 .
  • each structural unit 302 includes a plurality of operating units 304, and the plurality of operating units 304 are parallel to each other; each operating unit 304 is composed of sequentially stacked multi-layer storage structures, and each layer of storage structures includes a The spin-orbit torque SOT electrode line perpendicular to the line 304 and a storage unit 301 arranged on the SOT electrode line, the storage unit 301 includes a magnetic tunnel junction, one end of the magnetic tunnel junction is connected to the SOT electrode line of this layer, and the other end It is connected with the auxiliary current line, and all SOT electrode lines in one operation unit are connected in parallel through metal wires.
  • the auxiliary current lines 303 are in one-to-one correspondence with the memory cells 301, that is to say, each memory cell 301 has a corresponding auxiliary current line 303 for the write operation.
  • the storage unit 301 provides a magnetic field.
  • the multiple auxiliary current lines 303 are parallel to each other; the planes where the multiple structural units 302 are located are parallel to each other, and the plane where each structural unit 302 is located is perpendicular to the multiple auxiliary current lines 303 .
  • the MRAM shown in FIG. 3 shows an xyz coordinate system.
  • the auxiliary current lines 303 are arranged in parallel along the y-axis; the plane where each structural unit 302 is located is parallel to the x-axis; in each operation unit 304, the multi-layer memory structure is sequentially arranged along the z-axis direction stacked, and the SOT electrode lines corresponding to each storage structure are arranged along the x-axis, perpendicular to the auxiliary current line 303 .
  • the storage unit 301 is the smallest unit in the MRAM with data storage and read/write functions, and can be used to store a minimum information unit, that is, 1-bit data (such as 0 or 1), that is, a binary bit. Through multiple storage units 301, storage of multiple binary bit data can be realized.
  • one storage unit 301 includes one MTJ for storing one binary bit.
  • the free layer is connected to the SOT electrode lines, and the pinned layer is connected to the auxiliary current lines. That is, the free layer is close to the SOT electrode line connected to the MTJ, the pinning layer is farthest from the SOT electrode line, and the tunneling layer is located between the free layer and the reference layer.
  • the magnetic moment directions of the free layer and the pinned layer can be in the xy plane, or can be vertical On the xy plane, or at a certain oblique angle to the xy plane.
  • the magnetic moment directions of the free layer and the pinned layer there is no specific limitation on the magnetic moment directions of the free layer and the pinned layer, as long as the magnetic moment directions of the free layer and the pinned layer are arranged in parallel or antiparallel.
  • the magnetic random access memory selects a specific memory cell 301 to write or read data according to different bit lines.
  • all SOT electrode lines in each operation unit pass through The metal wires are connected in parallel. Specifically, the first ends of all SOT electrode wires are connected by a metal wire, and the second ends of all SOT electrode wires are connected by another metal wire, so that each SOT electrode wire is connected as a parallel A parallel branch of the circuit; for example, a transistor can be connected in series in each operation unit 304 to control the on and off of the operation unit 304, and the transistor can be connected to any metal wire of the operation unit 304, The metal wire can be connected to the source of the transistor, and can also be connected to the drain of the transistor, which is not specifically limited.
  • the MRAM also includes a plurality of different bit lines, and the plurality of operation units 304 are connected to the bit lines in the following manner: along the x-axis direction, in the operation unit 304, the first terminal connected with the transistor is connected to the third bit line, and the operation unit The second terminal of 304 is connected to the fourth bit line, that is, current can be supplied to all SOT electrode lines in one operation unit 304 by applying different voltages to the third bit line and the fourth bit line; the gate of the transistor is connected to the word line , the gate bias voltage can be applied to the gate of the transistor through the word line to control the turn-on and turn-off of the transistor of the operation unit 304 .
  • a plurality of auxiliary current lines 303 are parallel to the y-axis, and the memory cells 301 of one layer in a column of operation units 304 arranged in sequence along the y-axis direction are correspondingly connected to one Auxiliary current lines 303; and the first bit line 305 is connected to the first end of all auxiliary current lines 303 of an entire layer of memory structure, and the second bit line 306 is connected to the second ends of all auxiliary current lines 303 of an entire layer of memory structure , that is, during a write operation, a first bit line 305 and a second bit line 306 can provide a closed loop for the auxiliary current line 303 corresponding to a whole layer of memory cells 301, and pass a bias current to it, so that a The auxiliary current lines of the whole layer are current-passed and can generate a magnetic field.
  • a plurality of third bit lines 307 are parallel to the x-axis, wherein, the first end of the operation unit 304 in each structural unit 302 is connected to the same third bit line 307, and the first end of the operation unit 304 in each structural unit 302
  • the two terminals are connected to the same fourth bit line 308;
  • multiple word lines 309 are parallel to the y-axis, perpendicular to the plane where the structural unit 302 is located, and the transistor gates of the multiple operation units 304 arranged along the y-axis are connected to the same word line 309 , that is, when a gate bias voltage is applied through one word line 309, all transistors in the plurality of operation units 304 arranged along the y-axis will be turned on.
  • the first bit line 305 includes BL 1 , BL 2 and BL 3
  • the second bit line 306 includes SL 1 , SL 2 and SL 3
  • the third bit line 307 includes sl 1 , sl 2 and sl 3
  • the fourth bit line The lines 306 include bl 1 , bl 2 and bl 3
  • the word lines include WL 1 , WL 2 and WL 3
  • the MRAM can arrange a plurality of operation units 304 in any direction, and the number is not limited.
  • Writing of data in memory cells utilizes the SOT effect.
  • the word line applies a gate bias voltage to the transistor of the operation unit to which the memory cell to be written belongs, so that the transistor is turned on; the auxiliary current line feeds a bias current for the memory cell to be written A magnetic field is provided, and the SOT electrode line corresponding to the memory cell to be written needs to be fed with a write current to reverse the magnetic moment of the free layer to complete data writing.
  • the MTJ can have high resistance characteristics, such as the MTJ
  • the resistance value of the MTJ is not less than 100K ⁇ , so that the resistance value of the MTJ is much greater than the resistance value of the electrode wire, which can effectively prevent the write current from flowing through the MTJ and reduce the influence of the sneak path.
  • the directions of the magnetic moments of the free layer and the pinned layer are arranged in parallel or antiparallel.
  • the directions of the magnetic moments of the free layer and the pinned layer can be in the xy plane, can be perpendicular to the xy plane, or have a certain oblique angle with the xy plane.
  • there is no specific limitation on the magnetic moment directions of the free layer and the pinned layer as long as the magnetic moment directions of the free layer and the pinned layer are arranged in parallel or antiparallel.
  • the process of passing current on the SOT electrode line can be controlled by the third bit line 307 and the fourth bit line 308, the third bit line
  • the bit line 307 is connected to the first end of the transistor in the operation unit 304, which may be connected to the source of the transistor or the drain of the transistor, and the fourth bit line 308 is connected to the other end of the operation unit 304, There is no specific limit.
  • the turn-on and turn-off of the transistor is controlled by the word line 309, and the gate bias voltage is applied to the transistor on the corresponding word line 309 so that the transistor is turned on, and the third bit line 307 and the fourth bit line corresponding to the operation unit 304 Different voltages are applied to 308, that is, the target memory string can be selected to implement writing current to the SOT electrode line of the target operation unit.
  • the MRAM shown in FIG. 3 when writing data to the storage unit to be written, first determine the operation unit 302 described in the storage unit to be written, and then use the word line corresponding to the operation unit 304 to 309 applies a gate bias voltage, so that the transistors of a row of operation units arranged along the y-axis to which the operation unit belongs are turned on; optionally, the remaining word lines 503 do not apply a gate bias voltage, which is equivalent to A column of operation units 304 arranged along the y-axis corresponding to the storage units to be written is selected.
  • the write voltage can be applied through the third bit line 307 corresponding to the structural unit 302, and then the fourth bit line 308 corresponding to the structural unit 302 is grounded; Lines 308 all apply write voltages, and like this, only the SOT electrode line in the structural unit 302 where the memory cell to be written is located has a write current (x axis). Since the word line 309 only selects the memory cell to be written The operation unit (y-axis) of the column where the unit is located.
  • the operation unit 304 where the storage unit to be written is located is the only operation unit in which one end is connected to the write voltage, the other end is grounded, and the transistor is turned on.
  • the SOT electrode line has a writing current, which is equivalent to selecting the operating unit where the memory unit to be written is located.
  • a bias current can be supplied to the auxiliary current line 303 of each layer through the first bit line 305 and the second bit line 306.
  • the first bit line and the second bit line corresponding to the memory cell are written into, and a bias current is provided to the auxiliary current line through the first bit line and the second bit line, forming a closed loop.
  • Control other first bit lines and second bit lines not to generate the bias current for example, apply the same voltage to other first bit lines and second bit lines, so that the auxiliary current lines of other layers become
  • the equal pressure line, or grounding the other first bit line or the second bit line is not specifically limited.
  • the bias current is used to generate a magnetic field.
  • the magnetic field can realize the deterministic inversion of the free layer, and on the other hand, it can reduce the write current density required for the inversion of the free layer.
  • the memory cell to be written completes the writing of data through the applied writing current and bias current.
  • the writing of different data can be completed by changing the direction of the current in the SOT electrode line or changing the direction of the bias current in the auxiliary current line.
  • the third bit line 307 corresponding to the structural unit 302 can be grounded, and then a write voltage is applied to the fourth bit line 308 corresponding to the structural unit 302; and then the remaining third bit line 307 and the fourth bit line All lines 308 apply a write voltage, so that the SOT electrode line in the operation unit 304 has a reverse write current, which is equivalent to selecting the operation unit where the storage unit to be written is located; then different data can be written .
  • the direction of the writing current in the SOT electrode line is not changed, that is, the writing voltage is still applied through the third bit line 307 corresponding to the structural unit 302, and then the corresponding structural unit 302 is The fourth bit line is grounded, but the current direction in the auxiliary current line corresponding to the memory cell to be written is changed, and the current direction in the auxiliary current line is changed by controlling the first bit line and the second bit line, so that different Data writing.
  • the above-mentioned first bit line 305, second bit line 306, third bit line 307, fourth bit line 308 and word line 309 apply a voltage or pass a current
  • the process can be controlled by the level control circuit configured in the MRAM.
  • the first bit line 305, the second bit line 306, the third bit line 307, the fourth bit line 308 and the word line 309 provide the required voltage or current.
  • the process of applying a voltage on the auxiliary current line 303 can also be controlled by the level control circuit, and the level control circuit is used to provide the auxiliary current line 303 with the required voltage or current.
  • the MRAM can also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding memory cell through the word line and the bit line when writing or reading data.
  • the above-mentioned level control circuit can be based on the row address
  • the selection of the decoding circuit and the column address decoding circuit is used to determine the voltage or current that needs to be applied to the first bit line, the second bit line, the third bit line, the fourth bit line and the word line, and realize the decoding circuit of the row address and the column address
  • One or several memory cells selected by the address decoding circuit are read and written.
  • control circuit the row address decoding circuit and the column address decoding circuit may be collectively referred to as a control circuit.
  • the data stored in all storage units in a certain operation unit can be read at one time.
  • Reading of data in memory cells utilizes the TMR effect.
  • the word lines respectively apply gate bias voltages to the transistors, so that the transistors are turned on; each auxiliary current line in the plurality of auxiliary current lines is used to apply read to the correspondingly connected memory cells voltage or read current, and receive feedback information from a correspondingly connected storage unit, where the feedback information is used to indicate data stored in the correspondingly connected storage unit.
  • the feedback information of the memory cell may be information such as the current and capacitance of the memory cell, and when the read voltage applied by each auxiliary current line is the same
  • the feedback current or capacitance is different
  • the feedback information of the storage unit can be the voltage and capacitance of the storage unit, etc.
  • Information when the read current applied by each auxiliary current line is the same, when the memory cells are in different resistance states, the feedback voltage or capacitance is different.
  • the MRAM may also include a plurality of sense amplifiers respectively connected to the plurality of first bit lines in one-to-one correspondence, and each amplifier in the plurality of sense amplifiers is used to read the feedback received by the correspondingly connected auxiliary current line. information.
  • each sense amplifier and its peripheral circuits jointly form a readout loop for receiving feedback information from a storage unit corresponding to an auxiliary current line connected to the sense amplifier, thereby reading data in the storage unit.
  • each amplifier can judge whether the storage unit is in a high-resistance state or a low-resistance state by comparing the feedback information (such as voltage, current, capacitance, charge and discharge time) of the storage unit with a reference value, and then determine the The data stored in the storage unit.
  • the feedback information such as voltage, current, capacitance, charge and discharge time
  • All read voltages are applied on the four bit lines 308, thus ensuring that only the operation unit to be read can form a read loop, and a read current flows through, which is equivalent to selecting the operation unit to be read, and then all the first bit lines Both 305 and the second bit line 306 apply a read voltage, so that all auxiliary current lines become equal pressure lines, and finally judge each layer in the memory string to be read through the feedback information received by the amplifier corresponding to the first bit line one-to-one.
  • the high and low configurations corresponding to the memory cells so as to realize the readout of a whole memory string data.
  • each operation unit includes a multi-layer storage structure, which can realize 3D stacking of storage structures and increase the storage density of the MRAM.
  • the writing of the storage unit can utilize the SOT effect, that is, a bias current is applied to the auxiliary current line connected to the magnetic tunnel junction, so that the auxiliary current line generates a magnetic field, and at the same time, it is connected to the magnetic tunnel junction.
  • a current is applied to the electrode line connected by the junction, and the magnetic moment in the free layer is reversed by using the SOT effect to realize the writing of data.
  • FIG. 4 is a structural schematic diagram of another magnetic random access memory provided by the embodiment of the present application.
  • the magnetic random access memory includes a plurality of storage units 401, which are sequentially stacked in three-dimensional space; includes a plurality of structural units 402 and a plurality of auxiliary currents The line 403 ; the plurality of structural units 402 and the plurality of auxiliary current lines can be regarded as the storage circuit in FIG. 1 .
  • each structural unit 402 includes a plurality of operating units 404, and the plurality of operating units 404 are parallel to each other; each operating unit 404 is composed of multi-layer storage structures stacked in sequence, and each storage structure includes a The spin-orbit torque SOT electrode line perpendicular to the line 404 and a memory cell 401 arranged on the SOT electrode line, the memory cell 401 includes a magnetic tunnel junction, one end of the magnetic tunnel junction is connected to the SOT electrode line of this layer, and the other end It is connected with the auxiliary current line, and all SOT electrode lines in one operation unit are connected in series through metal wires.
  • the auxiliary current line 403 is in one-to-one correspondence with the storage unit 401, that is, each storage unit 401 has a corresponding auxiliary current line 403, which is used for the write operation.
  • the storage unit 401 provides a magnetic field.
  • the multiple auxiliary current lines 403 are parallel to each other; the planes where the multiple structural units 402 are located are parallel to each other, and the plane where each structural unit 402 is located is perpendicular to the multiple auxiliary current lines 403 .
  • an xyz coordinate system is shown in the MRAM shown in FIG. 4 .
  • the auxiliary current lines 403 are arranged in parallel along the x-axis; the plane where each structural unit 402 is located is perpendicular to the x-axis; in each operation unit 404, the multi-layer memory structure is sequentially arranged along the z-axis direction stacked, and the SOT electrode lines corresponding to each storage structure are arranged along the y-axis, perpendicular to the auxiliary current line 403 .
  • the storage unit 401 is the smallest unit in the MRAM with data storage and read/write functions, and can be used to store a minimum information unit, that is, 1-bit data (such as 0 or 1), that is, a binary bit. Through multiple storage units 401, storage of multiple binary bit data can be realized.
  • one storage unit 401 includes one MTJ for storing one binary bit.
  • the free layer is connected to the SOT electrode lines, and the pinned layer is connected to the auxiliary current lines. That is, the free layer is close to the SOT electrode line connected to the MTJ, the pinning layer is farthest from the SOT electrode line, and the tunneling layer is located between the free layer and the reference layer.
  • the magnetic moment directions of the free layer and the pinned layer can be in the xy plane, or can be vertical On the xy plane, or at a certain oblique angle to the xy plane.
  • the magnetic moment directions of the free layer and the pinned layer there is no specific limitation on the magnetic moment directions of the free layer and the pinned layer, as long as the magnetic moment directions of the free layer and the pinned layer are arranged in parallel or antiparallel.
  • each operation unit 404 all SOT electrode wires are connected in series through metal wires, and there may be multiple connection methods, which are not specifically limited; for example, the following two series connection methods may be included:
  • FIG. 5 it is a schematic diagram of connection of a serial operation unit 404 provided by the embodiment of the present application.
  • a plurality of memory cells 401 are stacked sequentially along the z-axis direction, and each memory cell 401 includes a magnetic tunnel junction, which is arranged on a SOT electrode line, and will be stacked sequentially when metal wires are used
  • the SOT electrode lines of the Nth layer storage structure are connected in series, the first end of the SOT electrode line of the Nth layer storage structure can be connected to the first end of the SOT electrode line of the N+1th layer storage structure, and then the N+1th layer storage structure
  • the second end of the SOT electrode line is connected to the second end of the SOT electrode line of the N+2th layer storage structure; exemplary, as shown in Figure 5, the SOT electrode line can be divided into a left end and a right end, that is, the first layer
  • the left end of the second layer is connected to the left end of the second layer, the right end of the second layer
  • FIG. 6 it is a schematic diagram of connection of another operating unit 404 provided by the embodiment of the present application.
  • multiple storage units 401 are still stacked in sequence along the z-axis direction, and the storage units 401 in the operation unit 404 can be arranged in sequence along the positive direction of the z-axis, or can be staggered from each other.
  • metal wires are used to sequentially stack SOT
  • the first end of the SOT electrode line of the Nth layer storage structure can be connected to the second end of the SOT electrode line of the N+1th layer storage structure.
  • the right end of one layer of SOT electrode lines is connected to the left end of the second layer of SOT electrode lines, and the right end of the second layer of SOT electrode lines is connected to the left end of the third layer of SOT electrode lines, which are connected end to end in sequence;
  • the current flows in the SOT electrode lines corresponding to the magnetic tunnel junctions of each layer are the same.
  • Magnetic random access memory selects a specific memory cell 401 according to different bit lines and writes or reads data.
  • the on and off of the string 404 for example, can be directly connected to the SOT electrode line corresponding to the first layer storage structure of the operation unit 404, or can be connected to the SOT electrode line corresponding to the uppermost storage structure of the operation unit 404, SOT The electrode wires may be connected to the source of the transistor, or may be connected to the drain of the transistor, which is not specifically limited.
  • the MRAM also includes a plurality of different bit lines, and the connection mode between the plurality of operation units 404 and the bit lines is as follows: along the z-axis direction, the uppermost end of the operation unit 404 is connected to a sixth bit line, and the transistor at the lower end of the operation unit 404 Connect a fifth bit line among the plurality of fifth bit lines, that is, current can be provided to all SOT electrode lines in the operation unit 404 by applying different voltages to the sixth bit line and the fifth bit line; the gate of the transistor The word line is connected, and the gate bias voltage can be applied to the gate of the transistor through the word line to control the turn-on and turn-off of the transistor of the operation unit 404 .
  • a plurality of auxiliary current lines 403 are parallel to the x-axis, and a row of operation units 404 arranged in sequence along the x-axis direction is connected to a corresponding storage unit 401 of one layer.
  • Auxiliary current lines 403; and the first bit line 405 is connected to the first end of all auxiliary current lines 403 of an entire layer of memory structure, and the second bit line 406 is connected to the second ends of all auxiliary current lines 403 of an entire layer of memory structure , that is, during a write operation, a first bit line 405 and a second bit line 406 can provide a closed loop for the auxiliary current line 403 corresponding to a whole layer of memory cells 401, and pass a bias current to it, so that a The auxiliary current lines of the whole layer are current-passed and can generate a magnetic field.
  • the plurality of fifth bit lines 407 are parallel to the auxiliary current line 403, perpendicular to the plane where the structural unit 402 is located, and the gates/drains of the transistors in a row of operation units 404 arranged in sequence along the x-axis are correspondingly connected to a second bit line 407 .
  • the magnetic random access memory also includes a sixth bit line 408 and a plurality of bit lines 409, the sixth bit line 408 connects all the ends of all operation units 404 not connected with transistors through metal wires; the plurality of word lines 409 are connected to the y-axis In parallel, the transistor gates in the operation unit 404 of each structural unit 402 are connected to the same word line 409, that is, when a gate bias voltage is applied through a word line 409, all transistors in a structural unit 402 will be turned on .
  • the first bit line 405 includes BL 1 , BL 2 and BL 3
  • the second bit line 406 includes SL 1 , SL 2 and SL 3
  • the fifth bit line 407 includes bl 1 , bl 2 and bl 3
  • the The six bit lines 408 include bl 0
  • the word lines 409 include WL 1 , WL 2 and WL 3
  • the MRAM can arrange a plurality of operation units 404 in any direction, and the number is not limited.
  • Writing of data in memory cells utilizes the SOT effect.
  • the word line applies a gate bias voltage to the transistor of the operation unit to which the memory cell to be written belongs, so that the transistor is turned on; the auxiliary current line feeds a bias current for the memory cell to be written A magnetic field is provided, and the SOT electrode line corresponding to the memory cell to be written needs to be fed with a write current to reverse the magnetic moment of the free layer to complete data writing.
  • the MTJ can have high resistance characteristics, such as the MTJ
  • the resistance value of the MTJ is not less than 100K ⁇ , so that the resistance value of the MTJ is much greater than the resistance value of the electrode wire, which can effectively prevent the write current from flowing through the MTJ and reduce the influence of the sneak path.
  • the directions of the magnetic moments of the free layer and the pinned layer are arranged in parallel or antiparallel.
  • the directions of the magnetic moments of the free layer and the pinned layer can be in the xy plane, can be perpendicular to the xy plane, or have a certain oblique angle with the xy plane.
  • there is no specific limitation on the magnetic moment directions of the free layer and the pinned layer as long as the magnetic moment directions of the free layer and the pinned layer are arranged in parallel or antiparallel.
  • the process of passing current on the SOT electrode line can be controlled by the fifth bit line 407 and the sixth bit line 408, exemplary Yes, the sixth bit line 408 is directly connected to the upper end of the operation unit 404, and the fifth bit line 407 is connected to one end of the transistor in the operation unit 404, which may be connected to the source of the transistor or the drain of the transistor Connected, not specifically limited.
  • the turn-on and turn-off of the transistor is controlled by the word line 409, and the gate bias voltage is applied to the transistor on the corresponding word line 409 to make the transistor turn on, and the fifth bit line 407 and the sixth bit line corresponding to the operation unit 404
  • Different voltages are applied to 408 , that is, the target operation unit can be selected, and the write current can be applied to the SOT electrode line of the target operation unit.
  • a write voltage can be applied through the fifth bit line 407 corresponding to the structural unit 402, and then the sixth bit line 408 is grounded; the write voltage can be applied to the remaining fifth bit lines 407,
  • the operation unit 404 where the storage unit to be written is located is the only operation unit whose one end is connected to the write voltage and the other end is grounded, that is, the SOT electrode line in the operation unit 404 has a write current, which is equivalent to selecting the storage unit to be written.
  • a bias current can be supplied to the auxiliary current line 403 of each layer through the first bit line 405 and the second bit line 406.
  • first determine the The first bit line and the second bit line corresponding to the memory cell are written into, and a bias current is provided to the auxiliary current line through the first bit line and the second bit line, forming a closed loop.
  • Control other first bit lines and second bit lines not to generate the bias current for example, apply the same voltage to other first bit lines and second bit lines, so that the auxiliary current lines of other layers become The equal pressure line, or grounding the other first bit line or the second bit line, is not specifically limited.
  • the bias current is used to generate a magnetic field.
  • the magnetic field can realize the deterministic inversion of the free layer, and on the other hand, it can reduce the write current density required for the inversion of the free layer.
  • the memory cell to be written completes the writing of data through the applied writing current and bias current.
  • the writing of different data can be completed by changing the direction of the current in the SOT electrode line or changing the direction of the bias current in the auxiliary current line.
  • a write voltage can be applied to the sixth bit line 408, then the fifth bit line 407 corresponding to the above-mentioned structural unit 402 can be grounded, and a write voltage can be applied to the rest of the fifth bit lines 407.
  • the operation unit The SOT electrode line in 404 has a reverse write current, which is equivalent to selecting the operation unit where the storage unit to be written is located; then different data can be written.
  • the direction of the writing current in the SOT electrode line is not changed, that is, the writing voltage is still applied through the fifth bit line 407 corresponding to the structural unit 402, and then the sixth bit line 408 is grounded , but change the current direction in the auxiliary current line corresponding to the memory cell to be written, and change the current direction in the auxiliary current line by controlling the first bit line and the second bit line, so that writing of different data can also be completed.
  • the SOT electrode lines in the operation unit 404 are connected in various ways, if the SOT electrode lines in the operation unit 404 are connected in series as shown in Figure 5, it can be known that when the storage string 204 is provided with a write voltage, the The flow direction of the writing current in the SOT electrode line corresponding to the unit is different, so if the same data is written in two adjacent storage units, the control methods are also different; for example, if the first storage unit needs to write data " 1”, you can choose to apply a write voltage through the fifth bit line, and connect the sixth bit line to ground. If the second-layer memory cells want to write data “1”, you can choose to apply a write voltage through the sixth bit line. Connect the fifth bit wire to ground.
  • the above-mentioned first bit line 405, the second bit line 406, the fifth bit line 407, the sixth bit line 408 and the word line 409 apply a voltage or pass a current
  • the process can be controlled by the level control circuit configured in the MRAM.
  • the first bit line 405, the second bit line 406, the fifth bit line 407, the sixth bit line 408 and the word line 409 provide the required voltage or current.
  • the process of applying a voltage on the auxiliary current line 403 can also be controlled by the level control circuit, and the level control circuit is used to provide the auxiliary current line 403 with the required voltage or current.
  • the MRAM can also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding memory cell through the word line and the bit line when writing or reading data.
  • the above-mentioned level control circuit can be based on the row address
  • the selection of the decoding circuit and the column address decoding circuit is used to determine the voltage or current that needs to be applied to the first bit line, the second bit line, the third bit line, the fourth bit line and the word line, and realize the decoding circuit of the row address and the column address
  • One or several memory cells selected by the address decoding circuit are read and written.
  • control circuit the row address decoding circuit and the column address decoding circuit may be collectively referred to as a control circuit.
  • the data stored in all storage units in a certain operation unit can be read at one time.
  • Reading of data in memory cells utilizes the TMR effect.
  • the word lines respectively apply gate bias voltages to the transistors, so that the transistors are turned on; each auxiliary current line in the plurality of auxiliary current lines is used to apply read to the correspondingly connected memory cells voltage or read current, and receive feedback information from a correspondingly connected storage unit, where the feedback information is used to indicate data stored in the correspondingly connected storage unit.
  • the feedback information of the memory cell may be information such as the current and capacitance of the memory cell, and when the read voltage applied by each auxiliary current line is the same
  • the feedback current or capacitance is different
  • the feedback information of the storage unit can be the voltage and capacitance of the storage unit, etc.
  • Information when the read current applied by each auxiliary current line is the same, when the memory cells are in different resistance states, the feedback voltage or capacitance is different.
  • the MRAM may further include a plurality of amplifiers respectively connected to the plurality of first bit lines in a one-to-one correspondence, and each amplifier in the plurality of amplifiers is used to read feedback information received by a correspondingly connected auxiliary current line.
  • each amplifier and its peripheral circuits together form a readout loop for receiving feedback information from the storage unit corresponding to the auxiliary current line connected to the amplifier, so as to read data in the storage unit.
  • each amplifier can judge whether the storage unit is in a high-resistance state or a low-resistance state by comparing the feedback information (such as voltage, current, capacitance, charge and discharge time) of the storage unit with a reference value, and then determine the The data stored in the storage unit.
  • the feedback information such as voltage, current, capacitance, charge and discharge time
  • an embodiment of the present application also provides a method for writing data into a magnetic random access memory, including:
  • the MRAM includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the multiple structural units
  • the plane where the structural unit is located is perpendicular to a plurality of auxiliary current lines, and the auxiliary current line passes a bias current that generates a magnetic field when writing data to the magnetic random access memory;
  • each structural unit includes a plurality of operating units parallel to each other,
  • Each operation unit in the plurality of operation units includes a multi-layer storage structure stacked in sequence, and each layer storage structure of the multi-layer storage structure includes a spin-orbit torque SOT electrode line perpendicular to the auxiliary current line and a SOT electrode line arranged on the SOT electrode line.
  • a storage unit on the storage unit includes a magnetic tunnel junction, one end of the storage unit is connected to an auxiliary current line in a plurality of auxiliary current lines, the other end of the storage unit is connected to the SOT electrode line, and all of the storage units in each storage unit SOT electrode wires are connected in parallel through metal wires;
  • each structure in the plurality of structural units Each unit includes a third bit line and a fourth bit line; the third bit line and the fourth bit line are perpendicular to a plurality of auxiliary current lines; the third bit line connects the first bit lines of all operating units in each structural unit through metal wires. end, the fourth bit line is used to connect and control the second end of all operating units in each structural unit through metal wires;
  • the embodiment of the present application also provides another method for writing data into a magnetic random access memory, including:
  • the MRAM includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the multiple structural units
  • the plane where each structural unit is located is perpendicular to a plurality of auxiliary current lines, and the auxiliary current lines pass a bias current that generates a magnetic field when writing data to the magnetic random access memory;
  • each structural unit includes multiple parallel operations
  • Each operation unit in the plurality of operation units includes a multi-layer storage structure stacked in sequence, and each layer storage structure of the multi-layer storage structure includes a spin-orbit torque SOT electrode line perpendicular to the auxiliary current line and arranged on the SOT A storage unit on the electrode line;
  • the storage unit includes a magnetic tunnel junction, one end of the storage unit is connected to an auxiliary current line in a plurality of auxiliary current lines, and the other end of the storage unit is connected to the SOT electrode line, in each storage unit All SOT electrode wires are connected in parallel
  • each structure in the plurality of structural units Each unit includes a third bit line and a fourth bit line; the third bit line and the fourth bit line are perpendicular to a plurality of auxiliary current lines; the third bit line connects the first bit lines of all operating units in each structural unit through metal wires. end, the fourth bit line is used to connect and control the second end of all operating units in each structural unit through metal wires;
  • the embodiment of the present application also provides another method for writing data into a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the multiple structural units
  • the plane where each structural unit is located is perpendicular to a plurality of auxiliary current lines, and the auxiliary current lines pass a bias current that generates a magnetic field when writing data to the magnetic random access memory;
  • each structural unit includes multiple parallel operations
  • Each operation unit in the plurality of operation units includes a multi-layer storage structure stacked in sequence, and each layer storage structure of the multi-layer storage structure includes a spin-orbit torque SOT electrode line perpendicular to the auxiliary current line and arranged on the SOT A storage unit on the electrode line;
  • the storage unit includes a magnetic tunnel junction, one end of the storage unit is connected to one of the auxiliary current lines, the other end of the storage unit is connected to the SOT electrode line, and all the storage units in each storage unit
  • the SOT electrode wires are connected in series through metal
  • the magnetic random access memory includes a plurality of fifth Bit lines and a sixth bit line, multiple fifth bit lines and a sixth bit line are parallel to multiple auxiliary current lines; the first end of each operation unit is connected to the sixth bit line, and each operation unit’s The second end is connected to a fifth bit line among the plurality of fifth bit lines;
  • each structural unit in the plurality of structural units also includes a word line, the word line and a plurality of auxiliary currents
  • the lines are vertical; the first end of each operation unit is connected to the sixth bit line, the second end of each operation unit is connected to the first end of the transistor, and the second end of the transistor is connected to one of the fifth bit lines fifth bit line;
  • the embodiment of the present application also provides another method for writing data into a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the multiple structural units
  • the plane where each structural unit is located is perpendicular to a plurality of auxiliary current lines, and the auxiliary current lines pass a bias current that generates a magnetic field when writing data to the magnetic random access memory;
  • each structural unit includes multiple parallel operations
  • Each operation unit in the plurality of operation units includes a multi-layer storage structure stacked in sequence, and each layer storage structure of the multi-layer storage structure includes a spin-orbit torque SOT electrode line perpendicular to a plurality of auxiliary current lines and a set A storage unit on the SOT electrode line;
  • the storage unit includes a magnetic tunnel junction, one end of the storage unit is connected to an auxiliary current line in a plurality of auxiliary current lines, and the other end of the storage unit is connected to the SOT electrode line, each storage All SOT electrode wires in
  • the magnetic random access memory includes a plurality of fifth bit lines and a sixth bit line, and a plurality of fifth bit lines
  • the fifth bit line and the sixth bit line are parallel to a plurality of auxiliary current lines; the first end of each operation unit is connected to the sixth bit line, and the second end of each operation unit is connected to one of the plurality of fifth bit lines fifth bit line;
  • each structural unit in the plurality of structural units also includes a word line, and the word line is connected with a plurality of auxiliary currents.
  • the lines are vertical; the first end of each operation unit is connected to the sixth bit line, the second end of each operation unit is connected to the first end of the transistor, and the second end of the transistor is connected to the same number of fifth bit lines. a fifth bit line;
  • the embodiment of the present application also provides a data reading method of a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and each structural unit of the multiple structural units is located The plane of the plane is perpendicular to a plurality of auxiliary current lines, and the auxiliary current lines pass a bias current that generates a magnetic field when writing data to the magnetic random access memory; each structural unit includes a plurality of operating units parallel to each other, and the plurality of operating units Each operation unit in the system includes a multilayer storage structure stacked in sequence, and each storage structure of the multilayer storage structure includes a spin-orbit torque SOT electrode line perpendicular to a plurality of auxiliary current lines and a SOT electrode line arranged on the SOT electrode line A storage unit; the storage unit includes a magnetic tunnel junction, one end of the storage unit is connected to an auxiliary current line in a plurality of auxiliary current lines, the other end of the storage unit is connected to the SOT electrode line, and all
  • a read voltage is applied to all third bit lines in the magnetic random access memory; wherein, each structural unit in the plurality of structural units includes a third bit line and a fourth bit line; the third bit line and the fourth bit line Perpendicular to multiple auxiliary current lines; the third bit line connects the first ends of all operating units in each structural unit through metal wires, and the fourth bit line is used to connect and control all operations in each structural unit through metal wires the second end of the unit;
  • the data corresponding to the operation unit to be read is determined according to the read voltage.
  • the embodiment of the present application also provides a data reading method of a magnetic random access memory, including:
  • the magnetic random access memory includes multiple structural units and multiple auxiliary current lines, the multiple auxiliary current lines are parallel, the planes where the multiple structural units are located are parallel, and the multiple structural units The plane where each structural unit is located is perpendicular to multiple auxiliary current lines, and the auxiliary current lines pass through a bias current that generates a magnetic field when writing data to the magnetic random access memory; each structural unit includes multiple operating units parallel to each other
  • Each operation unit in the plurality of operation units includes a multi-layer storage structure stacked in sequence, and each layer storage structure of the multi-layer storage structure includes a spin-orbit torque SOT electrode line perpendicular to a plurality of auxiliary current lines and arranged on A storage unit on the SOT electrode line;
  • the storage unit includes a magnetic tunnel junction, one end of the storage unit is connected to an auxiliary current line in a plurality of auxiliary current lines, and the other end of the storage unit is connected to the SOT electrode line, each storage unit All SOT electrode wires in
  • the magnetic random access memory also includes a plurality of fifth bit lines and a sixth bit line, a plurality of fifth bit lines and a sixth bit line and a plurality of auxiliary currents
  • each operation unit in the plurality of operation units includes a transistor, the first end of each operation unit is connected to the sixth bit line, the second end of each operation unit is connected to the first end of the transistor, and the transistor The second end of the second end is connected to a fifth bit line in the plurality of fifth bit lines;
  • the data corresponding to the operation unit to be read is determined according to the read voltage.
  • the computing storage device includes a controller 701 and a magnetic random access memory 702 coupled to the controller.
  • the magnetic random access memory 702 may be the magnetic random access memory shown in FIG. 3 or FIG. 4 .
  • the controller 701 can call the software program stored in the MRAM 702 to execute a corresponding method and realize a corresponding function of the electronic device.

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Abstract

一种磁性随机存储器，用于提高磁性随机存储器的存储密度；包括多个结构单元以及多条辅助电流线，其中，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面均与所有辅助电流线垂直；在多个结构单元的每个结构单元中，都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构均包括与辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的存储单元；存储单元包括磁性隧道结，其一端与多条辅助电流线中的一条辅助电流线连接，另一端与SOT电极线连接。

Description

一种磁性随机存储器及电子设备 技术领域
本申请实施例涉及存储技术领域，尤其涉及一种磁性随机存储器及电子设备。
背景技术
信息技术的发展对存储介质的容量、速度、功耗和稳定性等提出了更高要求，相比于传统的半导体存储技术，以磁性隧道结(magnetic tunnel junction，MTJ)为存储单元的磁性随机存储器(magnetic random access memory，MRAM)由于同时具有很多优异的特性如：存储数据的非易失性，读写速度快，无限次的擦写寿命，较低的读写功耗等，被认为是未来很有应用前景的一种存储技术。
MTJ的核心结构包括自由层、隧穿层和钉扎层；其中，钉扎层的磁矩方向固定，自由层的磁矩方向可以发生改变；在向MTJ写入数据时，可以通过改变自由层的磁矩方向(即控制MTJ自由层和钉扎层的磁矩平行排列或反平行排列)来写入不同的数据。从MTJ中读取数据时，可以通过判断MTJ的高低阻态来实现数据的读取。
现有技术中，MRAM的写入方式通常为自旋转移力矩型(STT-MRAM)写入方式，在该种方式中，写入电流在流经MTJ隧穿层时会有击穿MTJ的风险，导致写入单元的可靠性降低；而自旋轨道力矩型(SOT-MRAM)写入方式作为一种新的写入方式，是利用纯自旋流来翻转自由层磁矩的，没有电荷流经MTJ的隧穿层，因此有效避免了MTJ的击穿问题，受到了广泛的关注和研究。对于自由层磁矩方向垂直于衬底的MTJ(简称垂直磁化MTJ)，当采用SOT方式写入信息时，需要有一个外磁场打破对称性来实现MTJ自由层的确定性翻转，但是在半导体工艺中引入外磁场是很困难的，因此如何实现无外磁场的SOT写入以及如何设计SOT-MRAM的存储阵列方案及读写操作，成为亟需解决的问题。
发明内容
本申请实施例提供了一种磁性随机存储器、磁性随机存储器的数据读写方法及电子设备，用以提供一种新的磁性随机存储器的数据读写方式，并且提高磁性随机存储器的存储密度。
本申请实施例的第一方面提供一种磁性随机存储器，包括：
该磁性随机存储器包括多个结构单元以及多条辅助电流线，每一个结构单元所在的平面都相互平行，并且所有的辅助电流线与每一个平面都垂直；每个结构单元均包括了依次堆叠的多层存储结构，在每一层层存储结构中，包括多个存储单元，该存储单元都设置在自旋轨道力矩SOT电极线上，其中，所有的SOT电极线与多条辅助电流线都垂直，每个存储单元均包括磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，另一端与SOT电极线连接。
其中，每个磁性隧道结都包括依次堆叠的自由层、势垒层和参考层，自由层与SOT电极线连接，参考层与辅助电流线连接。
采用第一方面提供的磁性随机存储器，可以利用辅助电流线中的电流来为磁性隧道结提供磁场，并通过SOT电极线中的写入电流，完成自由层磁矩的定向翻转，控制存储单元 写入准确的数据信息；同时，由于存储阵列是三维(3dimensions，3D)的，该方案相比现有技术中的2D阵列，可以在保证存储单元的热稳定的前提下，通过垂直方向存储单元的叠加增加面存储密度，进而提高磁性随机存储器的存储密度。
在一种可能的设计中，磁性随机存储器还包括多条第一位线和多条第二位线，第一位线和第二位线都与多条辅助电流线垂直；具体的，第一位线可以连接一层存储结构对应的所有的辅助电流线的一端，第二位线来连接一层存储结构的所有的辅助电流线的另一端。
采用上述设计，可以通过第一位线和第二位线来为一整层存储结构对应的辅助电流线提供电流或者电压，从而减少位线在外围电路平面的排线空间，通过较少的位线实现对磁性随机存储器中多层存储结构的寻址和访问。
在一种可能的设计中，结构单元的内部构造可以有多种，下面以其中两种为例进行说明：
第一种
磁性随机存储器中的每个结构单元都是由相互平行的多个操作单元组成的，具体的，每个操作单元都包括依次堆叠的多层存储单元，每一层都包括一条SOT电极线和设置在该电极线上的存储单元，在每个操作单元里，所有层的SOT电极线通过金属导线并联连接。
在该磁性随机存储器中，由于金属导线将垂直方向上每一层的一个存储单元对应的SOT电极线并联连接构成一个操作单元，因而在向该磁性随机存储器中写入数据或者从读取数据时，可以通过位线实现同时在多层存储结构中位置对应的多个SOT电极线上施加读写电流，从而减少位线在外围电路平面的排线空间，通过较少的位线实现对磁性随机存储器中多层存储结构的寻址和访问。
在一种可能的设计中，可以通过第三位线和第四位线控制多个SOT电极线上的电流通入，具体的，多个结构单元中的每个结构单元均包括第三位线和第四位线，第三位线和第四位线在空间分布上与多条辅助电流线垂直；其中，第三位线用于通过金属导线连接和控制每个结构单元中的所有操作单元的第一端，第四位线用于通过金属导线连接和控制每个结构单元中的所有操作单元的第二端。
在一种可能的设计中，每一个操作单元还可以包括一个晶体管，可以将该晶体管连接在操作单元的一端，作为该操作单元的控制开关；具体的，晶体管的第一端与操作单元的第一端相连，晶体管的另一端连接在第三位线上，示例性的，同一个结构单元中的所有操作单元对应的晶体管的第二端连接同一条第三位线；磁性随机存储器还可以包括多条字线，多条字线与多条辅助电流线平行，上述晶体管的栅级可以连接多条字线中的一条字线。
采用上述设计，可以通过在一条字线上施加栅极偏置电压使得多个操作单元的晶体管导通，进而通过在对应的第三位线和第四位线上施加不同的电压使得一个操作单元对应的所有SOT电极线上有读写电流通过。
在第一种提供的磁性随机存储器中，写入数据和读取数据可以通过以下的方式实现：
在向磁性随机存储器写入数据时，先通过待写入存储单元所属的操作单元对应的字线向该操作单元中的晶体管施加栅极偏置电压；然后向待写入存储单元所属的结构单元对应的第三位线施加写入电压，再将待写入存储单元所属的结构单元对应的第四位线接地，这样，就相当于选中了存储单元所在的操作单元，使得操作单元上的多个存储单元对应的SOT 电极线都有写入电流；由于一个操作单元内，每个存储单元都在不同层，而不同层对应不同的电流辅助线，因此，通过待写入存储单元连接的电流辅助线对应的第一位线和第二位线就可以向其施加偏置电流，写入相应的数据。在向磁性随机存储器写入不同数据时，也可以将待写入存储单元所属的结构单元对应的第三位线接地，向所述待写入存储单元所属的结构单元对应的第四位线施加写入电压，从而选中存储单元所在的操作单元，使得操作单元上的多个存储单元对应的SOT电极线上都有反向写入电流，写入不同的数据。
可以理解的，在向磁性随机存储器写入不同数据时，还可以不改变SOT电极线上的电流方向，而是通过第一位线和第二位线来改变辅助电流线上偏置电流的方向，同样也可以写入不同的数据。
在上述方案中，可以通过在字线上施加不同栅极偏置电压使得仅待写入存储单元所属的操作单元中的晶体管导通。进而通过在第三位线和第四位线上施加不同的电压使得仅待写入存储单元所属的操作单元中的SOT电极线上有写电流通过。同时，通过第一位线和第二位线在待写入存储单元所连接的辅助电流线上施加偏置电流，其他辅助电流线上无偏置电流，在写电流和偏置电流的共同作用下仅待写入存储单元完成信息写入而其他存储单元信息不变。
在向磁性随机存储器读取数据时，一次性读取一个操作单元上所有存储单元的数据，首先确定待读取操作单元对应的字线，然后通过该字线对待读取操作单元中的晶体管施加栅极偏置电压，使得该操作单元的晶体管导通，然后在所有第三位线都用于施加读取电压；将待读取操作单元所属的结构单元对应的第四位线接地，同时在其他第四位线、所有的第一位线、第二位线施加读取电压，一次性读取一整个操作单元上的数据。
第二种
磁性随机存储器中的每个结构单元都是由相互平行的多个操作单元组成的，具体的，每个操作单元都包括依次堆叠的多层存储单元，每一层包括一条SOT电极线和设置在该电极线上的存储单元，在每个操作单元里，所有层的SOT电极线都通过金属导线串联连接在一起。
由于在该磁性随机存储器中，通过金属导线将垂直方向上每一层的一个存储单元对应的SOT电极线串联连接构成一个操作单元，因而在向该磁性随机存储器中写入数据或者从读取数据时，可以通过位线实现同时在多层存储结构中位置对应的多个SOT电极线上施加读写电流，从而减少位线在外围电路平面的排线空间，通过较少的位线实现对磁性随机存储器中多层存储结构的寻址和访问。
在一种可能的设计中，该磁性随机存储器中还包括多条第五位线和第六位线，第五位线和第六位线与多条辅助电流线平行；其中，每一个操作单元还包括一个晶体管，晶体管的漏极/源极与该操作单元的第二端连接；在磁性随机存储器中，所有操作单元的第一端均与第六位线连接，而包括有晶体管的一端与多条第五位线中的一条第五位线连接。
采用上述设计，可以通过在不同的第五位线上施加不同的电压来控制操作单元中SOT电极线上的读写电流的有无，进而实现对磁性随机存储器中多个操作单元的寻址和访问。
在一种可能的设计中，磁性随机存储器靠第五位线、第六位线和多条字线来连接多个操作单元；其中，多条字线相互平行并且与多条辅助电流线垂直，属于同一结构单元的所 有操作单元的所有操作单元中的晶体管的栅级连接同一条字线。
在一种可能的设计中，对每一个操作单元的所有SOT电极线进行串联的连接方式可以有多种，下面以其中两种为例进行说明：
(一)在每个操作单元中，SOT电极线依次堆叠；其串联方式为，第N层存储单元的SOT电极线的第一端通过金属导线连接第N+1层存储单元的SOT电极线的第一端，第N+1层存储单元的SOT电极线的第二端连接第N+2层存储单元的SOT电极线的第二端。
(二)在每个操作单元中，SOT电极线依次堆叠；其串联方式为，第N层存储单元的SOT电极线的第一端通过金属导线连接第N+1层存储单元的SOT电极线的第二端。
在第二种设计提供的磁性随机存储器中，写入数据和读取数据可以通过以下的方式实现：
在向磁性随机存储器写入数据时，先通过待写入存储单元所属的结构单元对应的字线向该待写入存储单元所属的操作单元中的晶体管施加栅极偏置电压；然后向第六位线施加写入电压，将该操作单元对应的第五位线接地，这样，就相当于选中了存储单元所在的操作单元，使得操作单元上的多个存储单元对应的SOT电极线都有写入电流；由于一个操作单元内，每个存储单元都在不同层，而不同层对应不同的辅助电流线，因此，通过待写入存储单元连接的辅助电流线对应的第一位线和第二位线向辅助电流线施加偏置电流，就可以写入相应的数据。在向磁性随机存储器写入不同数据时，也可以将第六位线接地，向该操作单元对应的第五位线施加写入电压，从而选中存储单元所在的操作单元，使得操作单元上的多个存储单元对应的SOT电极线上都有反向写入电流，写入不同的数据。
可以理解的，在向磁性随机存储器写入不同数据时，还可以不改变SOT电极线上的电流方向，而是通过第一位线和第二位线来改变辅助电流线上的偏置电流，同样也可以写入不同的数据。
在上述方案中，可以通过在字线上施加不同栅极偏置电压使得仅待写入存储单元所属的操作单元中的晶体管导通。进而通过在第五位线和第六位线上施加不同的电压使得仅待写入存储单元所属的操作单元中的SOT电极线上有写电流通过。同时，通过第一位线和第二位线在待写入存储单元所连接的辅助电流线上施加偏置电流，其他辅助电流线上无偏置电流，在写电流和偏置电流的共同作用下仅待写入存储单元完成信息写入而其他存储单元信息不变。
在向磁性随机存储器读取数据时，一次性读取一个操作单元上所有存储单元的数据，首先确定待读取操作单元所属的结构单元对应的字线，然后通过该字线对待读取操作单元中的晶体管施加栅极偏置电压，使得该操作单元的晶体管导通，然后在第六位线上施加读取电压，将该待读取操作单元对应的第五位线接地，同时在其他第五位线、所有的第一位线、第二位线施加读取电压，一次性读取一整个操作单元上的数据。
在一种可能的设计中，每个所述磁性隧道结包括依次堆叠的自由层、势垒层和参考层，其中，自由层与SOT电极线连接，参考层与辅助电流线连接；自由层和参考层磁矩方向为垂直磁化，磁性隧道结的电阻值不小于100KΩ。
在一种可能的设计中，磁性随机存储器还包括多个灵敏放大器SA；多个放大器SA与多条第一位线一一对应连接，多个放大器中的每个放大器用于读取对应连接的第一位线所 接收的信号。
本申请实施例第二方面提供了一种磁性随机存储器的数据写入方法，包括：
磁性随机存储器包括多个结构单元以及多条辅助电流线，其中，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线均垂直，每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于该SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线并联连接。
多个结构单元中的每个结构单元均包括第三位线和第四位线；第三位线和第四位线与多条辅助电流线垂直；第三位线通过金属导线连接每个结构单元中的所有操作单元的第一端，第四位线通过金属导线连接和控制每个结构单元中的所有操作单元的第二端。
磁性随机存储器还包括多条字线，字线与多条辅助电流线平行，晶体管的第一端与操作单元的第一端相连；属于同一个结构单元中的所有操作单元对应的晶体管的第二端连接多条第三位线中的同一条第三位线。
在向磁性随机存储器写入数据时，先确定待写入存储单元所属的操作单元，然后通过该操作单元对应的字线向待写入存储单元对应的晶体管施加栅极偏置电压；然后通过互通第一位线和第二位线向待写入存储单元连接的辅助电流线施加偏置电流；然后向待写入存储单元所属的结构单元对应的第三位线施加写入电压并将待写入存储单元所属的结构单元对应的第四位线接地，保证待写入存储单元的SOT电极线上有写入电流且待写入存储单元的辅助电流线上有偏置电流，然后根据写入电流和偏置电流，向待写入存储单元写入数据。
在写入不同数据时，就可以将待写入存储单元所属的结构单元对应的第三位线接地并向待写入存储单元所属的结构单元对应的第四位线施加写入电压，使得待写入存储单元对应的SOT电极线上有相反的写入电流，然后根据相反的写入电流和偏置电流完成不同数据的写入。
本申请实施例第三方面提供了另一种磁性随机存储器的数据写入方法，包括：
磁性随机存储器包括多个结构单元以及多条辅助电流线，其中，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与多条辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于该SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线串联连接。
其中，磁性随机存储器还包括多条第五位线和第六位线，多条第五位线和第六位线与多条辅助电流线平行；每个操作单元的第一端均与第六位线连接，每个操作单元的第二端连接多条第五位线中的一条第五位线。
其中，多个结构单元中的每个结构单元还包括字线，字线与多条辅助电流线垂直；每个操作单元的第一端均与第六位线连接，每个操作单元的第二端与晶体管的第一端相连，晶体管的第二端连接多条第五位线中的一条第五位线。
在向该磁性随机存储器写入数据时，先确定待写入存储单元所属的操作单元，然后通过该操作单元所属结构单元对应的字线向待写入存储单元所属操作单元中的晶体管施加栅极偏置电压；然后向待写入存储单元所属操作单元对应的第五位线施加写入电压并将其他第五位线和第六位线接地，保证待写入存储单元的SOT电极线上有写入电流且待写入存储单元的辅助电流线上有偏置电流，然后根据写入电流和偏置电流，向待写入存储单元写入数据。
在写入不同数据时，可以向第六位线施加写入电压，并将待写入存储单元所属操作单元对应的第五位线接地，使得待写入存储单元的SOT电极线上有相反的写入电流，然后根据相反的写入电流和偏置电流完成不同数据的写入。
本申请实施例第四方面提供了一种磁性随机存储器的数据读取方法，包括：
磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于该SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线并联连接。
其中，多个结构单元中的每个结构单元均包括第三位线和第四位线，第三位线和第四位线与多条辅助电流线垂直；第三位线通过金属导线连接每个结构单元中所有操作单元的第一端，第四位线通过金属导线连接和控制每个结构单元中的所有操作单元的第二端；其中，磁性随机存储器还包括多条字线，多条字线与多条辅助电流线平行。
在向该磁性随机存储器读取数据时，先确定待读取操作单元，然后通过该操作单元对应字线向待读取操作单元的晶体管施加栅极偏置电压；然后向所有第三位线都施加读取电压；向待读取操作单元所属的结构单元对应的第四位线接地，保证待写入操作单元有读取电流，最后，在所有辅助电流线上施加读取电压，然后根据读取电压，读取待读取操作单元中存储的数据。
本申请实施例第五方面提供了另一种磁性随机存储器的数据读取方法，包括：
磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与多条辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT 电极线连接，每个存储单元中的所有SOT电极线通过金属导线串联连接；
磁性随机存储器还包括多条第五位线和第六位线，多条第五位线和第六位线与多条辅助电流线平行，多个操作单元中的每个操作单元均包括晶体管，每个操作单元的第一端均与第六位线连接，每个操作单元的第二端与晶体管的第一端相连，该晶体管的第二端连接多条第五位线中的一条第五位线。
在向该磁性随机存储器读取数据时，先确定待读取操作单元，然后通过该待读取操作单元所属的结构单元对应的字线向待读取操作单元的晶体管施加栅极偏置电压；然后向第六位线施加读取电压；将待读取操作单元连接的第五位线接地并向其他第五位线施加读取电压，保证待读取操作单元有读取电流，最后，在所有辅助电流线上施加读取电压，然后根据读取电压，读取待读取操作单元中的数据。
本申请实施例第六方面提供一种存算装置，该存算装置包括磁性存储器以及控制器，该磁性随机存储器如第一方面及其任一可能的设计中提供的磁性随机存储器，磁性存储器在控制器的控制下存储数据和计算数据。
具体地，控制器可以调用磁性随机存储器中存储的软件程序，以执行相应的方法，实现存算装置的相应功能。
附图说明
图1为本申请实施例中提供的一种磁性随机存储器的结构框图；
图2为本申请实施例提供的一种MTJ的结构示意图；
图3为本申请实施例提供的一种磁性随机存储器的结构示意图；
图4为本申请实施例提供的另一种磁性随机存储器的结构示意图；
图5为本申请实施例提供的一种操作单元的连接示意图；
图6为本申请实施例提供的另一种操作单元的连接示意图；
图7为本申请实施例提供的一种存取装置的结构框图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
本申请实施例提供一种磁性随机存储器及电子设备，用于利用辅助电流线为MRAM写入信息，同时提高磁性随机存储器的存储密度、提升存储单元的稳定性。
下面，对本申请实施例的应用场景加以简单介绍。
本申请实施例可以应用于图1所示的磁性随机存储器。该磁性随机存储器包括控制电路以及至少一个存储电路。
具体地，每个存储电路用于写入和读取数据。控制电路用于对存储电路写入和读取数据的过程进行控制，比如，在写入数据时选择要写入数据的存储单元、通过施加相应电压和通入相应电流以实现在选择的存储单元中写入数据，再比如，在读取数据时选择要读取的存储单元，通过施加相应电压和通入相应电流以实现从选择的存储单元中读取数据。
其中，每个存储电路中包括多个存储单元，存储单元是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。
下面将结合附图对本申请实施例作进一步地详细描述。
需要说明的是，本申请中所涉及的多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
一、下面对本申请提供的随机存储器的读写原理进行介绍：
本申请提供的磁性随机存储器在写入数据时利用了自旋轨道力矩(spin-orbit torque，SOT)效应，在读取数据时利用了隧穿磁电阻(tunnel magneto resistance，TMR)效应。
(一)MTJ写入数据：
SOT效应的原理是：在电极线中通入电流，将会产生向上(垂直磁化)扩散的自旋极化电流，进入MTJ的自由层中。当电流达到一定值(临界翻转电流密度)时，在自旋轨道相互作用力矩作用下，自由层的磁矩发生翻转，实现数据的写入。如果改变电极线中电流的方向，自旋流的极化方向会发生改变，自由层的磁矩翻转方向也相应改变，这样就可以写入不同数据(0或1)。
然而，该种写入方式中，自由层磁矩翻转的极性是不确定的，即写入0或1是不确定。因此，在SOT电极线中施加写电流的同时，再为MTJ施加一个写电流方向上的磁场，就可以打破对称性，实现自由层磁矩的确定性翻转；该磁场不仅可以实现自由层的确定性翻转，还可以降低自由层翻转所需的写电流密度。通过改变磁场或写电流的方向，自由层磁矩翻转的极性发生改变，写入不同的信息；但是，引入外加磁场在技术难度上比较高，并且磁场难以高密度集成；由于磁性多层材料的层与层之间存在耦合作用，相邻磁性层之间一般有两种耦合，铁磁性耦合和反铁磁性耦，因此可以利用MTJ薄膜的层间耦合场替代外加磁场，实现自由层的确定性翻转，但由于层间耦合为磁性材料的属性，要利用层间耦合场来提供稳定的磁场，往往需要优化存储单元MTJ的结构，通常伴随着牺牲掉MTJ的一部分性能的代价，例如TMR变小或热稳定性变差等，因此，亟需一种更优的方法来实现MTJ信息的确定性写入。
有鉴于此，本申请提出了一种新的无外磁场的SOT写入方法，即利用两条垂直的电流来实现MTJ自由层的磁矩的确定性翻转。示例性地，图2示出了磁性随机存储器中的单个MTJ器件的信息写入示意图，图2所示结构存在于图1所示的存储电路中，从图2中可以看出，MTJ的自由层与SOT电极线201连接，MTJ的钉扎层与辅助电流线202连接。
应理解，MTJ包括沿竖直方向依次堆叠的自由层、隧穿层和钉扎层。其中，钉扎层的磁矩方向固定，自由层的磁矩方向可以在数据写入时发生改变，自由层与钉扎层的磁矩呈平行或反平行排列时对应不同的数据，隧穿层用于产生隧道磁电阻效应。
其中，辅助电流线202与SOT电极线201垂直，辅助电流线202为通常的金属导线，SOT电极线是具有较大自旋霍尔效应的材料，实际应用中，SOT电极线可以由重金属材料制成，或者由其他可以产生自旋流的材料制成。在辅助电流线202中通入电流I1，根据电流的磁效应，电流I1会在下方的MTJ中产生磁场，磁场方向与SOT电极线中电流I2平行，该磁场即代替MTJ所需的外来磁场；这样，在电流I2产生的自旋极化电子和电流I1产生的磁场共同作用下自由层磁矩方向就会发生定向翻转，完成信息的确定性写入。改变电流 I1或I2的电流方向，自由层翻转的方向发生改变，这样就可以不同的信息的写入。
本发明提供的SOT写入方法，可以有效的避免了引入外来磁场对MTJ性能造成的损失，并且可以为MTJ写入确定信息(0或1)。
(二)MTJ读取数据：
TMR效应的原理是：当MTJ的自由层和钉扎层的磁矩平行排列时，MTJ为低电阻态；当自由层和钉扎层的磁矩反平行排列(即平行且方向相反)时，MTJ为高电阻态。高低电阻代表了两种不同的数据状态，例如0或1；根据MTJ为高阻态或低阻态可以读取出不同的数据。
也就是说，在从MTJ读取数据时，需要为MTJ提供回路，测量MTJ的阻值，这样就可以根据MTJ的阻值来确定其所表示的数据，完成数据的读取。
基于上述读写原理，本发明还提出了一种新的三维(3dimensions，3D)MRAM阵列结构及相应的操作方法，可以通过控制SOT电极线和辅助电流线中的电流，来实现3D MRAM阵列的选址和读写操作。
二、图3为本申请实施例提供的一种磁性随机存储器的结构示意图，该磁性随机存储器包括多个存储单元301，在三维空间内依次堆叠；磁性随机存储器包括多个结构单元302以及多条辅助电流线303；多个结构单元302以及多条辅助电流线可以视为图1中的存储电路。
其中，每一个结构单元302中包括多个操作单元304，多个操作单元304相互平行；每一个操作单元304都是由依次堆叠的多层存储结构构成的，每层存储结构包括一条与辅助电流线304垂直的自旋轨道力矩SOT电极线以及设置在SOT电极线上的一个存储单元301，该存储单元301包括一个磁性隧道结，磁性隧道结的一端与该层的SOT电极线连接，另一端与辅助电流线相连，一个操作单元中所有SOT电极线之间通过金属导线并联连接。
在磁性随机存储器中，辅助电流线303与存储单元301是一一对应的，也就是说，每个存储单元301均有与之对应的一个辅助电流线303，用于在写操作时，为该存储单元301提供磁场。
可选地，多个辅助电流线303相互平行；多个结构单元302所在的平面相互平行，且每个结构单元302所在的平面与多个辅助电流线303垂直。
需要说明的是，本申请实施例中，多个辅助电流线303平行的概念并不是严格意义上的平行，在磁性随机存储器的制备过程中，由于制备工艺和制备设备的影响，可能存在多个辅助电流线303并非严格平行的情况，这种情况是由于具体制备流程导致的，并不能说明多个辅助电流线303不严格平行的情况超脱本申请的保护范围。此外，对于平面平行和垂直这两种位置关系也有类似理解，此处不再赘述。
为了方便描述，图3所示的磁性随机存储器中示出了xyz坐标系。其中，在磁性随机存储器中，辅助电流线303沿y轴平行排列；每个结构单元302所在的平面均与x轴平行；在每个操作单元304中，多层存储结构沿着z轴方向依次堆叠，且每层存储结构对应的SOT电极线沿x轴排列，与辅助电流线303垂直。
应理解，存储单元301是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。通过 多个存储单元301，可以实现多个二进制位数据的存储。具体地，本申请实施例中，一个存储单元301中包括一个MTJ，用于存储一个二进制位。具体地，本申请中，自由层与SOT电极线连接，钉扎层与辅助电流线连接。即自由层靠近与MTJ连接的SOT电极线，钉扎层与该SOT电极线距离最远，隧穿层位于自由层和参考层之间。
具体地，本申请实施例中，对于自由层和钉扎层的磁矩方向平行排列或反平行排列，可以有如下理解：自由层和钉扎层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和钉扎层的磁矩方向不做具体限定，只要自由层和钉扎层的磁矩方向平行排列或反平行排列即可。
下面将根据图3所示的结构框架，来介绍如何对存储单元301进行控制以及如何向存储单元301写入数据或者读取存储单元301存储的数据。
磁性随机存储器是根据不同的位线来选择特定的存储单元301写入或者读取数据的，在图3所示的结构示意图中，示例性的，每一个操作单元中所有SOT电极线之间通过金属导线并联连接，具体的，所有SOT电极线的第一端通过一根金属导线相连接，所有SOT电极线的第二端通过另一根金属导线相连接，使得每个SOT电极线均作为并联电路的并联支路；示例性的，每一个操作单元304中还可以串联一个晶体管，用于控制操作单元304的导通和关断，晶体管可以与操作单元304的任意一根金属导线进行连接，该金属导线既可以连接晶体管的源极，也可以连接晶体管的漏极，具体不做限定。
磁性随机存储器还包括多条不同的位线，多个操作单元304与位线的连接方式为：沿x轴方向，操作单元304中，连接有晶体管的第一端连接第三位线，操作单元304的第二端连接第四位线，即可以通过向第三位线和第四位线施加不同的电压来向一个操作单元304中的所有SOT电极线提供电流；晶体管的栅级连接字线，通过字线可以向晶体管的栅级施加栅极偏置电压，控制操作单元304的晶体管的导通和关断。
示例性的，如图3所示，在磁性随机存储器中，多条辅助电流线303与y轴平行，沿着y轴方向依次排列的一列操作单元304中的一层的存储单元301对应连接一条辅助电流线303；而第一位线305连接一整层存储结构的所有辅助电流线303的第一端，第二位线306则连接一整层存储结构的所有辅助电流线303的第二端，即当写入操作时，一条第一位线305和一条第二位线306可以为一整层的存储单元301对应的辅助电流线303提供闭合回路，向其通入偏置电流，使得一整层的辅助电流线中都通有电流且都能产生磁场。
而多条第三位线307与x轴平行，其中，每一个结构单元302中的操作单元304的第一端连接同一条第三位线307，每一个结构单元302中的操作单元304的第二端连接同一条第四位线308；多条字线309与y轴平行，与结构单元302所在的平面垂直，沿y轴排列的多个操作单元304的晶体管栅级连接同一条字线309，即当通过一条字线309施加栅极偏置电压时，沿y轴排列的多个操作单元304内的所有晶体管都将导通。
此外，需要说明的是，在图3所示的磁性随机存储器中，为了示意简便，仅示出了x轴方向依次排列的三个操作单元304和y轴方向依次排列的三个操作单元304，因此，第一位线305包括BL 1、BL 2和BL 3，第二位线306包括SL 1、SL 2和SL 3；第三位线307包括sl 1、sl 2和sl 3，第四位线306包括bl 1、bl 2和bl 3，字线包括WL 1、WL 2和WL 3；磁性随机存储器可以沿任意方向排列多个操作单元304，对数量不进行限定。
(一)磁性随机存储器的数据写入：
在从磁性随机存储器写入数据时，需要根据待写入单元的位置，逐个选中存储单元，然后进行数据写入。
存储单元中数据的写入利用SOT效应。在从磁性随机存储器写入数据时，字线向待写入存储单元所属的操作单元的晶体管施加栅极偏置电压，使得晶体管导通；辅助电流线通入偏置电流为待写入存储单元提供磁场，待写入存储单元对应的SOT电极线需要通入写入电流使得自由层磁矩进行翻转，完成数据写入。
为了避免在写入数据时，电极线上的电流流经MTJ，形成潜行通路(sneak path)，对写入数据的准确性产生影响，本申请实施例中，MTJ可以具有高电阻特性，例如MTJ的电阻值不低于100KΩ，使得MTJ的电阻值远大于电极线的电阻值，这样可以有效避免写入电流流经MTJ，降低sneak path的影响。
此外，在图3所示的磁性随机存储器中，自由层和钉扎层的磁矩方向平行排列或反平行排列。具体地，自由层和钉扎层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和钉扎层的磁矩方向不做具体限定，只要自由层和钉扎层的磁矩方向平行排列或反平行排列即可。
基于如前所述的磁性随机存储器的结构框架，当向存储单元301写入数据时，在SOT电极线上通入电流的过程可以由第三位线307和第四位线308控制，第三位线307与操作单元304中的晶体管的第一端相连，其可以是与晶体管的源极相连，也可以与晶体管的漏极相连，第四位线308则与操作单元304的另一端相连，具体不做限定。晶体管的导通和关断由字线309控制，在对应的字线309上向晶体管施加栅极偏置电压使得晶体管导通，并且在操作单元304对应的第三位线307和第四位线308上施加不同的电压，即可以选中目标存储串，实现向目标操作单元的SOT电极线上施加写电流。
具体的，在图3所示的磁性随机存储器中，在向待写入存储单元写入数据时，先确定待写入存储单元所述的操作单元302，然后通过该操作单元304对应的字线309施加栅极偏置电压，这样，会使得该操作单元所属的沿y轴排列的一列操作单元的晶体管导通；可选的，剩余的字线503不施加栅极偏置电压，这样相当于选中了待写入存储单元所对应的沿y轴排列的一列操作单元304。
然后，需要确定待写入存储单元所属的结构单元302，确定该结构单元302对应的第三位线307和第四位线308。在一种方式中，可以通过该结构单元302对应的第三位线307施加写入电压，然后该结构单元302对应的第四位线308接地；向其余的第三位线307和第四位线308都施加写入电压，这样，只有待写入存储单元所在的结构单元302中的SOT电极线上才通有写入电流(x轴)，由于字线309又只选中了待写入存储单元所在列的操作单元(y轴),这样，待写入存储单元所在的操作单元304为唯一的一端接写入电压，另一端接地，且晶体管导通的操作单元，即使得该存储304中的SOT电极线有了写入电流，相当于选中了待写入存储单元所在的操作单元。
当选中待写入存储单元所在的操作单元204后，可以通过第一位线305和第二位线306来为每一层的辅助电流线303通入偏置电流，可选的，先确定待写入存储单元对应的第一位线和第二位线，通过第一位线和第二位线为辅助电流线提供偏置电流，形成闭合回路。 控制其他的第一位线和第二位线不产生该偏置电流，示例性的，给其他的第一位线和第二位线都施加相同的电压，使得其他层的辅助电流线变成等压线，又或者将其他第一位线或第二位线都接地，具体不做限制。
其中，偏置电流用于产生磁场，该磁场一方面可以实现自由层的确定性翻转，另一方面可以降低自由层翻转所需的写电流密度。待写入存储单元通过施加的写入电流和偏置电流，完成数据的写入。
可以理解的，可以通过改变SOT电极线中电流的方向或者改变辅助电流线中偏置电流的方向，来完成不同数据的写入。示例性的，可以将上述结构单元302对应的第三位线307接地，然后向该结构单元302对应的第四位线308施加写入电压；然后向其余的第三位线307和第四位线308都施加写入电压，这样，该操作单元304中的SOT电极线有了反向写入电流，也相当于选中了待写入存储单元所在的操作单元；然后就可以写入不同的数据。
示例性的，在写入相反数据时，不改变SOT电极线内的写入电流的方向，即仍然通过上述结构单元302对应的第三位线307施加写入电压，然后将该结构单元302对应的第四位线接地，而是改变待写入存储单元对应的辅助电流线中的电流方向，通过控制第一位线和第二位线改变辅助电流线中的电流方向，这样也可以完成不同数据的写入。
实际应用中，在向磁性随机存储器写入数据时，上述在第一位线305、第二位线306、第三位线307、第四位线308以及字线309施加电压或通入电流的过程可以由磁性随机存储器中配置的电平控制电路进行控制第一位线305、第二位线306、第三位线307、第四位线308以及字线309提供所需的电压或电流。同样地，在从磁性随机存储器读取数据时，辅助电流线303上施加电压的过程也可以由该电平控制电路控制，该电平控制电路用于为辅助电流线303提供所需的电压或电流。
此外，磁性随机存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线和位线选择对应的存储单元，上述电平控制电路可以根据行地址解码电路和列地址解码电路的选择来判断需要在第一位线、第二位线、第三位线、第四位线和字线上施加的电压或电流，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元进行读写操作。
其中，电平控制电路、行地址解码电路和列地址解码电路可以统称为控制电路。
(二)磁性随机存储器的数据读取：
在从磁性随机存储器读取数据时，可以一次性读取某个操作单元中所有存储单元存储的数据。
存储单元中数据的读取利用TMR效应。在从磁性随机存储器读取数据时，字线分别向晶体管施加栅极偏置电压，使得晶体管导通；多个辅助电流线中的每个辅助电流线用于向对应连接的存储单元施加读取电压或读取电流，以及接收对应连接的存储单元的反馈信息，该反馈信息用于指示对应连接的存储单元中存储的数据。
其中，每个辅助电流线向对应连接的存储单元施加读取电压时，存储单元的反馈信息可以是存储单元的电流、电容量等信息，在每个辅助电流线施加的读取电压相同的情况下，存储单元处于不同阻态时，反馈的电流或电容量不同；每个辅助电流线向对应连接的存储单元施加读取电流时，存储单元的反馈信息可以是存储单元的电压、电容量等信息，在每 个辅助电流线施加的读取电流相同的情况下，存储单元处于不同阻态时，反馈的电压或电容量不同。
此外，磁性随机存储器中还可以包括分别与多个第一位线一一对应连接的多个灵敏放大器，多个灵敏放大器中的每个放大器用于读取对应连接的辅助电流线所接收的反馈信息。
其中，每个灵敏放大器及其外围电路等共同组成读出回路，用于接收灵敏放大器所连接的辅助电流线对应的存储单元的反馈信息，从而读取存储单元中的数据。
具体地，每个放大器可以通过将存储单元的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元处于高阻态还是低阻态，进而确定该存储单元中存储的数据。
在向所述磁性随机存储器读取数据时，一次性读取一个操作单元304上所有存储单元301的数据；一种示例为：首先需要确定待读取操作单元所对应的字线303，然后通过该字线303对待读取存储串中的晶体管施加栅极偏置电压，使得该待读取操作单元的晶体管导通，这样相当于选中了该待读取操作单元所在的一列操作单元(y轴)。在待读取操作单元所在的结构单元302对应的第三位线307上施加读取电压，该结构单元302对应的第四位线308接地，同时还需要将其余的第三位线307和第四位线308上全部施加读取电压，这样就保证只有待读取操作单元能形成读出回路，有读电流流过，相当于选中了该待读取操作单元，接着所有的第一位线305和第二位线306都施加读取电压，使得所有辅助电流线变为等压线，最后通过与第一位线一一对应的放大器接收的反馈信息来判断待读取存储串中各层存储单元对应的高低组态，从而实现一整个存储串数据的读出。
采用本申请实施例提供的磁性随机存储器，每个操作单元包括多层存储结构，可以实现存储结构的3D堆叠，提高磁性随机存储器的存储密度。采用本申请实施例提供的磁性随机存储器，存储单元的写入可以利用SOT效应，即在与磁性隧道结连接的辅助电流线上施加偏置电流，使得辅助电流线产生磁场，同时在与磁性隧道结连接的电极线上通入电流，利用SOT效应使得自由层中的磁矩发生翻转，实现数据的写入。
三、图4为本申请实施例提供的另一种磁性随机存储器的结构示意图，该磁性随机存储器包括多个存储单元401，在三维空间内依次堆叠；包括多个结构单元402以及多条辅助电流线403；多个结构单元402以及多条辅助电流线可以视为图1中的存储电路。
其中，每一个结构单元402中包括多个操作单元404，多个操作单元404相互平行；每一个操作单元404都是由依次堆叠的多层存储结构构成的，每层存储结构包括一条与辅助电流线404垂直的自旋轨道力矩SOT电极线以及设置在SOT电极线上的一个存储单元401，该存储单元401包括一个磁性隧道结，磁性隧道结的一端与该层的SOT电极线连接，另一端与辅助电流线相连，一个操作单元中所有SOT电极线之间通过金属导线串联连接。
在磁性随机存储器中，辅助电流线403与存储单元401是一一对应的，也就是说，每个存储单元401均有与之对应的一个辅助电流线403，用于在写操作时，为该存储单元401提供磁场。
可选地，多个辅助电流线403相互平行；多个结构单元402所在的平面相互平行，且每个结构单元402所在的平面与多个辅助电流线403垂直。
需要说明的是，本申请实施例中，多个辅助电流线403平行的概念并不是严格意义上 的平行，在磁性随机存储器的制备过程中，由于制备工艺和制备设备的影响，可能存在多个辅助电流线403并非严格平行的情况，这种情况是由于具体制备流程导致的，并不能说明多个辅助电流线403不严格平行的情况超脱本申请的保护范围。此外，对于平面平行和垂直这两种位置关系也有类似理解，此处不再赘述。
为了方便描述，图4所示的磁性随机存储器中示出了xyz坐标系。其中，在磁性随机存储器中，辅助电流线403沿x轴平行排列；每个结构单元402所在的平面均与x轴垂直；在每个操作单元404中，多层存储结构沿着z轴方向依次堆叠，且每层存储结构对应的SOT电极线沿y轴排列，与辅助电流线403垂直。
应理解，存储单元401是磁性随机存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。通过多个存储单元401，可以实现多个二进制位数据的存储。具体地，本申请实施例中，一个存储单元401中包括一个MTJ，用于存储一个二进制位。具体地，本申请中，自由层与SOT电极线连接，钉扎层与辅助电流线连接。即自由层靠近与MTJ连接的SOT电极线，钉扎层与该SOT电极线距离最远，隧穿层位于自由层和参考层之间。
具体地，本申请实施例中，对于自由层和钉扎层的磁矩方向平行排列或反平行排列，可以有如下理解：自由层和钉扎层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和钉扎层的磁矩方向不做具体限定，只要自由层和钉扎层的磁矩方向平行排列或反平行排列即可。
具体的，在每个操作单元404中，所有SOT电极线之间通过金属导线串联连接，连接的方式可以有多种，具体不做限定；示例性的，可以包括下面两种串联方式：
参见图5，为本申请实施例提供的一种串联操作单元404的连接示意图。在一个操作单元404中，多个存储单元401沿z轴方向依次堆叠，每个存储单元401都包括一个磁性隧道结，该磁性隧道结设置在一条SOT电极线上，当使用金属导线将依次堆叠的SOT电极线进行串联时，可以将第N层存储结构的SOT电极线的第一端和第N+1层存储结构的SOT电极线的第一端相连，然后将第N+1层存储结构的SOT电极线的第二端与第N+2层存储结构的SOT电极线的第二端相连；示例性的，如图5所示，SOT电极线可以分为左端和右端，即第一层的左端与第二层的左端连接，第二层的右端与第三层的右端连接，第三层的左端与第四层的左端连接，按照该顺序依次连接多层的SOT电极线；可以理解的，当通过金属导线给存储串的SOT电极线通入电流时，相邻两层磁性隧道结对应的SOT电极线中电流流向是不同的。
参见图6，为本申请实施例提供的另一种操作单元404的连接示意图。一个操作单元404中，多个存储单元401仍然沿z轴方向依次堆叠，操作单元404中的存储单元401可以沿Z轴正方向依次排列，也可以相互错开，当使用金属导线将依次堆叠的SOT电极线进行串联时，可以将第N层存储结构的SOT电极线的第一端与第N+1层存储结构的SOT电极线的第二端相连，示例性的，如图6所示，第一层SOT电极线的右端连接第二层SOT电极线的左端，第二层SOT电极线的右端连接第三层SOT电极线的左端，依次首尾相连；可以理解的，当通过金属导线给存储串的SOT电极线通入电流时，每一层磁性隧道结对应的SOT电极线中电流流向是相同的。
下面将根据图4所示的结构框架，来介绍如何对存储单元401进行控制以及如何向存储单元401写入数据或者读取存储单元401存储的数据。
磁性随机存储器是根据不同的位线来选择特定的存储单元401并写入或者读取数据的，在图4所示的结构示意图中，每一个操作单元404还可以串联一个晶体管，用于控制存储串404的导通和关断，示例性的，可以直接与操作单元404的第一层存储结构对应的SOT电极线连接，也可以与操作单元404最上层存储结构对应的SOT电极线连接，SOT电极线可以连接晶体管的源极，也可以连接晶体管的漏极，具体不做限定。
磁性随机存储器还包括多条不同的位线，多个操作单元404与位线的连接方式为：沿z轴方向，操作单元404的最上端均连接一条第六位线，操作单元404下端的晶体管连接多条第五位线中的一条第五位线，即可以通过向第六位线和第五位线施加不同的电压来向操作单元404中的所有SOT电极线提供电流；晶体管的栅级连接字线，通过字线可以向晶体管的栅级施加栅极偏置电压，控制操作单元404的晶体管的导通和关断。
示例性的，如图4所示，在磁性随机存储器中，多条辅助电流线403与x轴平行，沿着x轴方向依次排列的一行操作单元404中的一层的存储单元401对应连接一条辅助电流线403；而第一位线405连接一整层存储结构的所有辅助电流线403的第一端，第二位线406则连接一整层存储结构的所有辅助电流线403的第二端，即当写入操作时，一条第一位线405和一条第二位线406可以为一整层的存储单元401对应的辅助电流线403提供闭合回路，向其通入偏置电流，使得一整层的辅助电流线中都通有电流且都能产生磁场。
而多条第五位线407与辅助电流线403平行，与结构单元402所在的平面垂直，沿着x轴方向依次排列的一行操作单元404中的晶体管的栅极/漏极对应连接一条第二位线407。
该磁性随机存储器还包括一条第六位线408和多条位线409，第六位线408通过金属导线将所有操作单元404未连接有晶体管的一端全部进行连接；多条字线409与y轴平行，每一个结构单元402的操作单元404中的晶体管栅级连接同一条字线409，即当通过一条字线409施加栅极偏置电压时，一个结构单元402内的所有晶体管都将导通。
此外，需要说明的是，在图4所示的磁性随机存储器中，为了示意简便，仅示出了x轴方向依次排列的三个操作单元404和y轴方向依次排列的三个操作单元404，因此，因此，第一位线405包括BL 1、BL 2和BL 3，第二位线406包括SL 1、SL 2和SL 3；第五位线407包括bl 1、bl 2和bl 3，第六位线408包括bl 0，字线409包括WL 1、WL 2和WL 3；磁性随机存储器可以沿任意方向排列多个操作单元404，对数量不进行限定。
(一)磁性随机存储器的数据写入：
在从磁性随机存储器写入数据时，需要根据待写入单元的位置，逐个选中存储单元，然后进行数据写入。
存储单元中数据的写入利用SOT效应。在从磁性随机存储器写入数据时，字线向待写入存储单元所属的操作单元的晶体管施加栅极偏置电压，使得晶体管导通；辅助电流线通入偏置电流为待写入存储单元提供磁场，待写入存储单元对应的SOT电极线需要通入写入电流使得自由层磁矩进行翻转，完成数据写入。
为了避免在写入数据时，电极线上的电流流经MTJ，形成潜行通路(sneak path)，对写入数据的准确性产生影响，本申请实施例中，MTJ可以具有高电阻特性，例如MTJ的电 阻值不低于100KΩ，使得MTJ的电阻值远大于电极线的电阻值，这样可以有效避免写入电流流经MTJ，降低sneak path的影响。
此外，在图3所示的磁性随机存储器中，自由层和钉扎层的磁矩方向平行排列或反平行排列。具体地，自由层和钉扎层的磁矩方向可以在xy平面内，可以垂直于xy平面，或者与xy平面呈一定倾斜角度。本申请实施例中对自由层和钉扎层的磁矩方向不做具体限定，只要自由层和钉扎层的磁矩方向平行排列或反平行排列即可。
基于如前所述的磁性随机存储器的结构框架，当向存储单元401写入数据时，在SOT电极线上通入电流的过程可以由第五位线407和第六位线408控制，示例性的，第六位线408直接与操作单元404的上端相连，第五位线407则与操作单元404中的晶体管的一端相连，其可以是与晶体管的源极相连，也可以与晶体管的漏极相连，具体不做限定。晶体管的导通和关断由字线409控制，在对应的字线409上向晶体管施加栅极偏置电压使得晶体管导通，并且在操作单元404对应的第五位线407和第六位线408上施加不同的电压，即可以选中目标操作单元，实现向目标操作单元的SOT电极线上施加写电流。
具体的，在图4所示的磁性随机存储器中，在向待写入存储单元写入数据时，先确定待写入存储单元所属的结构单元402；然后通过该结构单元402对应的字线409施加栅极偏置电压，这样，则使得一个结构单元402中所有的操作单元404的晶体管都导通；可选的，剩余的字线409不施加栅极偏置电压，这样相当于选中了待写入存储单元所在的结构单元402。
可以理解的，在一种方式中，可以通过该结构单元402对应的第五位线407施加写入电压，然后将第六位线408接地；向剩余的第五位线407施加写入电压，这样，待写入存储单元所在的操作单元404为唯一的一端接写入电压，另一端接地的操作单元，即使得该操作单元404中的SOT电极线有了写入电流，相当于选中了待写入存储单元所在的操作单元。
当选中待写入存储单元所在的操作单元404后，可以通过第一位线405和第二位线406来为每一层的辅助电流线403通入偏置电流，可选的，先确定待写入存储单元对应的第一位线和第二位线，通过第一位线和第二位线为辅助电流线提供偏置电流，形成闭合回路。控制其他的第一位线和第二位线不产生该偏置电流，示例性的，给其他的第一位线和第二位线都施加相同的电压，使得其他层的辅助电流线变成等压线，又或者将其他第一位线或第二位线都接地，具体不做限制。
其中，偏置电流用于产生磁场，该磁场一方面可以实现自由层的确定性翻转，另一方面可以降低自由层翻转所需的写电流密度。待写入存储单元通过施加的写入电流和偏置电流，完成数据的写入。
可以理解的，可以通过改变SOT电极线中电流的方向或者改变辅助电流线中偏置电流的方向，来完成不同数据的写入。示例性的，可以将向第六位线408施加写入电压，然后将上述结构单元402对应的第五位线407接地，向其余的第五位线407施加写入电压，这样，该操作单元404中的SOT电极线有了反向写入电流，也相当于选中了待写入存储单元所在的操作单元；然后就可以写入不同的数据。
示例性的，在写入相反数据时，不改变SOT电极线内的写入电流的方向，即仍然通过 结构单元402对应的第五位线407施加写入电压，然后将第六位线408接地，而是改变待写入存储单元对应的辅助电流线中的电流方向，通过控制第一位线和第二位线改变辅助电流线中的电流方向，这样也可以完成不同数据的写入。
由于操作单元404中SOT电极线串联的方式多样，若操作单元404中SOT电极线串联的方式如图5所示，可以得知当为该存储串204提供写入电压时，相邻两层存储单元对应的SOT电极线中写入电流的流向不同，因此若相邻两层存储单元写入同一个数据时，其控制方式也不同；示例性的，若第一层存储单元要写入数据“1”，则可以选择通过第五位线施加写入电压，将第六位线接地，若第二层存储单元要写入数据“1”，则可以选择通过第六位线施加写入电压，将第五位线接地。
实际应用中，在向磁性随机存储器写入数据时，上述在第一位线405、第二位线406、第五位线407、第六位线408以及字线409施加电压或通入电流的过程可以由磁性随机存储器中配置的电平控制电路进行控制第一位线405、第二位线406、第五位线407、第六位线408以及字线409提供所需的电压或电流。同样地，在从磁性随机存储器读取数据时，辅助电流线403上施加电压的过程也可以由该电平控制电路控制，该电平控制电路用于为辅助电流线403提供所需的电压或电流。
此外，磁性随机存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线和位线选择对应的存储单元，上述电平控制电路可以根据行地址解码电路和列地址解码电路的选择来判断需要在第一位线、第二位线、第三位线、第四位线和字线上施加的电压或电流，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元进行读写操作。
其中，电平控制电路、行地址解码电路和列地址解码电路可以统称为控制电路。
(二)磁性随机存储器的数据读取：
在从磁性随机存储器读取数据时，可以一次性读取某个操作单元中所有存储单元存储的数据。
存储单元中数据的读取利用TMR效应。在从磁性随机存储器读取数据时，字线分别向晶体管施加栅极偏置电压，使得晶体管导通；多个辅助电流线中的每个辅助电流线用于向对应连接的存储单元施加读取电压或读取电流，以及接收对应连接的存储单元的反馈信息，该反馈信息用于指示对应连接的存储单元中存储的数据。
其中，每个辅助电流线向对应连接的存储单元施加读取电压时，存储单元的反馈信息可以是存储单元的电流、电容量等信息，在每个辅助电流线施加的读取电压相同的情况下，存储单元处于不同阻态时，反馈的电流或电容量不同；每个辅助电流线向对应连接的存储单元施加读取电流时，存储单元的反馈信息可以是存储单元的电压、电容量等信息，在每个辅助电流线施加的读取电流相同的情况下，存储单元处于不同阻态时，反馈的电压或电容量不同。
此外，磁性随机存储器中还可以包括分别与多个第一位线一一对应连接的多个放大器，多个放大器中的每个放大器用于读取对应连接的辅助电流线所接收的反馈信息。
其中，每个放大器及其外围电路等共同组成读出回路，用于接收放大器所连接的辅助电流线对应的存储单元的反馈信息，从而读取存储单元中的数据。
具体地，每个放大器可以通过将存储单元的反馈信息(例如电压、电流、电容量、充放电时间)与参考值做比较，来判断该存储单元处于高阻态还是低阻态，进而确定该存储单元中存储的数据。
在向所述磁性随机存储器读取数据时，一次性读取一个操作单元404上所有存储单元401的数据；一种示例为：首先需要确定待读取操作单元所属的结构单元402对应的字线409，然后通过该字线409对待读取操作单元中的晶体管施加栅极偏置电压，使得该操作单元404的晶体管导通，这样相当于选中了该操作单元404所在的结构单元；然后，在所有的第一位线405和第二位线406都施加读取电压，使得所有辅助电流线变为等压线，然后在第六位线408上施加读取电压，将待读取操作单元所属的结构单元402对应的第五位线407接地，其余的第五位线407都接读取电压，这样就保证只有待读取操作单元能形成读出回路，有读电流流过，相当于选中了该待读取操作单元，最后通过与第一位线一一对应的放大器接收的反馈信息来判断待读取存储串中各层存储单元对应的高低组态，从而实现一整个存储串数据的读出。
基于同一发明构思，本申请实施例还提供一种磁性随机存储器的数据写入方法，包括：
确定待写入存储单元所属的操作单元；其中，磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线并联连接；
向待写入存储单元所属的结构单元对应的第三位线施加写入电压并将待写入存储单元所属的结构单元对应的第四位线接地；其中，多个结构单元中的每个结构单元均包括第三位线和第四位线；第三位线和第四位线与多条辅助电流线垂直；第三位线通过金属导线连接每个结构单元中的所有操作单元的第一端，第四位线用于通过金属导线连接和控制每个结构单元中的所有操作单元的第二端；
通过操作单元对应的字线向待写入存储单元所对应的晶体管施加栅极偏置电压；其中，多条字线与多条辅助电流线平行，晶体管的第一端与操作单元的第一端相连；属于同一个结构单元中的所有操作单元对应的晶体管的第二端连接同一条第三位线；
向待写入存储单元连接的辅助电流线施加偏置电流；
根据写入电压和偏置电流，向待写入存储单元写入数据。
基于同一发明构思，本申请实施例还提供另一种磁性随机存储器的数据写入方法，包括：
确定待写入存储单元所属的操作单元；其中，磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写 入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线并联连接；
向待写入存储单元所属的结构单元对应的第四位线施加写入电压并将待写入存储单元所属的结构单元对应的第三位线接地；其中，多个结构单元中的每个结构单元均包括第三位线和第四位线；第三位线和第四位线与多条辅助电流线垂直；第三位线通过金属导线连接每个结构单元中的所有操作单元的第一端，第四位线用于通过金属导线连接和控制每个结构单元中的所有操作单元的第二端；
通过操作单元对应的字线向待写入存储单元所对应的晶体管施加栅极偏置电压；其中，多条字线与多条辅助电流线平行，晶体管的第一端与操作单元的第一端相连；属于同一个结构单元中的所有操作单元对应的晶体管的第二端连接多条第三位线中的同一条位线；
向待写入存储单元连接的辅助电流线施加偏置电流；
根据写入电压和偏置电流，向待写入存储单元写入数据。
基于同一发明构思，本申请实施例还提供另一种磁性随机存储器的数据写入方法，包括：
确定待写入存储单元所属的结构单元；其中，磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线串联连接；
通过待写入存储单元所属操作单元对应的第五位线向待写入存储单元施加写入电压，并将其他第五位线和第六位线接地；其中，磁性随机存储器包括多条第五位线和一条第六位线，多条第五位线和一条第六位线与多条辅助电流线平行；每个操作单元的第一端均与第六位线连接，每个操作单元的第二端连接多条第五位线中的一条第五位线；
通过结构单元对应的字线向待写入存储单元所属操作单元中的晶体管施加栅极偏置电压，其中，多个结构单元中的每个结构单元还包括字线，字线与多条辅助电流线垂直；每个操作单元的第一端均与第六位线连接，每个操作单元的第二端与晶体管的第一端相连，晶体管的第二端连接多条第五位线中的一条第五位线；
向待写入存储单元连接的辅助电流线施加偏置电流；
根据写入电压和偏置电流，向待写入存储单元写入数据。
基于同一发明构思，本申请实施例还提供另一种磁性随机存储器的数据写入方法，包 括：
确定待写入存储单元所属的结构单元；其中，磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与多条辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线串联连接；
向第六位线施加写入电压，并将待写入存储单元所属操作单元对应的第五位线接地；其中，磁性随机存储器包括多条第五位线和一条第六位线，多条第五位线和第六位线与多条辅助电流线平行；每个操作单元的第一端均与第六位线连接，每个操作单元的第二端连接多条第五位线中的一条第五位线；
通过结构单元对应的字线向待写入存储单元所属存储串中的晶体管施加栅极偏置电压，其中，多个结构单元中的每个结构单元还包括字线，字线与多条辅助电流线垂直；每个操作单元的第一端均与第六位线连接，每个操作单元的第二端与晶体管的第一端相连，晶体管的第二端连接多条第五位线中的同一条第五位线；
向待写入存储单元连接的辅助电流线施加偏置电流；
根据写入电压和偏置电流，向待写入存储单元写入数据。
基于同一发明构思，本申请实施例还提供一种磁性随机存储器的数据读取方法，包括：
确定待读取操作单元；磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与多条辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线并联连接；
向磁性随机存储器中的所有第三位线都施加读取电压；其中，多个结构单元中的每个结构单元均包括第三位线和第四位线；第三位线和第四位线与多条辅助电流线垂直；第三位线通过金属导线连接每个结构单元中的所有操作单元的第一端，第四位线用于通过金属导线连接和控制每个结构单元中的所有操作单元的第二端；
通过待读取操作单元对应的字线，向待读取操作单元中的晶体管施加栅极偏置电压；其中，多条字线与多条辅助电流线平行；
向待读取存储单元所属的结构单元对应的第四位线接地，其他第四位线施加读取电压；
向多条辅助电流线施加读取电压；
根据读取电压确定待读取操作单元所对应的数据。
基于同一发明构思，本申请实施例还提供一种磁性随机存储器的数据读取方法，包括：
确定待读取操作单元所属的目标结构单元；磁性随机存储器包括多个结构单元以及多条辅助电流线，多条辅助电流线平行，多个结构单元所在的平面平行，且多个结构单元中的每个结构单元所在的平面与多条辅助电流线垂直，辅助电流线在向磁性随机存储器写入数据时通有产生磁场的偏置电流；每个结构单元中都包括相互平行的多个操作单元，多个操作单元中的每个操作单元都包括依次堆叠的多层存储结构，多层存储结构的每层存储结构包括一条与多条辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于SOT电极线上的一个存储单元；存储单元包括一个磁性隧道结，存储单元的一端与多条辅助电流线中的一条辅助电流线连接，存储单元的另一端与SOT电极线连接，每个存储单元中的所有SOT电极线通过金属导线串联连接；
向磁性随机存储器中的第六位线施加读取电压；磁性随机存储器还包括多条第五位线和一条第六位线，多条第五位线和一条第六位线与多条辅助电流线平行，多个操作单元中的每个操作单元均包括晶体管，每个操作单元的第一端均与第六位线连接，每个操作单元的第二端与晶体管的第一端相连，晶体管的第二端连接多条第五位线中的一条第五位线；
通过待读取操作单元所属的结构单元对应的字线向待读取操作单元中的晶体管施加栅极偏置电压；
将待读取操作单元所属的操作单元连接的第五位线接地并向其他第五位线施加读取电压；
向多条辅助电流线施加读取电压；
根据读取电压确定待读取操作单元所对应的数据。
基于同一发明构思，本申请实施例还提供一种存算装置。参见图7，该一种存算装置包括控制器701以及与控制器耦合的磁性随机存储器702，磁性随机存储器702可以是图3或图4所示的磁性随机存储器。
具体地，控制器701可以调用磁性随机存储器702中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (19)

  1. 一种磁性随机存储器，其特征在于，包括多个结构单元以及多条辅助电流线，所述多条辅助电流线平行，所述多个结构单元所在的平面平行，且所述多个结构单元中的每个结构单元所在的平面与所述多条辅助电流线垂直；
    其中，所述多个结构单元中的每个结构单元都包括依次堆叠的多层存储结构，所述多层存储结构的每层存储结构均包括与所述多条辅助电流线垂直的自旋轨道力矩SOT电极线以及设置于所述SOT电极线上的存储单元；所述存储单元包括磁性隧道结，所述存储单元的一端与所述多条辅助电流线中的一条辅助电流线连接，所述存储单元的另一端与所述SOT电极线连接。
  2. 如权利要求1所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多条第一位线和多条第二位线；所述多条第一位线和所述多条第二位线都与所述多条辅助电流线垂直；
    所述多条第一位线中的每一条位线用于连接所述多层存储结构中一层存储结构所对应的辅助电流线的一端；所述多条第二位线中的每条第二位线用于连接所述多层存储结构中一层存储结构所对应的辅助电流线的另一端。
  3. 根据权利要求1或2所述的磁性随机存储器，其特征在于，所述多个结构单元中的每个结构单元均包括相互平行的多个操作单元，所述多个操作单元中的每个操作单元都包括依次堆叠的多层存储单元，所述每层存储单元均对应一个存储单元和一条SOT电极线；所述每个操作单元中的所有SOT电极线通过金属导线并联连接。
  4. 根据权利要求3所述的磁性随机存储器，其特征在于，所述多个结构单元中的每个结构单元均包括第三位线和第四位线；所述第三位线和所述第四位线与所述多条辅助电流线垂直；
    其中，所述第三位线用于通过金属导线连接和控制所述每个结构单元中的所有操作单元的第一端，所述第四位线用于通过金属导线连接和控制所述每个结构单元中的所有操作单元的第二端。
  5. 根据权利要求4所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多条字线，所述多条字线与所述多条辅助电流线平行，所述晶体管的栅级连接所述多条字线中的一条字线；
    所述每个操作单元还包括晶体管，所述晶体管的第一端与所述操作单元的第一端相连；属于同一个结构单元中的所有操作单元对应的晶体管的第二端连接所述多条第三位线中的同一条第三位线。
  6. 如权利要求5所述的磁性随机存储器，其特征在于，在向所述磁性随机存储器写入数据时，待写入存储单元所属的操作单元对应的字线用于向所述待写入存储单元所属的操作单元中的晶体管施加栅极偏置电压；所述待写入存储单元所属的结构单元对应的第三位线用于施加写入电压，所述待写入存储单元所属的结构单元对应的第四位线接地；所述待写入存储单元连接的辅助电流线对应连通的第一位线和第二位线用于施加偏置电流。
  7. 如权利要求5所述的磁性随机存储器，其特征在于，在向所述磁性随机存储器写入 数据时，待写入存储单元所属的操作单元对应的字线用于向所述待写入存储单元所属的操作单元中的晶体管施加栅极偏置电压；所述待写入存储单元所属的结构单元对应的第四位线用于施加写入电压，所述待写入存储单元所属的结构单元对应的第三位线接地；所述待写入存储单元连接的辅助电流线对应连通的第一位线和第二位线用于施加偏置电流。
  8. 如权利要求5所述的磁性随机存储器，其特征在于，在从所述磁性随机存储器读取数据时，所述第一位线和所述第二位线用于施加读取电压；待读取操作单元对应的字线用于向所述待读取操作单元中的晶体管施加栅极偏置电压；所述磁性随机存储器中的所有第三位线都用于施加读取电压；所述待读取存储单元所属的结构单元对应的第四位线接地，其他所述第四位线用于施加读取电压。
  9. 根据权利要求1或2所述的磁性随机存储器，其特征在于，所述多个结构单元中的每个结构单元均包括相互平行的多个操作单元，所述多个操作单元中的每个操作单元都包括依次堆叠的多层存储单元，所述每层存储单元均对应一个存储单元和一条SOT电极线；所述每个操作单元中的所有SOT电极线通过金属导线串联连接。
  10. 如权利要求9所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多条第五位线和第六位线，所述多条第五位线和所述第六位线与所述多条辅助电流线平行；
    所述多个操作单元中的每个操作单元均包括晶体管，所述每个操作单元的第一端均与所述第六位线连接，所述每个操作单元的第二端与所述晶体管的第一端相连，所述晶体管的第二端与所述多条第五位线中的一条第五位线连接。
  11. 根据权利要求10所述的磁性随机存储器，其特征在于，所述多个结构单元中的每个结构单元还包括字线，所述字线与所述多条辅助电流线垂直；其中，属于同一个结构单元中的所有操作单元对应的晶体管的栅级连接所述多条字线中的同一条字线。
  12. 如权利要求9至11所述的磁性随机存储器，其特征在于，在所述多个操作单元中的每个操作单元中，所述SOT电极线依次堆叠；其中，所述多层存储单元中的第N层存储单元对应的SOT电极线的第一端通过金属导线连接所述多层存储单元中的第N+1层存储单元的SOT电极线的第一端，所述第N+1层存储单元的SOT电极线的第二端连接所述多层存储单元中的第N+2层存储单元的SOT电极线的第二端。
  13. 如权利要求9至11所述的磁性随机存储器，其特征在于，在所述多个操作单元中的每个操作单元中，所述SOT电极线依次堆叠；其中，所述多层存储单元中的第N层存储单元的SOT电极线的第一端通过金属导线连接所述多层存储单元中的第N+1层存储单元的SOT电极线的第二端。
  14. 如权利要求12或13所述的磁性随机存储器，其特征在于，在向所述磁性随机存储器写入数据时，所述待写入存储单元所属的结构单元对应的字线用于向所述待写入存储单元所属的操作单元中的晶体管施加栅极偏置电压；所述待写入存储单元连接的辅助电流线对应连通的第一位线和第二位线用于施加所述偏置电流；其中，所述待写入存储单元所属的操作单元连接的第五位线用于施加写入电压，所述第六位线接地。
  15. 如权利要求12或13所述的磁性随机存储器，其特征在于，在向所述磁性随机存储器写入数据时，所述待写入存储单元所属的结构单元对应的字线用于向所述待写入存储单元所属的操作单元中的晶体管施加栅极偏置电压；所述待写入存储单元连接的辅助电流 线对应连通的第一位线和第二位线用于施加所述偏置电流；其中，所述第六位线用于施加写入电压，所述待写入存储单元所属的操作单元连接的第五位线接地，其他第五位线用于施加写入电压。
  16. 如权利要求12或13所述的磁性随机存储器，其特征在于，在从所述磁性随机存储器读取数据时，所述第一位线和所述第二位线用于施加读取电压，所述待读取操作单元所属的结构单元对应的字线用于向所述待读取操作单元中的晶体管施加栅极偏置电压；所述第六位线用于施加读取电压，所述待写入操作单元连接的第五位线接地，其他第五位线用于施加读取电压。
  17. 如权利要求1至16任一项所述的磁性随机存储器，其特征在于，所述每个磁性隧道结均包括依次堆叠的自由层、势垒层和参考层，所述自由层与所述SOT电极线连接，所述参考层与所述辅助电流线连接；其中，所述自由层和所述参考层磁矩方向为垂直磁化，所述磁性隧道结的电阻值不小于100KΩ。
  18. 如权利要求2至17任一项所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多个灵敏放大器SA；
    所述多个灵敏放大器SA与所述多条第一位线一一对应连接，所述多个放大器中的每个放大器用于读取对应连接的第一位线所接收的信号。
  19. 一种存算装置，其特征在于，包括：磁性存储器以及控制器；所述磁性存储器在所述控制器的控制下存储数据和计算数据，所述磁性存储器为如权利要求1至18中任一项所述的磁性存储器。
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