WO2020154988A1 - 一种存储器及电子设备 - Google Patents

一种存储器及电子设备 Download PDF

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Publication number
WO2020154988A1
WO2020154988A1 PCT/CN2019/074012 CN2019074012W WO2020154988A1 WO 2020154988 A1 WO2020154988 A1 WO 2020154988A1 CN 2019074012 W CN2019074012 W CN 2019074012W WO 2020154988 A1 WO2020154988 A1 WO 2020154988A1
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WIPO (PCT)
Prior art keywords
transistor
memory
transistors
word line
memory cell
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PCT/CN2019/074012
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English (en)
French (fr)
Inventor
潘越
刘燕翔
巴德尔斯蒂芬
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19913902.3A priority Critical patent/EP3910634A4/en
Priority to CN201980090877.5A priority patent/CN113383389A/zh
Priority to PCT/CN2019/074012 priority patent/WO2020154988A1/zh
Publication of WO2020154988A1 publication Critical patent/WO2020154988A1/zh
Priority to US17/387,588 priority patent/US20210358531A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Definitions

  • This application relates to the field of information technology, in particular to a memory and electronic equipment.
  • STT-MRAM Spin-transfer torque magnetic random access memory
  • STT-MRAM spin-transfer torque magnetic memory
  • Magnetic tunnel junction is the memory cell 10 in STT-MRAM, which usually consists of two ferromagnetic layers sandwiching a thin tunnel oxide layer 12 (for example, magnesium oxide) composition.
  • One of the ferromagnetic layers has a fixed magnetization along the easy axis of magnetization and is called the pinned layer 13; the other ferromagnetic layer whose magnetization can be flipped freely between two orientations is called the free layer 11.
  • the arrow points represent the magnetization orientation.
  • the resistance of the MTJ presents a lower resistance value.
  • the resistance of the MTJ exhibits a higher resistance value.
  • the memory cell is usually a 1T1MTJ structure composed of one transistor and one MTJ. It has three terminals connected to the word line (WL) and the bit line (BL). ), Source Line (SL).
  • WL word line
  • BL bit line
  • SL Source Line
  • the stored information depends on the MTJ resistance value read, and the current direction can be arbitrary; when writing, writing to a specific state (AP or P) needs to use the corresponding current direction ( Figure 2).
  • the bandwidth of the memory can be increased by increasing the input and output of the storage array, but this will cause the memory layout to appear flat, the read delay will also increase to a certain extent, and the range in which the number of input and output can be increased is limited.
  • the bandwidth can be increased by reducing the size of the array to increase the total number of arrays, but this will increase the proportion of peripheral circuits, thereby increasing the area of the entire memory.
  • the present application provides a memory to reduce the size of the memory.
  • a memory in a first aspect, includes a memory cell for storing data and two transistors for writing or reading the memory cell.
  • the two transistors are a first transistor and a second transistor.
  • the memory cell is respectively coupled to the first bit line and the second bit line through the first transistor and the second transistor.
  • the first transistor and the second transistor are used to control the writing and reading of the memory cell.
  • the first transistor and the second transistor are turned on together during the writing operation.
  • one of the first transistor and the second transistor is turned on during the reading operation.
  • the turn-on current of the first transistor and the turn-on current of the second transistor are both smaller than the write current of the memory cell, and the turn-on current of the first transistor is the same as that of the second transistor.
  • the sum of the turn-on currents is greater than 1 times the write current of the memory cell and less than 2 times the write current of the memory cell. Therefore, when the two transistors are used in parallel, they can just provide the writing current required by the memory cell. Compared with one transistor to provide the required writing current, two transistors to provide the writing current can make smaller transistors meet the demand and reduce the area required by the entire memory. At the same time, the memory of the present application can still support dual-port characteristics in read operations.
  • the first transistor and the second transistor are turned on together in this application means that at a certain time during the writing operation, the first transistor and the second transistor are both in the on state , So as to provide sufficient writing current.
  • the memory further includes a first word line and a second word line, wherein the first word line and the second word line are respectively coupled to the gates of the first transistor and the second transistor, that is, the first A word line is coupled to the gate of the first transistor, and a second word line is coupled to the gate of the second transistor.
  • the memory further includes a control circuit for controlling the on and off of the first transistor and the second transistor.
  • the control circuit uses the first word line and the second word line to separately Turn on or turn off the first transistor and the second transistor.
  • the write operation and read operation are realized through the control of the control circuit.
  • the memory cell includes a first terminal and a second terminal, wherein the first terminal is coupled to the first transistor and the second transistor, and the second terminal is coupled to the source line.
  • the first transistor and the second transistor share an active area. Therefore, the source and drain of the first transistor and the second transistor are arranged in the same active region.
  • the first transistor and the second transistor are the same type of transistors.
  • the first transistor and the second transistor are both fin-type transistors or the first transistor and the second transistor are both planar transistors.
  • an electronic device which includes the memory described in any one of the above.
  • Two transistors are used to provide the write current, so that a smaller transistor can meet the demand and the area required by the entire memory is reduced.
  • the memory of the present application can still support dual-port characteristics in read operations.
  • a memory in a third aspect, includes a plurality of storage structures arranged in a rectangular array, and a plurality of groups of bit lines corresponding to a plurality of columns of the rectangular array, each group of bit lines including a first A bit line and a second bit line; and each of the plurality of memory structures includes a memory cell, a first transistor and a second transistor: wherein, according to the row of the memory structure in the rectangular array , The memory cell is respectively coupled to the corresponding first bit line and the second bit line through the first transistor and the second transistor; and the first transistor and the second transistor are in a write operation to the memory cell Conducted together.
  • the turn-on current of the first transistor and the turn-on current of the second transistor are both smaller than the write current of the memory cell, and the turn-on current of the first transistor is the same as that of the second transistor.
  • the sum of the turn-on currents is greater than 1 times the write current of the memory cell and less than 2 times the write current of the memory cell. Therefore, when the two transistors are used in parallel, they can just provide the writing current required by the memory cell; when reading data, it can be read through any transistor.
  • the performance of the first transistor and the second transistor can be improved.
  • the structure enables the area of the memory to be similar to that of a traditional single-port memory, reducing the area of the entire memory.
  • the memory further includes multiple sets of word lines one-to-one corresponding to multiple rows of the rectangular array, each set of word lines includes a first word line and a second word line, according to the storage structure In the row located in the rectangular array, the gates of the first transistor and the second transistor are respectively coupled to the corresponding first word line and the second word line.
  • the memory When specifically implementing the write operation and the read operation, the memory further includes a control circuit for turning on or off the first transistor and the second transistor through the first word line and the second word line.
  • the control circuit realizes the control of write operation and read operation.
  • the storage unit is a magnetic tunnel junction.
  • the first transistor and the second transistor are alternately arranged in pairs except for the transistors located at the end and the end.
  • the first transistor and the second transistor share an active area. This further reduces the memory area.
  • adjacent first transistors share a first contact hole to connect to the first bit line; adjacent second transistors share a second contact hole to connect to the second bit line. It further reduces the memory area.
  • an electronic device in a fourth aspect, includes the memory described in any one of the foregoing.
  • Two transistors are used to provide the write current, so that a smaller transistor can meet the demand and the area required by the entire memory is reduced.
  • the memory of the present application can still support dual-port characteristics in read operations.
  • Figures 1a and 1b show the MTJ structure in the prior art
  • FIG. 2 is a schematic diagram of the structure of a memory in the prior art
  • FIG. 3 is a schematic diagram of the structure of the memory provided by this application.
  • Figure 4 is a layout of a memory provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of the memory array provided by this application.
  • Figure 6 is the layout of the memory array provided by this application.
  • FIG. 7 is a schematic diagram of a memory provided by an embodiment of the application.
  • FIG. 8 is a read timing diagram of the memory provided by an embodiment of the application.
  • FIG. 9 is a write timing diagram of the memory provided by an embodiment of the application.
  • the memory is used to store data and can write and read data.
  • the memory is often arranged in an array.
  • multiple ports are required.
  • the first row of memory and the second row of memory need to be read, two bit lines are required to read the memory respectively. This requires the memory to have two ports.
  • an embodiment of the present application provides a memory, which will be described in detail below with reference to the accompanying drawings.
  • FIG. 3 shows the structure of a memory provided by an embodiment of the present application.
  • the memory includes a storage unit for storing data.
  • the storage unit is a magnetic tunnel junction (MTJ). Tunnel junction).
  • MTJ magnetic tunnel junction
  • Tunnel junction Referring to Figures 1a and 1b together, Figures 1a and 1b show the memory cell 10.
  • the memory cell 10 is usually composed of two ferromagnetic layers and a thin layer sandwiched between the two ferromagnetic layers.
  • the tunnel oxide layer 12 (for example, MgO) is composed.
  • fixed layer 13 the magnetization of the other ferromagnetic layer can be flipped freely between two orientations, which is called free layer 11.
  • the resistance of the MTJ presents a lower resistance value.
  • the resistance of the MTJ exhibits a higher resistance value.
  • the memory provided in the embodiment of the application uses transistors for control, and in order to correspond to multiple ports, two transistors and two bit lines are provided in the memory provided in the embodiment of the application. .
  • the two transistors are named the first transistor 21 and the second transistor 22, and the two bit lines are named the first bit line (BLA) and the second bit line (BLB);
  • BLA first bit line
  • BLB second bit line
  • each transistor includes a gate, a source and a drain; wherein, the gate is used to control the conduction of the channel between the source and the drain to form a path.
  • a fin-type transistor or a planar transistor can be used.
  • the memory also includes a first word line (WLA) and a second word line (WLB).
  • WLA first word line
  • WLB second word line
  • the gate of the first transistor 21 is connected to the WLA
  • the drain is connected to the BLA and the memory cell (MTJ) respectively; in specific connection, the source can be connected to the BLA, and the drain is connected to the fixed layer 13 (first end) of the memory cell, or the drain can be connected to The BLA is connected, and the source is connected to the fixed layer 13 (first end) of the memory cell.
  • the gate of the second transistor 22 is connected to the WLB, and the source and drain are respectively connected to the BLB and the memory cell; when specifically connected, the source of the second transistor 22 is connected to The BLB is connected, and the drain of the second transistor 22 is connected to the fixed layer 13 (first end) of the memory cell, or the drain is connected to the BLB and the source is connected to the memory cell.
  • the source of the first transistor 21 and the second transistor 22 can be P-type transistors or N-type transistors at the same time; preferably, the source of the first transistor 21 and the source of the second transistor 22 are connected to the memory cell, or The drain of the first transistor 21 and the drain of the second transistor 22 are connected to the memory cell.
  • FIG. 3 shows the connection between the first transistor 21 and the second transistor 22 and the memory cell.
  • the schematic diagram, and FIG. 4 shows the layout when the first transistor 21 and the second transistor 22 are connected to the memory cell.
  • the first transistor 21 and the second transistor 22 are connected in parallel.
  • the gate of the first transistor 21 is connected to WLA
  • the gate of the second transistor 22 is connected to WLB
  • the source of the first transistor 21 is connected to BLA
  • the source of the second transistor 22 is connected to BLB
  • the first transistor 22 is connected to BLB.
  • the drain of the transistor 21 and the drain of the second transistor 22 are simultaneously connected to the fixed layer 13 (first terminal) of the memory cell, or the source of the first transistor 21 and the source of the second transistor 22 are simultaneously fixed to the memory cell Layer 13 (first end) is connected.
  • the free layer 11 (second end) of the memory cell is connected to the source line (SL).
  • the first transistor 21 and the second transistor 22 are specifically set, the first transistor 21 and the second transistor 22 are turned on together during the write operation. It should be noted that the “first transistor and the second transistor” mentioned in this application “Transistors are turned on together” means that at a certain time during the writing operation, the first transistor and the second transistor are both in the on state, so as to provide sufficient writing current.
  • the turn-on current of the first transistor 21 and the turn-on current of the second transistor 22 provided in the embodiment of the present application are both smaller than the write current of the memory cell, and the first transistor 21
  • the sum of the turn-on current and the turn-on current of the second transistor 22 is greater than or equal to 1 times the write current of the memory cell and less than twice the write current of the memory cell.
  • the turn-on current through the first transistor 21 is named I1
  • the turn-on current of the second transistor 22 is named I2
  • the write current of the memory cell is named I3.
  • I1, I2, and I3 satisfy: I3 ⁇ I1 +I2 ⁇ 2 times I3.
  • I1, I2, and I3 can be different values such as I3, 1.2 times I3, 1.4 times I3, or 1.5 times I3.
  • the source and drain of each transistor are arranged in the active region 23. Therefore, the channel width of the transistor can be equivalent to the width of the active region 23.
  • the active area 23 of the first transistor 21 and the active area 23 of the second transistor 22 can be shared, that is, the first transistor 21 and the second transistor 22 The same active area 23 is used.
  • the active area 23 of the first transistor 21 and the active area of the second transistor 22 may not be shared. In this case, the first transistor 21 and the second transistor 22 respectively correspond to one Source area.
  • FIG. 4 shows the layout of the memory.
  • the first transistor 21 and the second transistor 22 are both planar transistors, and the active regions 23 of the two transistors are shared. Therefore, the width of the channel It can be equivalent to the width of the active region 23.
  • Figure 4 also shows the positional relationship between WLA and WLB.
  • the WLA and WLB are arranged horizontally and arranged in the Y direction, while the SL is arranged vertically and multiple SL is arranged along the X direction.
  • the embodiment of the present application describes in detail the process of the memory during the write operation and the read operation.
  • the memory When performing a write operation and a read operation, the memory further includes a control circuit 70, which is used to turn on or off the first transistor and the second transistor respectively through the first word line and the second word line. That is, the control circuit 70 realizes the control of the first transistor and the second transistor.
  • the first transistor is turned on, the second transistor is turned on, or the first transistor and the second transistor are turned on at the same time, and the memory cell is read.
  • the WLA electric position is high, SL is connected to low electric potential, and BLA electric potential is set to reading potential Vr; then the sensitive amplifier (the peripheral circuit connected to the memory) will read the current flowing through the BLA Compare with the current on the reference branch to determine the information stored in the storage unit.
  • the method of reading through WLB is similar, and even if WLA and WLB read the same cell, they will not cause mutual interference. Therefore, the memory cell of the present application can support simultaneous reading of two addresses at most. As shown in Figure 5, different rows of memory can be read during reading.
  • WLA refers to the word line connected to the first transistor 21 in each memory
  • WLB refers to the word line connected to the second transistor 22 in each memory.
  • WLnA and WLnB different rows are represented by WLnA and WLnB, where n is a positive integer greater than or equal to 1.
  • bit lines arranged in columns The bit lines of different columns are represented by BLmA and BLmB, and the source lines of different columns are represented by SLm, where m is a positive integer greater than or equal to 1.
  • the first transistor and the second transistor are turned on at the same time to write into the memory cell.
  • WLA and WLB are set to high level at the same time
  • BLA and BLB are also set to the same potential.
  • SL Connect to high level when writing the P state, BLA and BLB are both at low potential, SL Connect to high level; when writing AP state, BLA and BLB are connected to high level at the same time, and SL is connected to low level.
  • the total of the turn-on current I1 of the first transistor 21 and the turn-on current I2 of the second transistor 22 in parallel is equal to the current flowing through the memory cell, because the turn-on current I1 of the first transistor 21 and the turn-on current I2 of the second transistor 22
  • the current I2 is greater than or equal to the write current I3 of the memory cell, and the memory cell can be written at this time.
  • the memory provided in the embodiment of the present application can implement multi-port reading and can process one write request.
  • the read operation is more frequent and more important than the write operation. Therefore, in the memory provided by the embodiment of the present application, for the operating characteristics of the memory, a multi-port read is realized through the first transistor and the second transistor provided. Take, single port write.
  • the memory provided by the embodiment of the present application can satisfy the reading and writing of storage, and by using the turn-on current of the first transistor 21
  • the turn-on current of the second transistor 22 and the second transistor 22 are both smaller than the write current of the memory cell.
  • the write current provided by two transistors can make the smaller transistor meet the demand. , which reduces the area required for the entire memory.
  • the memory of the present application can still support dual-port characteristics in read operations. Compared with using separate two transistors for reading and writing in the prior art, the area occupied by the memory is greatly reduced.
  • the first transistor 21 and the second transistor 22 are both planar transistors as an example, but the first transistor 21 and the second transistor 22 provided in the embodiment of the present application are still Other types of transistors may be used.
  • the first transistor and the second transistor may also be fin-type transistors.
  • the functions of the fin-type transistors are similar to those of the above-described transistors and will not be repeated here.
  • the first transistor 21 and the second transistor 22 can be considered to use planar transistors at the same time, or the first transistor 21 and the second transistor 22 are both fin type transistors.
  • RRAM resistive random access memory
  • an embodiment of the present application also provides a memory, which includes a plurality of storage structures arranged in a rectangular array, and a plurality of groups of bit lines corresponding to a plurality of columns of the rectangular array, each group of bit lines includes The first bit line and the second bit line; each of the plurality of memory structures includes a memory cell, a first transistor and a second transistor: according to the row of the memory structure in the rectangular array, the memory cell passes through the first transistor and The second transistor is respectively coupled to the corresponding first bit line and the second bit line, and the first transistor and the second transistor are simultaneously turned on during a write operation.
  • the memory When the memory is specifically set up, the memory also includes multiple sets of word lines one-to-one corresponding to multiple rows of the rectangular array, and each set of word lines includes a first word line and a second word line, and is located in the rectangular array according to the storage structure.
  • the gates of the first and second transistors are coupled to the corresponding first and second word lines, respectively.
  • the control circuit is also used, and the control circuit turns on or off the first transistor and the second transistor through the first word line and the second word line.
  • an embodiment of the present application provides an electronic device, which includes the memory described in any one of the foregoing.
  • the memory can realize multi-port reading and can handle a write request.
  • the read operation is more frequent and more important than the write operation. Therefore, in the memory provided by the embodiment of the present application, for the operating characteristics of the memory, a multi-port read is realized through the first transistor and the second transistor provided. Take, single port write.
  • the memory provided by the embodiment of the present application can satisfy the reading and writing of storage, and by using the turn-on current of the first transistor 21
  • the turn-on current of the second transistor 22 and the second transistor 22 are both smaller than the write current of the memory cell.
  • the write current provided by two transistors can make the smaller transistor meet the demand. , which reduces the area required for the entire memory.
  • the memory of the present application can still support dual-port characteristics in read operations. Compared with using separate two transistors for reading and writing in the prior art, the area occupied by the memory is greatly reduced.
  • the number of storage structures in the memory is multiple, and the multiple storage structures are arranged in an array.
  • the area of the memory is reduced, and at the same time, it is convenient to write and read data in the memory.
  • FIG. 6 shows the layout corresponding to a column of memory in FIG. 5.
  • the first transistor 21 in the adjacent storage structure is adjacent, and the corresponding second transistor 22 is also adjacently arranged. As shown in the first storage structure in FIG. 6, the first transistor 21 of the storage structure is located above and the second transistor 22 is located below.
  • the second transistor 22 is located above and the first transistor 21
  • the third storage structure is set, the first transistor 21 is located above and the second transistor 22 is located below.
  • the transistors of the storage structure are arranged in this order, so that when the transistors are arranged in a column, except for the transistors at the end
  • the first transistor 21 and the second transistor 22 appear as a pair.
  • the first transistor 21 in the column of memory is connected to WLA, and the second transistor 22 is connected to WLB. And when reading data, the data of one address is read through WLA and the data of another address is read through WLB. Therefore, the two first transistors 21 in adjacent memories will not be supplied with power at the same time. , The two second transistors 22 will not supply power at the same time.
  • the memory provided by the embodiment of the present application may use the second transistor 22 in two adjacent storage structures to share a contact hole to be connected to the BLB, and the first transistor 21 in two adjacent storage structures to share a contact hole It is connected with the BLA, which can further reduce the size of the storage structure arranged in the array, and facilitate the miniaturization of the storage structure array.
  • each column in the array is formed by closely splicing memory structures. Adjacent memory structure contact holes are shared with each other to connect with bit lines, and word lines are arranged in the order of ABBA, that is, the arrangement of transistors The first transistor 21, the second transistor 22, the second transistor 22, and the first transistor 21 are arranged in a manner.
  • FIG. 7 also shows a peripheral circuit. It should be understood that FIG. 7 is only for the convenience of understanding one of the peripheral circuits listed in the memory structure array provided by the embodiment of the application. The memory provided in the embodiment of the application may Other existing circuits are used to connect with the array in the storage structure.
  • the array and peripheral circuits are controlled by two sets of port signals, with their own clock, address, and data signals.
  • Enable signal A and enable signal B, clock signal A and clock signal B, address signal A and address signal B are respectively connected to row decoder 70 (Row Decoder) and column decoder through predecoder 60 (PreDecoder) ⁇ 50 and multiplexer.
  • the output signal of the row decoder 70 is connected to the word line signal in the array.
  • the column decoder 50 and the multiplexer are connected to the bit lines and source lines in the array.
  • the signal on the bit line passes through the column decoder 50 and the multiplexer, and then is recognized by the sensitive amplifier 30 and converted into output signal A and output signal B; when writing, when the write enable signal When the A and the write enable signal B are valid, the data A and the data B are connected to the column to be written from the write drive circuit 40 through the column decoder 50 and the multiplexer.
  • each signal in a certain write cycle is as follows: enable signal A and enable signal B are the same and valid, write enable signal A and write enable signal B are the same and valid, and when clock signal A and clock signal Before the rising edge of signal B arrives, address signal A and address signal B, as well as data A and data B to be written are ready; at the moment of the rising edge of the clock, the address signal and data to be written are read, and at a certain time After that, the data to be written will be successfully written to the corresponding address.
  • the memory provided in the embodiment of the present application can implement multi-port reading and can process one write request.
  • the read operation is more frequent and more important than the write operation. Therefore, in the memory provided by the embodiment of the present application, for the operating characteristics of the memory, a multi-port read is realized through the first transistor and the second transistor provided. Take, single port write.
  • the memory provided by the embodiment of the present application can satisfy the reading and writing of storage, and by using the turn-on current of the first transistor 21
  • the turn-on current of the second transistor 22 and the second transistor 22 are both smaller than the write current of the memory cell.
  • the write current provided by two transistors can make the smaller transistor meet the demand. , which reduces the area required for the entire memory.
  • the memory of the present application can still support dual-port characteristics in read operations. Compared with using separate two transistors for reading and writing in the prior art, the area occupied by the memory is greatly reduced.
  • an embodiment of the present application also provides an electronic device, which includes the above-mentioned memory, and the memory can realize multi-port reading and can process a write request.
  • the read operation is more frequent and more important than the write operation. Therefore, in the memory provided by the embodiment of the present application, for the operating characteristics of the memory, a multi-port read is realized through the first transistor and the second transistor provided. Take, single port write.
  • the memory provided by the embodiment of the present application can satisfy the reading and writing of storage, and by using the turn-on current of the first transistor 21 The turn-on current of the second transistor 22 and the second transistor 22 are both smaller than the write current of the memory cell.
  • the write current provided by two transistors can make the smaller transistor meet the demand. , which reduces the area required for the entire memory.
  • the memory of the present application can still support dual-port characteristics in read operations. Compared with using separate two transistors for reading and writing in the prior art, the area occupied by the memory is greatly reduced.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种存储器及电子设备，该存储器包括存储单元（10）、第一晶体管（21）、第二晶体管（22）、第一位线（BLA）、第二位线（BLB），其中，所述存储单元（10）通过所述第一晶体管（21）和所述第二晶体管（22）被分别耦合至所述第一位线（BLA）和第二位线（BLB），所述第一晶体管（21）和第二晶体管（22）在写操作时导通。在采用上述方案时，相对于通过一个晶体管来提供需要的写入电流，通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，所述存储器照样能在读操作中支持双端口的特性。

Description

一种存储器及电子设备 技术领域
本申请涉及信息技术领域，尤其涉及一种存储器及电子设备。
背景技术
Spin-transfer torque magnetic random access memory(STT-MRAM，自旋转移矩磁存储器)是一种极具潜力的新型存储器，具有读取速度较快，耐久周期数(endurance)长，集成度高，与互补金属氧化物半导体工艺兼容等优点。
如图1a及图1b所示，Magnetic tunnel junction(MTJ，磁隧道结)是STT-MRAM中的存储单元10，其通常由两层铁磁层中间夹一层很薄的隧穿氧化层12(例如氧化镁)组成。其中一层铁磁层其磁化沿易磁化轴方向是固定的，称为固定层13；另一层铁磁层其磁化可以在两个取向间自由翻转，称为自由层11。继续参考图1a及图1b，其中箭头的指向代表了磁化取向，当自由层11的磁化取向与固定层13的磁化取向相同时，如图1a所示，MTJ的电阻呈现较低的阻值，当自由层11的磁化取向与固定层13的磁化取向相反时，如图1b所示，MTJ的电阻呈现较高的阻值。
如图2所示，在STT-MRAM中，存储单元通常为由一个晶体管和一个MTJ组成的1T1MTJ结构，其有三个端点，分别连接字线(Word Line，WL)、位线(Bit Line，BL)、源线(Source Line，SL)。读取时，存储信息取决于读取到的MTJ阻值，其电流方向可以是任意的；写入时，写入特定的状态(AP或P)需要采用相对应的电流方向(图2)。
在一些应用中，例如多核系统，有时需要同时对一块存储阵列中的地址进行读取，这时就需要该阵列具有多个端口。现有的几种常用的方法可以增加存储器的带宽，但同时也会造成其他指标的下降。例如，可以通过增加存储阵列的输入输出目来提升带宽，但是这会造成存储器版图显得扁平，读取延时也会有一定的增加，而且输入输出数目能够增大的范围是有限的。又如，可以通过减小阵列的尺寸从而增加阵列的总数来提高带宽，但是这会增加外围电路的占比，从而增加整个存储器的面积。
发明内容
本申请提供一种存储器，用以降低存储器的尺寸。
第一方面，提供了一种存储器，该存储器包括一个用于存储数据的存储单元，还包括两个用于写入或者读取存储单元的晶体管，两个晶体管分别为第一晶体管及第二晶体管，还包括两个位线，分别为第一位线及第二位线。其中，存储单元通过第一晶体管及第二晶体管分别被耦合至第一位线及第二位线。该第一晶体管及第二晶体管用于控制存储单元的写入及读取，在写入时，第一晶体管及第二晶体管在写操作时一起导通。在读取时，第一晶体管及第二晶体管中的一个在读取操作时导通。其中，在写入时，所述第一晶体管的开启电流及所述第二晶体管的开启电流均小于所述存储单元的写入电流，且所述第一晶体管的开启电流与所述第二晶体管的开启电流之和大于1 倍的所述存储单元的写入电流且小于2倍所述存储单元的写入电流。从而两个晶体管并联使用时刚好能够提供与存储单元所需的写入电流。相对于通过一个晶体管来提供需要的写入电流，通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，本申请的存储器照样能在读操作中支持双端口的特性。
需要注意的是，本申请中所述的“第一晶体管及第二晶体管一起导通”是指在写操作的过程中的某个时刻，所述第一晶体管和第二晶体管均处于导通状态，从而提供足够的写入电流。
在一个具体的可实施方案中，该存储器还包括第一字线和第二字线，其中，第一字线及第二字线分别耦合至第一晶体管及第二晶体管的栅极，即第一字线耦合至第一晶体管的栅极，第二字线耦合至第二晶体管的栅极。
在一个具体的可实施方案中，存储器还包括控制电路，该控制电路用于控制第一晶体管及第二晶体管的通断，具体的，该控制电路通过第一字线和第二字线来分别导通或关断所述的第一晶体管和第二晶体管。通过控制电路的控制来实现写操作以及读取操作。
在一个具体的可实施方案中，存储单元包括第一端及第二端，其中，第一端被耦合至第一晶体管及第二晶体管，而第二端被耦合至源线。
在具体设置该第一晶体管及第二晶体管的源漏极时，该第一晶体管及所述第二晶体管共用有源区。因此，上述的第一晶体管及第二晶体管的源漏极设置在同一有源区。
该第一晶体管及第二晶体管为相同类型的晶体管，如所述第一晶体管及所述第二晶体管均为鳍片型晶体管或第一晶体管及第二晶体管均为平面型晶体管。
第二方面，提供了一种电子设备，该电子设备包括上述任一项所述的存储器。通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，本申请的存储器照样能在读操作中支持双端口的特性。
第三方面，提供了一种存储器，该存储器包括排布成矩形阵列的多个存储结构，以及，与所述矩形阵列的多个列一一对应的多组位线，每组位线包括第一位线和第二位线；而其中的多个存储结构中的每一个存储结构均包括存储单元，第一晶体管和第二晶体管：其中，根据存储结构在所述矩形阵列中所处的行，所述存储单元通过所述第一晶体管和第二晶体管被分别耦合至对应的第一位线和第二位线；并且所述第一晶体管和第二晶体管在对所述存储单元写操作时一起导通。其中，在写入时，所述第一晶体管的开启电流及所述第二晶体管的开启电流均小于所述存储单元的写入电流，且所述第一晶体管的开启电流与所述第二晶体管的开启电流之和大于1倍的所述存储单元的写入电流且小于2倍所述存储单元的写入电流。从而两个晶体管并联使用时刚好能够提供与存储单元所需的写入电流；在读取数据时，可以通过任意一个晶体管进行读取。在采用上述方案时，实现了通过在读取时，能够采用两个端口读取，在写入时，可以处理一个写请求，并且在采用该结构时，可以改善第一晶体管及第二晶体管的结构，使得存储器的面积可以与传统的单端口存储器的面积类似，降低了整个存储器的面积。
在一个具体的可实施方案中，所述存储器还包括与所述矩形阵列的多个行一一对应的多组字线，每组字线包括第一字线和第二字线，根据存储结构在所述矩形阵列中 所处的行，所述第一晶体管和第二晶体管的栅极被分别耦合至对应的第一字线和第二字线。
在具体实现写操作与读取操作时，所述存储器还包括控制电路，所述控制电路用于通过第一字线和第二字线来导通或关断第一晶体管和第二晶体管。通过控制电路实现对写操作与读取操作的控制。
在一个具体的可实施方案中，所述存储单元为磁隧道结。
在一个具体的可实施方案中，在每列存储结构中，除位于首尾两端的晶体管外，第一晶体管及第二晶体管成对交替排列。
并且在设置时，所述第一晶体管及第二晶体管共用有源区。从而更进一步的降低存储器的面积。
在具体设置位线时，相邻的第一晶体管共用第一接触孔与所述第一位线连接；相邻的第二晶体管共用第二接触孔与所述第二位线连接。更进一步的降低了存储器的面积。
第四方面，提供了一种电子设备，该电子设备包括上述任一项所述的存储器。通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，本申请的存储器照样能在读操作中支持双端口的特性。
附图说明
图1a及图1b为现有技术中的MTJ结构；
图2为现有技术中的存储器的结构示意图；
图3为本申请提供的存储器的结构示意图；
图4为本申请实施例提供的存储器的版图；
图5为本申请提供的存储器阵列的示意图；
图6为本申请提供的存储器阵列的版图；
图7为本申请实施例提供的存储器的示意图；
图8为本申请实施例提供的存储器的读取时序图；
图9为本申请实施例提供的存储器的写入时序图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
为了方便理解本申请实施例提供的存储器，下面首先说明一下本申请实施例提供的存储器的应用场景，该存储器应用于存储数据，可以进行数据的写入以及读取。在存储器使用时，往往排列成阵列，当需要同时进行多个地址读取时，需要采用多端口。当需要读取第一行存储器及第二行存储器时，需要两个位线分别读取存储器。这就需要存储器具备两个端口，为了适应多端口，本申请实施例提供了一种存储器，下面结合附图对其进行详细的说明。
参考图3，图3示出了本申请实施例提供的存储器的结构，该存储器包括一个用于存储数据的存储单元，在图3所示结构中，该存储单元为Magnetic tunnel junction (MTJ，磁隧道结)。一并参考图1a及图1b，图1a及图1b示出了该存储单元10，该存储单元10通常由两层铁磁层，以及夹在两层铁磁层之间的一层很薄的隧穿氧化层12(例如MgO)组成。在设置时，其中的一层铁磁层的磁化方向是固定，称为固定层13；另一层铁磁层其磁化可以在两个取向间自由翻转，称为自由层11。当自由层11的磁化取向与固定层13的磁化取向相同时，如图1a所示，MTJ的电阻呈现较低的阻值，当自由层11的磁化取向与固定层13的磁化取向相反时，如图1b所示，MTJ的电阻呈现较高的阻值。在存储单元10被读取时，存储信息取决于读取到的MTJ阻值，其电流方向可以是任意的；但是在存储单元10被写入时，写入特定的状态(AP或P)需要采用相对应的电流方向，并且满足存储单元10的写入电流才能进行写入。
在具体控制写入以及读取时，在本申请实施例提供的存储器采用晶体管进行控制，并且为了对应多端口，在本申请实施例提供的存储器中，设置了两个晶体管，以及两个位线。为了方便描述两个晶体管及位线，将两个晶体管分别命名为第一晶体管21及第二晶体管22，两个位线分别命名为第一位线(BLA)和第二位线(BLB)；在连接时，存储单元10通过第一晶体管21和第二晶体管22被分别耦合至第一位线BLA及第二位线BLB。其中，每个晶体管包含栅极、源极和漏极；其中，栅极用于控制源极和漏极之间的沟道导通形成通路。该晶体管在具体设置时，可以采用鳍片型晶体管或者平面型晶体管。
该存储器还包括第一字线(WLA)和第二字线(WLB)，在第一晶体管21及第二晶体管22与存储单元连接时，其中的第一晶体管21的栅极连接了WLA，源漏极分别与BLA及存储单元(MTJ)连接；在具体连接时，可以是源极与BLA连接，而漏极与存储单元的固定层13(第一端)连接，或者还可以采用漏极与BLA连接，而源极与存储单元的固定层13(第一端)连接。而第二晶体管22在与存储单元连接时，该第二晶体管22的栅极与WLB连接，源漏极分别与BLB及存储单元连接；在具体连接时，可以是第二晶体管22的源极与BLB连接，而第二晶体管22的漏极与存储单元的固定层13(第一端)连接，或者还可以采用漏极与BLB连接，而源极与存储单元连接。第一晶体管21的源极及第二晶体管22可以同时采用P型晶体管，或者同时采用N型晶体管；优选的，第一晶体管21的源极及第二晶体管22的源极与存储单元连接，或第一晶体管21的漏极及第二晶体管22的漏极与存储单元连接。
为了直观地了解第一晶体管21及第二晶体管22与存储单元的连接，一并参考图3及图4，其中，图3示出了第一晶体管21及第二晶体管22与存储单元连接时的原理图，而图4示出了第一晶体管21及第二晶体管22与存储单元连接时的版图。首先参考图3，由图3可以看出，第一晶体管21及第二晶体管22并联。其中，第一晶体管21的栅极连接了WLA，第二晶体管22的栅极连接了WLB；而第一晶体管21的源极连接了BLA，第二晶体管22的源极连接了BLB，并且第一晶体管21的漏极与第二晶体管22的漏极同时与存储单元的固定层13(第一端)连接，或者第一晶体管21的源极与第二晶体管22的源极同时与存储单元的固定层13(第一端)连接。此外，存储单元的自由层11(第二端)与源线(SL)连接。
在具体设置第一晶体管21及第二晶体管22时，该第一晶体管21和第二晶体管22在写操作时一起导通，需要注意的是，本申请中所述的“第一晶体管及第二晶体管一起导通”是指在写操作的过程中的某个时刻，所述第一晶体管和第二晶体管均处于 导通状态，从而提供足够的写入电流。因此，在设置第一晶体管21及第二晶体管22时，本申请实施例提供的第一晶体管21的开启电流及第二晶体管22的开启电流均小于存储单元的写入电流，且第一晶体管21的开启电流与第二晶体管22的开启电流之和大于等于1倍的存储单元的写入电流且小于2倍存储单元的写入电流。为了方便描述，经第一晶体管21的开启电流命名为I1，第二晶体管22的开启电流命名为I2，存储单元的写入电流命名为I3，此时，I1、I2、I3满足：I3≤I1+I2＜2倍I3。还可以采用I1、I2、I3满足：I3≤I1+I2≤1.5倍I3。在具体设置时，I1+I2可以为I3、1.2倍I3、1.4倍I3或者1.5倍I3等不同的数值。在一个具体的实施方案中，该第一晶体管21的开启电流I1与第二晶体管22的开启电流I2满足：I1+I2＝I3。并且在设置时，采用第一晶体管21的开启电流及第二晶体管22的开启电流相等，即I1＝I2。
对于平面型晶体管来说，决定其开启电流的因素是晶体管的沟道的宽度，因此，在现有技术中通过单个晶体管控制存储单元进行写操作时，每个晶体管的开启电流至少等于存储单元的写入电流，而在本申请实施例中，第一晶体管及第二晶体管的开启电流均小于存储单元的写入电流，因此，本申请实施例提供的每个晶体管的沟道宽度小于现有技术中的采用的晶体管的沟道的宽度。在I1＝I2时，第一晶体管21的沟道宽度与第二晶体管22的沟道宽度相等，并且可以等于现有技术中的单端口的存储器中的晶体管的沟道宽度的一半。而在本申请实施例提供的晶体管，每个晶体管的源漏极均设置在了有源区23，因此，晶体管的沟道宽度可以等效成有源区23的宽度。而在本申请实施例提供的结构中，如图4中所示，第一晶体管21的有源区23及第二晶体管22的有源区23可以共用，即第一晶体管21及第二晶体管22采用同一个有源区23，当然，也可以采用第一晶体管21的有源区23及第二晶体管22的有源区不共用，此时，第一晶体管21及第二晶体管22分别对应一个有源区。
一并参考图4，其中，图4示出了存储器的版图。为了方便描述，建立了XY坐标系，在图4所示的结构中第一晶体管21及第二晶体管22均为平面型晶体管，且两个晶体管的有源区23共用，因此，沟道的宽度可以等效成有源区23的宽度，如图4中所示，由于第一晶体管21及第二晶体管22的有源区23共用，第一晶体管21及第二晶体管22的沟道的宽度相等，即I1＝I2。继续参考图4，在图4中还示出了WLA和WLB的位置关系，由图4可以看出，该WLA和WLB横向布置，并沿Y方向上排列，而SL竖直布置，且多个SL沿X方向排列。为了方便理解本申请实施例提供的上述存储器，本申请实施例详细描述一下该存储器在进行写操作和读取操作时的过程。在进行写操作和读取操作时，存储器还包括控制电路70，控制电路70用于通过第一字线和第二字线来分别导通或关断第一晶体管和第二晶体管。即通过控制电路70来实现对第一晶体管和第二晶体管的控制。
在读取时，打开所述第一晶体管、或打开所述第二晶体管、或同时打开第一晶体管及第二晶体管，读取所述存储单元。
例如，要通过WLA进行读取时，WLA电位置高，SL接到低电位，BLA电位置于读取电位Vr；接着灵敏放大器(存储器连接的外围电路)会将流过BLA上的读取电流与参考支路上的电流进行比较来判断存储单元中存储的信息。通过WLB进行读取的方法与之类似，并且WLA和WLB即使对同一单元进行读取也不会造成相互干扰，因此本申请的存储单元最多可以支持对两个地址同时进行读取。如图5中所示，在读 取时可以通过对不同行的存储器进行读取，以图5中的第一行存储器100及第二行存储器200为例，在读取时，采用BLA对第一行存储器100进行读取，同时，采用BLB对第二行存储器200进行读取。其中，在存储器阵列排列时，WLA指的是与每个存储器中的第一晶体管21连接的字线，而WLB指的是与每个存储器中的第二晶体管22连接的字线。并且针对不同的行用WLnA、WLnB表示，其中，n为大于等于1的正整数。同样的对于成列排列的位线也是，不同列的位线，用BLmA与BLmB表示，对于不同列的源线，用SLm表示，其中，m为大于等于1的正整数。
在写入时，同时打开所述第一晶体管及所述第二晶体管，写入所述存储单元。此时，WLA和WLB同时置于高电平，并且BLA和BLB也置于相同电位，例如对于参考层在底层的磁隧道结，在写入P态时，BLA、BLB同时为低电位，SL接高电平；在写AP态时，BLA、BLB同时接高电平，而SL接低电位。此时，第一晶体管21的开启电流I1与第二晶体管22的开启电流I2并联后的总和是等于流过存储单元的电流，由于该第一晶体管21的开启电流I1与第二晶体管22的开启电流I2大于等于存储单元的写入电流I3，此时可以对存储单元进行写入。
通过上述描述可以看出，在本申请实施例提供的存储器可以实现多端口的读取，并且可以处理一个写入请求。而对于存储器来说，读取操作比写入操作更频繁，也更重要，因此，在本申请实施例提供的存储器针对存储器的工作特性，通过设置的第一晶体管及第二晶体管实现多端口读取，单端口写入。相比与现有技术中，采用两个晶体管单独进行读取和写入来说，本申请实施例提供的存储器可以满足对存储的读取以及写入，并且通过采用第一晶体管21的开启电流及第二晶体管22的开启电流均小于存储单元的写入电流，相对于通过一个晶体管来提供需要的写入电流，通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，本申请的存储器照样能在读操作中支持双端口的特性。相比与现有技术中采用单独的两个晶体管进行读取和写入来说，极大的降低了存储器的占用的面积。
应当理解的是，在上述实施例中，以第一晶体管21及第二晶体管22均为平面型晶体管为例进行的说明，但是在本申请实施例提供的第一晶体管21及第二晶体管22还可以采用其他类型的晶体管，如该第一晶体管及第二晶体管还可以为鳍片型晶体管，该鳍片型晶体管的作用与上述描述的晶体管的作用相近似，在此不予赘述。第一晶体管21及第二晶体管22可以考虑同时选用平面型晶体管，或者，第一晶体管21及第二晶体管22同时采用鳍片型晶体管。
对于存储单元，除了上述列举的MTJ外，还可以采用其他类型的存储单元，例如阻变存储单元(Resistive Random Access Memory，(RRAM))，也可以实现同样的效果。
此外，本申请实施例还提供了一种存储器，该存储器包括排布成矩形阵列的多个存储结构，以及，与矩形阵列的多个列一一对应的多组位线，每组位线包括第一位线和第二位线；多个存储结构中的每一个均包括存储单元，第一晶体管和第二晶体管：根据存储结构在矩形阵列中所处的行，存储单元通过第一晶体管和第二晶体管被分别耦合至对应的第一位线和第二位线，第一晶体管和第二晶体管在写操作时同时导通。
在具体设置该存储器时，存储器还包括与矩形阵列的多个行一一对应的多组字线，每组字线包括第一字线和第二字线，根据存储结构在矩形阵列中所处的行，第一晶体 管和第二晶体管的栅极被分别耦合至对应的第一字线和第二字线。在具体到每个存储单元与第一晶体管、第二晶体管及第一字线、第二字线、第一位线、第二位线的连接方式，可以参考上述针对图3及图5中对应的描述。且在进行写入操作和读取操作时，第一晶体管及第二晶体管的工作方式也相同，因此，在此不予赘述。此外，在具体实现对第一晶体管及第二晶体管的控制时，也是通过控制电路，该控制电路通过第一字线及第二字线来导通或关断第一晶体管和第二晶体管。
此外，本申请实施例提供了一种电子设备，该电子设备包括上述的任一项所述的存储器。在采用上述存储器时，存储器可以实现多端口的读取，并且可以处理一个写入请求。而对于存储器来说，读取操作比写入操作更频繁，也更重要，因此，在本申请实施例提供的存储器针对存储器的工作特性，通过设置的第一晶体管及第二晶体管实现多端口读取，单端口写入。相比与现有技术中，采用两个晶体管单独进行读取和写入来说，本申请实施例提供的存储器可以满足对存储的读取以及写入，并且通过采用第一晶体管21的开启电流及第二晶体管22的开启电流均小于存储单元的写入电流，相对于通过一个晶体管来提供需要的写入电流，通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，本申请的存储器照样能在读操作中支持双端口的特性。相比与现有技术中采用单独的两个晶体管进行读取和写入来说，极大的降低了存储器的占用的面积。
如图7中所示，该存储器中的存储结构的个数为多个，并且多个存储结构采用阵列排列。从而降低存储器的面积，同时方便对存储器的数据进行写入以及读取。
存储器在读取时，不存在两个WLA或者两个WLB同时有效的情况，因此，在设置阵列的存储结构时，可以将相邻存储结构中的晶体管共用有源区，并且两个相邻的存储器中的第二晶体管22的源漏极可以通过一个接触孔连接在BLB或BLA上。结合到图6的版图中，图6示出了图5中一列存储器对应的版图。在本申请实施例提供的存储器中，对于每一列存储结构在设置时，采用相邻的存储结构中的第一晶体管21相邻，对应的第二晶体管22也进行相邻设置。如图6中的第一个存储结构，该存储结构的第一晶体管21位于上方，第二晶体管22位于下方，对应在设置第二个存储结构时，第二晶体管22位于上方，第一晶体管21位于下方，在设置第三个存储结构时，第一晶体管21位于上方，第二晶体管22位于下方，按照此顺序依次排列存储结构的晶体管，使得晶体管在排列成列时，除了首尾端部的晶体管外，第一晶体管21及第二晶体管22成对出现。
此外，在一列存储器中，如图5中所示，该列存储器中的第一晶体管21与WLA连接，第二晶体管22与WLB连接。且在读取数据时，通过WLA读取一个地址的数据，通过WLB读取另一个地址的数据，因此，相邻的存储器中的两个第一晶体管21不会出现同时供电的情况，同样的，两个第二晶体管22不会出现同时供电的情况。因此，本申请实施例提供的存储器可以采用两个相邻的存储结构中的第二晶体管22共用一个接触孔与BLB连接，并且两个相邻的存储结构中的第一晶体管21共用一个接触孔与BLA连接，从而可以更进一步的减小阵列排列的存储结构的尺寸，便于存储结构阵列的小型化。
继续参考图7，该阵列中的每一列都是由存储结构紧密拼接而成，相邻的存储结构接触孔相互共用以与位线连接，字线则以ABBA的顺序进行排列，即晶体管的排列 方式为第一晶体管21、第二晶体管22、第二晶体管22、第一晶体管21的方式进行排列。此外，该图7中还示出了外围电路，应当理解的是，图7仅仅为了方便理解本申请实施例提供的存储结构阵列所列举的一种外围电路，在本申请实施例提供的存储器可以采用现有的其他电路来与存储结构中的阵列连接。以图7为例，阵列及外围电路受两套端口信号控制，有各自的时钟、地址、数据信号。使能信号A和使能信号B、时钟信号A和时钟信号B、地址信号A和地址信号B分别通过预译码器60(PreDecoder)连接到行译码器70(Row Decoder)和列译码器50以及多路选通器。行译码器70的输出信号与阵列中的字线信号相连。列译码器50和多路选通器与阵列中的位线和源线相连。在读取时，位线上的信号通过列译码器50和多路选通器，进而被灵敏放大器30识别并转换成输出信号A和输出信号B；在写入时，在写使能信号A和写使能信号B有效的情况下，数据A和数据B从写驱动电路40通过列译码器50和多路选通器连接到待写入的列。
对于读取操作，由于每个存储结构中的两个晶体管分别连接的是两个端口的字线和位线，因此整个阵列最多可以同时对两个地址进行读取。一种可能的读取时序如下图8所示。假设考虑A这套信号，在某一个读取周期内各信号的操作如下：使能信号A有效，写使能信号A置于无效位，在时钟信号(A上升沿到来前，地址信号A就已经准备好；在时钟上升沿那一刻，地址信号被读取，并且在一定时间之后相应地址内的数据被读出到输出信号A，完成读出。
对于写入操作，由于每个存储结构中的两个晶体管必须并联使用以提供足够的写入电流，在写入时两个端口的地址信号和数据信号必须相同(可以由内部电路实现)，将同一个存储结构的两个晶体管同时打开，两根位线置于相同的逻辑值来实现写入。一次只能处理一个写入请求。一种可能的写入时序如下图9所示。在某一个写入周期(twcycle)内各信号的操作如下：使能信号A和使能信号B相同且有效，写使能信号A和写使能信号B相同且有效，在时钟信号A和时钟信号B上升沿到来前，地址信号A和地址信号B以及待写入数据A和数据B就已经准备好；在时钟上升沿那一刻，地址信号和待写入数据被读取，并且在一定时间之后会成功将待写入数据写入到相应地址内。
通过上述描述可以看出，在本申请实施例提供的存储器可以实现多端口的读取，并且可以处理一个写入请求。而对于存储器来说，读取操作比写入操作更频繁，也更重要，因此，在本申请实施例提供的存储器针对存储器的工作特性，通过设置的第一晶体管及第二晶体管实现多端口读取，单端口写入。相比与现有技术中，采用两个晶体管单独进行读取和写入来说，本申请实施例提供的存储器可以满足对存储的读取以及写入，并且通过采用第一晶体管21的开启电流及第二晶体管22的开启电流均小于存储单元的写入电流，相对于通过一个晶体管来提供需要的写入电流，通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，本申请的存储器照样能在读操作中支持双端口的特性。相比与现有技术中采用单独的两个晶体管进行读取和写入来说，极大的降低了存储器的占用的面积。
此外，本申请实施例还提供了一种电子设备，该电子设备包括上述的存储器，该存储器可以实现多端口的读取，并且可以处理一个写入请求。而对于存储器来说，读取操作比写入操作更频繁，也更重要，因此，在本申请实施例提供的存储器针对存储 器的工作特性，通过设置的第一晶体管及第二晶体管实现多端口读取，单端口写入。相比与现有技术中，采用两个晶体管单独进行读取和写入来说，本申请实施例提供的存储器可以满足对存储的读取以及写入，并且通过采用第一晶体管21的开启电流及第二晶体管22的开启电流均小于存储单元的写入电流，相对于通过一个晶体管来提供需要的写入电流，通过两个晶体管来提供写入电流，可以使得更小的晶体管就能满足需求，降低了整个存储器需要的面积。同时，本申请的存储器照样能在读操作中支持双端口的特性。相比与现有技术中采用单独的两个晶体管进行读取和写入来说，极大的降低了存储器的占用的面积。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种存储器，其特征在于，包括：存储单元、第一晶体管、第二晶体管，第一位线，第二位线，其中，
    所述存储单元通过所述第一晶体管和所述第二晶体管被分别耦合至所述第一位线和第二位线，
    所述第一晶体管和第二晶体管在对所述存储单元写操作时一起导通。
  2. 如权利要求1所述的存储器，其特征在于，所述存储器还包括第一字线和第二字线，所述第一字线和第二字线被分别耦合至所述第一晶体管和第二晶体管的栅极。
  3. 如权利要求2所述的存储器，其特征在于，所述存储器还包括控制电路，所述控制电路用于通过所述第一字线和第二字线来分别导通或关断所述第一晶体管和第二晶体管。
  4. 如权利要求1-3任一项所述的存储器，其特征在于，所述存储单元为磁隧道结。
  5. 如权利要求1-4任一项所述的存储器，其特征在于，所述存储单元包括第一端和第二端，所述第一端被耦合至所述第一晶体管和第二晶体管，
    所述存储器还包括源线，
    所述第二端被耦合至所述源线。
  6. 如权利要求1-5任一项所述的存储器，其特征在于，所述第一晶体管及所述第二晶体管共用有源区。
  7. 如权利要求1-6任一项所述的存储器，其特征在于，所述第一晶体管及所述第二晶体管均为鳍片型晶体管或均为平面型晶体管。
  8. 一种电子设备，其特征在于，包括如权利要求1-7任意一项所述的存储器。
  9. 一种存储器，其特征在于，所述存储器包括排布成矩形阵列的多个存储结构，以及，与所述矩形阵列的多个列一一对应的多组位线，每组位线包括第一位线和第二位线；
    所述多个存储结构中的每一个均包括存储单元，第一晶体管和第二晶体管：
    根据存储结构在所述矩形阵列中所处的行，所述存储单元通过所述第一晶体管和第二晶体管被分别耦合至对应的第一位线和第二位线，
    所述第一晶体管和第二晶体管在对所述存储单元写操作时一起导通。
  10. 如权利要求9所述的存储器，其特征在于，所述存储器还包括与所述矩形阵列的多个行一一对应的多组字线，每组字线包括第一字线和第二字线，根据存储结构 在所述矩形阵列中所处的行，所述第一晶体管和第二晶体管的栅极被分别耦合至对应的第一字线和第二字线。
  11. 如权利要求10所述的存储器，其特征在于，所述存储器还包括控制电路，所述控制电路用于通过第一字线和第二字线来导通或关断第一晶体管和第二晶体管。
  12. 如权利要求8-11任一项所述的存储器，其特征在于，在每列存储结构中，除位于首尾两端的晶体管外，其余的所述第一晶体管及所述第二晶体管成对交替排列。
  13. 如权利要求12所述的存储器，其特征在于，所述第一晶体管及所述第二晶体管共用有源区。
  14. 如权利要求12所述的存储器，其特征在于，相邻的第一晶体管共用第一接触孔与所述第一位线连接；相邻的第二晶体管共用第二接触孔与所述第二位线连接。
  15. 一种电子设备，其特征在于，包括如权利要求9-14任意一项所述的存储器。
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