CN105244352A - 可高度微缩的单层多晶硅非易失性存储单元 - Google Patents

可高度微缩的单层多晶硅非易失性存储单元 Download PDF

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CN105244352A
CN105244352A CN201510394078.0A CN201510394078A CN105244352A CN 105244352 A CN105244352 A CN 105244352A CN 201510394078 A CN201510394078 A CN 201510394078A CN 105244352 A CN105244352 A CN 105244352A
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memory cell
volatile memory
oxide definition
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CN105244352B (zh
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徐德训
黎俊霄
陈学威
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eMemory Technology Inc
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Abstract

本发明公开了一种单层多晶硅非易失性存储单元，包括半导体衬底；第一氧化物定义区及第二氧化物定义区；隔离区域，分隔第一氧化物定义区及第二氧化物定义区；PMOS选择晶体管设于第一氧化物定义区上；PMOS浮动栅极晶体管设于第一氧化物定义区上并与PMOS选择晶体管串联；PMOS浮动栅极晶体管包括一浮动栅极；存储器P型阱区位于半导体衬底中；存储器N型阱区位于存储器P型阱区中；存储器P型阱区与第一氧化物定义区及第二氧化物定义区重叠；存储器P型阱区的接合深度比隔离区域的沟渠深度深；存储器N型阱区的接合深度比隔离区域的沟渠深度浅。

Description

可高度微缩的单层多晶硅非易失性存储单元
技术领域
本发明涉及半导体存储器技术领域，特别涉及一种可高度微缩的单层多晶硅非易失性存储单元，其具有更小的(＜1μm2)存储单元尺寸，同时能够维持原本的存储器特性。
背景技术
随着科技发展，半导体存储器器件已应用于各种电子装置。例如，非易失性存储器(NVM)已被广泛使用在手机、数位相机、个人数位助理、行动运算装置，以及其他电子产品中。
非易失性存储器器件大致上分成多次编程存储器(MTP)和单次编程存储器(OTP)。多次编程存储器(MTP)可多次读取和编程，例如电可擦可编程只读存储器(EEPROM)和闪存被设计具有相关的电子电路，可支援不同的操作，例如编程，擦除和读取。单次编程存储器(OTP)具有编程和读取功能的电子电路，但并不具备擦除功能的电子电路。
单层多晶硅非易失性存储器结构因为可减少额外工艺步骤而被提出来。单层多晶硅非易失性存储器用单层多晶硅形成存储电荷的浮动栅极，可和一般互补式金氧半导体场效晶体管(CMOS)工艺相容，因此可应用在嵌入式存储器、混合模式电路的嵌入式非易失性存储器，以及微控制器(例如系统整合芯片，SOC)等领域。
非易失性存储器的单位位元平均成本随着单位位元的尺寸缩小而降低，因此本领域中，追求尺寸越来越小的非易失性存储器器件是目前的技术趋势。然而，非易失性存储器器件可微缩程度受到输入/输出(I/O)离子阱注入设计规范的限制。通常所述离子阱注入需将掺杂注入到衬底中，到达比存储器阵列区域的浅沟渠隔离深度更深的接合深度。
发明内容
本发明的主要目的为提供一改良的单层多晶硅多次编程非易失性存储单元，其存储单元尺寸能够小于1μm2。
本发明另一个目的为提供一改良的单层多晶硅多次编程非易失性存储单元，具有缩小的存储单元尺寸，不受限于输入/输出(I/O)离子阱注入设计规范。
根据本发明提供的单层多晶硅非易失性存储单元，包括一半导体衬底；一第一氧化物定义区及一第二氧化物定义区；一隔离区域分隔所述第一氧化物定义区及所述第二氧化物定义区，且所述隔离区域具有一沟渠深度；一PMOS选择晶体管设于所述一第一氧化物定义区上；一PMOS浮动栅极晶体管设于所述第一氧化物定义区上并与所述PMOS选择晶体管串联，其中所述PMOS浮动栅极晶体管包括一覆盖在所述第一氧化物定义区上的一浮动栅极；一存储器P型阱区位于所述半导体衬底中，其中所述存储器P型阱区与所述一第一氧化物定义区及所述第二氧化物定义区重叠，且其中所述存储器P型阱区的接合深度大于所述隔离区域的所述沟渠深度；以及一存储器N型阱区位于所述存储器P型阱区中，其中所述存储器N型阱区仅与所述第一氧化物定义区重叠，且其中所述存储器N型阱区的接合深度小于所述隔离区域的所述沟渠深度。
毋庸置疑的，本领域的技术人员读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1为本发明一实施例的平面示意图，为一单层多晶硅非易失性存储单元。
图2为沿着图1切线I-I’截取的单层多晶硅非易失性存储单元剖面示意图。
图3到图9为剖面示意图，说明根据本发明一实施例在半导体衬底中制作存储器N型阱区、存储器P型阱区及重叠扩散漏极区的步骤。
须注意的是所有附图均为示意图，以说明和制图方便为目的，相对尺寸及比例都经过调整。相同的符号在不同的实施例中代表相对应或类似的特征。
其中，附图标记说明如下：
1单层多晶硅非易失性存储单元
10选择晶体管
11N+掺杂区
12P+源极掺杂区
14共享P+掺杂区
16P+漏极掺杂区
18N+掺杂区
20浮动栅极晶体管
30擦除栅极区域
32选择栅极沟道区
34浮动栅极沟道区
100半导体衬底
100a主表面
101P+提取区
102存储器P型阱区
104存储器N型阱区
108重叠扩散漏极区
110选择栅极
110a栅极介电层
120浮动栅极
120a栅极介电层
122浮动栅极延伸部
122a栅极介电层
200隔离区域
210第一氧化物定义区
220第二氧化物定义区
400第一注入遮罩
410开口
401离子注入工艺
402离子注入工艺
403离子注入工艺
500第二注入遮罩
510开口
501离子注入工艺
502离子注入工艺
d沟渠深度
d1接合深度
d2接合深度
w宽度
MNW存储器N型井
MNW-1第一浅层存储器N型阱区
MNW-2第二浅层存储器N型阱区
MPW存储器P型阱区
MPW-1第一存储器P型阱区
MPW-2第二存储器P型阱区
P-SubP型掺杂硅衬底
WL字线
SG选择栅极
FG浮动栅极
EG擦除栅极
SL源极线
BL位线
EL擦除线
具体实施方式
在下面的描述中，已提供若干具体细节以便彻底理解本发明。然而，很明显，对本领域技术人员而言，本发明还是可以在没有这些具体细节的情况下实施。此外，一些公知的系统配置和工艺步骤没有被巨细无遗的披露出来，因为这些应是本领域技术人员所熟知的。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
同样的，例示的装置的实施例的附图是半示意且未按比例绘制，并且，附图中为了清楚呈现，某些尺寸可能被放大。此外，公开和描述多个实施例中具有通用的某些特征时，相同或类似的特征通常以相同的附图标记描述，以方便说明和描述。
专有名词“氧化物定义(oxidedefine,OD)区”在本领域中普遍认为是一衬底上硅质主表面的某一区域，通常为硅的局部氧化(LOCOS)或浅沟渠隔离(STI)区域以外的区域。专有名词“氧化物定义(OD)区”也普遍可被理解为形成及操作有源电路器件例如晶体管的“有源区域”。
图1为本发明一实施例的平面示意图，为一单层多晶硅非易失性存储单元。图2为沿着图1切线I-I’截取的剖面示意图。例示的单层多晶硅非易失性存储单元可以是多次编程存储器(MTP)单元，但不限于此。须了解的是本发明也可应用在其他类型的存储器。
如图1所示，单层多晶硅非易失性存储单元1包括至少两个被隔开但紧密靠近的氧化物定义区，分别为第一氧化物定义区210与第二氧化物定义区220。埋设在半导体衬底100中的隔离区域200将第一氧化物定义区210与第二氧化物定义区220分隔开。半导体衬底100可以是P型掺杂硅衬底(P-Sub)。根据本发明实施例，隔离区域200可以是浅沟渠隔离(STI)区域，但不限于此。须了解图1所示布局仅为例示说明，当然，其它依照图1修改或变化的布局图案也可以使用。
根据本发明实施例，位于第一氧化物定义区210与第二氧化物定义区220间的隔离区域200具有一宽度w，可小于或等于0.25微米，但不限于此。根据本发明实施例，位于第一氧化物定义区210与第二氧化物定义区220间的隔离区域200的宽度w并不受限于输入/输出(I/O)离子阱注入的设计规范。根据本发明实施例，所述存储器阵列并不会使用到或注入上述输入/输出(I/O)离子阱。
如图1和图2所示，单层多晶硅非易失性存储单元1包括一选择晶体管10及一与选择晶体管10串联的浮动栅极晶体管20。串联的选择晶体管10与浮动栅极晶体管20直接位于第一氧化物定义区210上。根据本发明实施例，选择晶体管10可以是PMOS晶体管，包括P+源极掺杂区12，与一源极线SL耦合；一共享P+掺杂区14，与P+源极掺杂区12分隔开；一选择栅极沟道区32，位于P+源极掺杂区12与共享P+掺杂区14之间且靠近半导体衬底100的主表面100a；一选择栅极(SG)110，覆盖在选择栅极沟道区32上方且与一字线(WL)耦合；以及一栅极介电层110a，位于选择栅极110与选择栅极沟道区32之间。选择栅极110的相对侧壁上可具有间隙壁(图未示)。
根据本发明实施例，一N+掺杂区11设置在P+源极掺杂区12旁边。N+掺杂区与P+源极掺杂区12相连。另提供一相邻接触点(图未示)使N+掺杂区11与P+源极掺杂区12之间形成短路。
浮动栅极晶体管20直接位于第一氧化物定义区210上，与选择晶体管10共享第一氧化物定义区210。浮动栅极晶体管20通过共享P+掺杂区14与选择晶体管10串联。浮动栅极晶体管20与选择晶体管10通过共享P+掺杂区14彼此串联起来，在此例中形成两个串联在一起的PMOS晶体管。
浮动栅极晶体管20包括一浮动栅极120覆盖在第一氧化物定义区210上。根据本发明实施例，浮动栅极120由单层多晶硅构成。根据本发明实施例，浮动栅极晶体管20作为单层多晶硅非易失性存储单元1的电荷存储器件。根据本发明实施例，选择栅极110与浮动栅极120都为直线型延伸且互相平行。
浮动栅极晶体管20另包括位于浮动栅极120一侧的共享P+掺杂区14；位于浮动栅极120另外一侧的P+漏极掺杂区16；一浮动栅极沟道区34介于共享P+掺杂区14与P+漏极掺杂区16之间；P+漏极掺杂区16与一位线BL耦合；一栅极介电层120a位于浮动栅极120与浮动栅极沟道区34之间。根据本发明实施例，栅极介电层120a与栅极介电层110a的厚度大致相同。
根据本发明实施例，单层多晶硅非易失性存储单元1另包括一浮动栅极延伸部122，自浮动栅极120连续延伸到第二氧化物定义区220，与一位于第二氧化物定义区的擦除栅极(EG)区域30(与一擦除线EL耦合)相邻。浮动栅极延伸部122横跨第一氧化物定义区210与第二氧化物定义区220之间的隔离区域200，并且覆盖部分第二氧化物定义区220以与擦除栅极区域30电容偶合。根据本发明实施例，擦除栅极区域30包括一重叠扩散漏极(doublediffuseddrain,DDD)区108，及一位于重叠扩散漏极区108内的N+掺杂区18。根据本发明实施例，浮动栅极延伸部122与重叠扩散漏极区108之间具有一栅极介电层122a。
根据本发明实施例，重叠扩散漏极区108可以是N型掺杂区域。根据本发明实施例，一N+掺杂区18位于未被浮动栅极延伸部122覆盖的重叠扩散漏极区108中。当存储器在运作状态时，N+掺杂区18与重叠扩散漏极区108同时和一擦除线电压VEL电性连接。根据本发明实施例，在擦除栅极区域30内设置重叠扩散漏极区108，可增加接面的崩溃电压，强化器件特性。
根据本发明实施例，单层多晶硅非易失性存储单元1另包括一位于半导体衬底100中的存储器P型阱区102，与一位于存储器P型阱区102中的浅层存储器N型阱区104。根据本发明实施例，存储器P型阱区102具有自半导体衬底100主表面100a以下的接合深度d1，大于隔离区域200的沟渠深度d。根据本发明实施例，存储器N型阱区104具有自半导体衬底100主表面100a以下的接合深度d2，小于隔离区域200的沟渠深度d。根据本发明实施例，隔离区域200的沟渠深度d可以是2700到3700埃之间，但不限于此。
如图2所示，根据本发明实施例，选择晶体管10与浮动栅极晶体管20位于存储器N型阱区104内。N+掺杂区11、P+源极掺杂区12、共享P+掺杂区14和P+漏极掺杂区16也都位于存储器N型阱区104内。N+掺杂区18和重叠扩散漏极区108则位于存储器P型阱区102内。根据本发明实施例，擦除栅极区域30另包括位于重叠扩散漏极区108正下方的部分存储器P型阱区102。根据本发明实施例，通过一P+提取区101，可将半导体衬底100电性连接到一衬底电压Vsub。
图3到图9为剖面示意图，说明根据本发明一实施例在半导体衬底100中制作存储器N型阱区104、存储器P型阱区102及重叠扩散漏极区108的步骤。其中，沿用相同的附图标记来表示相同的材料层、区域与器件。根据本发明实施例，需要额外两道光罩，定义存储器N型阱区104、存储器P型阱区102和重叠扩散漏极区108在半导体衬底100中所属的区域。
如图3所示，在半导体衬底100中形成隔离区域200(例如浅沟渠隔离)，在半导体衬底100主表面100a上定义出第一氧化物定义区210和第二氧化物定义区220。隔离区域200的沟渠深度如先前所述，为2700到3700埃之间。
如图4所示，提供第一注入遮罩400覆盖住半导体衬底100。第一注入遮罩400具有开口410，定义出后续将形成的存储器N型阱区104的区域。离子注入工艺401将N型掺杂经由开口410注入到半导体衬底100中，形成第一浅层存储器N型阱区(MNW-1)，目的是避免器件发生穿透效应造成不正常导通。根据本发明实施例，第一浅层存储器N型阱区(MNW-1)的接面深度小于隔离区域200的沟渠深度d。
如图5所示，接着，离子注入工艺402同样利用第一注入遮罩400，在第一浅层存储器N型阱区(MNW-1)中形成第二浅层存储器N型阱区(MNW-2)，目的是调整器件的临界电压(Vt)。根据本发明实施例，第二浅层存储器N型阱区(MNW-2)的接面深度小于第一浅层存储器N型阱区(MNW-1)的接面深度。
如图6所示，再次利用第一注入遮罩400进行离子注入工艺403，在半导体衬底100中形成第一存储器P型阱区(MPW-1)，目的是提供器件更完整的隔离。第一存储器P型阱区(MPW-1)的接面深度不仅大于第一浅层存储器N型阱区(MNW-1)的接面深度，也大于隔离区域200的沟渠深度d。形成第一存储器P型阱区(MPW-1)之后，即可移除第一注入遮罩400。
接着如图7所示，提供第二注入遮罩500覆盖住半导体衬底100。第二注入遮罩500具有开口510，定义出后续将形成的N型重叠扩散漏极区108的区域。接着进行离子注入工艺501，将P型掺杂经由开口510注入半导体衬底100中，形成N型重叠扩散漏极区108。
如图8所示，接着，离子注入工艺502同样利用第二注入遮罩500，将P型掺杂经由开口510注入半导体衬底100中，形成第二存储器P型阱区(MPW-2)，目的是提供器件更完整的隔离。第二存储器P型阱区(MPW-2)的接面深度不仅大于第一浅层存储器N型阱区(MNW-1)的接面深度，也大于隔离区域200的沟渠深度d。
如图9所示，第二存储器P型阱区(MPW-2)与第一存储器P型阱区(MPW-1)合并成为存储器P型阱区102。第一浅层存储器N型阱区(MNW-1)与第二浅层存储器N型阱区(MNW-2)合并成为存储器N型阱区104。接着，通过与公知的互补式金氧半导体逻辑工艺相容的工艺，在半导体衬底100上形成选择晶体管、浮动栅极晶体管与擦除栅极区域。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

1.一种单层多晶硅非易失性存储单元，其特征在于，包括：
一半导体衬底；
一第一氧化物定义区及一第二氧化物定义区；
一隔离区域分隔所述第一氧化物定义区及所述第二氧化物定义区，且所述隔离区域具有一沟渠深度；
一PMOS选择晶体管设于所述第一氧化物定义区上；
一PMOS浮动栅极晶体管设于所述第一氧化物定义区上并与所述PMOS选择晶体管串联，其中所述PMOS浮动栅极晶体管包括一覆盖在所述第一氧化物定义区上的一浮动栅极；
一存储器P型阱区位于所述半导体衬底中，其中所述存储器P型阱区与所述第一氧化物定义区及所述第二氧化物定义区重叠，且其中所述存储器P型阱区的接合深度大于所述隔离区域的所述沟渠深度；以及
一存储器N型阱区位于所述存储器P型阱区中，其中所述存储器N型阱区仅与所述第一氧化物定义区重叠，且其中所述存储器N型阱区的接合深度小于所述隔离区域的所述沟渠深度。
2.根据权利要求1所述的单层多晶硅非易失性存储单元，其特征在于，其中所述PMOS选择晶体管与所述PMOS浮动栅极晶体管共享所述存储器N型阱区。
3.根据权利要求1所述的单层多晶硅非易失性存储单元，其特征在于，所述P型选择晶体管包括一P+源极掺杂区，位于所述存储器N型阱区内；一共享P+掺杂区，与所述P+源极掺杂区分隔开；一选择栅极沟道区，位于所述P+源极掺杂区与所述共享P+掺杂区之间且接近所述半导体衬底的主表面；一选择栅极，覆盖在所述选择栅极沟道区上方；以及一栅极介电层，位于所述选择栅极与所述选择栅极沟道区之间。
4.根据权利要求3所述的单层多晶硅非易失性存储单元，其特征在于，所述P+源极掺杂区与一源极线SL耦合。
5.根据权利要求1所述的单层多晶硅非易失性存储单元，其特征在于，所述PMOS浮动栅极晶体管另包括所述共享P+掺杂区位于所述浮动栅极一侧；一P+漏极掺杂区位于所述浮动栅极另一侧；一浮动栅极沟道区介于所述共享P+掺杂区与所述P+漏极掺杂区之间；以及一栅极介电层位于所述浮动栅极与所述浮动栅极沟道区之间。
6.根据权利要求5所述的单层多晶硅非易失性存储单元，其特征在于，所述P+漏极掺杂区与一位线BL耦合。
7.根据权利要求1所述的单层多晶硅非易失性存储单元，其特征在于，所述浮动栅极作为一电荷存储器件。
8.根据权利要求1所述的单层多晶硅非易失性存储单元，其特征在于，另包括一浮动栅极延伸部，从所述浮动栅极连续延伸到所述第二氧化物定义区，且与一位于所述第二氧化物定义区的擦除栅极区域相邻。
9.根据权利要求8所述的单层多晶硅非易失性存储单元，其特征在于，所述浮动栅极延伸部横跨所述第一氧化物定义区与所述第二氧化物定义区之间的所述隔离区域，且覆盖部分所述第二氧化物定义区以与所述擦除栅极区域电容耦合。
10.根据权利要求8所述的单层多晶硅非易失性存储单元，其特征在于，所述擦除栅极区域包括一重叠扩散漏极区，及一N+掺杂区位于所述重叠扩散漏极区内。
11.根据权利要求10所述的单层多晶硅非易失性存储单元，其特征在于，其中所述重叠扩散漏极区为N型掺杂区域。
12.根据权利要求10所述的单层多晶硅非易失性存储单元，其特征在于，其中所述N+掺杂区及所述重叠扩散漏极区与一擦除线电压VEL电性连接。
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