JP6092315B2 - 高スケーラブルな単一ポリ不揮発性メモリセル - Google Patents
高スケーラブルな単一ポリ不揮発性メモリセル Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 34
- 238000002955 isolation Methods 0.000 claims description 25
- 230000006870 function Effects 0.000 claims description 5
- 238000003860 storage Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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- 238000000926 separation method Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
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- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H01L29/92—Capacitors having potential barriers
- H01L29/93—Variable capacitance diodes, e.g. varactors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
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- H10B20/00—Read-only memory [ROM] devices
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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Description
10 選択トランジスタ
11 N+ドーピング領域
12 P+ソースドーピング領域
14 共通P+ドーピング領域
16 P+ドレインドーピング領域
18 N+ドーピング領域
20 フローティングゲートトランジスタ
30 消去ゲート(EG)領域
32 選択ゲートチャネル領域
34 フローティングゲートチャネル領域
100 半導体基体
100a 主表面
101 ピックアップ領域
102 メモリPウェル(MPW)
104 メモリNウェル(MNW)
108 二重拡散ドレイン(DDD)領域
110 選択ゲート(SG)
110a ゲート誘電体層
120 フローティングゲート(FG)
120a ゲート誘電体層
122 フローティングゲート拡張部
122a ゲート誘電体層
200 分離領域
210 第1のOD領域
220 第2のOD領域
400 第1の注入マスク
410 開口部
500 第2の注入マスク
510 開口部
BL ビットライン
EL 消去ライン
SL ソースライン
WL ワードライン
Claims (12)
- 不揮発性メモリ(NVM)セルであって、
半導体基体と、
第1のOD領域及び第2のOD領域と、
前記第2のOD領域から前記第1のOD領域を分離するとともに、トレンチ深さを有する分離領域と、
前記第1のOD領域に沿って配置されたPMOS選択トランジスタと、
前記PMOS選択トランジスタに直列に結合されるとともに、前記第1のOD領域に沿って配置され、前記第1のOD領域を覆うフローティングゲートを含むPMOSフローティングゲートトランジスタと、
前記半導体基体におけるメモリPウェルであって、前記第1のOD領域及び前記第2のOD領域と重なるとともに、前記分離領域の前記トレンチ深さより深い接合深さを有する前記メモリPウェルと、
前記メモリPウェルにおけるメモリNウェルであって、単に前記第1のOD領域と重なるとともに、前記分離領域の前記トレンチ深さより浅い接合深さを有する前記メモリNウェルと、
前記メモリPウェルにおけるN + ドーピング領域とを備え、
前記メモリNウェルは、第1のシャローメモリNウェル及び第2のシャローメモリNウェルにより構成され、前記第2のシャローメモリNウェルは、前記第1のシャローメモリNウェルにおいて形成されると共に、前記第1のシャローメモリNウェルの接合深さより浅い接合深さを有し、
前記PMOS選択トランジスタは、前記メモリNウェルにおけるP + ソースドーピング領域を含み、前記N + ドーピング領域は、前記P + ソースドーピング領域の隣に配置されると共に、前記P + ソースドーピング領域に接触し、
前記N + ドーピング領域を前記P + ソースドーピング領域を短絡させるための突合せ接点(butted contact)が形成される、NVMセル。 - 前記PMOS選択トランジスタ及び前記PMOSフローティングゲートトランジスタが、通常は前記メモリNウェルを共用する、請求項1に記載のNVMセル。
- 前記PMOS選択トランジスタが、さらに、
前記P+ソースドーピング領域から離れて間隔を開けられた共通P+ドーピング領域と、
前記P+ソースドーピング領域と前記共通P+ドーピング領域との間の前記半導体基体の主表面の近くの選択ゲートチャネル領域と、
前記選択ゲートチャネル領域を覆う選択ゲートと、
前記選択ゲートと前記選択ゲートチャネル領域との間のゲート誘電体層とを備える、請求項1に記載のNVMセル。 - 前記P+ソースドーピング領域がソースラインSLに連結される、請求項3に記載のNVMセル。
- 前記PMOSフローティングゲートトランジスタが、
前記フローティングゲートの一方の側面に沿った共通P+ドーピング領域と、
前記フローティングゲートのもう一方の側面に沿ったP+ドレインドーピング領域と、
前記共通P+ドーピング領域と前記P+ドレインドーピング領域との間のフローティングゲートチャネル領域と、
前記フローティングゲートと前記フローティングゲートチャネル領域との間のゲート誘電体層とを更に備える、請求項1に記載のNVMセル。 - 前記P+ドレインドーピング領域がビットラインBLに連結される、請求項5に記載のNVMセル。
- 前記PMOSフローティングゲートトランジスタが、当該NVMセルの電荷蓄積素子としての機能を果たす、請求項1に記載のNVMセル。
- 前記フローティングゲートから前記第2のOD領域まで連続的に拡張されるとともに、前記第2のOD領域における消去ゲート(EG)領域に隣接しているフローティングゲート拡張部を更に備える、請求項1に記載のNVMセル。
- 前記フローティングゲート拡張部が、前記第1のOD領域と前記第2のOD領域との間の前記分離領域を横断し、前記EG領域に容量結合するように前記第2のOD領域と部分的に重なる、請求項8に記載のNVMセル。
- 前記EG領域が、二重拡散ドレイン(DDD)領域と、前記DDD領域におけるN+ドーピング領域とを備える、請求項8に記載のNVMセル。
- 前記DDD領域がN型ドーピング領域である、請求項10に記載のNVMセル。
- 前記N+ドーピング領域及び前記DDD領域が、消去ライン電圧(VEL)に電気的に連結される、請求項10に記載のNVMセル。
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US9214933B2 (en) | 2014-02-25 | 2015-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Input/output circuit |
US9508396B2 (en) * | 2014-04-02 | 2016-11-29 | Ememory Technology Inc. | Array structure of single-ploy nonvolatile memory |
US10109364B2 (en) * | 2015-10-21 | 2018-10-23 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Non-volatile memory cell having multiple signal pathways to provide access to an antifuse of the memory cell |
US10014066B2 (en) * | 2015-11-30 | 2018-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness |
US9847133B2 (en) * | 2016-01-19 | 2017-12-19 | Ememory Technology Inc. | Memory array capable of performing byte erase operation |
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