CN108346662B - 单层多晶硅非易失性存储单元的操作方法 - Google Patents

单层多晶硅非易失性存储单元的操作方法 Download PDF

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CN108346662B
CN108346662B CN201810010973.1A CN201810010973A CN108346662B CN 108346662 B CN108346662 B CN 108346662B CN 201810010973 A CN201810010973 A CN 201810010973A CN 108346662 B CN108346662 B CN 108346662B
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CN108346662A (zh
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许家荣
孙文堂
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eMemory Technology Inc
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Abstract

本发明公开了一种单层多晶硅非易失性存储单元的擦除操作方法，将一源极线电压VSL施加到PMOS选择晶体管的P+源极掺杂区，其中VSL＝0V，将字线电压VWL施加到PMOS选择晶体管的选择栅极，其中VWL＝0V，将位线电压VBL施加到PMOS浮置栅极晶体管的P+漏极掺杂区，其中VBL＝0V，对擦除栅极区施加擦除线电压VEL，其中VEL＝VEE，VEE是相对高于VBL的正电压，对N型阱施加N型阱电压VNW，其中VNW>0V，以擦除该单层多晶硅非易失性存储单元。

Description

单层多晶硅非易失性存储单元的操作方法
技术领域
本发明是有关于一种非易失性存储单元的操作方法。更具体地说，本发明是有关于一种自我限制(self-limiting)或逐位自动饱和(bit-by-bit self-saturated)的擦除方法，用来擦除一具有擦除栅极区域的单层多晶硅浮置栅极非易失性存储单元。
背景技术
半导体存储器组件，如非易失性存储器(NVM)，已广泛应用于各种电子组件，例如，移动电话、数字相机、个人数字助理、移动计算设备及其他应用中。
通常，NVM可分为多次可编程(MTP)存储器及单次可编程(OTP)存储器。MTP存储器可以进行多次读写。例如，EEPROM及闪存设计有相应的电路，以支持编程、擦除或读取等不同的操作。OTP存储器具有编程及读取功能，不需要用于擦除操作的电路。
已知，单层多晶硅NVM的设计可以减少额外的工艺成本。单层多晶硅NVM是以单一层的多晶硅构成电荷储存浮置栅极。由于单层多晶硅NVM与一般CMOS工艺兼容，因此常应用于嵌入式存储器领域、混合模式电路及微控制器(如系统单芯片，SOC)中的嵌入式非易失性存储器。
此外，已知通过热电子注入技术(也称为信道热电子或CHE编程)可实现存储器单元的编程，经由擦除栅极的FN隧穿可以擦除存储器单元。当浮置栅极储有电荷时，存储单元即处于被编程状态(programmed)。当电荷自浮置栅极释出时，存储单元即处于未编程(unprogrammed)或擦除状态。通过擦除操作，可以将电荷从浮置栅极移除。
现有技术中，单层多晶硅非易失性存储单元的问题之一在于过度擦除(over-erasure)，这可能会导致例如陷位(stuck bits)等硬错误(hard errors)，并可能导致写入失败。为了避免造成存储单元的过度擦除，通常使用较高压的软编程(soft-program mode)模式，但是，这样的作法却可能会导致飞逝位(fly bits)并使互扰问题(disturbance)更严重。
发明内容
本发明的主要目的在提供具有擦除栅极及较佳擦除效率的单层多晶非易失性存储器(NVM)。
本发明一实施例提供一种单层多晶硅非易失性存储单元的操作方法，其中该单层多晶硅非易失性存储单元包含设置在一N型阱上且互相串联的一PMOS选择晶体管及一PMOS浮置栅极晶体管，其中该PMOS浮置栅极晶体管包括一浮置栅极及一浮置栅极延伸部，而该浮置栅极延伸部与一擦除栅极区域电容耦合，该方法包含：通过将一源极线电压VSL施加到该PMOS选择晶体管的一P+源极掺杂区，其中VSL＝0V，将一字线电压VWL施加到该PMOS选择晶体管的一选择栅极，其中VWL＝0V，将一位线电压VBL施加到该PMOS浮置栅极晶体管的P+漏极掺杂区，其中VBL＝0V，对该擦除栅极区施加一擦除线电压VEL，其中VEL＝VEE，VEE是相对高于VBL的正电压，对该N型阱施加一N型阱电压VNW，其中VNW>0V，以擦除该单层多晶硅非易失性存储单元；其中，VNW低于一第一漏极-源极饱和电压VDS-Sat1且高于一第二漏极-源极饱和电压VDS-Sat2，其中该第一漏极-源极饱和电压VDS-Sat1是确保在擦除操作初始时在该浮置栅极之下的一P通道两端不会发生夹断现象(pinchoff)的一上限电压，而该第二漏极-源极饱和电压VDS-Sat2是当该浮置栅极处于擦除状态时，确保在P通道的两端发生夹断现象的一下限电压。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
附图提供对实施例的进一步理解，并且被并入并构成本说明书的一部分。附图用以例示部分实施例，并用于解释其原理。在附图中：
图1为根据本发明一实施例所绘示的单层多晶硅非易失性存储单元的例示性布局示意图。
图2例示性的显示出已处于编程状态的浮置栅极晶体管并且刚开始进行擦除。
图3例示性的显示出处于擦除状态的浮置栅极晶体管。
图4例示性的显示出浮置栅极晶体管处于编程状态并且刚开始被擦除。
图5例示性的显示出处于擦除状态的浮置栅极晶体管。
图6例示性的显示出NMOS浮置栅极晶体管处于编程状态并且刚开始被擦除。
图7例示性的显示出处于擦除状态的NMOS浮置栅极晶体管。
图8例示性的显示出NMOS浮置栅极晶体管处于编程状态并且刚开始被擦除。
图9例示性的显示出处于擦除状态的NMOS浮置栅极晶体管。
应该注意的是，附图仅供例示说明。为方便说明及为求清楚，部分附图的相对尺寸及比例被放大或缩小。通常，相同的附图标记在各不同实施例中表示对应或相似特征。
其中，附图标记说明如下：
1 非易失性存储单元
100 半导体衬底
100a、100c 氧化物界定区域
101 N型阱(NW)
102 P型阱(PW)
103 P型阱
105 深N型阱(DNW)
110 沟道隔离区域
121 源极掺杂区
122 共享掺杂区
123 漏极掺杂区
21 选择晶体管
210 选择栅极通道区
211 栅极介电层
212 选择栅极(SG)
22 浮置栅极晶体管
220 浮置栅极通道区
220a P通道
220b N通道
221 栅极介电层
221a 栅极介电层
222 浮置栅极(FG)
222a 浮置栅极延伸部
30 擦除栅极(EG)区域
302 重掺杂区
303 轻掺杂漏极(LDD)区域
322 电子
VNW N型阱电压
VPW P型阱电压
VWL 字线电压
VSL 源极线电压
VBL 位线电压
VEL 擦除线电压
E1、E2 P通道两个相对端
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容亦构成说明书细节描述的一部份，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技艺人士可以具以实施。
当然，亦可实行其他的实施例，或是在不悖离下文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，相反地，其中所包含的实施例将由随附的申请专利范围来加以界定。
在本技术领域中，用语“氧化物界定(OD)区域”(“OD”区域有时被称为“氧化物界定”区域或“氧化物定义”区域)通常指衬底的硅主表面上除了局部氧化硅(LOCOS)或浅沟槽绝缘(STI)区域之外的区域。用语“氧化物界定(OD)区域”也通常指“有源区域(activearea)”，即用来形成及操作例如晶体管等有源电路组件的区域。
图1为根据本发明一实施例所绘示的单层多晶硅非易失性存储单元的例示性布局示意图。如图1所示，非易失性存储单元1包括一选择晶体管21及串联到选择晶体管21的一浮置栅极晶体管22。选择晶体管21与浮置栅极晶体管22可以直接形成在相同的氧化物界定区域100a上。在半导体衬底100如P型硅衬底(P-Sub)上可以形成有一N型阱(NW)101。N型阱101涵盖氧化物界定区100a，这使得选择晶体管21与浮置栅极晶体管22均设置在N型阱101上。操作时，N型阱101电性耦合一N型阱电压(VNW)。
根据例示实施例，选择晶体管21包括在N型阱101中的源极掺杂区121、与源极掺杂区121间隔开的共享掺杂区122、半导体衬底的主表面附近源极掺杂区121与共享掺杂区122之间的选择栅极通道区210、位于选择栅极通道区210上的选择栅极(SG)212，以及选择栅极212与选择栅极通道区210之间的栅极介电层211。选择栅极212电性耦合到一字线电压(VWL)。
根据例示实施例，选择晶体管21可以是PMOS晶体管，且选择栅极212可以是P+掺杂多晶硅栅极，但不限于此。源极掺杂区121及共享掺杂区122可以是P+掺杂区。根据例示实施例，源极掺杂区121可以电性耦合到一源极线电压(VSL)。
尽管未在附图中示出，但是可以理解的是，在选择栅极212的相对侧墙上可以形成间隙壁，并且可以在间隙壁的正下方可以形成轻掺杂漏极(LDD)区域。尽管附图中未示出，但是应该理解，在一些实施例中，源极掺杂区121及共享掺杂区122可以包括例如PLDD区域的LDD区域。
浮置栅极晶体管22是直接形成在氧化物界定区域100a上。浮置栅极晶体管22通过共享掺杂区122串联到选择晶体管21。共享掺杂区122由浮置栅极晶体管22及选择晶体管21共享，如此形成两个串联的晶体管21及22，在此实施例中，为两个串联的PMOS晶体管。
浮置栅极晶体管22包括设在氧化物界定区域100a上的浮置栅极(FG)222。根据例示实施例，浮置栅极222由单层多晶硅，例如，P+掺杂多晶硅所组成。根据例示实施例，浮置栅极222是单层多晶硅栅极。也就是说，在浮置栅极222上不会堆叠额外的栅极层。根据例示实施例，浮置栅极晶体管22做为非易失性存储单元1的电荷储存组件。
浮置栅极晶体管22还包括浮置栅极(FG)222一侧的共享掺杂区122、浮置栅极222另一侧与共享掺杂区122相对的漏极掺杂区123、共享掺杂区122与漏极掺杂区123之间的浮置栅极通道区220，以及在浮置栅极222与浮置栅极通道区220之间的栅极介电层221。尽管未在附图中示出，但是可以理解的是，在浮置栅极222的相对侧墙上可以形成间隙壁。根据例示实施例，漏极掺杂区123可以是P+掺杂区并且电性耦合到一位线电压(VBL)。
根据例示实施例，非易失性存储单元1进一步包括浮置栅极延伸部222a，从浮置栅极222连续地延伸到氧化物界定区域100c并且与擦除栅极(EG)区域30相邻，所述擦除栅极区域30电性耦合到擦除线电压(VEL)。浮置栅极延伸部222a穿过在氧化物界定区域100a与氧化物界定区域100c之间的沟道隔离区域110，并与氧化物界定区域100c部分重叠，从而电容耦合到擦除栅极区域30。P型阱(PW)102可以设置在半导体衬底100中。P型阱102涵盖氧化物界定区域100c。操作时，P型阱101被施加P型阱电压(VPW)。
擦除栅极区域30可以包括重掺杂区302，例如与浮置栅极延伸部222a相邻的N+掺杂区。例如NLDD的轻掺杂漏极(LDD)区域303可以设置在半导体衬底100中，并且可以位于间隙壁的正下方。轻掺杂漏极区域303与重掺杂区302相邻接。
根据例示实施例，可以在浮置栅极延伸区222a及半导体衬底100之间形成栅极介电层221a。根据例示实施例，重掺杂区302形成在未被浮置栅极延伸部222a覆盖的区域中。操作时，例如擦除操作，重掺杂区302电性耦合到擦除线电压(VEL)。
根据例示实施例，PMOS型非易失性存储单元1的擦除操作涉及经由浮置栅极延伸部222a从存储单元的浮置栅极222去除电子的隧穿机制。
例如，在非易失性存储单元1的擦除操作期间，施加于选择晶体管21的源极掺杂区121的源极线电压VSL是0V(VSL＝0V)，施加于选择晶体管21的选择栅极212的字线电压(或选择栅极电压)VWL也是0V(VWL＝0V)。位线电压VBL是0V(VBL＝0V)。擦除线电压VEL为正的高电压VEE(VEL＝VEE)，VEE大约在12～20V之间。N型阱电压VNW大于0V，其范围大约在1～3V(VNW＝1～3V)之间，例如2V。P型阱电压VPW为0V(VPW＝0V)。半导体衬底100被施加衬底电压VP-Sub，其中VP-Sub＝0V。
从图2及图3可以较容易理解本发明擦除技术的进行过程。为了简化说明，图中仅示出了非易失性存储单元1的一部分。图2例示性的显示出已处于编程状态的浮置栅极晶体管22并且刚开始进行擦除。图3例示性的显示出处于擦除状态的浮置栅极晶体管22。
如图2所示，在擦除操作的早期阶段，在浮置栅极222下方形成P信道220a，P信道220a的两个相对端E1和E2分别与共享掺杂区122和漏极掺杂区123邻接。由于浮置栅极222与P通道220a(0V)完全耦合，所以起始的擦除效率相对较高。由于较高的擦除偏压条件(VEE相对0V)，在擦除操作刚开始时，电子322经由浮置栅极延伸部222a从浮置栅极222被快速移除。
如图3所示，随着擦除操作的继续，浮置栅极222中的电子322的数量减少，并且P通道220a的两个相对端E1和E2处逐渐消失(或开始渐缩或萎缩)，最终P通道220a的两个相对端E1和E2会分别与共享掺杂区122及漏极掺杂区123断开。此时(当夹断pinchoff发生时)，浮置栅极222部分地耦合到萎缩的P通道220a，并且部分地耦合到萎缩的P通道220a与共同掺杂区122之间的N型阱101以及萎缩的P通道220a与漏极掺杂区123之间的N型阱101。此时，由于擦除偏压(VEE相对VNW)下降，导致擦除效率降低，这减缓了存储单元1的擦除操作。
本发明的优点在于，擦除操作是自我限制的，而无需修改单层多晶硅非易失性存储单元的布局，并且存储器数组中的每个存储单元的最终擦除状态可以收敛到近似相同的水平，并且是逐位自动饱和。如此一来，可以避免过度擦除的问题。此外，可以采用较少应力的软编程模式，从而提高了可靠性，并且可以采用较低压的电源供应。由于软编程模式的电压应力较小，可以避免飞逝位及互扰。
根据本发明实施例，以下描述如何决定施加到N型阱101的N型阱电压VNW的上限电压水平及下限电压水平的方法。对于浮置栅极处于编程状态的PMOS存储单元的擦除操作，施加到N型阱101的VNW必须被设定为低于第一漏极-源极饱和电压VDS-Sat1(上限电压)以确保在擦除操作开始时在P通道220a的两端E1及E2处不发生夹断，因此擦除效率较高。当浮置闸处于擦除状态时，施加到N型阱101的VNW必须被设定为高于第二漏极-源极饱和电压VDS-Sat2(下限电压)，以确保夹断发生在P通道220a的两端E1及E2，如此可以避免过度擦除。
图4及图5例示出根据另一实施例用于非易失性存储单元1的擦除操作的电压条件，其中为简化说明，仅示出了非易失性存储单元1的一部分。同样的，图4例示性的显示出浮置栅极晶体管22处于编程状态并且刚开始被擦除。图5例示性的显示出处于擦除状态的浮置栅极晶体管22。
在非易失性存储单元1的擦除操作期间，施加于选择晶体管21的源极掺杂区121的源极线电压VSL是负电压，例如VSL＝-VBB，施加于选择晶体管21的选择栅极212的字线电压(或选择栅极电压)VWL是-VBB或比VBB絶对值更大的负电压。位线电压VBL是负电压，例如VBL＝-VBB。VBB的范围大约在1～3V之间(VBB＝1～3V)。擦除线电压VEL为正的高电压VEE(VEL＝VEE)，VEE大约在12～20V之间。N型阱电压VNW为0V(VNW＝0V)。P型阱电压VPW为0V(VPW＝0V)。半导体衬底100被施加衬底电压VP-Sub，其中VP-Sub＝0V。
如图4所示，在擦除操作的早期阶段，浮置栅极222下方形成P通道220a，且P通道220a的两个相对端E1和E2分别与共享掺杂区122及漏极掺杂区123邻接。由于浮置栅极222与P通道220a(-VBB)耦合，所以起始的擦除效率相对较高。较高的擦除偏压条件(VEE相对-VBB)使得在擦除操作开始时，电子322经由浮置栅极延伸部222a从浮置栅极222被快速移除。
如图5所示，随着擦除操作的继续，浮置极222中的电子322的数量减少，且P通道220a的相对两端E1和E2处逐渐消失(或开始渐缩或萎缩)，最终使萎缩的P通道220a的相对两端E1和E2分别与共享掺杂区122及漏极掺杂区123断开。此时(当夹断发生时)，浮置栅极222耦合到N型阱101(0V)。由于擦除偏压条件降低(VEE相对0V)，导致擦除效率降低，减缓了存储单元1的擦除操作。
本发明可以应用于NMOS型存储单元。NMOS型存储单元可以包括在氧化物界定区域100a下面的P型阱103以及在P型阱103下面的深N型阱(DNW)105。
图6及图7例示本发明另一实施例用于NMOS型非易失性存储单元的擦除操作的电压条件，其中为简化说明，仅示出了NMOS型非易失性存储单元的一部分。同样的，图6例示性的显示出NMOS浮置栅极晶体管处于编程状态并且刚开始被擦除。图7例示性的显示出处于擦除状态的NMOS浮置栅极晶体管。
在对NMOS型非易失性存储单元的擦除操作期间，施加于选择晶体管21的源极掺杂区121的源极线电压VSL是0V，VSL＝0V，施加于选择晶体管21的选择栅极212的字线电压(或选择栅极电压)VWL是0V(VWL＝0V)。位线电压VBL是0V，VBL＝0V。擦除线电压VEL为正的高电压VEE(VEL＝VEE)，VEE大约在12～20V之间。施加到P型阱103的P型阱电压VPW是负电压(VPW＝-VBB，VBB大约在1～3V之间(VBB＝1～3V)。
如图6所示，在擦除操作的早期阶段，浮置栅极222与P型阱电压VPW耦合，起始的擦除效率较高。由于较高的擦除偏压条件，在擦除操作开始时，电子322经由浮置栅极延伸部222a从浮置栅极222被快速移除。
如图7所示，随着擦除操作的继续，浮置栅极222中的电子322的数量减少，N通道220b逐渐出现，从而最终连接共享掺杂区122与漏极掺杂区123。此时，浮置栅极222耦合到N通道220b(0V)。由于擦除偏压条件降低(VEE相对0V)，导致擦除效率降低，减缓了存储单元的擦除操作。
图8及图9例示本发明又另一实施例用于NMOS型非易失性存储单元的擦除操作的电压条件，其中深N型阱可以被省略。图8例示性的显示出NMOS浮置栅极晶体管处于编程状态并且刚开始被擦除。图9例示性的显示出处于擦除状态的NMOS浮置栅极晶体管。
在NMOS型非易失性存储单元的擦除操作期间，施加于选择晶体管21的源极掺杂区121的源极线电压VSL是正电压，VSL＝+VBB，施加于选择晶体管21的选择栅极212的字线电压(或选择栅极电压)VWL是+VBB或比VBB更高一点的电压。位线电压VBL是正电压，VBL＝+VBB。VBB的范围大约在1～3V之间(VBB＝1～3V)。擦除线电压VEL为正的高电压VEE(VEL＝VEE)，VEE大约在12～20V之间。施加到P型阱103的P型阱电压VPW是0V(VPW＝0V)。根据该实施例，深N型阱可以被省略。
如图8所示，在擦除操作的早期阶段，浮置栅极222与P型阱电压VPW完全耦合，起始的擦除效率较高。由于较高的擦除偏压条件，在擦除操作开始时，电子322经由浮置栅极延伸部222a从浮置栅极222被快速移除。
在图9中，随着擦除操作的继续，浮置栅极222中的电子322的数量减少，N通道220b逐渐出现，从而N通道220b最终连接共享掺杂区122及漏极掺杂区123。此时，浮置栅极222耦合到N通道220b(+VBB)。由于擦除偏压条件降低(VEE相对+VBB)，导致擦除效率降低，减缓了存储单元的擦除操作。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种单层多晶硅非易失性存储单元的操作方法，其特征在于，该单层多晶硅非易失性存储单元包含设置在一N型阱上且互相串联的一PMOS选择晶体管及一PMOS浮置栅极晶体管，其中该PMOS浮置栅极晶体管包括一浮置栅极及一浮置栅极延伸部，而该浮置栅极延伸部与一擦除栅极区域电容耦合，该单层多晶硅非易失性存储单元更包含一第一氧化物界定区域，设于一半导体衬底上，及一第二氧化物界定区域与该第一氧化物界定区域隔离，其中该擦除栅极区域设于该第二氧化物界定区域内，该方法包含：
通过将一位线电压施加到该PMOS浮置栅极晶体管的P+漏极掺杂区，对该擦除栅极区施加一擦除线电压，对该N型阱施加一N型阱电压，以擦除该单层多晶硅非易失性存储单元，其中该位线电压为0V，而该擦除线电压是相对高于该位线电压的正电压；
其中，该N型阱电压大于0V，且其电压值介于一第一漏极-源极饱和电压VDS-Sat1及一第二漏极-源极饱和电压VDS-Sat2之间，其中该第一漏极-源极饱和电压VDS-Sat1是确保在擦除操作初始时在该浮置栅极之下的一P通道两端不会发生夹断现象(pinchoff)的一上限电压，而该第二漏极-源极饱和电压VDS-Sat2是当该浮置栅极处于擦除状态时，确保在P通道的两端发生夹断现象的一下限电压。
2.根据权利要求1所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，更包括将一源极线电压施加到该PMOS选择晶体管的一P+源极掺杂区，将一字线电压施加到该PMOS选择晶体管的一选择栅极，其中该源极线电压及该字线电压皆为0V。
3.根据权利要求1所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，该半导体衬底为一P型硅衬底，该擦除栅极区域设于一P型阱中，其中该擦除栅极区域包含一重掺杂区，设于该P型阱中，并邻近该浮置栅极延伸部。
4.根据权利要求3所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，该重掺杂区为一N+掺杂区。
5.根据权利要求3所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，另包含：
对该P型阱施加一P型阱电压；以及
对该半导体衬底施加一衬底电压，其中该P型阱电压及该衬底电压皆为0V。
6.根据权利要求1所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，该单层多晶硅非易失性存储单元另包含一沟道隔离区域，将该第一氧化物界定区域与该第二氧化物界定区域隔离。
7.根据权利要求6所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，该PMOS选择晶体管及该PMOS浮置栅极晶体管均设置在该第一氧化物界定区域上，其中该PMOS选择晶体管透过一P+共享掺杂区与该PMOS浮置栅极晶体管串接在一起。
8.根据权利要求1所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，该擦除线电压介于12～20V。
9.根据权利要求1所述的单层多晶硅非易失性存储单元的操作方法，其特征在于，该N型阱电压介于1～3V。
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