CN108288486A - 非易失性存储器的驱动电路 - Google Patents
非易失性存储器的驱动电路 Download PDFInfo
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Abstract
本发明提供一种非易失性存储器的驱动电路。该驱动电路包括:一第一驱动器、一切换电路与一第二驱动器。第一驱动器接收一输入信号与一反相的输入信号,并产生一驱动信号。切换电路,接收该驱动信号与一第一模式信号,并在一输出端产生一输出信号。第二驱动器,连接于该输出端。
Description
技术领域
本发明涉及一种驱动电路,且特别涉及一种运用于非易失性存储器的驱动电路。
背景技术
众所周知,非易失性存储器可在电源消失之后,仍可保存数据,因此非易失性存储器已经广泛的运用于电子产品中。再者,非易失性存储器中包括多个非易失性存储器胞(non-volatile cell)排列而成非易失性存储器胞阵列(non-volatile cell array),而每个非易失性存储器胞中皆包含一浮动栅晶体管(floating gate transistor)。
请参照图1,其所绘示为易失性存储器示意图。非易失性存储器中包括一非易失性存储器胞阵列110与一驱动电路(driving circuit)120。其中,驱动电路120连接至非易失性存储器胞阵列110,且驱动电路120可在各种运作模式下提供各种驱动信号OUT至非易失性存储器胞阵列110。
举例来说,根据非易失性存储器胞阵列的运作模式,驱动电路120提供适当的驱动信号OUT来操控非易失性存储器胞阵列110进行读取运作(read operation)或者编程运作(program operation)。
发明内容
本发明的主要目的是提出一种非易失性存储器中的驱动电路,可在高温的环境下,稳定地提供驱动信号至非易失性存储器胞阵列。
本发明涉及一种驱动电路,包括:一第一晶体管,其源极与体极连接至一第一供应电压,漏极连接至一节点a1、栅极连接至一节点b1或一节点b2;一第二晶体管,其源极与体极连接至该第一供应电压,漏极连接至该节点b1、栅极连接至一节点a1或一节点a2;一第三晶体管,其源极连接至一第二供应电压,体极连接至该第一供应电压或该节点a1,漏极与栅极连接至该节点a1;一第四晶体管,其源极连接至该第二供应电压,体极连接至该第一供应电压或该节点b1,漏极与栅极连接至该节点b1;一第五晶体管,其源极与体极连接至该节点a1,栅极连接至该第二供应电压、漏极连接至该节点a2;一第六晶体管,其源极与体极连接至该节点b1,栅极连接至该第二供应电压、漏极连接至该节点b2;其中,该节点b2产生一驱动信号;一第七晶体管,其源极与体极连接至该节点a2,栅极连接至一第三供应电压、漏极连接至一节点a3;一第八晶体管,其源极与体极连接至该节点b2,栅极连接至该第三供应电压、漏极连接至一节点b3;一第九晶体管,其漏极连接至该节点a3、栅极连接至一第四供应电压、源极连接至一节点a4、体极连接至一第五供应电压,其中该第四供应电压异于该第三供应电压;一第十晶体管,其漏极连接至该节点b3、栅极连接至该第四供应电压、源极连接至一节点b4、体极连接至该第五供应电压;一第十一晶体管,其漏极连接至该节点a4、栅极接收一输入信号、源极与体极连接至该第五供应电压;一第十二晶体管,其漏极连接至该节点b4、栅极接收一反相的输入信号、源极连接至一第六供应电压、体极连接至该第五供应电压;一第一偏压电路,连接至该节点a2;以及一第二偏压电路,连接至该节点b2。
本发明涉及一种驱动电路,包括:一第一驱动器,包括:一第一晶体管,其源极与体极连接至一第一供应电压,漏极连接至一节点a1、栅极连接至一节点b1或一节点b2;一第二晶体管,其源极与体极连接至该第一供应电压,漏极连接至该节点b1、栅极连接至一节点a1或一节点a2;一第三晶体管,其源极连接至一第二供应电压,体极连接至该第一供应电压或该节点a1,漏极与栅极连接至该节点a1;一第四晶体管,其源极连接至该第二供应电压,体极连接至该第一供应电压或该节点b1,漏极与栅极连接至该节点b1;一第五晶体管,其源极与体极连接至该节点a1,栅极连接至该第二供应电压、漏极连接至该节点a2;一第六晶体管,其源极与体极连接至该节点b1,栅极连接至该第二供应电压、漏极连接至该节点b2;一第七晶体管,其源极与体极连接至该节点a2,栅极连接至一第三供应电压、漏极连接至一节点a3;一第八晶体管,其源极与体极连接至该节点b2,栅极连接至该第三供应电压、漏极连接至一节点b3;一第九晶体管,其漏极连接至该节点a3、栅极连接至一第四供应电压、源极连接至一节点a4、体极连接至一第五供应电压,其中该第四供应电压异于该第三供应电压;一第十晶体管,其漏极连接至该节点b3、栅极连接至该第四供应电压、源极连接至一节点b4、体极连接至该第五供应电压;一第十一晶体管,其漏极连接至该节点a4、栅极接收一输入信号、源极与体极连接至该第五供应电压;一第十二晶体管,其漏极连接至该节点b4、栅极接收一反相的输入信号、源极连接至一第六供应电压、体极连接至该第五供应电压;一第一偏压电路,连接至该节点a2;以及一第二偏压电路,连接至该节点b2;一第一切换电路,连接于该节点b2与一第一输出端之间;以及一第二驱动器,连接于该第一输出端,且该第一输出端产生一第一输出信号。
为了对本发明的上述及其他方面有更佳的了解,下文特举实施例,并配合附图详细说明如下:
附图说明
图1所所绘示为易失性存储器示意图。
图2所绘示为本发明的第一实施例非易失性存储器的驱动电路。
图3A所绘示为本发明的第二实施例运用于非易失性存储器的驱动电路。
图3B所绘示为本发明第二实施例中的第一偏压电路。
图3C所绘示为本发明第二实施例中的第二偏压电路。
图4A所绘示为本发明的第三实施例运用于非易失性存储器的驱动电路。
图4B所绘示为本发明第三实施例中的第三偏压电路。
图4C所绘示为本发明第三实施例中的第四偏压电路。
图4D所绘示为本发明第三实施例驱动电路运作于各种操作状态时的真值表。
【符号说明】
110:非易失性存储器胞阵列
120、200、300:驱动电路
310、320、430、440:偏压电路
400、460、465:驱动器
450、455:切换电路
具体实施方式
请参照图2,其所绘示为本发明的第一实施例非易失性存储器的驱动电路。驱动电路200可提供一驱动信号OUT至非易失性存储器胞阵列(未绘示)。
驱动电路200包括:包括多个p型晶体管m1~m8,以及多个n型晶体管m9~m12。其中,晶体管m1~m4的体极(body terminal)连接至第一供应电压Vpp1,晶体管m9~m12的体极连接至第五供应电压Vnn,第一供应电压Vpp1有最高的电压值,第五供应电压Vnn有最低的电压值。
晶体管m1源极连接至第一供应电压Vpp1、栅极连接至节点b2、漏极连接至节点a1;晶体管m2源极连接至第一供应电压Vpp1、栅极连接至节点a2、漏极连接至节点b1;晶体管m3源极连接至第二供应电压Vpp2、栅极与漏极连接至节点a1;晶体管m4源极连接至第二供应电压Vpp2、栅极与漏极连接至节点b1。
另外,第一实施例的晶体管m3与晶体管m4的体极连接至连接至第一供应电压Vpp1。在此领域的技术人员也可以将晶体管m3的体极连接至节点a1,并将晶体管m4的体极连接至节点b1,以降低体极效应(body effect)。
另外,第一实施例的晶体管m1与晶体管m2的栅极分别连接至节点b2与节点a2。在此领域的技术人员也可以将晶体管m1的栅极连接至节点b1,并将晶体管m2的栅极连接至节点a1。如此,晶体管m1与晶体管m2的栅极与源极之间的电压差(voltage difference)会比第一实施例中晶体管m1与晶体管m2的栅极与源极之间的电压差还要小,以确定晶体管m1与晶体管m2可以操作在安全运作区(safe operation area,SOA)的保护范围。
晶体管m5源极与体极连接至节点a1、栅极连接至第二供应电压Vpp2、漏极连接至节点a2;晶体管m6源极与体极连接至节点b1、栅极连接至第二供应电压Vpp2、漏极连接至节点b2;其中,第二供应电压Vpp2小于等于第一供应电压Vpp1,且节点b2可产生驱动信号OUT。
再者,晶体管m7源极与体极连接至节点a2、栅极连接至第三供应电压Vpp3、漏极连接至节点a3;晶体管m8源极与体极连接至节点b2、栅极连接至第三供应电压Vpp3、漏极连接至节点b3;其中,第三供应电压Vpp3小于等于第二供应电压Vpp2。
晶体管m9漏极连接至节点a3、栅极连接至第四供应电压Vpp4、源极连接至节点a4;晶体管m10漏极连接至节点b3、栅极连接至第四供应电压Vpp4、源极连接至节点b4;晶体管m11漏极连接至节点a4、栅极连接至输入信号IN、源极连接至第五供应电压Vnn;晶体管m12漏极连接至节点b4、栅极连接至反相的输入信号INb、源极连接至第六供应电压Vpr。其中,第六供应电压Vpr小于等于第三供应电压Vpp3,且第六供应电压Vpr大于等于第五供应电压Vnn。
当驱动电路200在运作时,在某些状况下会造成节点a2或者节点b2呈现浮接状态(floating)。举例来说,在节点b2呈现浮接状态时,晶体管m6的源极与漏极之间的电压差(voltage difference)可能超过其安全运作区(safe operation area,简称SOA)。同理,晶体管m1的源极与栅极之间的电压差也可能超过其安全运作区。另外,当晶体管m1与晶体管m6超过安全运作区后,会导致漏电流(leakage current)增加,进而影响供应电压与驱动信号OUT,并使得非易失性存储器胞阵列无法正常运作。再者,所谓的安全运作区(SOA)的定义为晶体管在运作的过程中不会造成自我损伤(self-damage)的电压状况。根据安全运作区(SOA)的规格书,晶体管的源极与漏极之间的电压差Vds_soa必须小于等于8.5V,晶体管的栅极与源极之间的电压差Vgs_soa必须小于等于11.5V。
请参照图3A,其所绘示为本发明的第二实施例运用于非易失性存储器的驱动电路。与第一实施例的差异在于,第二实施例的驱动电路300中,增加一第一偏压电路310与第二偏压电路320分别连接至节点a2与b2。
相同地,第二实施例的驱动电路中,晶体管m3的体极也可改连接至节点a1,晶体管m4的体极也可改连接至节点b1,以降低体极效应(body effect)。
另外,晶体管m1的栅极也可改连接至节点b1,晶体管m2的栅极也可改连接至节点a1。如此,晶体管m1与晶体管m2的栅极与源极之间的电压会比第二实施例中晶体管m1与晶体管m2的栅极与源极之间的电压差还要小,以确定晶体管m1与晶体管m2可以操作在安全运作区(SOA)的保护范围。
根据本发明的第二实施例,第一供应电压Vpp1为为非易失性存储器的编程电压(program voltage),第六供应电压Vpr为非易失性存储器的读取电压,第二供应电压Vpp2不大于两倍的Vds_soa,第三供应电压Vpp3不大于Vgs_soa。举例来说,第一供应电压Vpp1为21V,第二供应电压Vpp2为17V(2×8.5V),第三供应电压Vpp3为11.5,第四供应电压Vpp4为4.5V,第五供应电压Vnn为0V,第六供应电压Vpr为1.5V。
请参照图3B,其所绘示为本发明第二实施例中的第一偏压电路。请参照图3C,其所绘示为本发明第二实施例中的第二偏压电路。
如图3B所示,第一偏压电路310:包括n型晶体管m13与p型晶体管m14。晶体管m13漏极连接至节点a2,栅极接收第一特定电压VM1;以及,晶体管m14源极连接至晶体管m13源极,栅极接收反相的输入信号INb,漏极接收第二特定电压VN1。根据本发明的实施例,第二特定电压VN1小于等于第一特定电压VM1。例如,第一特定电压VM1与第二特定电压VN1皆为Vds_soa(8.5V)。
如图3C所示,第二偏压电路320:包括n型晶体管m15与p型晶体管m16。晶体管m15漏极连接至节点b2,栅极接收第三特定电压VM2;以及,晶体管m16源极连接至晶体管m15源极,栅极接收输入信号IN,漏极接收第四特定电压VN2。根据本发明的实施例,第四特定电压VN2小于等于第三特定电压VM2。例如,第三特定电压VM2与第四特定电压VN2皆为Vds_soa(8.5V)。
另外,晶体管m13与晶体管m15的体极可以连接至第五供应电压Vnn,晶体管m14的体极与漏极相互连接,晶体管m16的体极与漏极相互连接。
以下以节点a2为例来做说明为何节点a2不会呈现浮接状态。当输入信号IN为高逻辑电平且反相的输入信号INb为低逻辑电平时,第二偏压电路320被禁能(diasble),第一偏压电路310被致能(enable)。当第二偏压电路320被禁能时,节点b2的电压为第一供电电压Vpp1。当第一偏压电路310被致能时,节点a2的电压为(VM1-Vth13),其中Vth13为晶体管m13的临限电压(threshold voltage),例如Vth13为0.8V。在此情况下,节点a2的电压为7.7V(8.5V-0.8V)。因此,对于晶体管m7来说,其漏极与源极的电压差Vds7为7.7V。也就是说,晶体管m7会在安全运作区(SOA)内。
反之,当输入信号IN为低逻辑电平且反相的输入信号INb为高逻辑电平时,第一偏压电路310被禁能(diasble),第二偏压电路320被致能(enable)。节点b2的电压为(VM2-Vth15),其中Vth15为晶体管m15的临限电压,例如Vth13为0.8V。在此情况下,节点b2的电压为7.7V(8.5V-0.8V)。因此,对于晶体管m8来说,其的漏极与源极的电压差Vds8为7.7V。也就是说,晶体管m8会在安全运作区(SOA)内。
由以上的说明可知,第二实施例的驱动电路300可以使得节点a2不会呈现浮接状态。同理,第二实施例的驱动电路300也可以使得节点b2不会呈现浮接状态。
请参照图4A,其所绘示为本发明的第三实施例运用于非易失性存储器的驱动电路。第三实施例的驱动电路包括一第一驱动器(driver)400、一第二驱动器460、一第三驱动器465、一第一切换电路(switching circuit)450与一第二切换电路455。其中,第一驱动器400与第二实施例的驱动电路300完全相同,此处不再赘述。
相较于第二实施例,第三实施例增加了第一切换电路450、第二切换电路455、第二驱动器460与第三驱动器465。其中,第一切换电路450连接于节点b2与一第一输出端之间,且第一输出端可产生第一输出信号OUT1。第二切换电路455连接于节点b2与一第二输出端之间,且第二输出端可产生第二输出信号OUT2。再者,第二驱动器460连接至第一输出端;第三驱动器465连接至第二输出端。
第一切换电路450中,p型晶体管m17~m19作为开关(switch)的用途。其中,晶体管m17源极接收驱动信号OUT、体极连接至源极、栅极接收模式信号(mode signal)M1、漏极连接至节点x1;晶体管m18源极连接至节点x1、体极连接至源极、栅极接收第二供应电压Vpp2、漏极连接至节点x2;晶体管m19源极连接至节点x2、体极连接至源极、栅极接第三供应电压Vpp3、漏极连接至第一输出端以产生第一输出信号OUT1。
第二驱动器460包括n型晶体管m20~m22,晶体管m20~m22的体极皆连接至第五供应电压Vnn。晶体管m20漏极连接至第一输出端,栅极接收第四供应电压Vpp4;晶体管m21漏极连接至晶体管m20源极、栅极接收反相的输入信号INb、源极连接至第六供应电压Vpr;晶体管m22极漏极连接至晶体管m20源极、栅极接收模式信号M2、源极连接至第六供应电压Vpr。
同理,为了防止节点x1与x2在驱动电路运作的过程呈现浮接状态,本发明更提供一第三偏压电路430连接于节点x1,以及提供一第四偏压电路440连接于节点x2。
第二切换电路455中,p型晶体管m26作为开关的用途。其中,晶体管m26源极接收驱动信号OUT、体极连接至源极、栅极接收第七特定电压VM4、漏极连接至第二输出端以产生第二输出信号OUT2。其中,第七特定电压VM4等于Vds_soa(8.5V)。
第三驱动器465包括n型晶体管m27、m28,晶体管m27、28的体极皆连接至第五供应电压Vnn。晶体管m27漏极连接至第二输出端,栅极接收第四供应电压Vpp4;晶体管m28漏极连接至晶体管m27源极、栅极接收反相的输入信号INb、源极连接至第六供应电压Vpr。
请参照图4B,其所绘示为本发明第三实施例中的第三偏压电路430。请参照图4C,其所绘示为本发明第三实施例中的第四偏压电路440。
第三偏压电路430:包括p型晶体管m23。晶体管m23源极连接接收第二供应电压Vpp2、栅极、体极与漏极皆连接至节点x1。根据本发明的实施例,第三偏压电路430可供应(Vpp2-|Vth23|)至节点x1。其中,Vth23为晶体管m23的临限电压。
第四偏压电路440:包括或门(OR gate)411、非门412、n型晶体管m24与p型晶体管m25。非门412接收模式信号M2并产生反相的模式信号M2。或门411接收输入信号IN与反相的模式信号M2。晶体管m24漏极连接至节点x2,栅极接收第五特定电压VM3;晶体管m25源极连接至晶体管m24源极,栅极连接至或非门411的输出端,漏极接收第六特定电压VN3。根据本发明的实施例,第六特定电压VN3大于等于第五特定电压VM3。例如,第五特定电压VM3与第六特定电压VN3皆等于Vsd_soa(8.5V)。
当输入信号IN为低逻辑电平且模式信号M2为高逻辑电平时,第四偏压电路440被致能(enable),使得节点x2电压为(VM3-|Vth24|)。其中,Vth24为晶体管m24的临限电压,例如Vth24为0.8V。因此,节点x2电压为7.7V(8.5V-0.8V)。
请参照图4D,其所绘示为本发明第三实施例驱动电路运作于各种操作状态时的真值表。
其中,在第一模式时,模式信号M1为Vpp1,模式信号M2为Vdd;在第二模式时,模式信号M1为Vpp2或者VM3,而模式信号M2为0V。
在第一操作状态时,驱动电路处在第一模式、输入信号IN为Vdd且反相的输入信号INb为0V时,节点a2的电压为(VM1-|Vth13|)、节点b2的电压为第一供应电压Vpp1、节点x1的电压为(Vpp2-|Vth23|)、x2的电压为(VM3-|Vth24|)、第一输出信号OUT1为第六供应电压Vpr、且第二输出信号OUT2为第一供应电压Vp1。
在第二操作状态时,驱动电路处于第二模式、输入信号IN为Vdd且反相的输入信号INb为0V时,节点a2的电压为(VM1-|Vth13|)、节点b2的电压为第一供应电压Vpp1、节点x1、x2与第一输出信号OUT1的电压皆为第一供应电压Vpp1、且第二输出信号OUT2为第一供应电压Vpp1。
在第三操作状态时,驱动电路处在第一模式、输入信号IN为0V且反相的输入信号INb为Vdd时,节点a2的电压为第一供应电压Vpp1、节点b2的电压为(VM2-|Vth15|)、节点x1的电压为(Vpp2-|Vth23|)、x2的电压为(VM3-|Vth24|)、第一输出信号OUT1为第六供应电压Vpr、且第二输出信号OUT2为第六供应电压Vpr。
在第四操作状态时,驱动电路处于第二模式、输入信号IN为0V且反相的输入信号INb为Vdd时,节点a2的电压为第一供应电压Vpp1、节点b2的电压为(VM2-|Vth15|)、节点x1的电压为(Vpp2-|Vth23|)、节点x2的电压为(VM3-|Vth24|)、第一输出信号OUT1为第六供应电压Vpr、且第二输出信号OUT2为第六供应电压Vpr。
由以上的说明可知,本发明第二实施例与第三实施例的驱动电路确实可以让节点不会呈现浮接状态。因此,第二实施例与第三实施例的驱动电路可以使非易失性存储器胞阵列正常运作。
再者,在此技术领域的技术人员也可以对本发明进行修改并达成本发明所教示的功能。举例来说,驱动电路可以修改为仅有第一驱动器、第二驱动器与第一切换电路。而驱动电路仅输出第一输出信号OUT1。而省略输出第二驱动信号OUT2的第三驱动器与第二切换电路。
综上所述,虽然本发明已以实施例公开如上,然其并非用以限定本发明。本发明所属领域技术人员在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视所附权利要求书界定范围为准。
Claims (19)
1.一种驱动电路,连接至非易失性存储器胞阵列,该驱动电路包括:
第一晶体管,其源极与体极连接至第一供应电压,漏极连接至节点(a1)、栅极连接至节点(b1)或节点(b2);
第二晶体管,其源极与体极连接至该第一供应电压,漏极连接至该节点(b1)、栅极连接至节点(a1)或节点(a2);
第三晶体管,其源极连接至第二供应电压,体极连接至该第一供应电压或该节点(a1),漏极与栅极连接至该节点(a1);
第四晶体管,其源极连接至该第二供应电压,体极连接至该第一供应电压或该节点(b1),漏极与栅极连接至该节点(b1);
第五晶体管,其源极与体极连接至该节点(a1),栅极连接至该第二供应电压、漏极连接至该节点(a2);
第六晶体管,其源极与体极连接至该节点(b1),栅极连接至该第二供应电压、漏极连接至该节点(b2);其中,该节点(b2)产生驱动信号;
第七晶体管,其源极与体极连接至该节点(a2),栅极连接至第三供应电压、漏极连接至节点(a3);
第八晶体管,其源极与体极连接至该节点(b2),栅极连接至该第三供应电压、漏极连接至节点(b3);
第九晶体管,其漏极连接至该节点(a3)、栅极连接至第四供应电压、源极连接至节点(a4)、体极连接至第五供应电压,其中该第四供应电压异于该第三供应电压;
第十晶体管,其漏极连接至该节点(b3)、栅极连接至该第四供应电压、源极连接至节点(b4)、体极连接至该第五供应电压;
第十晶体管,其漏极连接至该节点(a4)、栅极接收输入信号、源极与体极连接至该第五供应电压;
第十二晶体管,其漏极连接至该节点(b4)、栅极接收反相的输入信号、源极连接至第六供应电压、体极连接至该第五供应电压;
第一偏压电路,连接至该节点(a2);以及
第二偏压电路,连接至该节点(b2)。
2.如权利要求1所述的驱动电路,其中该第一偏压电路包括:
第十三晶体管,栅极接收第一特定电压、漏极连接至该节点(a2);以及
第十四晶体管,源极连接至该第十三晶体管的源极、栅极接收该反相的输入信号、漏极连接至第二特定电压。
3.如权利要求2所述的驱动电路,其中该第二偏压电路包括:
第十五晶体管,栅极接收第三特定电压、漏极连接至该节点(b2);以及
第十六晶体管,源极连接至该第十五晶体管的源极、栅极接收该输入信号、漏极接收第四特定电压。
4.如权利要求3所述的驱动电路,其中该第十三晶体管的体极连接至该第五供应电压,该第十四晶体管的体极与漏极相互连接,该第十五晶体管的体极连接至该第五供应电压,该第十六晶体管的体极与漏极相互连接。
5.如权利要求3所述的驱动电路,其中该第二特定电压小于等于该第一特定电压;以及该第四特定电压小于等于该第三特定电压。
6.如权利要求1所述的驱动电路,其中该第一供应电压大于等于该第二供应电压,该第二供应电压大于等于该第三供应电压,该第三供应电压大于该第四供应电压。
7.一种驱动电路,连接至非易失性存储器胞阵列,该驱动电路包括:
第一驱动器,包括:
第一晶体管,其源极与体极连接至第一供应电压,漏极连接至节点(a1)、栅极连接至节点(b1)或节点(b2);
第二晶体管,其源极与体极连接至该第一供应电压,漏极连接至该节点(b1)、栅极连接至节点(a1)或节点(a2);
第三晶体管,其源极连接至第二供应电压,体极连接至该第一供应电压或该节点(a1),漏极与栅极连接至该节点(a1);
第四晶体管,其源极连接至该第二供应电压,体极连接至该第一供应电压或该节点(b1),漏极与栅极连接至该节点(b1);
第五晶体管,其源极与体极连接至该节点(a1),栅极连接至该第二供应电压、漏极连接至该节点(a2);
第六晶体管,其源极与体极连接至该节点(b1),栅极连接至该第二供应电压、漏极连接至该节点(b2);
第七晶体管,其源极与体极连接至该节点(a2),栅极连接至第三供应电压、漏极连接至节点(a3);
第八晶体管,其源极与体极连接至该节点(b2),栅极连接至该第三供应电压、漏极连接至节点(b3);
第九晶体管,其漏极连接至该节点(a3)、栅极连接至第四供应电压、源极连接至节点(a4)、体极连接至第五供应电压,其中该第四供应电压异于该第三供应电压;
第十晶体管,其漏极连接至该节点(b3)、栅极连接至该第四供应电压、源极连接至节点(b4)、体极连接至该第五供应电压;
第十晶体管,其漏极连接至该节点(a4)、栅极接收输入信号、源极与体极连接至该第五供应电压;
第十二晶体管,其漏极连接至该节点(b4)、栅极接收反相的输入信号、源极连接至第六供应电压、体极连接至该第五供应电压;
第一偏压电路,连接至该节点(a2);以及
第二偏压电路,连接至该节点(b2);
第一切换电路,连接于该节点(b2)与第一输出端之间;以及
第二驱动器,连接于该第一输出端,且该第一输出端产生第一输出信号。
8.如权利要求7所述的驱动电路,其中该第一偏压电路包括:
第十三晶体管,栅极连接至第一特定电压、漏极连接至该节点(a2);以及
第十四晶体管,源极连接至该第十三晶体管的源极、栅极接收该反相的输入信号、漏极连接至第二特定电压。
9.如权利要求8所述的驱动电路,其中该第二偏压电路包括:
第十五晶体管,栅极连接至第三特定电压、漏极连接至该节点(b2);以及
第十六晶体管,源极连接至该第十五晶体管的源极、栅极接收该输入信号、漏极接收第四特定电压。
10.如权利要求9所述的驱动电路,其中该第十三晶体管的体极接收该第五供应电压,该第十四晶体管的体极与漏极相互连接,该第十五晶体管的体极接收该第五供应电压,该第十六晶体管的体极与漏极相互连接。
11.如权利要求9所述的驱动电路,其中该第二特定电压小于等于该第一特定电压;且该第四特定电压小于等于该第三特定电压。
12.如权利要求7所述的驱动电路,其中该第一供应电压大于等于该第二供应电压,该第二供应电压大于等于该第三供应电压,该第三供应电压大于该第四供应电压。
13.如权利要求7所述的驱动电路,其中该第一切换电路包括:
第十七晶体管,其源极与体极连接至该节点(b2)、栅极接收第一模式信号、漏极连接至节点(x1);
第十八晶体管,其源极与体极连接至该节点(x1)、栅极接收该第二供应电压、漏极连接至节点(x2);
第十九晶体管,其源极与体极连接至该节点(x2)、栅极接收该第三供应电压、漏极连接至该第一输出端;
第三偏压电路,连接至该节点(x1);以及
第四偏压电路,连接至该节点(x2)。
14.如权利要求13所述的驱动电路,其中该第二驱动器包括:
第二十晶体管,漏极连接至该第一输出端、栅极接收该第四供应电压、体极接收该第五供应电压;
第二十晶体管,漏极连接至该第二十晶体管的源极、栅极接收该反相的输入信号、体极接收该第五供应电压、源极接收该第六供应电压;以及
第二十二晶体管,漏极连接至该第二十晶体管的源极、栅极接收第二模式信号、体极接收该第五供应电压、源极接收该第六供应电压。
15.如权利要求13所述的驱动电路,其中该第三偏压电路包括:
第二十三晶体管,源极连接至该第二供应电压、栅极与漏极连接至该节点(x1)、体极连接至该节点(x1)。
16.如权利要求15所述的驱动电路,其中该第四偏压电路包括:
或门,据有二输入端接收该输入信号与反相的该第二模式信号;
第二十四晶体管,漏极连接至该节点(x2)、栅极连接至第五特定电压;以及
第二十五晶体管,源极连接至该第二十四晶体管的源极、栅极连接至或门的输出端、漏极连接至第六特定电压。
17.如权利要求7所述的驱动电路,还包括:
第二切换电路,连接于该节点(b2)与第二输出端之间;以及
第三驱动器,连接于该第二输出端,且该第二输出端产生第二输出信号。
18.如权利要求17所述的驱动电路,其中该第二切换电路包括:
第二十六晶体管,其源极与体极连接至该节点(b2)、栅极接收第七特定电压、漏极连接至该第二输出端。
19.如权利要求17所述的驱动电路,其中该第三驱动器包括:
第二十七晶体管,漏极连接至该第二输出端、栅极连接至该第四供应电压、体极连接至该第五供应电压;以及
第二十八晶体管,漏极连接至该第二十七晶体管的源极、栅极接收该反相的输入信号、体极连接至该第五供应电压、源极连接至该第六供应电压。
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CN101030448A (zh) * | 2006-03-01 | 2007-09-05 | 松下电器产业株式会社 | 半导体存储器件及半导体集成电路系统 |
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TW201826503A (zh) | 2018-07-16 |
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US20180197613A1 (en) | 2018-07-12 |
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CN108346662A (zh) | 2018-07-31 |
EP3346474B1 (en) | 2019-08-28 |
JP2018125057A (ja) | 2018-08-09 |
TW201842505A (zh) | 2018-12-01 |
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US20180197872A1 (en) | 2018-07-12 |
US9882566B1 (en) | 2018-01-30 |
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US20180197875A1 (en) | 2018-07-12 |
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US10224108B2 (en) | 2019-03-05 |
US10083976B2 (en) | 2018-09-25 |
US10127987B2 (en) | 2018-11-13 |
TW201826505A (zh) | 2018-07-16 |
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