1294662 16534twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶體元件，且特別是有關於 種非揮發性記憶體及其製造方法與抹除方法。 η 、 【先前技術】 _記憶體，顧名思義便是用以儲存資料或數據的半導體 疋件。當電腦微處理器之功能越來越強，軟體所進行之程 式與運算越來越龐大時，記憶體之需求也就越來越高，= I製造容量大且便宜的記憶體以収這種需求的趨勢，製 體元件之技術與製程，已成為半導體科技持續往高 孝貝集度挑戰之驅動力。 福在各種記憶體產品中，具有可進行多次資料之存入、 作，且存入之資料在斷電後也不會消失之 記憶體’已成為個人電腦和電子設備所廣 之才木用的一種記憶體元件。 t音體=面為習二一種單層多晶邦ingle ρ_揮發性記 體 _。_1〇== MU隔開二由構—,場氧化層(FieW _ 底14 、〒NMOS、t構10係形成於一 p型基 摻雜區18、有一浮置開極16、閑氧化層34、N+源極 —n型離子井區==PMOs結構12係形成於 !294662 !6534twf.doc/006 下方’緊鄰P源極推雜區26 —侧配置有一]型 擒區3G。此外，在浮置閘極16、24之間還必須配 =置閘極‘線32 ’使浮置閘極16、24維持相同電位。 0 4知單層多晶矽非揮發性記憶體具有如下述之問 ，。舉例來說，習知單層多晶㈣揮發性記憶體是由一 MOS U冓1〇與一 pM〇s結構12所構成，因此所佔的晶 !!面^較大，相對地其所需的製造成本也較多。另一方面， f知單層多晶矽非揮發性記憶體於進行抹除(Erase)操作 時丄抹除時間較長，以致元件的操作速度較慢。而且，由 於習知單層多晶矽非揮發性記憶體的抹除操作是從浮置閘 極經由閘氧化層將電子拉出至基底中以進行抹除，所以容 易對閘氧化層造成損傷(Damage)，而影響記憶體元件的可 重複抹寫次數(Cycling Number)及其可靠度。 圖2為習知一種分離式閘極(邱出Gate)非揮發性記情 體之剖面示意圖。習知分離式閘極非揮發性記憶體是由基 底40、浮置閘極42、控制閘極44、源極區46與汲極區48 所構成。習知分離式閘極非揮發性記憶體存在的問題是， 記憶體元件的尺寸增加，而且其抹除操作易引起電子陷入 (Trapping)，以及降低耐久性(Endurance)。 【發明内容】 有鑑於此’本發明的目的就是在提供一種非揮發性記 憶體及其製造方法與抹除方法，能夠縮短抹除時間[辦^ 元件的操作速度’以及提南可重複抹寫次數。 本發明提出一種非揮發性記憶體，其係包括控制閑 6 1294662 16534twf.doc/006 極、浮置閘極、閘氧化層、源極區、汲極區、第一介電層、 第二介電層與抹除閘極。其中，控制閘極位於基底中，而 浮置閘極配置於控制閘極上，且位於部分基底上，浮置閘 極包括一耦合部分與一閘極部分。閘氧化層配置於浮置閘 極與基底之間。源極區配置於基底中，且鄰接浮置閑極之 閘極部分的一側。汲極區配置於基底中，且鄰接浮置閘極 ^閘極部分的另-侧。第一介電層配置於浮置閘極上。 二介電層配置於浮置閘極側壁。另外，抹除閘極配置 置閘極之_合部分上，且覆蓋第—介電層與第二介電層’。 緣呈發明的實施例所述，上述之浮置問極的頂;邊 濃捧=、本發明的實施例所述’上述之控彻極例如是― 如是===述’上述之抹除開極的材質例 明的實施例所述，上述之浮置閘極的材質例 如疋夕日日石夕或摻雜多晶石夕。 、 如是ί:發明的實施例所述’上述之閘氧化層的材質例 非揮種二揮t性記憶體的抹除方法，其中 配置;二;:極位於基底中;-浮置問極 ^控制閘極上，且位於部分基底上， 底::分與;開極部分;一閘氧化層配置於浮i閘二: 氏之間，-源極區配置於基底中，且鄰接浮置閘極之問極 7 1294662 16534twf.doc/〇〇6 部分的一側；一汲極區配置於基底中，且鄰接浮置閘極之 閑極部分的另一侧；一第一介電層配置於浮置閘極上；一 ^二介電層配置於浮置閘極側壁；以及_抹除閘極配置於 夺置閘極之搞合部分上，且覆蓋第二介電層。抹除方法包 括對控制閘極施加一第一電壓，對汲極施加一第二電壓， 對源極施加一第三電壓，對抹除閘極施加—第四電壓，以 及對基底施加-第五錢，以使電子從浮置雜拉出 除閘極中以進行抹除。 胃依照本發明的實施例所述，上述之第一電壓、第二電 壓、第三電壓與第五電壓為〇伏特，第㈣壓為12伏；私 ^本發明又提出一種非揮發性記憶體的製造方法，係先 、基底，基底中已形成有一元件隔離結構，以定義出 多數對主動區。紐，於每—對絲區之其中之—的基底 ^形成-控制閘極。之後，於基底上依序形成閘氧化層: ^層與職化之罩幕層，其中_化之罩幕層暴露出部 $體層。接著’於所暴露出的部分導體層表面形成第一 ^電層。繼之，移除圖案化之罩幕層，之後移除未被第一 二電層覆^之導體層，以所保留之導體層當作浮置閘極。 後於浮置閘極側壁形成第二介電層。接著，於對應控 二閘極之#置閘極上方形成抹除閘極，其巾抹除閘極覆蓋 弟；、丨私層與第二介電層。之後，於每一對主動區之其中 另的基底中形成源極區與汲極區，且源極區與汲極區分 別形成於浮置閘極兩侧。 依妝本發明的實施例所述，上述之浮置閘極的頂部邊 1294662 16534twf.doc/006 緣呈尖角狀。浮置閘極的材質例如是多晶胃 矽，而其形成方法例如是化學氣相沈積法。％”隹夕曰曰 本Γ月的實施例所述，上述之控制閘極例如是-/辰4雜區，其形成方法例如是離子植入法。 依照本發明的實施例所述，上述之抹 :，婦雜偷，其形成方法=== 如是=發 依照本發明的實闕所述，上述之元件隔離結構 疋场乳化層，其形成方法例如是區域氧化法。 本發明之非揮發性記憶體係於基底中形成濃 控制閘極’以及於浮置閘極上形成—抹成除^隹 許隹^增加晶片面積’造成製程成本增加以及影響元件 tt。另外，本發8狀非揮發性記賴的抹除操作是於 2閉極上施加-高電壓，將電子㈣至抹除難以進行 =，因此不會有習知之單層多晶石夕(single poly)非揮發性 ;=體因f:’氧化層損傷(Damage)的問題，而影響記憶體元 、可重複抹寫次數(Cycling Number)及其可靠度。再者， 發，之非揮發性記憶體的抹除操作速度所需的時間較 =’、彳呆作速度較快。除此之外，浮置閘極的頂部邊緣呈尖 狀助於在進行抹除操作時，可更佳提高抹除速度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 重，下文特舉實施例，並配合所附圖式，作詳細說明如 9BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a memory element, and more particularly to a non-volatile memory, a method of fabricating the same, and an erasing method. η, [Prior Art] _ Memory, as its name implies, is a semiconductor component used to store data or data. When the functions of computer microprocessors become stronger and stronger, and the programs and operations performed by software become larger and larger, the demand for memory becomes higher and higher. = I manufactures large and cheap memory to collect this kind of memory. The trend of demand, the technology and process of body components, has become the driving force for semiconductor technology to continue to challenge the high filial piety. In various memory products, Fu has a memory that can store and process multiple data, and the stored data will not disappear after power-off, which has become a wide range of personal computers and electronic devices. A memory component. T-sound = face is a two-layer polycrystalline state ingle ρ_volatile record _. _1 〇 == MU is separated by two structures, and the field oxide layer (FieW _ bottom 14, NMOS, t structure 10 is formed in a p-type doped region 18, has a floating open electrode 16, and an idle oxide layer 34 , N + source - n type ion well area = = PMOs structure 12 series formed in !294662 !6534twf.doc / 006 Below 'near P source doping area 26 - side configuration has a type of 擒 area 3G. In addition, floating Between the gates 16, 24 must also be equipped with = gate 'line 32' to maintain the same potential of the floating gates 16, 24 0 4 Know the single-layer polycrystalline non-volatile memory has the following questions. In other words, the conventional single-layer polycrystalline (four) volatile memory is composed of a MOS U冓1〇 and a pM〇s structure 12, so that the crystal!! surface is larger and relatively required. On the other hand, it is known that the single-layer polycrystalline non-volatile memory has a long erase time during the Erase operation, so that the operation speed of the device is slow. Moreover, due to the conventional single The layer polycrystalline non-volatile memory is erased from the floating gate through the gate oxide layer to pull the electrons out into the substrate for erasing, so it is easy to gate oxygen The layer causes damage and affects the Cycling Number of the memory component and its reliability. Figure 2 is a cross section of a non-volatile grammar of a separate gate (Gate) The conventional split gate non-volatile memory is composed of a substrate 40, a floating gate 42, a control gate 44, a source region 46 and a drain region 48. Conventional split gate non-volatile The problem with the memory is that the size of the memory element is increased, and the erase operation thereof is liable to cause Trapping and lowering the durability. [Invention] In view of the above, the object of the present invention is to provide A non-volatile memory, a manufacturing method thereof and an erasing method capable of shortening an erasing time [operation speed of a component] and a number of repeatable erasing times of the south. The present invention provides a non-volatile memory, which includes Control idle 6 1294662 16534twf.doc/006 pole, floating gate, gate oxide layer, source region, drain region, first dielectric layer, second dielectric layer and erase gate. Among them, control gate Located in the base while floating The pole is disposed on the control gate and is located on a portion of the substrate, the floating gate includes a coupling portion and a gate portion. The gate oxide layer is disposed between the floating gate and the substrate. The source region is disposed in the substrate, and Adjacent to one side of the gate portion of the floating idler. The drain region is disposed in the substrate and adjacent to the other side of the floating gate and the gate portion. The first dielectric layer is disposed on the floating gate. The electrical layer is disposed on the sidewall of the floating gate. In addition, the gate is disposed on the junction portion of the gate and covers the first dielectric layer and the second dielectric layer. According to the embodiment of the invention, the top of the floating question pole is embossed=, and the above-mentioned control pole is, for example, ―============================================= In the embodiment of the material, the material of the floating gate is, for example, a day or a day of doping polysilicon. For example, in the embodiment of the invention, the material of the above-mentioned gate oxide layer is not the wiping method of the two-sweep memory, wherein the configuration is the second; the pole is located in the substrate; the floating questioner is ^ The control gate is located on a portion of the substrate, and the bottom portion is divided into: an open portion; a gate oxide layer is disposed between the floating gates and the source region is disposed in the substrate and adjacent to the floating gate One side of the portion of the pole 1 1294662 16534twf.doc / 〇〇 6; a drain region is disposed in the substrate and adjacent to the other side of the idle pole portion of the floating gate; a first dielectric layer is disposed on the float The gate electrode is disposed on the sidewall of the floating gate; and the erase gate is disposed on the engaging portion of the gate and covers the second dielectric layer. The erasing method includes applying a first voltage to the control gate, applying a second voltage to the drain, applying a third voltage to the source, applying a fourth voltage to the erase gate, and applying a fifth to the substrate. Money, so that electrons are pulled from the floating impurities in addition to the gate for erasing. According to an embodiment of the invention, the first voltage, the second voltage, the third voltage and the fifth voltage are 〇V, and the (IV) voltage is 12 volts; the invention further proposes a non-volatile memory The manufacturing method is first, the substrate, and a component isolation structure has been formed in the substrate to define a majority of the active regions. New, in each of the - to the silk area - the base ^ formation - control gate. Thereafter, a gate oxide layer is sequentially formed on the substrate: a layer and a mask layer, wherein the mask layer exposes the body layer. Then, a first electric layer is formed on the surface of the exposed portion of the conductor layer. Following this, the patterned mask layer is removed, and then the conductor layer not covered by the first second electrical layer is removed, with the remaining conductor layer acting as a floating gate. A second dielectric layer is then formed on the sidewalls of the floating gate. Then, an erase gate is formed on the top of the corresponding gate of the control gate, and the wiper wipes the gate to cover the younger brother; the private layer and the second dielectric layer. Thereafter, a source region and a drain region are formed in another substrate of each pair of active regions, and the source region and the drain region are formed on both sides of the floating gate. According to an embodiment of the invention, the top edge of the floating gate is 1294662 16534 twf.doc/006, and the edge is sharp. The material of the floating gate is, for example, a polycrystalline stomach, and the forming method thereof is, for example, a chemical vapor deposition method. In the embodiment of the present invention, the control gate is, for example, a -/4 phase, and the formation method thereof is, for example, ion implantation. According to an embodiment of the present invention, the above Wipe: maternal thief, its formation method === If it is according to the invention, the above-mentioned component isolation structure is a field emulsification layer, and its formation method is, for example, a zone oxidation method. The memory system forms a rich control gate in the substrate and is formed on the floating gate - the smearing is increased, the wafer area is increased, and the process cost is increased and the component tt is affected. In addition, the 8-shaped non-volatile memory The erase operation is to apply a high voltage on the 2 closed pole, and it is difficult to carry out the electron (4) to erase, so there is no known single layer polycrystalline non-volatile; = body factor f: 'The problem of oxide damage, which affects memory cells, Cycling Number and its reliability. Furthermore, the time required for the erasure operation of non-volatile memory Compared with =', you can stay faster. In addition, float The top edge of the gate is pointed to help improve the erasing speed during the erasing operation. To make the above and other objects, features and advantages of the present invention more apparent, the following specific embodiments are provided. And with the accompanying drawings, a detailed description such as 9
1294662 16534twf.doc/006 下。 【實施方式】 圖3A至圖3H為依照本發明實施例所繪示之非揮發 性記憶體的製造流程上視圖。 首先，請參照圖3A，於基底1〇〇上形成元件隔離結 構102，以定義出一對主動區丨〇4a、i〇4b。其中，元件隔 離結構102例如是場氧化層(Field Oxide Layer)，而其形成 方法例如是區域氧化法（Local Oxidation of Silicon， LOCOS)。 接著，請參照圖3B，於主動區i〇4a、川仆之其中之 一的基底100中形成一控制閘極1〇6。於本實施例中是以 在主動區104a的基底1〇〇中形成控制閘極1〇6為例做說 明。其中，控制閘極106可例如是形成於基底1〇〇中之一 濃摻雜區(heavily doped region)，而其形成方法例如是離子 植入法。 之後，請參照® 3C，於基底100 ±依序形成一間氧 化層108、-導體層110與一圖案化之罩幕層112，其中圖 案化之罩幕層112暴露出部分導體層m。閘氧化層應 的材質例如是氧化梦’而其形成方法例如是 (Thermd Oxidation)。導體層11〇的材質例如是多晶得 法例如是化學氣相沈積法。另外： 圖木化之罩幕層112的材質例如是氮化 料’而其形成方法例如是進行—化學氣相沈積=虽的材 繼之，請残圖3D，於所暴露出的部分導體層11〇 1294662 16534twf.doc/006 表面形成一介電層114。其中，介恭 氧化石夕，而其形成方法例如是化風=層114的材質例如是 例中，於形成介電f 114時，可二^目，法。在一實施 而其所使用之高溫製程會使得導 了虱化法以形成之， 角狀。 _ u〇的頂部邊緣呈尖 然後，請參照圖3E，移除圖安儿 移除未被介麵1H覆蓋之導體^ 罩幕層112，接著 層當作一浮置閘極1U。其中，"，以所保留之導體 的方法例如是進行-㈣製程。/夕^，案化之罩幕層112 覆蓋之導體層1U)的方法例如是除未被介電層114 接著，請參照圖3F，於浮置閑二綱製程。 層Π6。其中，介電層116例⑴侧壁形成-介電 ，層，械方法例如是化學氣相沈積法。 之後’請參照圖3G，於對廄知… 極m上方形成一抹除閉極118^=，之浮置閘 介電層m與介電層116。抹除門除閘極118覆蓋 iru’而其形成方法例如是化學氣相沈積法。 杰B，清參照圖3H，於主動區104b的基底100中形 ^一源極區12〇與-祕區122，且源極區12G與沒極區 、、刀別形成於洋置閘極111兩側。其中，源極區120與 ;及極區122的形成方法例如是進行—離子植入法。 ^接著，在完成非揮發性記憶體之製程後，更可進行後 、、貝之層間介電層（lnter Layer Dielectric，ILD)、接觸窗 (Contact)、導體層等製作，而其製程及相關製程參數，為 11 1294662 16534twf.doc/006 熟習此項技術者所能輕易達成，於此不再贅述。 由上述可知，本發明之非揮發性體= 利用-般半導體製程即可完成。亦即是，本;二: m-般半導體製程結合，而不需進行 耘，如此一來可節省製程成本與時間。 衣 接下來，係_本發明之非揮發性記倾的結構 -仅實施觸㈣之轉發性記憶體的剖面1294662 16534twf.doc/006. 3A to 3H are top views of a manufacturing process of a non-volatile memory according to an embodiment of the invention. First, referring to Fig. 3A, an element isolation structure 102 is formed on the substrate 1 to define a pair of active regions 丨〇4a, i〇4b. The component isolation structure 102 is, for example, a Field Oxide Layer, and the formation method thereof is, for example, Local Oxidation of Silicon (LOCOS). Next, referring to FIG. 3B, a control gate 1〇6 is formed in the substrate 100 of one of the active area i〇4a and the servant. In the present embodiment, the control gate 1〇6 is formed in the substrate 1A of the active region 104a as an example. Wherein, the control gate 106 can be formed, for example, in a heavily doped region of the substrate 1 , and the formation method thereof is, for example, ion implantation. Thereafter, referring to the ® 3C, an oxide layer 108, a conductor layer 110 and a patterned mask layer 112 are sequentially formed on the substrate 100, wherein the patterned mask layer 112 exposes a portion of the conductor layer m. The material of the gate oxide layer is, for example, an oxidized dream, and its formation method is, for example, (Thermd Oxidation). The material of the conductor layer 11A is, for example, a polycrystalline method such as a chemical vapor deposition method. In addition, the material of the mask layer 112 is, for example, a nitride material, and the formation method thereof is, for example, performing chemical vapor deposition = the material is followed, and the residual layer 3D is exposed. 11〇1294662 16534twf.doc/006 A dielectric layer 114 is formed on the surface. Here, the oxidized stone is formed, and the forming method is, for example, the material of the wind=layer 114. For example, in the case of forming the dielectric f 114, the method can be used. In one implementation, the high temperature process used will result in the formation of a squaring process. The top edge of the _ u 呈 is pointed. Then, referring to FIG. 3E, removing the conductor Shield layer 112 that is not covered by the interface 1H, and then the layer acts as a floating gate 1U. Among them, ", with the method of retaining the conductor, for example, is to carry out the - (four) process. For example, the method of covering the conductor layer 1U) of the mask layer 112 is, for example, followed by the dielectric layer 114, please refer to FIG. 3F for the floating process. Layer Π 6. Among them, the dielectric layer 116 (1) sidewall forming-dielectric, layer, mechanical method is, for example, chemical vapor deposition. Thereafter, please refer to FIG. 3G, and a floating gate dielectric layer m and a dielectric layer 116 are formed over the pole m. The erase gate gate 118 covers iru' and is formed by, for example, chemical vapor deposition. Jie B, according to FIG. 3H, a source region 12〇 and a secret region 122 are formed in the substrate 100 of the active region 104b, and the source region 12G and the non-polar region are formed, and the knife is formed on the ocean gate 111. On both sides. The method of forming the source regions 120 and the polar regions 122 is, for example, performing ion implantation. ^ Then, after the process of non-volatile memory is completed, the interlayer dielectric layer (ILD), contact window (Contact), conductor layer, etc. can be fabricated, and the process and related processes are performed. The process parameters are 11 1294662 16534twf.doc/006. Those skilled in the art can easily achieve this, and will not be described here. From the above, it can be understood that the nonvolatile body of the present invention can be completed by a general semiconductor process. That is, this; two: m-like semiconductor process combination, without the need to carry out, so as to save process costs and time. Next, the structure of the non-volatile tilting of the present invention - only the cross section of the transmissive memory of the touch (four)
η依據圖Μ沿14,方向之非揮發性記憶體的剖 面不意圖。 4 技錄圖3H與圖4，本發明之非揮發性記憶體 係由控制閘極1〇6、浮置閘極⑴、閘氧化層應、源極區 120、汲極區122、介電層114、介電層m，以及抹除閘 極118所構成。 不于閘η is not intended to follow the section of the non-volatile memory in the direction of the Μ. 4 Technical Record 3H and FIG. 4, the non-volatile memory system of the present invention comprises a control gate 1〇6, a floating gate (1), a gate oxide layer, a source region 120, a drain region 122, and a dielectric layer 114. The dielectric layer m and the erase gate 118 are formed. Not brake
控制閘極106位於基底刚中，其中控制閘極1〇6可 例如是-濃摻雜區。另外，浮置閘極ln配置於控制閑極 106上，且位於部分基底1〇〇上，而浮置閘極m包括一 ，合部分與—閘極部分，其中浮置閘極111 _合部分是 主動區l〇4a之浮置閘極⑴，浮置閘極nl的麵合 口P刀疋指位於主動區104b之浮置閘極ηι。浮置閘極Η 的材質例如是多晶石夕或摻雜多晶石夕。在—實施例中，浮置 閘極111的頂部邊緣呈如圖2之箭頭124所示的尖角狀。 另外’問氧化層108配置於浮置閘極111與基底100 之間’其材質例如是氧切，閘氧化層⑽係用以隔絕浮 置閘極111與控制閘極1〇6，以及浮置閘極⑴與基底 12 1294662 16534twf.doc/006 ιυυ。源極區The control gate 106 is located in the substrate just as the control gate 1 〇 6 can be, for example, a dense doped region. In addition, the floating gate ln is disposed on the control idler 106 and is located on a portion of the substrate 1 ,, and the floating gate m includes a merging portion and a gate portion, wherein the floating gate 111 _ part It is the floating gate (1) of the active region l〇4a, and the surface of the floating gate n1 is located at the floating gate η of the active region 104b. The material of the floating gate 例如 is, for example, polycrystalline or doped polycrystalline. In the embodiment, the top edge of the floating gate 111 has a pointed shape as indicated by an arrow 124 in FIG. In addition, the 'oxide layer 108 is disposed between the floating gate 111 and the substrate 100. The material thereof is, for example, oxygen cut. The gate oxide layer (10) is used to isolate the floating gate 111 and the control gate 1〇6, and is floating. Gate (1) and substrate 12 1294662 16534twf.doc/006 ιυυ. Source area
•里々；签低—»，儿w设汁置閑極iH 之閘極部分的一側。汲極區122配置於基底丨⑻中，且 接净置閘極111之閘極部分的另一側。抹除閘極118 I 於浮置閘極111之麵合部分上，且覆蓋介電層114與介 層116，其中抹除閘極118的材質例如是多晶石夕或換雜: 晶石夕。介電層114配置於浮置閘極lu上，而介電夕 配置於浮置閘極⑴側壁，其中介電層114與介電^ 6 係用以隔絕浮置閘極111與抹除閘極118。 、另一方面，本發明之非揮發性記憶體係於基底中 -濃掺雜區當作是控糊極，以及於浮置騎上形成」 除閘極’因此不會增加晶片面積，造成製程成本增加，以 及影響元件積集度。 以 接著，請再次參照圖4，以明瞼太恭a日杏#η 發性記紐之抹除(Em峨作模Μ之非揮 廳Λ對 =發性記憶體進行抹除操作時，對控制閘極 也口电壓V!，對汲極122施加一 120施加一電壓v對枯烬 电監2對源極 對基底刚施加一電壓ί 施加一電壓V4，以及 至抹除_财==使^置雜111拉出 恭歐V 、延仃抹除。其中，電壓Vi、電壓V2、 :太k私聖V5為0伏特’而電麼V4為12伏特。換古 施力ΐ5非揮發性記憶體的抹除操作是於抹除閘極I 細加一咼電壓以進行之。 上丄 是，二;:二：料㈣體進行程式化操作的方法例如 疋對“閉極106施加一電屋V】，對汲極122施加一電• Lieutenant; sign low –», set the side of the gate of the idle iH. The drain region 122 is disposed in the substrate (8) and is connected to the other side of the gate portion of the gate 111. The gate electrode 118 I is disposed on the surface of the floating gate 111 and covers the dielectric layer 114 and the dielectric layer 116. The material of the erase gate 118 is, for example, polycrystalline or mixed: . The dielectric layer 114 is disposed on the floating gate lu, and the dielectric layer is disposed on the sidewall of the floating gate (1). The dielectric layer 114 and the dielectric layer 6 are used to isolate the floating gate 111 and the erase gate. 118. On the other hand, the non-volatile memory system of the present invention acts as a control paste in the dense doped region of the substrate, and forms a "gate" on the floating ride, thereby not increasing the wafer area, resulting in process cost. Increase, and affect the component accumulation. Then, please refer to FIG. 4 again, and erase it with the 睑 睑 太 太 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A The control gate also has a voltage V!, a voltage applied to the drain 122 is applied to a voltage v. For a dry battery, 2 pairs of sources are applied to the substrate, a voltage V4 is applied, and a voltage V4 is applied, and the erased voltage == ^Insert 111 pulls out the Gong O V, delays the erase. Among them, the voltage Vi, the voltage V2: too k private V5 is 0 volts 'and the electricity V4 is 12 volts. For the ancient Shili ΐ 5 non-volatile memory The body erase operation is performed by erasing the gate I and applying a voltage to the gate. The upper layer is the second; the second: the material (four) body is programmed to operate, for example, the "closed 106 applies a electricity house." V], applying a voltage to the bungee 122
1294662 16534twf.doc/006 壓V2，對源極120施加一電壓v3，對抹除閘極118施加 一電壓V4，以及對基底1〇〇施加一電壓V5，以使電子藉 由熱載子效應(Hot carrier)，從汲極122處撞擊躍至浮置閘 極1U進行儲存電子。其中，電壓Vi為12伏特，電壓V2 為8伏特，電壓％、電壓Vs為〇伏特，而電壓％浮置。 ^此外，對非揮發性記憶體進行讀取操作的方法例如 是，對控制閘極106施加一電壓Vi，對汲極122施加一電 壓V2J對源極120施加一電壓γ3，對抹除閘極118施加 一電壓V4，以及對基底1〇〇施加一電壓V5。其中，電壓 Vi為2.5伏特，電壓％為2·5伏特，電壓％、電壓％為 〇伏特，而電壓V4浮置。 曰值得注意的是，本發明之非揮發性記憶體的抹除操作 =將電子拉出至抹除閘極以進行抹除，而不會經過間氧化 層。因此，不會有習知之單層多晶石夕(Single poly)#揮發性 =體_氧化層損傷(Damage)的問題’而影響記憶體元 件的可重複抹寫讀(Cyding Numbe狀降低元件的可靠 ^而且，本發明之非揮發性記憶體的抹除操作所需 間較短，操作速度較快。 ㈣1寺別ί’本發明之非揮發性記憶體的浮置閘極的頂部 邊、、彖壬尖角狀，因此於進行抹除操作時，電子可經 】極的頂部邊緣拉出至抹除雜，如此可更佳提高抹除速 综上所述，本發明至少具有下列之優點： •本毛明之非揮發性記憶體的抹除操作所需的時間較 14 1294662 16534twf.doc/006 迷戾較快 2. 化發:之非揮發性記憶體的抹除操作不會造成閘氧 的。大此可増加兀件重複抹寫次數，以及提高元件 積，性記憶體的結構不會增加晶片面 烕衣私成本增加，以及影響元件積隼产。 雜製製造方法;與-般半導 時間。 進仃頟外之衣程，可節省製程成本與 限定:發、佳實?例揭露如上’然其並非用以 【圖;:ί二申請專利範圍所界定者為準。 意圖圖1為w知—種單層多砂非揮發性記憶體之剖面示 意圖圖2為習知—種分離式難非揮發性記憶體之剖面示 的剖示之非揮發性記憶體 【主要元件符號說明】 10 : N型金氧半導體結構 1294662 16534twf.doc/006 11 :場氧化層 12 : P型金氧半導體結構 14 : P型基底 16、24、42、111 :浮置閘極 18 : N+源極摻雜區 20 : N+汲極摻雜區 22 : N型離子井區 26 : P+源極摻雜區 28 : P+汲極摻雜區 30 : N型通道阻擋區 32 :浮置閘極導線 34、36、108 :閘氧化層 40、100 :基底 44、106 :控制閘極 46、120 :源極區 48、122 · >及極區 102 :元件隔離結構 104a、104b :主動區 110 :導體層 112 :圖案化之罩幕層 114、116 :介電層 118 :抹除閘極 124 :箭頭1294662 16534twf.doc/006 Voltage V2, a voltage v3 is applied to the source 120, a voltage V4 is applied to the erase gate 118, and a voltage V5 is applied to the substrate 1 to cause electrons to pass the hot carrier effect ( Hot carrier), from the impact of the bungee 122 to the floating gate 1U for storing electrons. Wherein, the voltage Vi is 12 volts, the voltage V2 is 8 volts, the voltage %, the voltage Vs is 〇V, and the voltage % is floating. In addition, a method of performing a read operation on the non-volatile memory is, for example, applying a voltage Vi to the control gate 106, applying a voltage V2J to the drain 122, and applying a voltage γ3 to the source 120 to erase the gate. 118 applies a voltage V4 and applies a voltage V5 to the substrate 1A. Among them, the voltage Vi is 2.5 volts, the voltage % is 2.5 volts, the voltage %, the voltage % is 〇V, and the voltage V4 is floating. It is worth noting that the erasing operation of the non-volatile memory of the present invention = pulling the electrons out to the erase gate for erasing without passing through the inter-oxide layer. Therefore, there is no known problem of single polycrystalline polystyrene # volatile = bulk_damage damage (Damage problem) and affecting the rewritable reading of memory elements (Cyding Numbe-like reducing element Reliable ^ Moreover, the non-volatile memory of the present invention requires a shorter erase operation and a faster operation speed. (4) 1 Temple ί' The top edge of the floating gate of the non-volatile memory of the present invention, The invention has at least the following advantages: when the wiping operation is performed, the electrons can be pulled out to the eraser through the top edge of the pole, so that the eraser speed can be improved. • The time required for the erase operation of this non-volatile memory is faster than that of 14 1294662 16534twf.doc/006. 2. The non-volatile memory erase operation does not cause sluice. In this case, the number of times of repeated smearing can be increased, and the component product can be increased. The structure of the memory does not increase the cost of the wafer surface, and affects the component accumulation. Miscellaneous manufacturing methods; Time. In addition to the clothing process, you can save the process This and the limitations: the hair, the good example of the disclosure as above, but it is not used [Figure;: ί two application of the scope of the patent as defined. Intent Figure 1 is w know - a single layer of multi-sand non-volatile memory 2 is a non-volatile memory of a cross-sectional view of a conventional non-volatile memory. [Main component symbol description] 10: N-type MOS structure 1294662 16534twf.doc/006 11: Field oxide layer 12: P-type MOS structure 14: P-type substrate 16, 24, 42, 111: Floating gate 18: N+ source doped region 20: N+ drain doped region 22: N-type Ion well region 26: P+ source doped region 28: P+ drain doped region 30: N-type channel barrier region 32: floating gate conductors 34, 36, 108: gate oxide layer 40, 100: substrate 44, 106 : control gate 46, 120: source region 48, 122 · > and pole region 102: element isolation structure 104a, 104b: active region 110: conductor layer 112: patterned mask layer 114, 116: dielectric layer 118: Wipe the gate 124: arrow
Vi、V2、V3、V4、V5 :電壓 16Vi, V2, V3, V4, V5: voltage 16