CN108206186A - 具有擦除元件的单层多晶硅非易失性存储单元结构 - Google Patents

具有擦除元件的单层多晶硅非易失性存储单元结构 Download PDF

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CN108206186A
CN108206186A CN201710135824.3A CN201710135824A CN108206186A CN 108206186 A CN108206186 A CN 108206186A CN 201710135824 A CN201710135824 A CN 201710135824A CN 108206186 A CN108206186 A CN 108206186A
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floating grid
oxide
layer
volatile memory
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CN108206186B (zh
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孙文堂
陈纬仁
陈英哲
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eMemory Technology Inc
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Abstract

本发明公开了一种单层多晶硅非易失性存储单元结构，包含一硅覆绝缘衬底，包含一硅基底、一埋入氧化层及一半导体层；一第一氧化物定义区域及一第二氧化物定义区域，位于所述半导体层；一绝缘区域，位于所述半导体层，隔离所述第一氧化物定义区域与所述第二氧化物定义区域；一P型金氧半选择晶体管，设于所述第一氧化物定义区域；一P型金氧半浮置栅极晶体管，设于所述第一氧化物定义区域，并串接所述P型金氧半选择晶体管，所述P型金氧半浮置栅极晶体管包含一浮置栅极，位于所述第一氧化物定义区域上；以及一浮置栅极延伸，由所述浮置栅极连续延伸至所述第二氧化物定义区域，并与所述第二氧化物定义区域电容耦合。

Description

具有擦除元件的单层多晶硅非易失性存储单元结构
技术领域
本发明涉及非易失性存储器(nonvolatile memory)技术领域，特别是涉及一种具有擦除元件(erase device)且设于硅覆绝缘(SOI)衬底上的单层多晶硅非易失性存储单元结构。
背景技术
单层多晶硅非易失性存储器乃周知技艺。图1例示一单层多晶硅非易失性存储单元的布局示意图。如图1所示，单层多晶硅非易失性存储单元10包含两个串接在一起的P型金氧半晶体管12及14。P型金氧半晶体管12包含一选择栅极22、一P+源极掺杂区32，及一P+漏极/源极掺杂区34。P型金氧半晶体管14包含一浮置栅极24、P+漏极/源极掺杂区34，及一P+漏极掺杂区36。串接在一起的P型金氧半晶体管12及14共享P+漏极/源极掺杂区34。上述单层多晶硅非易失性存储单元10的优点是可以完全与CMOS逻辑工艺兼容。
操作时，P型金氧半晶体管12的选择栅极22耦合至一选择栅极电压VSG，P+源极掺杂区32经由一源极线接触件耦合至一源极线电压VSL，P+漏极/源极掺杂区34及P型金氧半晶体管14的浮置栅极24为电性上浮置，而P型金氧半晶体管14的P+漏极掺杂区36则是经由一位线接触件耦合至位线电压VBL。在写入模式下，电子被注入并贮存在浮置栅极24中。上述存储器结构可以在低电压条件下操作。
由于单层多晶硅非易失性存储器能与CMOS逻辑工艺兼容，因此被广泛应用在许多领域，例如嵌入式存储器、混合信号电路或微控制器(如系统单芯片)等等的嵌入式非易失性存储器。
目前的趋势是将非易失性存储器越做越小。随着非易失性存储器越做越小，可期待存储器的单位元成本(cost per bit)也会降低。然而，过去的非易失性存储单元的微缩能力受限于离子注入输出/输入离子阱(I/O ion well)的规则，其中植入基底存储矩阵区中的输出/输入离子阱的接面深度深于浅沟绝缘结构(STI)的深度。
发明内容
本发明的主要目的在提供一改良的单层多晶硅非易失性存储单元结构，特征是具有一擦除元件且形成在一硅覆绝缘衬底上，以解决背景技术的不足与缺点。
本发明的主要目的在提供一改良的单层多晶硅可多次写入(MTP)非易失性存储单元，其具有更小的存储单元尺寸。
根据本发明一实施例，提供一种单层多晶硅非易失性存储单元结构，包含一硅覆绝缘(SOI)衬底，包含一硅基底、一埋入氧化层及一半导体层；一第一氧化物定义区域及一第二氧化物定义区域，位于所述半导体层；一绝缘区域，位于所述半导体层，所述绝缘区域隔离所述第一氧化物定义区域与所述第二氧化物定义区域；一P型金氧半选择晶体管，设于所述第一氧化物定义区域；一P型金氧半浮置栅极晶体管，设于所述第一氧化物定义区域，并串接所述P型金氧半选择晶体管，其中所述P型金氧半浮置栅极晶体管包含一浮置栅极，位于所述第一氧化物定义区域上；以及一浮置栅极延伸，由所述浮置栅极连续地延伸至所述第二氧化物定义区域，并与所述第二氧化物定义区域电容耦合。
其中所述P型金氧半选择晶体管包含一选择栅极、一选择栅极氧化层，介于所述选择栅极与所述半导体层之间、一P+源极掺杂区，及一P+漏极/源极掺杂区，其中所述P+源极掺杂区耦合至一源极线。
其中所述P型金氧半浮置栅极晶体管包含一浮置栅极、一浮置栅极氧化层，介于所述浮置栅极与所述半导体层之间、所述P+漏极/源极掺杂区，及一P+漏极掺杂区，其中所述P型金氧半选择晶体管与所述P型金氧半浮置栅极晶体管共享所述P+漏极/源极掺杂区。
根据本发明一实施例，所述单层多晶硅非易失性存储单元结构另包含一离子阱，例如N型阱或P型阱，位于所述半导体层，其中所述离子阱完全重叠所述第二氧化物定义区域，以及一重掺杂区域，例如N+掺杂区或P+掺杂区，位于所述第二氧化物定义区域内的所述离子阱中。所述第二氧化物定义区域、所述重掺杂区域、所述浮置栅极氧化层，及与所述重掺杂区域电容耦合的所述浮置栅极延伸，共同构成一擦除元件。
根据本发明一实施例，所述单层多晶硅非易失性存储单元结构另包含一电荷收集区域，与所述第一氧化物定义区域接壤，其中电荷收集区域在所述单层多晶硅非易失性存储单元操作时收集累积在所述半导体层中的多余电子及电洞。其中所述电荷收集区域包含一第三氧化物定义区域、一N+掺杂区位于所述第三氧化物定义区域内，及一桥接区域，连接所述N+掺杂区与所述浮置栅极正下方的所述半导体层。
根据本发明另一实施例，所述单层多晶硅非易失性存储单元结构另包含一N+掺杂区，其与所述P+源极掺杂区接壤，所述N+掺杂区与所述P+源极掺杂区位于所述选择栅极同一侧，如此构成一毗接接触区。
附图说明
图1例示一单层多晶硅非易失性存储单元的布局示意图。
图2是依据本发明一实施例所绘示的单层多晶硅非易失性存储器的部分布局示意图。
图3是沿着图2中的切线I-I’所示的存储单元结构剖面示意图。
图4是沿着图2中的切线II-II’所示的剖面示意图。
图5至图7是依据本发明其他实施例所绘示的具擦除元件的单层多晶硅非易失性存储器的不同实施态样。
图8例示适用于第2图至第7图中的各存储单元的写入(PGM)、读取(READ)及擦除(ERS)的操作条件。
图9是依据本发明另一实施例所绘示的单层多晶硅非易失性存储器的部分布局示意图。
图10是沿着图9中的切线III-III’所示的剖面示意图。
图11是沿着图9中的切线IV-IV’所示的剖面示意图。
图12是依据本发明又另一实施例所绘示的具擦除元件的单层多晶硅非易失性存储器的实施态样。
图13例示适用于图9及图12中的各存储单元的写入(PGM)、读取(READ)及擦除(ERS)的操作条件。
其中，附图标记说明如下：
1、2、3、4、5、6 单层多晶硅非易失性存储器
10 单层多晶硅非易失性存储单元
12 P型金氧半晶体管
14 P型金氧半晶体管
22 选择栅极
24 浮置栅极
32 P+源极掺杂区
34 P+漏极/源极掺杂区
36 P+漏极掺杂区
50 电荷收集区域
60 毗接接触区
102 P型金氧半选择晶体管
104 P型金氧半浮置栅极晶体管
110 选择栅极
112 选择栅极氧化层
120 浮置栅极
120a、120b 延伸部(浮置栅极延伸)
122 浮置栅极氧化层
132 P+源极掺杂区
134 P+漏极/源极掺杂区
136 P+漏极掺杂区
138 重掺杂区域
162 N+掺杂区
200 硅覆绝缘(SOI)衬底
210 硅衬底
220 埋入氧化层
230 半导体层
250、450 擦除元件
300 浅沟绝缘(STI)区域
310 N型阱
320 离子阱
500 N+掺杂区
510 字线接触点
520 桥接区域
VSG 选择栅极电压
VSL 源极线电压
VBL 位线电压
VNW N型阱电压
C1～C4 存储单元单元
OD1、OD2、OD3、OD4 氧化物定义区域
WL1、WL2 字线
SL 源极线
BL 位线
EL 擦除线
具体实施方式
借由接下来的叙述及所提供的众多特定细节，可充分了解本发明。然而对于此领域中的技术人员，在没有这些特定细节下依然可实行本发明。并且，一些此领域中公知的系统配置和工艺步骤并未在此详述，因为这些应是此领域中的技术人员所熟知的。
同样地，实施例的附图为示意图，为了清楚呈现而放大一些尺寸，并未照实际比例绘制。在此公开和描述的多个实施例中若具有共通或类似的某些特征时，为了方便图示及描述，类似的特征通常会以相同的标号表示。
本发明涉及一种单层多晶硅非易失性存储器结构，具有一擦除元件，可以作为可多次写入(MTP)存储器。本发明单层多晶硅非易失性存储器结构是制造在一硅覆绝缘(silicon-on-insulator或semiconductor-on-insulator，简称SOI)衬底上。SOI衬底包含一硅基底、一埋入氧化层及一硅(或半导体)有源层，设于埋入氧化层上。本发明单层多晶硅非易失性存储器结构是制造在所述硅(或半导体)有源层中。SOI衬底可以是商业尚可获得的SOI产品，可以利用公知的SIMOX方法制造而成，但不限于此。本发明单层多晶硅非易失性存储器结构可以是一全空乏(fully depleted)SOI元件或部分空乏(partially depleted)SOI元件。
请参阅图2至图4。图2是依据本发明一实施例所绘示的单层多晶硅非易失性存储器的部分布局示意图。图3为沿着图2中的切线I-I’所示的存储单元结构剖面示意图。图4为沿着图2中的切线II-II’所示的剖面示意图。
如图2所示，本发明单层多晶硅非易失性存储器1包含多个存储单元，包括但不限于，例如，四个存储单元单元C1～C4。应理解的是，图2中所示的存储单元布局仅为例示说明。在图2中，举例来说，仅绘示三个氧化物定义(oxide define，OD)区域:OD1、OD2、OD3。根据本发明实施例，存储单元C1及C2是制造于氧化物定义区域OD1上，存储单元C3及C4是制造于氧化物定义区域OD2上。
根据本发明实施例，氧化物定义区域OD1、OD2可以是沿着参考y轴延伸的条状区域。氧化物定义区域OD1、OD2、OD3借由浅沟绝缘(shallow trench isolation，STI)区域300彼此隔离绝缘。在图2中，仅绘示两条沿着参考x轴延伸且与氧化物定义区域OD1、OD2交叉的字线WL1及WL2。在氧化物定义区域OD3上可以形成一擦除元件250。根据本发明实施例，擦除元件250可以被图中四个存储单元C1～C4共享。
根据本发明实施例，氧化物定义区域OD3是介于氧化物定义区域OD1与氧化物定义区域OD2之间。氧化物定义区域OD3与字线WL1及WL2有一段距离，所以从图2的布局示意图中可看出，氧化物定义区域OD3不会与字线WL1及WL2重叠。
根据本发明实施例，存储单元C1与存储单元C2共享同一P+漏极/源极掺杂区及相同的位线接触点。根据本发明实施例，存储单元C3与存储单元C4共享同一P+漏极/源极掺杂区及相同的位线接触点。
如图2至图4所示，四个存储单元C1～C4的各存储单元(以存储单元C1为例)均包含一P型金氧半选择晶体管102及一串接P型金氧半选择晶体管102的P型金氧半浮置栅极晶体管104。P型金氧半选择晶体管102及P型金氧半浮置栅极晶体管104一起形成在氧化物定义区域OD1上，其中氧化物定义区域OD1是定义于一SOI衬底200的一半导体层230中。存储单元单元C2的存储单元结构是镜面对称于存储单元单元C1。存储单元单元C3及C4的存储单元结构则分别镜面对称于存储单元单元C1及C2。
半导体层230可以是一单晶硅层，但不限于此。SOI衬底200可以进一步包含一埋入氧化层220及一硅衬底210。半导体层230是借由埋入氧化层220与硅衬底210电性隔离。STI区域300与下方的埋入氧化层220接壤。硅衬底210可以是一P型硅衬底，但不限于此。在半导体层230中，可以利用离子注入工艺形成一与氧化物定义区域OD1完全重叠的N型阱310。在某些实施例中，N型阱310可以被省略，如此一来通道可以形成在本征硅(intrinsicsilicon)中。
P型金氧半选择晶体管102包含一选择栅极110、一选择栅极氧化层112，介于选择栅极110与半导体层230之间、一P+源极掺杂区132，及一P+漏极/源极掺杂区134。P型金氧半浮置栅极晶体管104包含一浮置栅极120、一浮置栅极氧化层122，介于浮置栅极120与半导体层230之间、P+漏极/源极掺杂区134，及一P+漏极掺杂区136。P型金氧半选择晶体管102与P型金氧半浮置栅极晶体管104共享P+漏极/源极掺杂区134。为简化说明，图中选择栅极110与浮置栅极120侧壁上的侧壁子并未绘示出来。
从图2及图4可看出，浮置栅极120包括一延伸部(或称为浮置栅极延伸)120a，其沿着参考x轴方向连续地延伸出去，并与氧化物定义区域OD3重叠。延伸部120a可以具有一宽度，其小于浮置栅极120的宽度。根据本发明实施例，延伸部120a与氧化物定义区域OD3的重叠面积小于浮置栅极120与氧化物定义区域OD1的重叠面积。
在氧化物定义区域OD3中，形成有一重掺杂区域138。重掺杂区域138可以是一N+掺杂区或一P+掺杂区。一离子阱320，例如一N型阱或一P型阱，可以形成在半导体层230中，并与氧化物定义区域OD3完全重叠。或者，重掺杂区域138可以直接形成在本征硅中，此时，无需在氧化物定义区域OD3中形成离子阱。应理解的是，图中的浮置栅极的形状仅为例说明。
根据本发明实施例，氧化物定义区域OD3、重掺杂区域138、浮置栅极氧化层122及电容耦合于重掺杂区域138与氧化物定义区域OD3的延伸部120a共同构成擦除元件250。
操作时，P型金氧半选择晶体管102的选择栅极110经由一字线接触点510耦合至一选择栅极电压VSG，P型金氧半选择晶体管102的P+源极掺杂区132经由一源极线(SL)接触点耦合至一源极线电压VSL，P+漏极/源极掺杂区134及浮置栅极120为电性浮置，而P型金氧半浮置栅极晶体管104的P+漏极掺杂区136是经由一位线(BL)接触点耦合至一位线电压VBL。重掺杂区域138则是经由一擦除线(EL)接触点耦合至一擦除线电压VEL。
在写入模式下，电子通过信道热电子(channel hot electron，CHE)注入机制被选择性的注入浮置栅极120。在擦除模式下(区段或全芯片擦除)，电子则是通过福勒诺汉穿隧(Fowler-Nordheim(FN)tunneling)机制从浮置栅极120擦除。
图5至图7是依据本发明其他实施例所绘示的具擦除元件的单层多晶硅非易失性存储器的不同实施态样。
如图5所示，图5中的单层多晶硅非易失性存储器2与图2中的单层多晶硅非易失性存储器1差异在于图5中的单层多晶硅非易失性存储器2另包含一与氧化物定义区域OD1接壤的电荷收集区域50。电荷收集区域50能够在单层多晶硅非易失性存储器操作时收集累积在半导体层230中的多余电子及电洞。
根据本发明实施例，电荷收集区域50包含一氧化物定义区域OD4、一N+掺杂区500位于氧化物定义区域OD4内，及一桥接区域520连接N+掺杂区500与浮置栅极120正下方的半导体层230。N型阱310可以与桥接区域520及氧化物定义区域OD4重叠。在N+掺杂区500内可提供一N型阱接触点，使电荷收集区域50可以耦合至一N型阱电压VNW。在图5中，存储单元C1及存储单元C2共享一电荷收集区域，而存储单元C3及存储单元C4共享一电荷收集区域。
如图6所示，图6中的单层多晶硅非易失性存储器3与图2中的单层多晶硅非易失性存储器1差异在于图6中的单层多晶硅非易失性存储器3另包含一N+掺杂区162，其与P+源极掺杂区132接壤，N+掺杂区162与P+源极掺杂区132位于选择栅极110同一侧，如此构成一毗接接触区60。N+掺杂区162与P+源极掺杂区132皆耦合至一源极线电压VSL。
如图7所示，图7中的单层多晶硅非易失性存储器4与图2中的单层多晶硅非易失性存储器1差异在于图7中的单层多晶硅非易失性存储器4包含一与氧化物定义区域OD1接壤的电荷收集区域50。电荷收集区域50能够在存储器操作时收集累积在半导体层230中的多余电子及电洞。电荷收集区域50的细节同第5图所示。图7中的单层多晶硅非易失性存储器4另包含一N+掺杂区162，其与P+源极掺杂区132接壤，N+掺杂区162与P+源极掺杂区132位于选择栅极110同一侧，如此构成一毗接接触区60。N+掺杂区162与P+源极掺杂区132皆耦合至一源极线电压VSL。
图8例示适用于图2至图7中的各存储单元的写入(PGM)、读取(READ)及擦除(ERS)的操作条件。如图8所示，在写入(PGM)操作时，源极线(SL)耦合至一电压VPP，例如，电压VPP可以介于5～9V。位线(BL)接地(VBL＝0V)。另提供选择栅极(SG)110一介于0～1/2VPP的电压，提供擦除线(EL)一介于0～VPP的电压。对于具有电荷收集区域50的存储单元，如图5及图7所示，N+掺杂区500偶合至一VPP电压。图8中同时例示对存储单元进行写入-抑制(PGM-inhibit)操作或写入-未选择(PGM-unselect)操作的电压条件。
在擦除操作时，源极线(SL)接地(VSL＝0V)，位线(BL)接地(VBL＝0V)，选择栅极(SG)110接地(VSG＝0V)。另提供擦除线(EL)一VEE的电压。举例来说，VEE可以介于8～18V。对于具有电荷收集区域50的存储单元，如图5及图7所示，N+掺杂区500接地(VNW＝0V)。
另一擦除操作方式是，源极线(SL)耦合至一VBB电压。举例来说，VBB可以介于-4～-8V。位线(BL)耦合至一VBB电压。选择栅极(SG)110耦合至一VBB电压。另提供擦除线(EL)一VEE的电压。举例来说，VEE可以介于8～18V。对于具有电荷收集区域50的存储单元，如图5及图7所示，N+掺杂区500耦合至一VBB电压。
在读取操作时，源极线(SL)耦合至一VREAD电压。举例来说，VREAD可以介于2～2.8V。位线(BL)耦合至0.4V电压(VBL＝0.4V)。选择栅极(SG)110接地(VSG＝0V)。擦除线(EL)接地(VEL＝0V)。对于具有电荷收集区域50的存储单元，如图5及图7所示，N+掺杂区500耦合至VREAD电压。图8中同时例示对存储单元进行读取-未选择(READ-unselect)操作的电压条件。
请参阅图9至图11。图9是依据本发明另一实施例所绘示的单层多晶硅非易失性存储器的部分布局示意图。图10是沿着图9中的切线III-III’所示的剖面示意图。图11是沿着图9中的切线IV-IV’所示的剖面示意图。
如图9所示，本发明单层多晶硅非易失性存储器5包含多个存储单元，包括但不限于，例如，四个存储单元C1～C4。应理解的是，图9中所示的存储单元布局仅为例示说明。在图9中，举例来说，仅绘示三个氧化物定义区域:OD1、OD2、OD3。根据本发明实施例，存储单元C1及C2是制造于氧化物定义区域OD1上，存储单元C3及C4是制造于氧化物定义区域OD2上。
根据本发明实施例，氧化物定义区域OD1、OD2可以是沿着参考y轴延伸的条状区域。氧化物定义区域OD1、OD2、OD3借由浅沟绝缘(STI)区域300彼此隔离绝缘。在图9中，仅绘示两条沿着参考x轴延伸且与氧化物定义区域OD1、OD2交叉的字线WL1及WL2。在氧化物定义区域OD3上可以形成一擦除元件450。根据本发明实施例，擦除元件450可以被图中四个存储单元C1～C4共享。
根据本发明实施例，氧化物定义区域OD3介于氧化物定义区域OD1与氧化物定义区域OD2之间。氧化物定义区域OD3与字线WL1及WL2有一段距离，所以从图9的布局示意图中可看出，氧化物定义区域OD3不会与字线WL1及WL2重叠。
根据本发明实施例，存储单元C1与存储单元C2共享同一P+漏极/源极掺杂区及相同的位线接触点。根据本发明实施例，存储单元C3与存储单元C4共享同一P+漏极/源极掺杂区及相同的位线接触点。
如图9至图11所示，四个存储单元C1～C4的各存储单元(以存储单元C1为例)均包含一P型金氧半选择晶体管102及一串接P型金氧半选择晶体管102的P型金氧半浮置栅极晶体管104。P型金氧半选择晶体管102及P型金氧半浮置栅极晶体管104一起形成在氧化物定义区域OD1上，其中氧化物定义区域OD1是定义于一SOI衬底200的一半导体层230中。存储单元单元C2的存储单元结构镜面对称于存储单元单元C1。存储单元单元C3及C4的存储单元结构则分别镜面对称于存储单元单元C1及C2。
半导体层230可以是一单晶硅层，但不限于此。SOI衬底200可以进一步包含一埋入氧化层220及一硅衬底210。半导体层230是借由埋入氧化层220与硅衬底210电性隔离。STI区域300与下方的埋入氧化层220接壤。硅衬底210可以是一P型硅衬底，但不限于此。在半导体层230中，可以利用离子注入工艺形成一与氧化物定义区域OD1完全重叠的N型阱310。在某些实施例中，N型阱310可以被省略，如此一来通道可以形成在本征硅中。
P型金氧半选择晶体管102包含一选择栅极110、一选择栅极氧化层112，介于选择栅极110与半导体层230之间、一P+源极掺杂区132，及一P+漏极/源极掺杂区134。P型金氧半浮置栅极晶体管104包含一浮置栅极120、一浮置栅极氧化层122，介于浮置栅极120与半导体层230之间、P+漏极/源极掺杂区134，及一P+漏极掺杂区136。P型金氧半选择晶体管102与P型金氧半浮置栅极晶体管104共享P+漏极/源极掺杂区134。为简化说明，图中选择栅极110与浮置栅极120侧壁上的侧壁子并未绘示出来。
从图9及图11可看出，浮置栅极120包括一延伸部120b，其沿着参考x轴方向延伸出去，与氧化物定义区域OD3重叠。延伸部120b可以具有一宽度，其大于浮置栅极120的宽度。根据本发明实施例，延伸部120b与氧化物定义区域OD3的重叠面积大于浮置栅极120与氧化物定义区域OD1的重叠面积。
在氧化物定义区域OD3中，形成有一重掺杂区域138。重掺杂区域138可以是一N+掺杂区或一P+掺杂区。一离子阱320，例如一N型阱或一P型阱，可以形成在氧化物定义区域OD3。根据本发明实施例，重掺杂区域138为一N+掺杂区，离子阱320为一N型阱。根据本发明另一实施例，重掺杂区域138为一P+掺杂区，离子阱320为一P型阱。应理解的是，图中的浮置栅极的形状仅供例示参考。
根据本发明实施例，氧化物定义区域OD3、重掺杂区域138、浮置栅极氧化层122及电容耦合于重掺杂区域138与氧化物定义区域OD3的延伸部120b共同构成擦除元件450。氧化物定义区域OD3及重掺杂区域138可作为一控制栅极。
操作时，P型金氧半选择晶体管102的选择栅极110耦合至一选择栅极电压VSG，P型金氧半选择晶体管102的P+源极掺杂区132经由一源极线(SL)接触点耦合至一源极线电压VSL，P+漏极/源极掺杂区134及浮置栅极120为电性浮置，而P型金氧半浮置栅极晶体管104的P+漏极掺杂区136是经由一位线(BL)接触点耦合至一位线电压VBL。重掺杂区域138则是耦合至一控制栅极电压VCG。
在写入模式下，电子通过信道热电子(CHE)注入机制被选择性的注入浮置栅极120。在擦除模式下(区段或全芯片擦除)，电子则是通过福勒诺汉穿隧(FN tunneling)机制从浮置栅极120擦除。
图12是依据本发明又另一实施例所绘示的具擦除元件的单层多晶硅非易失性存储器的实施态样。
如图12所示，图12中的单层多晶硅非易失性存储器6与图9中的单层多晶硅非易失性存储器5差异在于图12中的单层多晶硅非易失性存储器6另包含一与氧化物定义区域OD1接壤的电荷收集区域50。电荷收集区域50能够在单层多晶硅非易失性存储器操作时收集累积在半导体层230中的多余电子及电洞。
根据本发明实施例，电荷收集区域50包含一氧化物定义区域OD4、一N+掺杂区500位于氧化物定义区域OD4内，及一桥接区域520连接N+掺杂区500与浮置栅极120正下方的半导体层230。N型阱310可以与桥接区域520及氧化物定义区域OD4重叠。在N+掺杂区500内可提供一N型阱接触点，使电荷收集区域50可以耦合至一N型阱电压VNW。在图12中，存储单元C1及存储单元C2共享一电荷收集区域，而存储单元C3及存储单元C4共享一电荷收集区域。
图13例示适用于图9及图12中的各存储单元的写入(PGM)、读取(READ)及擦除(ERS)的操作条件。如图13所示，在写入(PGM)操作时，源极线(SL)耦合至一电压VPP，例如，电压VPP可以介于5～9V。位线(BL)接地(VBL＝0V)。另提供选择栅极(SG)110一介于0～1/2VPP的电压，提供控制栅极(CG)一介于0～1/2VPP的电压。对于具有电荷收集区域50的存储单元，如第12图所示，N+掺杂区500偶合至一VPP电压。图13中同时例示对存储单元进行写入-抑制(PGM-inhibit)操作或写入-未选择(PGM-unselect)操作的电压条件。
在擦除操作时，源极线(SL)耦合至一VEE电压。举例来说，VEE可以介于8～18V。位线(BL)耦合至VEE电压。选择栅极(SG)110耦合至VEE电压，或者VEE-ΔV电压(ΔV>Vt)。控制栅极(CG)接地(VCG＝0V)。对于具有电荷收集区域50的存储单元，如图12所示，N+掺杂区500接地(VNW＝0V)。
在读取操作时，源极线(SL)耦合至一VREAD电压。举例来说，VREAD可以介于2～2.8V。位线(BL)耦合至0.4V电压(VBL＝0.4V)。选择栅极(SG)110接地(VSG＝0V)。控制栅极(CG)接地(VCG＝0V)。对于具有电荷收集区域50的存储单元，如图12所示，N+掺杂区500耦合至VREAD电压。图13中同时例示对存储单元进行读取-未选择(READ-unselect)操作的电压条件。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (17)

1.一种单层多晶硅非易失性存储单元结构，其特征在于，包含：
一硅覆绝缘衬底，包含一硅基底、一埋入氧化层及一半导体层；
一第一氧化物定义区域及一第二氧化物定义区域，位于所述半导体层；
一绝缘区域，位于所述半导体层，所述绝缘区域隔离所述第一氧化物定义区域与所述第二氧化物定义区域；
一P型金氧半选择晶体管，设于所述第一氧化物定义区域；
一P型金氧半浮置栅极晶体管，设于所述第一氧化物定义区域，并串接所述P型金氧半选择晶体管，其中所述P型金氧半浮置栅极晶体管包含一浮置栅极，位于所述第一氧化物定义区域上；以及
一浮置栅极延伸，由所述浮置栅极连续地延伸至所述第二氧化物定义区域，并与所述第二氧化物定义区域电容耦合。
2.根据权利要求1所述的单层多晶硅非易失性存储单元结构，其特征在于，所述P型金氧半选择晶体管包含一选择栅极、一选择栅极氧化层，介于所述选择栅极与所述半导体层之间、一P+源极掺杂区，及一P+漏极/源极掺杂区，其中所述P+源极掺杂区耦合至一源极线。
3.根据权利要求2所述的单层多晶硅非易失性存储单元结构，其特征在于，所述P型金氧半浮置栅极晶体管包含一浮置栅极、一浮置栅极氧化层，介于所述浮置栅极与所述半导体层之间、所述P+漏极/源极掺杂区，及一P+漏极掺杂区，其中所述P型金氧半选择晶体管与所述P型金氧半浮置栅极晶体管共享所述P+漏极/源极掺杂区。
4.根据权利要求1所述的单层多晶硅非易失性存储单元结构，其特征在于，另包含：
一N型阱，位于所述半导体层，其中所述N型阱完全重叠所述第一氧化物定义区域。
5.根据权利要求3所述的单层多晶硅非易失性存储单元结构，其特征在于，另包含：
一离子阱，位于所述半导体层，其中所述离子阱完全重叠所述第二氧化物定义区域；以及
一重掺杂区域，位于所述第二氧化物定义区域内的所述离子阱中。
6.根据权利要求5所述的单层多晶硅非易失性存储单元结构，其特征在于，所述离子阱包含一N型阱或一P型阱。
7.根据权利要求5所述的单层多晶硅非易失性存储单元结构，其特征在于，所述重掺杂区域是一N+掺杂区。
8.根据权利要求5所述的单层多晶硅非易失性存储单元结构，其特征在于，所述重掺杂区域是一P+掺杂区。
9.根据权利要求5所述的单层多晶硅非易失性存储单元结构，其特征在于，所述浮置栅极跨越所述第一氧化物定义区域与所述第二氧化物定义区域之间的所述绝缘区域，并且与所述第二氧化物定义区域部分重叠以电容耦合所述重掺杂区域。
10.根据权利要求5所述的单层多晶硅非易失性存储单元结构，其特征在于，所述第二氧化物定义区域、所述重掺杂区域、所述浮置栅极氧化层，及与所述重掺杂区域电容耦合的所述浮置栅极延伸，共同构成一擦除元件。
11.根据权利要求5所述的单层多晶硅非易失性存储单元结构，其特征在于，操作时，所述选择栅极耦合至一选择栅极电压，所述P型金氧半选择晶体管的P+源极掺杂区耦合至一源极线电压，所述P+漏极/源极掺杂区及所述浮置栅极为电性浮置，而所述P型金氧半浮置栅极晶体管的所述P+漏极掺杂区耦合至一位线电压VBL，所述重掺杂区域耦合至一擦除线电压。
12.根据权利要求1所述的单层多晶硅非易失性存储单元结构，其特征在于，所述浮置栅极延伸与所述第二氧化物定义区域的重叠面积小于所述浮置栅极与所述第一氧化物定义区域的重叠面积。
13.根据权利要求1所述的单层多晶硅非易失性存储单元结构，其特征在于，所述浮置栅极延伸与所述第二氧化物定义区域的重叠面积大于所述浮置栅极与所述第一氧化物定义区域的重叠面积。
14.根据权利要求4所述的单层多晶硅非易失性存储单元结构，其特征在于，另包含：
一电荷收集区域，与所述第一氧化物定义区域接壤，其中电荷收集区域在所述单层多晶硅非易失性存储单元操作时收集累积在所述半导体层中的多余电子及电洞。
15.根据权利要求14所述的单层多晶硅非易失性存储单元结构，其特征在于，所述电荷收集区域包含一第三氧化物定义区域、一N+掺杂区位于所述第三氧化物定义区域内，及一桥接区域，连接所述N+掺杂区与所述浮置栅极正下方的所述半导体层。
16.根据权利要求15所述的单层多晶硅非易失性存储单元结构，其特征在于，所述N型阱与所述桥接区域及所述第三氧化物定义区域重叠。
17.根据权利要求1所述的单层多晶硅非易失性存储单元结构，其特征在于，另包含：
一N+掺杂区，其与所述P+源极掺杂区接壤，所述N+掺杂区与所述P+源极掺杂区位于所述选择栅极同一侧，如此构成一毗接接触区。
CN201710135824.3A 2016-01-19 2017-03-08 具有擦除元件的单层多晶硅非易失性存储单元结构 Active CN108206186B (zh)

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