CN106981307B - 存储器装置、其外围电路及其单字节数据写入方法 - Google Patents

存储器装置、其外围电路及其单字节数据写入方法 Download PDF

Info

Publication number
CN106981307B
CN106981307B CN201710044103.1A CN201710044103A CN106981307B CN 106981307 B CN106981307 B CN 106981307B CN 201710044103 A CN201710044103 A CN 201710044103A CN 106981307 B CN106981307 B CN 106981307B
Authority
CN
China
Prior art keywords
data
array
page buffer
decoder
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710044103.1A
Other languages
English (en)
Other versions
CN106981307A (zh
Inventor
林义琅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
eMemory Technology Inc
Original Assignee
eMemory Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by eMemory Technology Inc filed Critical eMemory Technology Inc
Publication of CN106981307A publication Critical patent/CN106981307A/zh
Application granted granted Critical
Publication of CN106981307B publication Critical patent/CN106981307B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

存储器装置、其外围电路及其单字节数据写入方法。外围电路包括一Y解码器、一分页缓冲器及一写入电路。写入电路通过Y解码器耦接一存储器阵列及分页缓冲器，并且接收一字节的一编程数据。写入电路依据编程数据对应的一存储器地址通过Y解码器读取存储器阵列所存储的多字节的一阵列数据，以将所读取的阵列数据通过Y解码器写入至分页缓冲器。接着，编程数据通过写入电路及Y解码器写入至存储器阵列，并且阵列数据由分页缓冲器写入至存储器阵列。

Description

存储器装置、其外围电路及其单字节数据写入方法
技术领域
本发明涉及一种存储器装置，且特别涉及一种存储器装置、其外围电路及其单字节数据写入方法。
背景技术
在目前，随着科学与技术的快速发展，非易失性存储器已广泛用于电子装置中，并且非易失性存储器(例如，快闪存储器)用以存储电子装置的信息，且非易失性存储器对于电子装置的重要的日益增加。然而，受限于非易失性存储器的半导体结构，非易失性存储器的写入是以分页为单位，而不是单字节，因此会影响非易失性存储器的写入效能。
发明内容
本发明提供一种存储器装置、其外围电路及其单字节数据写入方法，可接收单字节的编程数据并且对应地对存储器阵列进行数据更新。
本发明的存储器装置的外围电路，包括一Y解码器、一分页缓冲器、一写入电路及一感测放大器。Y解码器耦接存储器装置的一存储器阵列。分页缓冲器耦接存储器阵列及Y解码器。写入电路通过Y解码器耦接存储器阵列及分页缓冲器，并且接收一字节的一编程数据。感测放大器耦接于Y解码器与写入电路之间，以通过Y解码器读取存储器阵列所存储的多字节的一阵列数据后提供阵列数据至写入电路。所读取的阵列数据是依据编程数据对应的一存储器地址，并且所读取的阵列数据通过Y解码器写入至分页缓冲器。接着，编程数据通过写入电路及Y解码器写入至存储器阵列，并且阵列数据由分页缓冲器写入至存储器阵列。
本发明的存储器装置，包括一存储器阵列及如上所述的外围电路。外围电路耦接存储器阵列，并且接收一字节的一编程数据，以将编程数据写入存储器阵列。
本发明的存储器装置的单字节数据写入方法，包括下列步骤。通过一写入电路接收一字节的一编程数据。通过一感测放大器及一Y解码器依据编程数据对应的一存储器地址读取一存储器阵列所存储的多字节的一阵列数据，并且通过写入电路及Y解码器将阵列数据写入至一分页缓冲器。通过写入电路及Y解码器将编程数据写入至存储器阵列。通过分页缓冲器将阵列数据写入至存储器阵列。
基于上述，本发明实施例的存储器装置、其外围电路及其单字节数据写入方法，其写入电路读取未选取的阵列数据并写入至分页缓冲器中，并且将选取的编程数据直接写入至存储器阵列中，而阵列数据通过分页缓冲器写入存储器阵列中。藉此，可在一分页写入的存储器阵列中进行单字节数据的数据更新。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1为依据本发明一实施例的存储器装置的系统示意图。
图2为依据本发明一实施例的存储器阵列、Y解码器、分页缓冲器及写入电路的电路示意图。
图3为依据本发明一实施例的缓冲单元的电路示意图。
图4为依据本发明一实施例的解码单元的电路示意图。
图5为依据本发明一实施例的写入单元的电路示意图。
图6为依据本发明一实施例的存储器装置的单字节数据写入方法的流程图。
图7为依据本发明一实施例的存储器装置的单字节数据写入方法的流程图。
【符号说明】
100：存储器装置
110：存储器阵列
111：存储器胞
120：分页缓冲器
121：缓冲单元
130：Y解码器
131：解码单元
140：感测放大器
150：写入电路
151：写入单元
160：字线解码器
310：三态反相器
ARDATA：阵列数据
BL1、BL2：位线
DL1、DL2：数据线
DSL：数据选择信号
ENPGBUF：页面缓冲致能信号
ENWR：写入致能信号
GND：第二参考电压
IE：输入端
IN_LAT：内部锁存节点
INV1：第一反相器
INV2：第二反相器
INV3：第三反相器
M1～M6：晶体管
OE：输出端
PDATA：编程数据
TR1：第一传输门
TR2：第二传输门
TR3：第三传输门
TR4：第四传输门
VCC：第一参考电压
YD1：Y解码信号
ZDSL：反相数据选择信号
ZENPGBUF：反相页面缓冲致能信号
ZYD1：反相Y解码信号
S610、S620、S630、S640、S710、S720、S730、S740、S750、S760、S770：步骤
具体实施方式
图1为依据本发明一实施例的存储器装置的系统示意图。请参照图1，在本实施例中，存储器装置100包括存储器阵列110、分页缓冲器120、Y解码器130、感测放大器140、写入电路150及字线解码器160，其中存储器装置100可以是非易失性存储器装置，并且存储器阵列110例如包括多个阵列排列的存储器胞(稍后说明)，但本发明实施例不以此为限。并且，分页缓冲器120、Y解码器130、感测放大器140、写入电路150及字线解码器160可视为一外围电路，耦接存储器阵列110，并且接收由外部所提供的一字节的编程数据PDATA后，将编程数据PDATA写入存储器阵列110。
存储器阵列110耦接至分页缓冲器120、Y解码器130及字线解码器160，其中存储器阵列110、分页缓冲器120及Y解码器130相互耦接。感测放大器140耦接至Y解码器130及写入电路150，并且写入电路150耦接至Y解码器130。
写入电路150接收编程数据PDATA，并且感测放大器140通过Y解码器130耦接至存储器阵列110，以通过Y解码器130依据编程数据PDATA对应的存储器地址读取存储器阵列110所存储的多字节的阵列数据ARDATA后，提供阵列数据ARDATA至写入电路150。
接着，写入电路150将所读取的阵列数据ARDATA通过Y解码器130写入至分页缓冲器120，并且接着编程数据PDATA通过写入电路150及Y解码器130写入至存储器阵列110，但编程数据PDATA不会经过分页缓冲器120。然后，阵列数据ARDATA由分页缓冲器120写入至存储器阵列110，但不会覆盖编程数据PDATA。
在本实施例中，存储器地址包括字线地址及位线地址，并且编程数据PDATA与阵列数据ARDATA例如对应同一字线地址。一般来说，一分页代表在一字线的存储器胞。进一步来说，在感测放大器140读取存储器阵列110时，字线解码器160会依据编程数据PDATA对应的存储器地址中的字线地址(亦即选定的字线地址)驱动存储器阵列110，以致能存储器阵列110中一分页的存储器胞(例如是控制逻辑上同一列的所有存储器胞)，接着位线地址会递增，以使感测放大器140可依序读取此分页的存储器胞中所存储的阵列数据ARDATA。
在本实施例中，当写入电路150通过感测放大器140接收存储器阵列110的阵列数据ARDATA时，开启存储器阵列110及Y解码器130，并且关闭分页缓冲器120；当写入电路150将阵列数据ARDATA写入分页缓冲器120时，开启Y解码器130及分页缓冲器120，并且关闭存储器阵列110；当写入电路150将编程数据PDATA写入存储器阵列110时，开启存储器阵列110、分页缓冲器120及Y解码器130；当阵列数据ARDATA由分页缓冲器120写入存储器阵列110时，开启存储器阵列110及分页缓冲器120，并且关闭Y解码器130。
在本发明的一实施例中，感测放大器140所读取的阵列数据ARDATA可包含编程数据PDATA所要写入的存储器胞中所存储的数据，也可以不包含编程数据PDATA所要写入的存储器胞中所存储的数据。在写入电路150将阵列数据ARDATA写入至分页缓冲器120后，可抹除编程数据PDATA及阵列数据ARDATA的存储器地址所对应的存储器胞(亦即一分页)。
图2为依据本发明一实施例的存储器阵列、Y解码器、分页缓冲器及写入电路的线路示意图。请参照图1及图2，其中相同或相似元件使用相同或相似标号。在本实施例中，存储器阵列110具有多个存储器胞111，Y解码器130具有多个解码单元131、分页缓冲器120具有多个缓冲单元121，并且写入电路150具有多个写入单元151。
在本实施例中，Y解码器130及分页缓冲器120通过多条位线(即BL1、BL2、…)耦接至存储器阵列110。换句话说，各个解码单元131及各缓冲单元121通过对应的位线(如BL1、BL2)耦接至对应的存储器胞111。并且，Y解码器130通过多条数据线(即DL1、DL2、…)耦接至感测放大器140及写入电路150。在一实施例中，编程数据PDATA为8位(bit)，写入电路150具有8个写入单元151，放大传感器140连接至数据线DL1～DL8，因此，当位线地址递增时，放大传感器140会依序送出8位编程数据PDATA至写入电路150。
图3为依据本发明一实施例的缓冲单元的电路示意图。请参照图1至图3，在本实施例中，各个缓冲单元121包括第一传输门TR1、第一反相器INV1及三态反相器310。第一传输门TR1的第一端耦接对应的位线BL1，第一传输门TR1的第二端耦接一内部锁存节点IN_LAT，第一传输门TR1的正控制端接收页面缓冲致能信号ENPGBUF，第一传输门TR1的负控制端接收一反相页面缓冲致能信号ZENPGBUF。第一反相器INV1的输入端耦接内部锁存节点IN_LAT。三态反相器310的输入端IE耦接第一反相器INV1的输出端，三态反相器310的输出端OE耦接内部锁存节点IN_LAT，其中三态反相器310受控于页面缓冲致能信号ENPGBUF、反相页面缓冲致能信号ZENPGBUF、Y解码信号YD1及反相Y解码信号ZYD1，页面缓冲致能信号ENPGBUF与反相页面缓冲致能信号ZENPGBUF互补，并且Y解码信号YD1与反相Y解码信号ZYD1互补。
三态反相器310包括晶体管M1～M6(对应第一晶体管至第六晶体管)。晶体管M1的源极(对应第一源/漏极)接收第一参考电压VCC，晶体管M1的栅极(对应第一栅极)接收Y解码信号YD1。晶体管M2的源极(对应第三源/漏极)耦接晶体管M1的漏极(对应第二源/漏极)，晶体管M2的栅极(对应第二栅极)耦接三态反相器310的输入端IE，晶体管M2的漏极(对应第四源/漏极)耦接三态反相器310的输出端OE。
晶体管M3的漏极(对应第五源/漏极)耦接三态反相器310的输出端OE，晶体管M3的栅极(对应第三栅极)耦接三态反相器310的输入端IE。晶体管M4的漏极(对应第七源/漏极)耦接晶体管M3的源极(对应第六源/漏极)，晶体管M4的栅极(对应第四栅极)接收反相Y解码信号ZYD1，晶体管M4的源极(对应第八源/漏极)接收第二参考电压GND。
晶体管M5的源极(对应第九源/漏极)接收第一参考电压VCC，晶体管M5的栅极(对应第五栅极)接收页面缓冲致能信号ENPGBUF，晶体管M五的漏极(对应第十源/漏极)耦接晶体管M1的漏极。晶体管M6的漏极(对应第十一源/漏极)耦接晶体管M3的源极(对应第六源/漏极)，晶体管M6的栅极(对应第六栅极)接收反相页面缓冲致能信号ZENPGBUF，晶体管M6的源极(对应第十二源/漏极)接收第二参考电压GND。
在本实施例中，当页面缓冲致能信号ENPGBUF致能时(例如为高电压电平)，亦即反相页面缓冲致能信号ZENPGBUF为禁能(例如为低电压电平)，第一传输门TR1会导通，亦即开启分页缓冲器120；反之，当页面缓冲致能信号ENPGBUF禁能时，第一传输门TR1会截止，亦即关闭分页缓冲器120。并且，当Y解码信号YD1及页面缓冲致能信号ENPGBUF皆致能时，亦即写入电路150写入数据至分页缓冲器120或存储器阵列110，数据线DL1连接至位线BL1，位线BL1连接至内部锁存节点IN_LAT，晶体管M1、M4～M6截止，并且位线BL1上的数据可易于写入到三态反相器310的输入端IE；当Y解码信号YD1禁能且页面缓冲致能信号ENPGBUF致能时，亦即分页缓冲器120写入数据至存储器阵列110，数据线DL1断开与位线BL1的连接，位线BL1连接至内部锁存节点IN_LAT，晶体管M1、M4导通，并且锁存的数据将会通过位线BL1写入至存储器阵列110；一旦页面缓冲致能信号ENPGBUF禁能时，位线BL1断开与内部锁存节点IN_LAT的连接，晶体管M5及M6导通，此时数据是锁存在缓冲单元121中的内部锁存节点IN_LAT。
图4为依据本发明一实施例的解码单元的电路示意图。请参照图1、图2及图4，在本实施例中，各个解码单元131包括第二传输门TR2。第二传输门TR2的第一端耦接对应的位线BL，第二传输门TR2的第二端耦接对应的数据线DL1，第二传输门TR2的正控制端接收Y解码信号YD1，第二传输门TR2的负控制端接收反相Y解码信号的ZYD1。当Y解码信号YD1致能时(例如为高电压电平)，亦即反相Y解码信号的ZYD1F为禁能(例如为低电压电平)，第二传输门TR2会导通，亦即开启Y解码器130；反之，当Y解码信号YD1禁能时，第二传输门TR2会截止，亦即关闭Y解码器130。在本发明的一实施例中，一分页为M个字节，位线(如BL1、BL2)的数目N为M的8倍，亦即N＝8Xm。因此，一条数据线(如DL1、DL2)连接至M个解码单元131。并且，位线会是BL1～BLN，Y解码信号会是YD1～YDN，并且反相Y解码信号会是ZYD1～ZYDN。
在本发明一实施例中，各个位线对应一Y解码信号(如YD1～YDN)及一反相Y解码信号(如ZYD1～ZYDN)，并且解码信号(如YD1～YDN)可以是部分致能、部分禁能、全部致能或全部禁能。缓冲单元(如121)的第一传输门TR1接收同一页面缓冲致能信号(如ENPGBUF)及同一反相页面缓冲致能信号(如ZENPGBUF)，亦即缓冲单元(如121)所接收的页面缓冲致能信号(如ENPGBUF)为全部致能或全部禁能。
在本发明一实施例中，存储器阵列110只能进行分页抹除操作及分页编程操作，亦即在同一字线上的存储器胞(如111)是同时抹除或同时编程。当执行一字节写入方案时(亦即将编程数据PDATA写人至存储器阵列110)，用以传送编程数据PDATA的位线(如BL1～BLN)所对应的Y解码信号(如YD1～YDN)为致能，其他Y解码信号(如YD1～YDN)为禁能，并且页面缓冲致能信号(如ENPGBUF)为致能。因此，编程数据PDATA通过写入电路150及Y解码器130写入至存储器阵列110，同时阵列数据ARDATA由分页缓冲器120写入至存储器阵列110。
图5为依据本发明一实施例的写入单元的电路示意图。请参照图1、图2及图4，在本实施例中，各个写入单元151包括第三传输门TR3、第四传输门TR4、第二反相器INV2及第三反相器INV3。第三传输门TR3的第一端接收阵列数据ARDATA，第三传输门TR3的正控制端接收反相数据选择信号ZDSL，第三传输门TR3的负控制端接收数据选择信号DSL。
第四传输门TR4的第一端接收编程数据PDATA，第四传输门TR4的第二端耦接第三传输门TR3的第二端，第四传输门TR4的正控制端接收数据选择信号DSL，第四传输门TR4的负控制端接收反相数据选择信号ZDSL。第二反相器INV2的输入端耦接第三传输门TR3的第二端。第三反相器INV3的输入端耦接第二反相器INV2的输出端，第三反相器INV3的输出端耦接对应的数据线DL1，第三反相器INV3的控制端接收写入致能信号ENWR。
在本实施例中，当数据选择信号DSL致能时(例如为高电压电平)，亦即反相数据选择信号ZDSL为禁能(例如为低电压电平)，第四传输门TR4会导通，第三传输门TR3会截止，亦即编程数据PDATA会提供至第二反相器INV2；反之，当数据选择信号DSL禁能时，第三传输门TR3会导通，第四传输门TR4会截止，亦即阵列数据ARDATA会提供至第二反相器INV2。
图6为依据本发明一实施例的存储器装置的单字节数据写入方法的流程图。请参照图6，在本实施例中，单字节数据写入方法包括下列步骤。在步骤S610中，会通过写入电路接收一字节的一编程数据。在步骤S620中，会通过一感测放大器及Y解码器依据编程数据对应的一存储器地址读取存储器阵列所存储的多字节的一阵列数据，并且通过写入电路及Y解码器将阵列数据写入至分页缓冲器。接着，在步骤S630中，在写入电路将阵列数据写入至分页缓冲器后，抹除所读取的阵列数据的存储器地址所对应的存储器阵列中的存储器胞。在步骤S640中，通过写入电路及Y解码器将编程数据写入至存储器阵列。此时，通过分页缓冲器将阵列数据写入至存储器阵列。
图7为依据本发明另一实施例的存储器装置的单字节数据写入方法的流程图。请参照图7，在本实施例中，单字节数据写入方法包括下列步骤。在步骤S710中，会设定选定的一字线地址及一位线地址。在步骤S720中，会递增位线地址。在步骤S730中，会读取存储器阵列的一分页中未选定的一字节的阵列数据。接着，在步骤S740中，将阵列数据存储在分页缓冲器中。
在步骤S750中，会判断位线地址是否对应此分页中最后一个未读取且未选定的阵列数据。当位线地址未对应此分页中最后一个未读取且未选定的阵列数据时，亦即步骤S750的判断结果为“否”，则回到步骤S720；当位线地址是对应此分页中最后一个未读取且未选定的阵列数据时，亦即步骤S750的判断结果为“是”，则停止阵列数据的读取，并且接着执行步骤S760。
在步骤S760中，会抹除此分页。最后，在步骤S770中，将编程数据(亦即选定的数据)直接写入存储器阵列中，以更新此分页中所存储的数据，并且通过分页缓冲器将阵列数据(亦即未选定的数据)写入存储器阵列中，以回写此分页中所存储的数据。
其中，上述步骤S610、S620、S630、S640、S710、S720、S730、S740、S750、S760及S770的顺序为用以说明，本发明实施例不以此为限。并且，上述步骤S610、S620、S630、S640、S710、S720、S730、S740、S750、S760及S770的细节可参照图1至图5的实施例所示，在此则不再赘述。
在本发明的一实施例中，假设一分页的大小为M字节，而单字节数据写入方法可由1计数至M，亦即分页的阵列数据是逐字节读取，以判断是否进行阵列数据的读取。换句话说，当计数结果小于M时，进行阵列数据的读取，当计数结果大于等于M时，停止阵列数据的读取。其中，M为一整数，并且阵列数据的读取步骤参照图7的步骤S720至S750，在此则不再赘述。
综上所述，本发明实施例的存储器装置、其外围电路及其单字节数据写入方法，其写入电路接收未选取的阵列数据并写入至分页缓冲器中，并且将选取的编程数据直接写入至存储器阵列中，而阵列数据通过分页缓冲器写入存储器阵列中。藉此，可在一分页写入的存储器阵列中进行单字节数据的数据更新。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附权利要求书界定范围为准。

Claims (20)

1.一种存储器装置的外围电路，其待征在于，包括：
Y解码器，耦接该存储器装置的存储器阵列；
分页缓冲器，耦接该存储器阵列及该Y解码器；
写入电路，通过该Y解码器耦接该存储器阵列及该分页缓冲器，并且接收一字节的编程数据；以及
感测放大器，耦接于该Y解码器与该写入电路之间，以通过该Y解码器读取该存储器阵列所存储的多字节的阵列数据后提供至该写入电路；
其中，所读取的该阵列数据是依据该编程数据对应的存储器地址，所读取的该阵列数据是通过该Y解码器写入至该分页缓冲器但不经过该分页缓冲器，并且接着该编程数据通过该写入电路及该Y解码器写入至该存储器阵列但不覆盖该编程数据，并且该阵列数据由该分页缓冲器写入至该存储器阵列。
2.如权利要求1所述的外围电路，其待征在于，该存储器地址包括字线地址及位线地址，并且该编程数据与该阵列数据对应同一字线地址。
3.如权利要求2所述的外围电路，其待征在于，还包括字线解码器，依据该字线地址驱动该存储器阵列。
4.如权利要求1所述的外围电路，其待征在于，该存储器阵列具有多个存储器胞，并且在该写入电路将该阵列数据写入至该分页缓冲器后，抹除该存储器地址对应的这些存储器胞及该阵列数据对应的这些存储器胞。
5.如权利要求1所述的外围电路，其待征在于，该Y解码器及该分页缓冲器通过多条位线耦接至该存储器阵列。
6.如权利要求5所述的外围电路，其待征在于，该存储器阵列具有多个存储器胞，该Y解码器具有多个解码单元，并且该分页缓冲器具有多个缓冲单元，其中各这些解码单元及各这些缓冲单元通过对应的位线耦接至对应的存储器胞。
7.如权利要求6所述的外围电路，其待征在于，各这些缓冲单元包括：
第一传输门，具有耦接对应的位线的第一端、耦接内部锁存节点的第二端、接收页面缓冲致能信号的正控制端、以及接收反相页面缓冲致能信号的负控制端；
第一反相器，具有耦接该内部锁存节点的输入端及输出端；
三态反相器，具有耦接该第一反相器的该输出端的输入端、以及耦接该内部锁存节点的输出端，其中该三态反相器受控于该页面缓冲致能信号及Y解码信号。
8.如权利要求7所述的外围电路，其待征在于，该三态反相器包括：
第一晶体管，具有接收第一参考电压的第一源/漏极、接收该Y解码信号的第一栅极、以及第二源/漏极；
第二晶体管，具有耦接该第二源/漏极的第三源/漏极、耦接该输入端的第二栅极、以及耦接该输出端的第四源/漏极；
第三晶体管，具有耦接该输出端的第五源/漏极、耦接该输入端的第三栅极、以及第六源/漏极；
第四晶体管，具有耦接该第六源/漏极的第七源/漏极、接收反相Y解码信号的第四栅极、以及接收第二参考电压的第八源/漏极；
第五晶体管，具有接收该第一参考电压的第九源/漏极、接收该页面缓冲致能信号的第五栅极、以及耦接该第二源/漏极的第十源/漏极；以及
第六晶体管，具有耦接该第六源/漏极的第十一源/漏极、接收该反相页面缓冲致能信号的第六栅极、以及接收该第二参考电压的第十二源/漏极。
9.如权利要求8所述的外围电路，其待征在于，该Y解码器通过多条数据线耦接至该写入电路。
10.如权利要求9所述的外围电路，其待征在于，各这些解码单元包括：
第二传输门，具有耦接对应的位线的第一端、耦接对应的数据线的第二端、接收该Y解码信号的正控制端、以及接收该反相Y解码信号的负控制端。
11.如权利要求9所述的外围电路，其待征在于，该写入电路具有多个写入单元，并且各这些写入单元包括：
第三传输门，具有接收该阵列数据的第一端、第二端、接收反相数据选择信号的正控制端、以及接收数据选择信号的负控制端；
第四传输门，具有接收该编程数据的第一端、耦接该第三传输门的该第二端的第二端、接收该数据选择信号的正控制端、以及接收该反相数据选择信号的负控制端；
第二反相器，具有耦接该第三传输门的该第二端的输入端及输出端；以及
第三反相器，具有耦接该第二反相器的该输出端的输入端、耦接对应的数据线的输出端以及接收写入致能信号的控制端。
12.如权利要求1所述的外围电路，其待征在于，当该感测放大器读取该存储器阵列的该阵列数据时，开启该存储器阵列及该Y解码器，并且关闭该分页缓冲器，当该写入电路将该阵列数据写入该分页缓冲器时，开启该Y解码器及该分页缓冲器，并且关闭该存储器阵列，当该写入电路将该编程数据写入该存储器阵列时，开启该存储器阵列、该分页缓冲器及该Y解码器，当该阵列数据由该分页缓冲器写入该存储器阵列时，开启该存储器阵列及该分页缓冲器，并且关闭该Y解码器。
13.一种存储器装置，其待征在于，包括：
存储器阵列；以及
如权利要求1所述的外围电路，耦接该存储器阵列，并且接收一字节的编程数据，以将该编程数据写入该存储器阵列。
14.一种存储器装置的单字节数据写入方法，其待征在于，包括：
通过写入电路接收一字节的编程数据；
通过感测放大器及Y解码器依据该编程数据对应的存储器地址读取存储器阵列所存储的多字节的阵列数据，并且通过该写入电路及该Y解码器将该阵列数据写入至分页缓冲器；
通过该写入电路及该Y解码器将该编程数据写入至该存储器阵列；以及
通过该分页缓冲器将该阵列数据写入至该存储器阵列。
15.如权利要求14所述的单字节数据写入方法，其待征在于，该存储器地址包括字线地址及位线地址，并且该编程数据与该阵列数据对应同一字元地址。
16.如权利要求14所述的单字节数据写入方法，其待征在于，该存储器阵列具有多个存储器胞，并且该单字节数据写入方法还包括：
在该写入电路将该阵列数据写入至该分页缓冲器后，抹除该存储器地址对应的这些存储器胞及该阵列数据对应的这些存储器胞。
17.如权利要求14所述的单字节数据写入方法，还包括：
当该感测放大器读取该存储器阵列的该阵列数据时，开启该存储器阵列及该Y解码器，并且关闭该分页缓冲器；
当该写入电路将该阵列数据写入该分页缓冲器时，开启该Y解码器及该分页缓冲器，并且关闭该存储器阵列；
当该写入电路将该编程数据写入该存储器阵列时，开启该存储器阵列、该分页缓冲器及该Y解码器：以及
当该阵列数据由该分页缓冲器写入该存储器阵列时，开启该存储器阵列及该分页缓冲器，并且关闭该Y解码器。
18.如权利要求14所述的单字节数据写入方法，其中在通过该写入电路及该Y解码器将该编程数据写入至该存储器阵列时，同时通过该分页缓冲器将该阵列数据写入至该存储器阵列。
19.如权利要求14所述的单字节数据写入方法，其中“通过该感测放大器及该Y解码器依据该编程数据对应的该存储器地址读取该存储器阵列所存储的该多字节的该阵列数据，并且通过该写入电路及该Y解码器将该阵列数据写入至该分页缓冲器”的步骤包括：
A)设定对应该编程数据的该存储器地址的字线地址及位线地址；
B)递增该位线地址；
C)依据递增的该位线地址通过该感测放大器及该Y解码器读取在该存储器阵列的分页中的一字节的该阵列数据；
D)通过该写入电路及该Y解码器将该阵列数据写入该分页缓冲器；以及
E)当递增的该位线地址非对应该分页中最后未读取的该阵列数据时，重复步骤B至E，其中最后未读取的该阵列数据非对应该存储器地址的该位线地址。
20.如权利要求14所述的单字节数据写入方法，其中在该存储器阵列的分页的大小为M字节，并且“依据该编程数据对应的该存储器地址读取该存储器阵列所存储的该多字节的该阵列数据”的步骤包括：
由1计数至N以产生计数结果，其中M为整数；
当该计数结果小于M时，读取一字节的该阵列数据；以及
当该计数结果等于M时，停止该阵列数据的读取。
CN201710044103.1A 2016-01-19 2017-01-19 存储器装置、其外围电路及其单字节数据写入方法 Active CN106981307B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662280683P 2016-01-19 2016-01-19
US62/280,683 2016-01-19

Publications (2)

Publication Number Publication Date
CN106981307A CN106981307A (zh) 2017-07-25
CN106981307B true CN106981307B (zh) 2020-04-07

Family

ID=56137184

Family Applications (10)

Application Number Title Priority Date Filing Date
CN201610555070.2A Active CN106981311B (zh) 2016-01-19 2016-07-14 电压切换电路
CN201610628752.1A Active CN106981309B (zh) 2016-01-19 2016-08-03 存储阵列
CN201610976441.4A Active CN106981492B (zh) 2016-01-19 2016-11-03 非挥发性存储器结构和阵列
CN201710026008.9A Active CN106981304B (zh) 2016-01-19 2017-01-13 非易失性存储器的驱动电路
CN201710036121.5A Active CN106981299B (zh) 2016-01-19 2017-01-17 运用于非易失性存储器的电源切换电路
CN201710040607.6A Active CN107017023B (zh) 2016-01-19 2017-01-18 存储阵列
CN201710044103.1A Active CN106981307B (zh) 2016-01-19 2017-01-19 存储器装置、其外围电路及其单字节数据写入方法
CN201710135824.3A Active CN108206186B (zh) 2016-01-19 2017-03-08 具有擦除元件的单层多晶硅非易失性存储单元结构
CN201710151469.9A Active CN108154898B (zh) 2016-01-19 2017-03-14 存储单元
CN201710290037.6A Active CN108320772B (zh) 2016-01-19 2017-04-27 存储单元及存储阵列

Family Applications Before (6)

Application Number Title Priority Date Filing Date
CN201610555070.2A Active CN106981311B (zh) 2016-01-19 2016-07-14 电压切换电路
CN201610628752.1A Active CN106981309B (zh) 2016-01-19 2016-08-03 存储阵列
CN201610976441.4A Active CN106981492B (zh) 2016-01-19 2016-11-03 非挥发性存储器结构和阵列
CN201710026008.9A Active CN106981304B (zh) 2016-01-19 2017-01-13 非易失性存储器的驱动电路
CN201710036121.5A Active CN106981299B (zh) 2016-01-19 2017-01-17 运用于非易失性存储器的电源切换电路
CN201710040607.6A Active CN107017023B (zh) 2016-01-19 2017-01-18 存储阵列

Family Applications After (3)

Application Number Title Priority Date Filing Date
CN201710135824.3A Active CN108206186B (zh) 2016-01-19 2017-03-08 具有擦除元件的单层多晶硅非易失性存储单元结构
CN201710151469.9A Active CN108154898B (zh) 2016-01-19 2017-03-14 存储单元
CN201710290037.6A Active CN108320772B (zh) 2016-01-19 2017-04-27 存储单元及存储阵列

Country Status (5)

Country Link
US (13) US9847133B2 (zh)
EP (6) EP3196883B1 (zh)
JP (4) JP6122531B1 (zh)
CN (10) CN106981311B (zh)
TW (11) TWI578322B (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9965267B2 (en) 2015-11-19 2018-05-08 Raytheon Company Dynamic interface for firmware updates
US9847133B2 (en) 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation
US9633734B1 (en) * 2016-07-14 2017-04-25 Ememory Technology Inc. Driving circuit for non-volatile memory
CN107768373B (zh) * 2016-08-15 2022-05-10 华邦电子股份有限公司 存储元件及其制造方法
US9882566B1 (en) * 2017-01-10 2018-01-30 Ememory Technology Inc. Driving circuit for non-volatile memory
TWI652683B (zh) * 2017-10-13 2019-03-01 力旺電子股份有限公司 用於記憶體的電壓驅動器
US10332597B2 (en) * 2017-11-08 2019-06-25 Globalfoundries Singapore Pte. Ltd. Floating gate OTP/MTP structure and method for producing the same
JP7143326B2 (ja) 2017-12-20 2022-09-28 タワー パートナーズ セミコンダクター株式会社 半導体装置
KR102385951B1 (ko) * 2018-02-23 2022-04-14 에스케이하이닉스 시스템아이씨 주식회사 프로그램 효율이 증대되는 원 타임 프로그래머블 메모리 및 그 제조방법
KR102422839B1 (ko) * 2018-02-23 2022-07-19 에스케이하이닉스 시스템아이씨 주식회사 수평 커플링 구조 및 단일층 게이트를 갖는 불휘발성 메모리 소자
US10522202B2 (en) * 2018-04-23 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and compensation method therein
US10964708B2 (en) * 2018-06-26 2021-03-30 Micron Technology, Inc. Fuse-array element
CN108986866B (zh) * 2018-07-20 2020-12-11 上海华虹宏力半导体制造有限公司 一种读高压传输电路
TWI659502B (zh) * 2018-08-02 2019-05-11 旺宏電子股份有限公司 非揮發性記憶體結構
CN110828464A (zh) * 2018-08-08 2020-02-21 旺宏电子股份有限公司 非易失性存储器结构
DE102019120605B4 (de) 2018-08-20 2022-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Speicherschaltung und verfahren zu deren herstellung
US11176969B2 (en) 2018-08-20 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit including a first program device
CN109147851B (zh) * 2018-08-31 2020-12-25 上海华力微电子有限公司 一种锁存电路
KR20200031894A (ko) * 2018-09-17 2020-03-25 에스케이하이닉스 주식회사 메모리 모듈 및 이를 포함하는 메모리 시스템
US10797064B2 (en) * 2018-09-19 2020-10-06 Ememory Technology Inc. Single-poly non-volatile memory cell and operating method thereof
CN109524042B (zh) * 2018-09-21 2020-03-17 浙江大学 一种基于反型模式阻变场效应晶体管的与非型存储阵列
TWI708253B (zh) 2018-11-16 2020-10-21 力旺電子股份有限公司 非揮發性記憶體良率提升的設計暨測試方法
CN111342541B (zh) * 2018-12-19 2021-04-16 智原微电子(苏州)有限公司 电源切换电路
KR20200104669A (ko) * 2019-02-27 2020-09-04 삼성전자주식회사 집적회로 소자
US10924112B2 (en) * 2019-04-11 2021-02-16 Ememory Technology Inc. Bandgap reference circuit
US11508719B2 (en) * 2019-05-13 2022-11-22 Ememory Technology Inc. Electrostatic discharge circuit
CN112086115B (zh) * 2019-06-14 2023-03-28 力旺电子股份有限公司 存储器系统
CN112131037B (zh) * 2019-06-24 2023-11-14 华邦电子股份有限公司 存储器装置
JP2021048230A (ja) * 2019-09-18 2021-03-25 キオクシア株式会社 半導体記憶装置
US11521980B2 (en) * 2019-11-14 2022-12-06 Ememory Technology Inc. Read-only memory cell and associated memory cell array
US11217281B2 (en) * 2020-03-12 2022-01-04 Ememory Technology Inc. Differential sensing device with wide sensing margin
US11139006B1 (en) * 2020-03-12 2021-10-05 Ememory Technology Inc. Self-biased sense amplification circuit
JP6887044B1 (ja) * 2020-05-22 2021-06-16 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および読出し方法
TWI739695B (zh) * 2020-06-14 2021-09-11 力旺電子股份有限公司 轉壓器
US11373715B1 (en) * 2021-01-14 2022-06-28 Elite Semiconductor Microelectronics Technology Inc. Post over-erase correction method with auto-adjusting verification and leakage degree detection
TWI819457B (zh) * 2021-02-18 2023-10-21 力旺電子股份有限公司 多次編程非揮發性記憶體的記憶胞陣列
US11854647B2 (en) * 2021-07-29 2023-12-26 Micron Technology, Inc. Voltage level shifter transition time reduction
US11972800B2 (en) * 2021-12-16 2024-04-30 Ememory Technology Inc. Non-volatile memory cell and non-volatile memory cell array
US12014783B2 (en) 2022-01-10 2024-06-18 Ememory Technology Inc. Driving circuit for non-volatile memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101650972A (zh) * 2009-06-12 2010-02-17 东信和平智能卡股份有限公司 智能卡的非易失性存储器数据更新方法
CN103534759A (zh) * 2011-06-24 2014-01-22 国际商业机器公司 用于在接收到包括混合的读取和写入命令的一系列命令时执行最优写入的线性记录设备及其执行方法和程序
CN104517644A (zh) * 2013-10-08 2015-04-15 力旺电子股份有限公司 非易失性存储器装置及其数据验证方法
CN105321570A (zh) * 2014-07-08 2016-02-10 力旺电子股份有限公司 非易失性存储器及其列解码器

Family Cites Families (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617652A (en) 1979-01-24 1986-10-14 Xicor, Inc. Integrated high voltage distribution and control systems
JP2685966B2 (ja) 1990-06-22 1997-12-08 株式会社東芝 不揮発性半導体記憶装置
US5331590A (en) 1991-10-15 1994-07-19 Lattice Semiconductor Corporation Single poly EE cell with separate read/write paths and reduced product term coupling
JP3180608B2 (ja) 1994-03-28 2001-06-25 松下電器産業株式会社 電源選択回路
JP3068752B2 (ja) 1994-08-29 2000-07-24 松下電器産業株式会社 半導体装置
US5648669A (en) * 1995-05-26 1997-07-15 Cypress Semiconductor High speed flash memory cell structure and method
US5742542A (en) * 1995-07-03 1998-04-21 Advanced Micro Devices, Inc. Non-volatile memory cells using only positive charge to store data
US5640344A (en) * 1995-07-25 1997-06-17 Btr, Inc. Programmable non-volatile bidirectional switch for programmable logic
US6005806A (en) * 1996-03-14 1999-12-21 Altera Corporation Nonvolatile configuration cells and cell arrays
JP4659662B2 (ja) 1997-04-28 2011-03-30 ペグレ・セミコンダクターズ・リミテッド・ライアビリティ・カンパニー 半導体装置及びその製造方法
FR2767219B1 (fr) * 1997-08-08 1999-09-17 Commissariat Energie Atomique Dispositif memoire non volatile programmable et effacable electriquement compatible avec un procede de fabrication cmos/soi
JP3037236B2 (ja) * 1997-11-13 2000-04-24 日本電気アイシーマイコンシステム株式会社 レベルシフタ回路
US5959889A (en) * 1997-12-29 1999-09-28 Cypress Semiconductor Corp. Counter-bias scheme to reduce charge gain in an electrically erasable cell
DE19808525A1 (de) 1998-02-27 1999-09-02 Siemens Ag Integrierte Schaltung
JP2000021183A (ja) 1998-06-30 2000-01-21 Matsushita Electric Ind Co Ltd 半導体不揮発性メモリ
US5999451A (en) 1998-07-13 1999-12-07 Macronix International Co., Ltd. Byte-wide write scheme for a page flash device
JP3344331B2 (ja) 1998-09-30 2002-11-11 日本電気株式会社 不揮発性半導体記憶装置
JP2000276889A (ja) 1999-03-23 2000-10-06 Toshiba Corp 不揮発性半導体メモリ
WO2001017030A1 (en) * 1999-08-27 2001-03-08 Macronix America, Inc. Non-volatile memory structure for twin-bit storage and methods of making same
JP2001068650A (ja) * 1999-08-30 2001-03-16 Hitachi Ltd 半導体集積回路装置
KR100338772B1 (ko) * 2000-03-10 2002-05-31 윤종용 바이어스 라인이 분리된 비휘발성 메모리 장치의 워드라인 드라이버 및 워드 라인 드라이빙 방법
US6370071B1 (en) * 2000-09-13 2002-04-09 Lattice Semiconductor Corporation High voltage CMOS switch
EP1451969A2 (en) * 2001-11-27 2004-09-01 Koninklijke Philips Electronics N.V. Semiconductor device having a byte-erasable eeprom memory
TW536818B (en) 2002-05-03 2003-06-11 Ememory Technology Inc Single-poly EEPROM
US6621745B1 (en) * 2002-06-18 2003-09-16 Atmel Corporation Row decoder circuit for use in programming a memory device
US6774704B2 (en) 2002-10-28 2004-08-10 Tower Semiconductor Ltd. Control circuit for selecting the greater of two voltage signals
US7038947B2 (en) * 2002-12-19 2006-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Two-transistor flash cell for large endurance application
CN1224106C (zh) * 2003-03-05 2005-10-19 力旺电子股份有限公司 只读存储器及其制作方法
JP2004326864A (ja) 2003-04-22 2004-11-18 Toshiba Corp 不揮発性半導体メモリ
FR2856185A1 (fr) 2003-06-12 2004-12-17 St Microelectronics Sa Memoire flash programmable par mot
US6963503B1 (en) 2003-07-11 2005-11-08 Altera Corporation. EEPROM with improved circuit performance and reduced cell size
JP2005051227A (ja) * 2003-07-17 2005-02-24 Nec Electronics Corp 半導体記憶装置
US7169667B2 (en) * 2003-07-30 2007-01-30 Promos Technologies Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate
US7081774B2 (en) * 2003-07-30 2006-07-25 Semiconductor Energy Laboratory Co., Ltd. Circuit having source follower and semiconductor device having the circuit
US7145370B2 (en) 2003-09-05 2006-12-05 Impinj, Inc. High-voltage switches in single-well CMOS processes
US20050134355A1 (en) 2003-12-18 2005-06-23 Masato Maede Level shift circuit
US20050205969A1 (en) * 2004-03-19 2005-09-22 Sharp Laboratories Of America, Inc. Charge trap non-volatile memory structure for 2 bits per transistor
US7580311B2 (en) * 2004-03-30 2009-08-25 Virage Logic Corporation Reduced area high voltage switch for NVM
US7629640B2 (en) * 2004-05-03 2009-12-08 The Regents Of The University Of California Two bit/four bit SONOS flash memory cell
DE602004010795T2 (de) * 2004-06-24 2008-12-11 Stmicroelectronics S.R.L., Agrate Brianza Verbesserter Seitenspeicher für eine programmierbare Speichervorrichtung
US6992927B1 (en) 2004-07-08 2006-01-31 National Semiconductor Corporation Nonvolatile memory cell
US7209392B2 (en) * 2004-07-20 2007-04-24 Ememory Technology Inc. Single poly non-volatile memory
KR100633332B1 (ko) * 2004-11-09 2006-10-11 주식회사 하이닉스반도체 음의 전압 공급회로
KR100642631B1 (ko) * 2004-12-06 2006-11-10 삼성전자주식회사 전압 발생회로 및 이를 구비한 반도체 메모리 장치
US7369438B2 (en) 2004-12-28 2008-05-06 Aplus Flash Technology, Inc. Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
US7193265B2 (en) 2005-03-16 2007-03-20 United Microelectronics Corp. Single-poly EEPROM
US7263001B2 (en) 2005-03-17 2007-08-28 Impinj, Inc. Compact non-volatile memory cell and array system
US7288964B2 (en) 2005-08-12 2007-10-30 Ememory Technology Inc. Voltage selective circuit of power source
JP4800109B2 (ja) 2005-09-13 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置
JP2007149997A (ja) 2005-11-29 2007-06-14 Nec Electronics Corp 不揮発性メモリセル及びｅｅｐｒｏｍ
US7382658B2 (en) 2006-01-26 2008-06-03 Mosys, Inc. Non-volatile memory embedded in a conventional logic process and methods for operating same
US7391647B2 (en) * 2006-04-11 2008-06-24 Mosys, Inc. Non-volatile memory in CMOS logic process and method of operation thereof
US20070247915A1 (en) * 2006-04-21 2007-10-25 Intersil Americas Inc. Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide
US7773416B2 (en) * 2006-05-26 2010-08-10 Macronix International Co., Ltd. Single poly, multi-bit non-volatile memory device and methods for operating the same
JP4901325B2 (ja) 2006-06-22 2012-03-21 ルネサスエレクトロニクス株式会社 半導体装置
US7768059B2 (en) 2006-06-26 2010-08-03 Ememory Technology Inc. Nonvolatile single-poly memory device
TWI373127B (en) * 2006-06-26 2012-09-21 Ememory Technology Inc Nonvolatile single-poly memory device
US20070296034A1 (en) 2006-06-26 2007-12-27 Hsin-Ming Chen Silicon-on-insulator (soi) memory device
JP5005970B2 (ja) 2006-06-27 2012-08-22 株式会社リコー 電圧制御回路及び電圧制御回路を有する半導体集積回路
CN100508169C (zh) * 2006-08-02 2009-07-01 联华电子股份有限公司 单层多晶硅可电除可程序只读存储单元的制造方法
US7586792B1 (en) * 2006-08-24 2009-09-08 National Semiconductor Corporation System and method for providing drain avalanche hot carrier programming for non-volatile memory applications
KR100805839B1 (ko) * 2006-08-29 2008-02-21 삼성전자주식회사 고전압 발생기를 공유하는 플래시 메모리 장치
US7483310B1 (en) * 2006-11-02 2009-01-27 National Semiconductor Corporation System and method for providing high endurance low cost CMOS compatible EEPROM devices
KR100781041B1 (ko) * 2006-11-06 2007-11-30 주식회사 하이닉스반도체 플래시 메모리 장치 및 그 소거 동작 제어 방법
JP4863844B2 (ja) * 2006-11-08 2012-01-25 セイコーインスツル株式会社 電圧切替回路
US8378407B2 (en) 2006-12-07 2013-02-19 Tower Semiconductor, Ltd. Floating gate inverter type memory cell and array
US7755941B2 (en) * 2007-02-23 2010-07-13 Panasonic Corporation Nonvolatile semiconductor memory device
US7436710B2 (en) 2007-03-12 2008-10-14 Maxim Integrated Products, Inc. EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well
WO2008114342A1 (ja) * 2007-03-16 2008-09-25 Fujitsu Microelectronics Limited 電源スイッチ回路及び半導体集積回路装置
US7663916B2 (en) 2007-04-16 2010-02-16 Taiwan Semicondcutor Manufacturing Company, Ltd. Logic compatible arrays and operations
US7903465B2 (en) * 2007-04-24 2011-03-08 Intersil Americas Inc. Memory array of floating gate-based non-volatile memory cells
JP4455621B2 (ja) * 2007-07-17 2010-04-21 株式会社東芝 エージングデバイス
US8369155B2 (en) * 2007-08-08 2013-02-05 Hynix Semiconductor Inc. Operating method in a non-volatile memory device
JP2009049182A (ja) 2007-08-20 2009-03-05 Toyota Motor Corp 不揮発性半導体記憶素子
US7700993B2 (en) * 2007-11-05 2010-04-20 International Business Machines Corporation CMOS EPROM and EEPROM devices and programmable CMOS inverters
KR101286241B1 (ko) 2007-11-26 2013-07-15 삼성전자주식회사 최대 전압 선택회로
US7968926B2 (en) 2007-12-19 2011-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Logic non-volatile memory cell with improved data retention ability
CN101965638B (zh) * 2008-01-18 2012-12-05 夏普株式会社 非易失性随机存取存储器
US7639536B2 (en) 2008-03-07 2009-12-29 United Microelectronics Corp. Storage unit of single-conductor non-volatile memory cell and method of erasing the same
US7800426B2 (en) 2008-03-27 2010-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Two voltage input level shifter with switches for core power off application
JP5266443B2 (ja) * 2008-04-18 2013-08-21 インターチップ株式会社 不揮発性メモリセル及び不揮発性メモリセル内蔵データラッチ
US8344443B2 (en) 2008-04-25 2013-01-01 Freescale Semiconductor, Inc. Single poly NVM devices and arrays
US8218377B2 (en) * 2008-05-19 2012-07-10 Stmicroelectronics Pvt. Ltd. Fail-safe high speed level shifter for wide supply voltage range
US7894261B1 (en) 2008-05-22 2011-02-22 Synopsys, Inc. PFET nonvolatile memory
US8295087B2 (en) * 2008-06-16 2012-10-23 Aplus Flash Technology, Inc. Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS
KR101462487B1 (ko) * 2008-07-07 2014-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
US7983081B2 (en) 2008-12-14 2011-07-19 Chip.Memory Technology, Inc. Non-volatile memory apparatus and method with deep N-well
US8189390B2 (en) * 2009-03-05 2012-05-29 Mosaid Technologies Incorporated NAND flash architecture with multi-level row decoding
US8319528B2 (en) * 2009-03-26 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interconnected transistors and electronic device including semiconductor device
KR101020298B1 (ko) 2009-05-28 2011-03-07 주식회사 하이닉스반도체 레벨 시프터 및 반도체 메모리 장치
JP2011009454A (ja) * 2009-06-25 2011-01-13 Renesas Electronics Corp 半導体装置
FR2952227B1 (fr) 2009-10-29 2013-09-06 St Microelectronics Rousset Dispositif de memoire du type electriquement programmable et effacable, a deux cellules par bit
EP2323135A1 (en) * 2009-11-12 2011-05-18 SiTel Semiconductor B.V. Method and apparatus for emulating byte wise programmable functionality into sector wise erasable memory
KR101071190B1 (ko) * 2009-11-27 2011-10-10 주식회사 하이닉스반도체 레벨 쉬프팅 회로 및 이를 이용한 비휘발성 반도체 메모리 장치
IT1397229B1 (it) * 2009-12-30 2013-01-04 St Microelectronics Srl Dispositivo di memoria ftp programmabile e cancellabile a livello di cella
CN107293322B (zh) * 2010-02-07 2021-09-21 芝诺半导体有限公司 含导通浮体晶体管、并具有永久性和非永久性功能的半导体存储元件及操作方法
US8284600B1 (en) 2010-02-08 2012-10-09 National Semiconductor Corporation 5-transistor non-volatile memory cell
KR101676816B1 (ko) * 2010-02-11 2016-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
US9082652B2 (en) 2010-03-23 2015-07-14 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate, and display device
KR101653262B1 (ko) * 2010-04-12 2016-09-02 삼성전자주식회사 멀티-비트 메모리의 프로그램 방법 및 그것을 이용한 데이터 저장 시스템
US8217705B2 (en) 2010-05-06 2012-07-10 Micron Technology, Inc. Voltage switching in a memory device
US8258853B2 (en) * 2010-06-14 2012-09-04 Ememory Technology Inc. Power switch circuit for tracing a higher supply voltage without a voltage drop
US8355282B2 (en) 2010-06-17 2013-01-15 Ememory Technology Inc. Logic-based multiple time programming memory cell
US9042174B2 (en) 2010-06-17 2015-05-26 Ememory Technology Inc. Non-volatile memory cell
US8958245B2 (en) 2010-06-17 2015-02-17 Ememory Technology Inc. Logic-based multiple time programming memory cell compatible with generic CMOS processes
US8279681B2 (en) 2010-06-24 2012-10-02 Semiconductor Components Industries, Llc Method of using a nonvolatile memory cell
US20120014183A1 (en) * 2010-07-16 2012-01-19 Pavel Poplevine 3 transistor (n/p/n) non-volatile memory cell without program disturb
US8044699B1 (en) * 2010-07-19 2011-10-25 Polar Semiconductor, Inc. Differential high voltage level shifter
KR101868332B1 (ko) * 2010-11-25 2018-06-20 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 데이터 저장 장치
US8461899B2 (en) * 2011-01-14 2013-06-11 Stmicroelectronics International N.V. Negative voltage level shifter circuit
JP5685115B2 (ja) * 2011-03-09 2015-03-18 セイコーインスツル株式会社 電源切換回路
US9455021B2 (en) 2011-07-22 2016-09-27 Texas Instruments Incorporated Array power supply-based screening of static random access memory cells for bias temperature instability
KR20130022743A (ko) * 2011-08-26 2013-03-07 에스케이하이닉스 주식회사 고전압 생성회로 및 이를 구비한 반도체 장치
US8999785B2 (en) * 2011-09-27 2015-04-07 Tower Semiconductor Ltd. Flash-to-ROM conversion
CN103078618B (zh) * 2011-10-26 2015-08-12 力旺电子股份有限公司 电压开关电路
JP2013102119A (ja) * 2011-11-07 2013-05-23 Ememory Technology Inc 不揮発性メモリーセル
US8508971B2 (en) 2011-11-08 2013-08-13 Wafertech, Llc Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
US9165661B2 (en) * 2012-02-16 2015-10-20 Cypress Semiconductor Corporation Systems and methods for switching between voltages
US9048137B2 (en) 2012-02-17 2015-06-02 Flashsilicon Incorporation Scalable gate logic non-volatile memory cells and arrays
US8941167B2 (en) 2012-03-08 2015-01-27 Ememory Technology Inc. Erasable programmable single-ploy nonvolatile memory
TWI467744B (zh) * 2012-03-12 2015-01-01 Vanguard Int Semiconduct Corp 單層多晶矽可電抹除可程式唯讀記憶裝置
US8787092B2 (en) 2012-03-13 2014-07-22 Ememory Technology Inc. Programming inhibit method of nonvolatile memory apparatus for reducing leakage current
US9390799B2 (en) * 2012-04-30 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory cell devices and methods, having a storage cell with two sidewall bit cells
TWI469328B (zh) 2012-05-25 2015-01-11 Ememory Technology Inc 具可程式可抹除的單一多晶矽層非揮發性記憶體
TWI498901B (zh) * 2012-06-04 2015-09-01 Ememory Technology Inc 利用程式化禁止方法減少漏電流的非揮發性記憶體裝置
US9729145B2 (en) * 2012-06-12 2017-08-08 Infineon Technologies Ag Circuit and a method for selecting a power supply
KR101334843B1 (ko) * 2012-08-07 2013-12-02 주식회사 동부하이텍 전압 출력 회로 및 이를 이용한 네거티브 전압 선택 출력 장치
KR102038041B1 (ko) 2012-08-31 2019-11-26 에스케이하이닉스 주식회사 전원 선택 회로
JP5988062B2 (ja) * 2012-09-06 2016-09-07 パナソニックＩｐマネジメント株式会社 半導体集積回路
US9130553B2 (en) 2012-10-04 2015-09-08 Nxp B.V. Low/high voltage selector
JP5556873B2 (ja) * 2012-10-19 2014-07-23 株式会社フローディア 不揮発性半導体記憶装置
JP6053474B2 (ja) * 2012-11-27 2016-12-27 株式会社フローディア 不揮発性半導体記憶装置
JP2014116547A (ja) 2012-12-12 2014-06-26 Renesas Electronics Corp 半導体装置
JP6078327B2 (ja) * 2012-12-19 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置
US8963609B2 (en) * 2013-03-01 2015-02-24 Arm Limited Combinatorial circuit and method of operation of such a combinatorial circuit
US9275748B2 (en) * 2013-03-14 2016-03-01 Silicon Storage Technology, Inc. Low leakage, low threshold voltage, split-gate flash cell operation
KR102095856B1 (ko) * 2013-04-15 2020-04-01 삼성전자주식회사 반도체 메모리 장치 및 그것의 바디 바이어스 방법
US9197200B2 (en) 2013-05-16 2015-11-24 Dialog Semiconductor Gmbh Dynamic level shifter circuit
US9362374B2 (en) * 2013-06-27 2016-06-07 Globalfoundries Singapore Pte. Ltd. Simple and cost-free MTP structure
US9520404B2 (en) 2013-07-30 2016-12-13 Synopsys, Inc. Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
CN103456359A (zh) * 2013-09-03 2013-12-18 苏州宽温电子科技有限公司 基于串联晶体管型的改进的差分架构Nor flash存储单元
US9236453B2 (en) * 2013-09-27 2016-01-12 Ememory Technology Inc. Nonvolatile memory structure and fabrication method thereof
KR20150042041A (ko) * 2013-10-10 2015-04-20 에스케이하이닉스 주식회사 전압발생기, 집적회로 및 전압 발생 방법
FR3012673B1 (fr) * 2013-10-31 2017-04-14 St Microelectronics Rousset Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire
KR102072767B1 (ko) * 2013-11-21 2020-02-03 삼성전자주식회사 고전압 스위치 및 그것을 포함하는 불휘발성 메모리 장치
US9159425B2 (en) * 2013-11-25 2015-10-13 Stmicroelectronics International N.V. Non-volatile memory with reduced sub-threshold leakage during program and erase operations
KR102157875B1 (ko) * 2013-12-19 2020-09-22 삼성전자주식회사 불휘발성 메모리 장치 및 그것을 포함한 메모리 시스템
JP6235901B2 (ja) * 2013-12-27 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置
US9331699B2 (en) 2014-01-08 2016-05-03 Micron Technology, Inc. Level shifters, memory systems, and level shifting methods
KR20160132405A (ko) * 2014-03-12 2016-11-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN103943570A (zh) * 2014-03-20 2014-07-23 上海华力微电子有限公司 一种一次性编程存储器中金属硅化物掩膜的制备方法
US9508396B2 (en) * 2014-04-02 2016-11-29 Ememory Technology Inc. Array structure of single-ploy nonvolatile memory
JP5745136B1 (ja) * 2014-05-09 2015-07-08 力晶科技股▲ふん▼有限公司 不揮発性半導体記憶装置とその書き込み方法
FR3021806B1 (fr) * 2014-05-28 2017-09-01 St Microelectronics Sa Procede de programmation d'une cellule memoire non volatile comprenant une grille de transistor de selection partagee
FR3021804B1 (fr) * 2014-05-28 2017-09-01 Stmicroelectronics Rousset Cellule memoire non volatile duale comprenant un transistor d'effacement
JP6286292B2 (ja) 2014-06-20 2018-02-28 株式会社フローディア 不揮発性半導体記憶装置
US20160006348A1 (en) 2014-07-07 2016-01-07 Ememory Technology Inc. Charge pump apparatus
CN104112472B (zh) * 2014-07-22 2017-05-03 中国人民解放军国防科学技术大学 兼容标准cmos工艺的超低功耗差分结构非易失性存储器
CN104361906B (zh) * 2014-10-24 2017-09-19 中国人民解放军国防科学技术大学 基于标准cmos工艺的超低功耗非易失性存储器
US9514820B2 (en) * 2014-11-19 2016-12-06 Stmicroelectronics (Rousset) Sas EEPROM architecture wherein each bit is formed by two serially connected cells
JP6340310B2 (ja) 2014-12-17 2018-06-06 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびウェラブル装置
TWI546903B (zh) * 2015-01-15 2016-08-21 聯笙電子股份有限公司 非揮發性記憶體單元
JP6457829B2 (ja) 2015-02-05 2019-01-23 ルネサスエレクトロニクス株式会社 半導体装置
CN104900266B (zh) * 2015-06-10 2018-10-26 上海华虹宏力半导体制造有限公司 Eeprom存储单元门极控制信号产生电路
US9799395B2 (en) 2015-11-30 2017-10-24 Texas Instruments Incorporated Sense amplifier in low power and high performance SRAM
US9847133B2 (en) 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101650972A (zh) * 2009-06-12 2010-02-17 东信和平智能卡股份有限公司 智能卡的非易失性存储器数据更新方法
CN103534759A (zh) * 2011-06-24 2014-01-22 国际商业机器公司 用于在接收到包括混合的读取和写入命令的一系列命令时执行最优写入的线性记录设备及其执行方法和程序
CN104517644A (zh) * 2013-10-08 2015-04-15 力旺电子股份有限公司 非易失性存储器装置及其数据验证方法
CN105321570A (zh) * 2014-07-08 2016-02-10 力旺电子股份有限公司 非易失性存储器及其列解码器

Also Published As

Publication number Publication date
US20170207228A1 (en) 2017-07-20
JP2017130247A (ja) 2017-07-27
EP3197051B1 (en) 2020-01-15
TWI614763B (zh) 2018-02-11
TW201828302A (zh) 2018-08-01
TWI613659B (zh) 2018-02-01
TW201824520A (zh) 2018-07-01
US10038003B2 (en) 2018-07-31
JP6392379B2 (ja) 2018-09-19
TW201737256A (zh) 2017-10-16
US20170206970A1 (en) 2017-07-20
CN107017023A (zh) 2017-08-04
TW201727632A (zh) 2017-08-01
CN108154898B (zh) 2021-02-02
US20180190357A1 (en) 2018-07-05
CN108320772A (zh) 2018-07-24
EP3196884A1 (en) 2017-07-26
CN106981492B (zh) 2020-10-20
CN108320772B (zh) 2020-07-10
TWI618072B (zh) 2018-03-11
US20180261294A1 (en) 2018-09-13
JP2018101767A (ja) 2018-06-28
EP3196885A1 (en) 2017-07-26
TWI641115B (zh) 2018-11-11
US9792993B2 (en) 2017-10-17
CN106981304A (zh) 2017-07-25
US9653173B1 (en) 2017-05-16
US9941011B2 (en) 2018-04-10
EP3196886A1 (en) 2017-07-26
CN106981304B (zh) 2020-02-07
EP3196884B1 (en) 2021-08-04
US9520196B1 (en) 2016-12-13
CN106981311A (zh) 2017-07-25
CN106981299A (zh) 2017-07-25
TW201727649A (zh) 2017-08-01
TWI613654B (zh) 2018-02-01
US20170206969A1 (en) 2017-07-20
US20170206941A1 (en) 2017-07-20
US10121550B2 (en) 2018-11-06
US10262746B2 (en) 2019-04-16
EP3196883A1 (en) 2017-07-26
US9812212B2 (en) 2017-11-07
US20170206976A1 (en) 2017-07-20
CN108154898A (zh) 2018-06-12
TWI630615B (zh) 2018-07-21
EP3410440A1 (en) 2018-12-05
EP3197051A1 (en) 2017-07-26
CN108206186B (zh) 2020-10-13
TW201740374A (zh) 2017-11-16
EP3410440B1 (en) 2020-05-13
CN107017023B (zh) 2020-05-05
TW201801084A (zh) 2018-01-01
TWI646665B (zh) 2019-01-01
US10096368B2 (en) 2018-10-09
JP6285001B2 (ja) 2018-02-28
US9786340B2 (en) 2017-10-10
US20170206968A1 (en) 2017-07-20
CN106981299B (zh) 2019-10-18
US20170206975A1 (en) 2017-07-20
TW201822212A (zh) 2018-06-16
CN106981311B (zh) 2019-08-30
US20170207230A1 (en) 2017-07-20
US9847133B2 (en) 2017-12-19
CN108206186A (zh) 2018-06-26
JP6566975B2 (ja) 2019-08-28
TWI578322B (zh) 2017-04-11
US9805776B2 (en) 2017-10-31
TW201830665A (zh) 2018-08-16
JP2017130646A (ja) 2017-07-27
JP2017139045A (ja) 2017-08-10
US20170206945A1 (en) 2017-07-20
EP3196885B1 (en) 2019-03-27
EP3196883B1 (en) 2019-09-04
TW201727838A (zh) 2017-08-01
US10255980B2 (en) 2019-04-09
TW201727651A (zh) 2017-08-01
TWI621123B (zh) 2018-04-11
EP3196886B1 (en) 2021-03-31
JP6122531B1 (ja) 2017-04-26
CN106981307A (zh) 2017-07-25
CN106981492A (zh) 2017-07-25
CN106981309B (zh) 2020-02-14
CN106981309A (zh) 2017-07-25
TWI587455B (zh) 2017-06-11
TWI613672B (zh) 2018-02-01

Similar Documents

Publication Publication Date Title
CN106981307B (zh) 存储器装置、其外围电路及其单字节数据写入方法
CN101819813B (zh) 进行高速缓存读取的方法
US7353326B2 (en) Flash memory device supporting cache read operation
US8199587B2 (en) Memory devices and their operation with different sets of logical erase blocks
JP4287158B2 (ja) Ｎａｎｄフラッシュメモリ装置
JP4122185B2 (ja) 不揮発性メモリ装置、そのプログラム方法及びパス／フェイルの検査方法
US7663924B2 (en) Non-volatile memory devices having multi-page programming capabilities and related methods of operating such devices
KR100551646B1 (ko) 페이지 복사 기능을 갖는 반도체 기억 장치
US7180784B2 (en) Page buffer and verify method of flash memory device using the same
JP2004192780A (ja) デュアルレジスタ構造のページバッファを有するメモリ装置
US9019780B1 (en) Non-volatile memory apparatus and data verification method thereof
JPH11176178A (ja) 不揮発性半導体記憶装置およびそれを用いたｉｃメモリカード
JP2001210082A (ja) 不揮発性半導体記憶装置およびデータ記憶システム
CN107578789B (zh) 非易失性半导体存储装置
TW200811870A (en) Methods for programming and reading NAND flash memory device and page buffer performing the same
US7102927B2 (en) Memory devices and programming methods that simultaneously store erase status indications for memory blocks
JP2004095001A (ja) 不揮発性半導体記憶装置、不揮発性半導体記憶装置組込システムおよび不良ブロック検出方法
JPH0256758B2 (zh)
JPH05282882A (ja) 不揮発性半導体メモリ
KR20140144989A (ko) 메모리 시스템, 반도체 메모리 장치 및 그것들의 동작 방법
JP4530562B2 (ja) 不揮発性メモリ
KR20060031989A (ko) 낸드 플래시 메모리 소자의 페이지 버퍼
JP3749846B2 (ja) 不揮発性メモリ
KR20220112169A (ko) 반도체 장치 및 연속 독출 방법
JP2008171565A (ja) 不揮発性半導体記憶装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant