FR3012673B1 - Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire - Google Patents

Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire

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Publication number
FR3012673B1
FR3012673B1 FR1360743A FR1360743A FR3012673B1 FR 3012673 B1 FR3012673 B1 FR 3012673B1 FR 1360743 A FR1360743 A FR 1360743A FR 1360743 A FR1360743 A FR 1360743A FR 3012673 B1 FR3012673 B1 FR 3012673B1
Authority
FR
France
Prior art keywords
memory
programming
memory cells
gate
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1360743A
Other languages
English (en)
Other versions
FR3012673A1 (fr
Inventor
Rosa Francesco La
Stephan Niel
Arnaud Regnier
Julien Delalleau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1360743A priority Critical patent/FR3012673B1/fr
Priority to US14/528,780 priority patent/US9224482B2/en
Priority to CN201410597510.1A priority patent/CN104599714B/zh
Priority to CN201420638857.1U priority patent/CN204332378U/zh
Publication of FR3012673A1 publication Critical patent/FR3012673A1/fr
Application granted granted Critical
Publication of FR3012673B1 publication Critical patent/FR3012673B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Abstract

L'invention concerne une mémoire comprenant au moins une ligne de mot (WLi) comprenant une rangée de cellules mémoire à grille divisée (C ) comprenant chacune une section de transistor de sélection comportant une grille de sélection (SG) et une section de transistor à grille flottante comportant une grille flottante (FG) et une grille de contrôle (CG). Selon l'invention, la mémoire comprend un plan de source (SP) commun aux cellules mémoire de la ligne de mot, pour collecter des courants de programmation (Ip) traversant des cellules mémoire lors de leur programmation, et les sections de transistor de sélection des cellules mémoire sont connectées au plan de source (SP). Un circuit de contrôle de courant de programmation (PCCT) est configuré pour contrôler le courant de programmation (Ip) traversant les cellules mémoire en agissant sur une tension de sélection (VS) appliquée à une ligne de sélection (SL).
FR1360743A 2013-10-31 2013-10-31 Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire Expired - Fee Related FR3012673B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1360743A FR3012673B1 (fr) 2013-10-31 2013-10-31 Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire
US14/528,780 US9224482B2 (en) 2013-10-31 2014-10-30 Hot-carrier injection programmable memory and method of programming such a memory
CN201410597510.1A CN104599714B (zh) 2013-10-31 2014-10-30 热载流子注入可编程存储器和编程该存储器的方法
CN201420638857.1U CN204332378U (zh) 2013-10-31 2014-10-30 集成电路存储器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1360743A FR3012673B1 (fr) 2013-10-31 2013-10-31 Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire

Publications (2)

Publication Number Publication Date
FR3012673A1 FR3012673A1 (fr) 2015-05-01
FR3012673B1 true FR3012673B1 (fr) 2017-04-14

Family

ID=49713386

Family Applications (1)

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FR1360743A Expired - Fee Related FR3012673B1 (fr) 2013-10-31 2013-10-31 Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire

Country Status (3)

Country Link
US (1) US9224482B2 (fr)
CN (2) CN104599714B (fr)
FR (1) FR3012673B1 (fr)

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FR3012673B1 (fr) * 2013-10-31 2017-04-14 St Microelectronics Rousset Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire
FR3012672B1 (fr) 2013-10-31 2017-04-14 Stmicroelectronics Rousset Cellule memoire comprenant des grilles de controle horizontale et verticale non auto-alignees
FR3017746B1 (fr) 2014-02-18 2016-05-27 Stmicroelectronics Rousset Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne
JP6503077B2 (ja) * 2015-01-22 2019-04-17 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 高密度スプリットゲート型メモリセル
FR3036221B1 (fr) * 2015-05-11 2017-04-28 Stmicroelectronics Rousset Structure d'interconnexion de cellules memoire jumelles
US9979649B2 (en) * 2015-12-04 2018-05-22 Wisconsin Alumin Research Foundation High density content addressable memory
US9847133B2 (en) * 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation
CN107305892B (zh) * 2016-04-20 2020-10-02 硅存储技术公司 使用两个多晶硅沉积步骤来形成三栅极非易失性闪存单元对的方法
JP2018005961A (ja) * 2016-07-01 2018-01-11 東芝メモリ株式会社 記憶装置
FR3054920B1 (fr) 2016-08-05 2018-10-26 Stmicroelectronics (Rousset) Sas Dispositif compact de memoire non volatile
US10340010B2 (en) 2016-08-16 2019-07-02 Silicon Storage Technology, Inc. Method and apparatus for configuring array columns and rows for accessing flash memory cells
US9953727B1 (en) 2017-02-10 2018-04-24 Globalfoundries Inc. Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing
CN106847889B (zh) * 2017-02-14 2019-09-17 上海华虹宏力半导体制造有限公司 一种基区电压可调的垂直npn双极型晶体管及其制造方法
CN108806751B (zh) * 2017-04-26 2021-04-09 中芯国际集成电路制造(上海)有限公司 多次可程式闪存单元阵列及其操作方法、存储器件
US10796763B2 (en) * 2018-01-26 2020-10-06 Stmicroelectronics (Rousset) Sas Method for programming a split-gate memory cell and corresponding memory device
CN108648777B (zh) * 2018-05-10 2020-08-11 上海华虹宏力半导体制造有限公司 双分离栅闪存的编程时序电路及方法
JP2019200828A (ja) * 2018-05-16 2019-11-21 東芝メモリ株式会社 半導体記憶装置
US10872666B2 (en) * 2019-02-22 2020-12-22 Micron Technology, Inc. Source line management for memory cells with floating gates
US11257550B2 (en) * 2020-06-12 2022-02-22 Taiwan Semiconductor Manufacturing Company Limited Bias control for memory cells with multiple gate electrodes

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US6496417B1 (en) * 1999-06-08 2002-12-17 Macronix International Co., Ltd. Method and integrated circuit for bit line soft programming (BLISP)
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Also Published As

Publication number Publication date
CN204332378U (zh) 2015-05-13
CN104599714A (zh) 2015-05-06
US20150117109A1 (en) 2015-04-30
US9224482B2 (en) 2015-12-29
CN104599714B (zh) 2020-01-10
FR3012673A1 (fr) 2015-05-01

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