TWI646665B - 具有抹除元件的單層多晶矽非揮發性記憶胞結構 - Google Patents

具有抹除元件的單層多晶矽非揮發性記憶胞結構 Download PDF

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TWI646665B
TWI646665B TW106104042A TW106104042A TWI646665B TW I646665 B TWI646665 B TW I646665B TW 106104042 A TW106104042 A TW 106104042A TW 106104042 A TW106104042 A TW 106104042A TW I646665 B TWI646665 B TW I646665B
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oxide
region
doped region
floating gate
memory cell
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TW201824520A (zh
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孫文堂
陳緯仁
陳英哲
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力旺電子股份有限公司
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    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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Abstract

一種單層多晶矽非揮發性記憶胞結構，包含一矽覆絕緣基板，包含一矽基底、一埋入氧化層及一半導體層；一第一氧化物定義區域及一第二氧化物定義區域，位於該半導體層；一絕緣區域，位於該半導體層，隔離該第一氧化物定義區域與該第二氧化物定義區域；一PMOS選擇電晶體，設於該第一氧化物定義區域；一PMOS浮置閘極電晶體，設於該第一氧化物定義區域，並串接該PMOS選擇電晶體，該PMOS浮置閘極電晶體包含一浮置閘極，位於該第一氧化物定義區域上；以及一浮置閘極延伸，由該浮置閘極連續延伸至該第二氧化物定義區域，並與該第二氧化物定義區域電容耦合。

Description

具有抹除元件的單層多晶矽非揮發性記憶胞結構
本發明係有關於非揮發性記憶體(nonvolatile memory)技術領域，特別是有關於一種具有抹除元件(erase device)且設於矽覆絕緣(SOI)基板上的單層多晶矽非揮發性記憶胞結構。
單層多晶矽非揮發性記憶體乃週知技藝。第1圖例示一單層多晶矽非揮發性記憶胞的佈局示意圖。如第1圖所示，單層多晶矽非揮發性記憶胞10包含兩個串接在一起的PMOS電晶體12及14。PMOS電晶體12包含一選擇閘極22、一P+源極摻雜區32，及一P+汲極/源極摻雜區34。PMOS電晶體14包含一浮置閘極24、P+汲極/源極摻雜區34，及一P+汲極摻雜區36。串接在一起的PMOS電晶體12及14共用P+汲極/源極摻雜區34。上述單層多晶矽非揮發性記憶胞10的優點是可以完全與CMOS邏輯製程相容。
操作時，PMOS電晶體12的選擇閘極22係耦合至一選擇閘極電壓VSG，P+源極摻雜區32係經由一源極線接觸件耦合至一源極線電壓VSL，P+汲極/源極摻雜區34及PMOS電晶體14的浮置閘極24為電性上浮置，而PMOS電晶體14的P+汲極摻雜區36則是經由一位元線接觸件耦合至位元線電壓VBL。在寫入模式下，電子被注入並儲存在浮置閘極24中。上述記憶體結構可以在低電壓條件下操作。
由於單層多晶矽非揮發性記憶體能與CMOS邏輯製程相容，因此被廣泛應用在許多領域，例如嵌入式記憶體、混合訊號電路或微控制器(如系統單 晶片)等等的嵌入式非揮發性記憶體。
目前的趨勢是將非揮發性記憶體越做越小。隨著非揮發性記憶體越做越小，可期待記憶體的單位元成本(cost per bit)也會降低。然而，過去的非揮發性記憶體的微縮能力受限於離子佈植輸出/輸入離子井(I/O ion well)的規則，其中植入基底記憶陣列區中的輸出/輸入離子井的接面深度深於淺溝絕緣結構(STI)的深度。
本發明的主要目的在提供一改良的單層多晶矽非揮發性記憶胞結構，特徵是具有一抹除元件且形成在一矽覆絕緣基板上，以解決先前技藝的不足與缺點。
本發明的主要目的在提供一改良的單層多晶矽可多次寫入(MTP)非揮發性記憶胞，其具有更小的記憶胞尺寸。
根據本發明一實施例，提供一種單層多晶矽非揮發性記憶胞結構，包含一矽覆絕緣(SOI)基板，包含一矽基底、一埋入氧化層及一半導體層；一第一氧化物定義區域及一第二氧化物定義區域，位於該半導體層；一絕緣區域，位於該半導體層，該絕緣區域隔離該第一氧化物定義區域與該第二氧化物定義區域；一PMOS選擇電晶體，設於該第一氧化物定義區域；一PMOS浮置閘極電晶體，設於該第一氧化物定義區域，並串接該PMOS選擇電晶體，其中該PMOS浮置閘極電晶體包含一浮置閘極，位於該第一氧化物定義區域上；以及一浮置閘極延伸，由該浮置閘極連續地延伸至該第二氧化物定義區域，並與該第二氧化物定義區域電容耦合。
其中該PMOS選擇電晶體包含一選擇閘極、一選擇閘極氧化層，介於該選擇閘極與該半導體層之間、一P+源極摻雜區，及一P+汲極/源極摻雜區，其中 該P+源極摻雜區耦合至一源極線。
其中該PMOS浮置閘極電晶體包含該浮置閘極、一浮置閘極氧化層，介於該浮置閘極與該半導體層之間、該P+汲極/源極摻雜區，及一P+汲極摻雜區，其中該PMOS選擇電晶體與該PMOS浮置閘極電晶體共用該P+汲極/源極摻雜區。
根據本發明一實施例，該單層多晶矽非揮發性記憶胞結構另包含一離子井，例如N型井或P型井，位於該半導體層，其中該離子井完全重疊該第二氧化物定義區域，以及一重摻雜區域，例如N+摻雜區或P+摻雜區，位於該第二氧化物定義區域內的該離子井中。該第二氧化物定義區域、該重摻雜區域、該浮置閘極氧化層，及與該重摻雜區域電容耦合的該浮置閘極延伸，共同構成一抹除元件。
根據本發明一實施例，該單層多晶矽非揮發性記憶胞結構另包含一電荷收集區域，與該第一氧化物定義區域接壤，其中電荷收集區域在該單層多晶矽非揮發性記憶體操作時收集累積在該半導體層中的多餘電子及電洞。其中該電荷收集區域包含一第三氧化物定義區域、一N+摻雜區位於該第三氧化物定義區域內，及一橋接區域，連接該N+摻雜區與該浮置閘極正下方的該半導體層。
根據本發明另一實施例，該單層多晶矽非揮發性記憶胞結構另包含一N+摻雜區，其與該P+源極摻雜區接壤，該N+摻雜區與該P+源極摻雜區位於該選擇閘極同一側，如此構成一毗接接觸區。
1、2、3、4、5、6‧‧‧單層多晶矽非揮發性記憶體
10‧‧‧單層多晶矽非揮發性記憶胞
12‧‧‧PMOS電晶體
14‧‧‧PMOS電晶體
22‧‧‧選擇閘極
24‧‧‧浮置閘極
32‧‧‧P+源極摻雜區
34‧‧‧P+汲極/源極摻雜區
36‧‧‧P+汲極摻雜區
50‧‧‧電荷收集區域
60‧‧‧毗接接觸區
102‧‧‧PMOS選擇電晶體
104‧‧‧PMOS浮置閘極電晶體
110‧‧‧選擇閘極
112‧‧‧選擇閘極氧化層
120‧‧‧浮置閘極
120a、120b‧‧‧延伸部(浮置閘極延伸)
122‧‧‧浮置閘極氧化層
132‧‧‧P+源極摻雜區
134‧‧‧P+汲極/源極摻雜區
136‧‧‧P+汲極摻雜區
138‧‧‧重摻雜區域
162‧‧‧N+摻雜區
200‧‧‧矽覆絕緣(SOI)基板
210‧‧‧矽基板
220‧‧‧埋入氧化層
230‧‧‧半導體層
250、450‧‧‧抹除元件
300‧‧‧淺溝絕緣(STI)區域
310‧‧‧N型井
320‧‧‧離子井
500‧‧‧N+摻雜區
510‧‧‧字元線接觸點
520‧‧‧橋接區域
VSG‧‧‧選擇閘極電壓
VSL‧‧‧源極線電壓
VBL‧‧‧位元線電壓
VNW‧‧‧N型井電壓
C1~C4‧‧‧記憶胞單元
OD1、OD2、OD3、OD4‧‧‧氧化物定義區域
WL1、WL2‧‧‧字元線
SL‧‧‧源極線
BL‧‧‧位元線
EL‧‧‧抹除線
第1圖例示一單層多晶矽非揮發性記憶胞的佈局示意圖。
第2圖為依據本發明一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。
第3圖為沿著第2圖中的切線I-I’所示的記憶胞結構剖面示意圖。
第4圖為沿著第2圖中的切線II-II’所示的剖面示意圖。
第5圖至第7圖為依據本發明其他實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的不同實施態樣。
第8圖例示適用於第2圖至第7圖中的各記憶胞的寫入(PGM)、讀取(READ)及抹除(ERS)的操作條件。
第9圖為依據本發明另一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。
第10圖為沿著第9圖中的切線III-III’所示的剖面示意圖。
第11圖為沿著第9圖中的切線IV-IV’所示的剖面示意圖。
第12圖為依據本發明又另一實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的實施態樣。
第13圖例示適用於第9圖及第12圖中的各記憶胞的寫入(PGM)、讀取(READ)及抹除(ERS)的操作條件。
藉由接下來的敘述及所提供的眾多特定細節，可充分了解本發明。然而對於此領域中的技術人員，在沒有這些特定細節下依然可實行本發明。再者，一些此領域中公知的系統配置和製程步驟並未在此詳述，因為這些應是此領域中的技術人員所熟知的。
同樣地，實施例的圖式為示意圖，為了清楚呈現而放大一些尺寸，並未照實際比例繪製。在此公開和描述的多個實施例中若具有共通或類似的某些特徵時，為了方便圖示及描述，類似的特徵通常會以相同的標號表示。
本發明係關於一種單層多晶矽非揮發性記憶體結構，具有一抹除元 件，可以作為可多次寫入(MTP)記憶體。本發明單層多晶矽非揮發性記憶體結構係製作在一矽覆絕緣(silicon-on-insulator或semiconductor-on-insulator，簡稱SOI)基板上。SOI基板包含一矽基底、一埋入氧化層及一矽(或半導體)主動層，設於埋入氧化層上。本發明單層多晶矽非揮發性記憶體結構係製作在所述矽(或半導體)主動層中。SOI基板可以是商業上可獲得的SOI產品，可以利用公知的SIMOX方法製作而成，但不限於此。本發明單層多晶矽非揮發性記憶體結構可以是一全空乏(fully depleted)SOI元件或部分空乏(partially depleted)SOI元件。
請參閱第2圖至第4圖。第2圖為依據本發明一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。第3圖為沿著第2圖中的切線I-I所示的記憶胞結構剖面示意圖。第4圖為沿著第2圖中的切線II-II’所示的剖面示意圖。
如第2圖所示，本發明單層多晶矽非揮發性記憶體1包含複數個記憶胞，包括但不限於，例如，四個記憶胞單元C1~C4。應理解的是，第2圖中所示的記憶胞佈局僅為例示說明。在第2圖中，舉例來說，僅繪示三個氧化物定義(oxide define，OD)區域：OD1、OD2、OD3。根據本發明實施例，記憶胞C1及C2係製作於氧化物定義區域OD1上，記憶胞C3及C4係製作於氧化物定義區域OD2上。
根據本發明實施例，氧化物定義區域OD1、OD2可以是沿著參考y軸延伸的條狀區域。氧化物定義區域OD1、OD2、OD3藉由淺溝絕緣(shallow trench isolation，STI)區域300彼此隔離絕緣。在第2圖中，僅繪示兩條沿著參考x軸延伸且與氧化物定義區域OD1、OD2交叉的字元線WL1及WL2。在氧化物定義區域OD3上可以形成一抹除元件250。根據本發明實施例，抹除元件250可以被圖中四個記憶胞單元C1~C4共用。
根據本發明實施例，氧化物定義區域OD3係介於氧化物定義區域OD1與氧化物定義區域OD2之間。氧化物定義區域OD3與字元線WL1及WL2有一段距 離，故從第2圖的佈局示意圖中可看出，氧化物定義區域OD3不會與字元線WL1及WL2重疊。
根據本發明實施例，記憶胞單元C1與記憶胞單元C2共用同一P+汲極/源極摻雜區及相同的位元線接觸點。根據本發明實施例，記憶胞單元C3與記憶胞單元C4共用同一P+汲極/源極摻雜區及相同的位元線接觸點。
如第2圖至第4圖所示，四個記憶胞單元C1~C4的各記憶胞單元(以記憶胞單元C1為例)均包含一PMOS選擇電晶體102及一串接PMOS選擇電晶體102的PMOS浮置閘極電晶體104。PMOS選擇電晶體102及PMOS浮置閘極電晶體104一起形成在氧化物定義區域OD1上，其中氧化物定義區域OD1係定義於一SOI基板200的一半導體層230中。記憶胞單元C2的記憶胞結構係鏡面對稱於記憶胞單元C1。記憶胞單元C3及C4的記憶胞結構則分別鏡面對稱於記憶胞單元C1及C2。
半導體層230可以是一單晶矽層，但不限於此。SOI基板200可以進一步包含一埋入氧化層220及一矽基板210。半導體層230係藉由埋入氧化層220與矽基板210電性隔離。STI區域300與下方的埋入氧化層220接壤。矽基板210可以是一P型矽基板，但不限於此。在半導體層230中，可以利用離子佈植製程形成一與氧化物定義區域OD1完全重疊的N型井310。在某些實施例中，N型井310可以被省略，如此一來通道可以形成在本徵矽(intrinsic silicon)中。
PMOS選擇電晶體102包含一選擇閘極110、一選擇閘極氧化層112，介於選擇閘極110與半導體層230之間、一P+源極摻雜區132，及一P+汲極/源極摻雜區134。PMOS浮置閘極電晶體104包含一浮置閘極120、一浮置閘極氧化層122，介於浮置閘極120與半導體層230之間、P+汲極/源極摻雜區134，及一P+汲極摻雜區136。PMOS選擇電晶體102與PMOS浮置閘極電晶體104共用P+汲極/源極摻雜區134。為簡化說明，圖中選擇閘極110與浮置閘極120側壁上的側壁子並未繪示出來。
從第2圖及第4圖可看出，浮置閘極120包括一延伸部(或稱之為浮置閘極延伸)120a，其沿著參考x軸方向連續地延伸出去，並與氧化物定義區域OD3重疊。延伸部120a可以具有一寬度，其小於浮置閘極120的寬度。根據本發明實施例，延伸部120a與氧化物定義區域OD3的重疊面積小於浮置閘極120與氧化物定義區域OD1的重疊面積。
在氧化物定義區域OD3中，形成有一重摻雜區域138。重摻雜區域138可以是一N+摻雜區或一P+摻雜區。一離子井320，例如一N型井或一P型井，可以形成在半導體層230中，並與氧化物定義區域OD3完全重疊。或者，重摻雜區域138可以直接形成在本徵矽中，此時，無需在氧化物定義區域OD3中形成離子井。應理解的是，圖中的浮置閘極的形狀僅為例說明。
根據本發明實施例，氧化物定義區域OD3、重摻雜區域138、浮置閘極氧化層122及電容耦合於重摻雜區域138與氧化物定義區域OD3的延伸部120a共同構成抹除元件250。
操作時，PMOS選擇電晶體102的選擇閘極110經由一字元線接觸點510耦合至一選擇閘極電壓VSG，PMOS選擇電晶體102的P+源極摻雜區132經由一源極線(SL)接觸點耦合至一源極線電壓VSL，P+汲極/源極摻雜區134及浮置閘極120為電性浮置，而PMOS浮置閘極電晶體104的P+汲極摻雜區136係經由一位元線(BL)接觸點耦合至一位元線電壓VBL。重摻雜區域138則是經由一抹除線(EL)接觸點耦合至一抹除線電壓VEL。
在寫入模式下，電子透過通道熱電子(channel hot electron，CHE)注入機制被選擇性的注入浮置閘極120。在抹除模式下(區段或全晶片抹除)，電子則是透過福勒諾漢穿隧(Fowler-Nordheim(FN)tunneling)機制從浮置閘極120抹除。
第5圖至第7圖為依據本發明其他實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的不同實施態樣。
如第5圖所示，第5圖中的單層多晶矽非揮發性記憶體2與第2圖中的單層多晶矽非揮發性記憶體1差異在於第5圖中的單層多晶矽非揮發性記憶體2另包含一與氧化物定義區域OD1接壤的電荷收集區域50。電荷收集區域50能夠在單層多晶矽非揮發性記憶體操作時收集累積在半導體層230中的多餘電子及電洞。
根據本發明實施例，電荷收集區域50包含一氧化物定義區域OD4、一N+摻雜區500位於氧化物定義區域OD4內，及一橋接區域520連接N+摻雜區500與浮置閘極120正下方的半導體層230。N型井310可以與橋接區域520及氧化物定義區域OD4重疊。在N+摻雜區500內可提供一N型井接觸點，使電荷收集區域50可以耦合至一N型井電壓VNW。在第5圖中，記憶胞C1及記憶胞C2共用一電荷收集區域，而記憶胞C3及記憶胞C4共用一電荷收集區域。
如第6圖所示，第6圖中的單層多晶矽非揮發性記憶體3與第2圖中的單層多晶矽非揮發性記憶體1差異在於第6圖中的單層多晶矽非揮發性記憶體3另包含一N+摻雜區162，其與P+源極摻雜區132接壤，N+摻雜區162與P+源極摻雜區132位於選擇閘極110同一側，如此構成一毗接接觸區60。N+摻雜區162與P+源極摻雜區132皆耦合至一源極線電壓VSL。
如第7圖所示，第7圖中的單層多晶矽非揮發性記憶體4與第2圖中的單層多晶矽非揮發性記憶體1差異在於第7圖中的單層多晶矽非揮發性記憶體4包含一與氧化物定義區域OD1接壤的電荷收集區域50。電荷收集區域50能夠在記憶體操作時收集累積在半導體層230中的多餘電子及電洞。電荷收集區域50的細節同第5圖所示。第7圖中的單層多晶矽非揮發性記憶體4另包含一N+摻雜區162，其與P+源極摻雜區132接壤，N+摻雜區162與P+源極摻雜區132位於選擇閘極110同一側，如此構成一毗接接觸區60。N+摻雜區162與P+源極摻雜區132皆耦合至一源極線電壓VSL。
第8圖例示適用於第2圖至第7圖中的各記憶胞的寫入(PGM)、讀取 (READ)及抹除(ERS)的操作條件。如第8圖所示，在寫入(PGM)操作時，源極線(SL)耦合至一電壓VPP，例如，電壓VPP可以介於5~9V。位元線(BL)接地(VBL=0V)。另提供選擇閘極(SG)110一介於0~1/2VPP的電壓，提供抹除線(EL)一介於0~VPP的電壓。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500偶合至一VPP電壓。第8圖中同時例示對記憶胞進行寫入-抑制(PGM-inhibit)操作或寫入-未選擇(PGM-unselect)操作的電壓條件。
在抹除操作時，源極線(SL)接地(VSL=0V)，位元線(BL)接地(VBL=0V)，選擇閘極(SG)110接地(VSG=0V)。另提供抹除線(EL)一VEE的電壓。舉例來說，VEE可以介於8~18V。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500接地(VNW=0V)。
另一抹除操作方式是，源極線(SL)耦合至一VBB電壓。舉例來說，VBB可以介於-4~-8V。位元線(BL)耦合至一VBB電壓。選擇閘極(SG)110耦合至一VBB電壓。另提供抹除線(EL)一VEE的電壓。舉例來說，VEE可以介於8~18V。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500耦合至一VBB電壓。
在讀取操作時，源極線(SL)耦合至一VREAD電壓。舉例來說，VREAD可以介於2~2.8V。位元線(BL)耦合至0.4V電壓(VBL=0.4V)。選擇閘極(SG)110接地(VSG=0V)。抹除線(EL)接地(VEL=0V)。對於具有電荷收集區域50的記憶胞，如第5圖及第7圖所示，N+摻雜區500耦合至VREAD電壓。第8圖中同時例示對記憶胞進行讀取-未選擇(READ-unselect)操作的電壓條件。
請參閱第9圖至第11圖。第9圖為依據本發明另一實施例所繪示的單層多晶矽非揮發性記憶體的部分佈局示意圖。第10圖為沿著第9圖中的切線III-III’所示的剖面示意圖。第11圖為沿著第9圖中的切線IV-IV’所示的剖面示意圖。
如第9圖所示，本發明單層多晶矽非揮發性記憶體5包含複數個記憶 胞，包括但不限於，例如，四個記憶胞單元C1~C4。應理解的是，第9圖中所示的記憶胞佈局僅為例示說明。在第9圖中，舉例來說，僅繪示三個氧化物定義區域：OD1、OD2、OD3。根據本發明實施例，記憶胞C1及C2係製作於氧化物定義區域OD1上，記憶胞C3及C4係製作於氧化物定義區域OD2上。
根據本發明實施例，氧化物定義區域OD1、OD2可以是沿著參考y軸延伸的條狀區域。氧化物定義區域OD1、OD2、OD3藉由淺溝絕緣(STI)區域300彼此隔離絕緣。在第9圖中，僅繪示兩條沿著參考x軸延伸且與氧化物定義區域OD1、OD2交叉的字元線WL1及WL2。在氧化物定義區域OD3上可以形成一抹除元件450。根據本發明實施例，抹除元件450可以被圖中四個記憶胞單元C1~C4共用。
根據本發明實施例，氧化物定義區域OD3係介於氧化物定義區域OD1與氧化物定義區域OD2之間。氧化物定義區域OD3與字元線WL1及WL2有一段距離，故從第9圖的佈局示意圖中可看出，氧化物定義區域OD3不會與字元線WL1及WL2重疊。
根據本發明實施例，記憶胞單元C1與記憶胞單元C2共用同一P+汲極/源極摻雜區及相同的位元線接觸點。根據本發明實施例，記憶胞單元C3與記憶胞單元C4共用同一P+汲極/源極摻雜區及相同的位元線接觸點
如第9圖至第11圖所示，四個記憶胞單元C1~C4的各記憶胞單元(以記憶胞單元C1為例)均包含一PMOS選擇電晶體102及一串接PMOS選擇電晶體102的PMOS浮置閘極電晶體104。PMOS選擇電晶體102及PMOS浮置閘極電晶體104一起形成在氧化物定義區域OD1上，其中氧化物定義區域OD1係定義於一SOI基板200的一半導體層230中。記憶胞單元C2的記憶胞結構係鏡面對稱於記憶胞單元C1。記憶胞單元C3及C4的記憶胞結構則分別鏡面對稱於記憶胞單元C1及C2。
半導體層230可以是一單晶矽層，但不限於此。SOI基板200可以進一步包含一埋入氧化層220及一矽基板210。半導體層230係藉由埋入氧化層220與矽 基板210電性隔離。STI區域300與下方的埋入氧化層220接壤。矽基板210可以是一P型矽基板，但不限於此。在半導體層230中，可以利用離子佈植製程形成一與氧化物定義區域OD1完全重疊的N型井310。在某些實施例中，N型井310可以被省略，如此一來通道可以形成在本徵矽中。
PMOS選擇電晶體102包含一選擇閘極110、一選擇閘極氧化層112，介於選擇閘極110與半導體層230之間、一P+源極摻雜區132，及一P+汲極/源極摻雜區134。PMOS浮置閘極電晶體104包含一浮置閘極120、一浮置閘極氧化層122，介於浮置閘極120與半導體層230之間、P+汲極/源極摻雜區134，及一P+汲極摻雜區136。PMOS選擇電晶體102與PMOS浮置閘極電晶體104共用P+汲極/源極摻雜區134。為簡化說明，圖中選擇閘極110與浮置閘極120側壁上的側壁子並未繪示出來。
從第9圖及第11圖可看出，浮置閘極120包括一延伸部120b，其沿著參考x軸方向延伸出去，與氧化物定義區域OD3重疊。延伸部120b可以具有一寬度，其大於浮置閘極120的寬度。根據本發明實施例，延伸部120b與氧化物定義區域OD3的重疊面積大於浮置閘極120與氧化物定義區域OD1的重疊面積。
在氧化物定義區域OD3中，形成有一重摻雜區域138。重摻雜區域138可以是一N+摻雜區或一P+摻雜區。一離子井320，例如一N型井或一P型井，可以形成在氧化物定義區域OD3。根據本發明實施例，重摻雜區域138為一N+摻雜區，離子井320為一N型井。根據本發明另一實施例，重摻雜區域138為一P+摻雜區，離子井320為一P型井。應理解的是，圖中的浮置閘極的形狀僅供例示參考。
根據本發明實施例，氧化物定義區域OD3、重摻雜區域138、浮置閘極氧化層122及電容耦合於重摻雜區域138與氧化物定義區域OD3的延伸部120b共同構成抹除元件450。氧化物定義區域OD3及重摻雜區域138可作為一控制閘極。
操作時，PMOS選擇電晶體102的選擇閘極110耦合至一選擇閘極電壓 VSG，PMOS選擇電晶體102的P+源極摻雜區132經由一源極線(SL)接觸點耦合至一源極線電壓VSL，P+汲極/源極摻雜區134及浮置閘極120為電性浮置，而PMOS浮置閘極電晶體104的P+汲極摻雜區136係經由一位元線(BL)接觸點耦合至一位元線電壓VBL。重摻雜區域138則是耦合至一控制閘極電壓VCG。
在寫入模式下，電子透過通道熱電子(CHE)注入機制被選擇性的注入浮置閘極120。在抹除模式下(區段或全晶片抹除)，電子則是透過福勒諾漢穿隧(FN tunneling)機制從浮置閘極120抹除。
第12圖為依據本發明又另一實施例所繪示的具抹除元件的單層多晶矽非揮發性記憶體的實施態樣。
如第12圖所示，第12圖中的單層多晶矽非揮發性記憶體6與第9圖中的單層多晶矽非揮發性記憶體5差異在於第12圖中的單層多晶矽非揮發性記憶體6另包含一與氧化物定義區域OD1接壤的電荷收集區域50。電荷收集區域50能夠在單層多晶矽非揮發性記憶體操作時收集累積在半導體層230中的多餘電子及電洞。
根據本發明實施例，電荷收集區域50包含一氧化物定義區域OD4、一N+摻雜區500位於氧化物定義區域OD4內，及一橋接區域520連接N+摻雜區500與浮置閘極120正下方的半導體層230。N型井310可以與橋接區域520及氧化物定義區域OD4重疊。在N+摻雜區500內可提供一N型井接觸點，使電荷收集區域50可以耦合至一N型井電壓VNW。在第12圖中，記憶胞C1及記憶胞C2共用一電荷收集區域，而記憶胞C3及記憶胞C4共用一電荷收集區域。
第13圖例示適用於第9圖及第12圖中的各記憶胞的寫入(PGM)、讀取(READ)及抹除(ERS)的操作條件。如第13圖所示，在寫入(PGM)操作時，源極線(SL)耦合至一電壓VPP，例如，電壓VPP可以介於5~9V。位元線(BL)接地(VBL=0V)。另提供選擇閘極(SG)110一介於0~1/2VPP的電壓，提供控制閘極(CG)一介於 0~1/2VPP的電壓。對於具有電荷收集區域50的記憶胞，如第12圖所示，N+摻雜區500偶合至一VPP電壓。第13圖中同時例示對記憶胞進行寫入-抑制(PGM-inhibit)操作或寫入-未選擇(PGM-unselect)操作的電壓條件。
在抹除操作時，源極線(SL)耦合至一VEE電壓。舉例來說，VEE可以介於8~18V。位元線(BL)耦合至VEE電壓。選擇閘極(SG)110耦合至VEE電壓，或者VEE-△V電壓(△V>Vt)。控制閘極(CG)接地(VCG=0V)。對於具有電荷收集區域50的記憶胞，如第12圖所示，N+摻雜區500接地(VNW=0V)。
在讀取操作時，源極線(SL)耦合至一VREAD電壓。舉例來說，VREAD可以介於2~2.8V。位元線(BL)耦合至0.4V電壓(VBL=0.4V)。選擇閘極(SG)110接地(VSG=0V)。控制閘極(CG)接地(VCG=0V)。對於具有電荷收集區域50的記憶胞，如第12圖所示，N+摻雜區500耦合至VREAD電壓。第13圖中同時例示對記憶胞進行讀取-未選擇(READ-unselect)操作的電壓條件。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (16)

  1. 一種單層多晶矽非揮發性記憶胞結構，包含：一矽覆絕緣(SOI)基板，包含一矽基底、一埋入氧化層及一半導體層；一第一氧化物定義區域及一第二氧化物定義區域，位於該半導體層；一絕緣區域，位於該半導體層，該絕緣區域隔離該第一氧化物定義區域與該第二氧化物定義區域；一PMOS選擇電晶體，設於該第一氧化物定義區域；一PMOS浮置閘極電晶體，設於該第一氧化物定義區域，並串接該PMOS選擇電晶體，其中該PMOS浮置閘極電晶體包含一浮置閘極，位於該第一氧化物定義區域上；一浮置閘極延伸，由該浮置閘極連續地延伸至該第二氧化物定義區域，並與該第二氧化物定義區域電容耦合；以及一電荷收集區域，與該第一氧化物定義區域接壤，其中該電荷收集區域包含一第三氧化物定義區域、一N+摻雜區位於該第三氧化物定義區域內，及一橋接區域，連接該N+摻雜區與該浮置閘極正下方的該半導體層。
  2. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中該PMOS選擇電晶體包含一選擇閘極、一選擇閘極氧化層，介於該選擇閘極與該半導體層之間、一P+源極摻雜區，及一P+汲極/源極摻雜區，其中該P+源極摻雜區耦合至一源極線。
  3. 如申請專利範圍第2項所述的單層多晶矽非揮發性記憶胞結構，其中該PMOS浮置閘極電晶體包含該浮置閘極、一浮置閘極氧化層，介於該浮置閘極與該半導體層之間、該P+汲極/源極摻雜區，及一P+汲極摻雜區，其中該PMOS選擇電晶體與該PMOS浮置閘極電晶體共用該P+汲極/源極摻雜區。
  4. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中另包含：一N型井，位於該半導體層，其中該N型井完全重疊該第一氧化物定義區域。
  5. 如申請專利範圍第3項所述的單層多晶矽非揮發性記憶胞結構，其中另包含：一離子井，位於該半導體層，其中該離子井完全重疊該第二氧化物定義區域；以及一重摻雜區域，位於該第二氧化物定義區域內的該離子井中。
  6. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該離子井包含一N型井或一P型井。
  7. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該重摻雜區域係為一N+摻雜區。
  8. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該重摻雜區域係為一P+摻雜區。
  9. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該浮置閘極跨越該第一氧化物定義區域與該第二氧化物定義區域之間的該絕緣區域，並且與該第二氧化物定義區域部分重疊以電容耦合該重摻雜區域。
  10. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中該第二氧化物定義區域、該重摻雜區域、該浮置閘極氧化層，及與該重摻雜區域電容耦合的該浮置閘極延伸，共同構成一抹除元件。
  11. 如申請專利範圍第5項所述的單層多晶矽非揮發性記憶胞結構，其中操作時，該選擇閘極耦合至一選擇閘極電壓VSG，該PMOS選擇電晶體的P+源極摻雜區耦合至一源極線電壓VSL，該P+汲極/源極摻雜區及該浮置閘極為電性浮置，而該PMOS浮置閘極電晶體的該P+汲極摻雜區耦合至一位元線電壓VBL，該重摻雜區域耦合至一抹除線電壓VEL。
  12. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中該浮置閘極延伸與該第二氧化物定義區域的重疊面積小於該浮置閘極與該第一氧化物定義區域的重疊面積。
  13. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中該浮置閘極延伸與該第二氧化物定義區域的重疊面積大於該浮置閘極與該第一氧化物定義區域的重疊面積。
  14. 如申請專利範圍第4項所述的單層多晶矽非揮發性記憶胞結構，其中：該電荷收集區域在該單層多晶矽非揮發性記憶體操作時收集累積在該半導體層中的多餘電子及電洞。
  15. 如申請專利範圍第14項所述的單層多晶矽非揮發性記憶胞結構，其中該N型井與該橋接區域及該第三氧化物定義區域重疊。
  16. 如申請專利範圍第1項所述的單層多晶矽非揮發性記憶胞結構，其中另包含：一N+摻雜區，其與該P+源極摻雜區接壤，該N+摻雜區與該P+源極摻雜區位於該選擇閘極同一側，如此構成一毗接接觸區。
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