CN106981311A - 电压切换电路 - Google Patents

电压切换电路 Download PDF

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CN106981311A
CN106981311A CN201610555070.2A CN201610555070A CN106981311A CN 106981311 A CN106981311 A CN 106981311A CN 201610555070 A CN201610555070 A CN 201610555070A CN 106981311 A CN106981311 A CN 106981311A
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voltage
transistor
receives
output end
node
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CN106981311B (zh
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柏正豪
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eMemory Technology Inc
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    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
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    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
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Abstract

一种电压切换电路，连接至一非易失性存储器的一存储器胞。在该非易失性存储器的一编程模式且该存储器胞为一选定存储器胞时，在二输出端皆提供一高电压。在该非易失性存储器的该编程模式且该存储器胞为一未选定存储器胞时，在二输出端提供一中间电压与一接地电压。在该非易失性存储器的一抹除模式且该存储器胞为该选定存储器胞时，在二输出端提供该高电压与该接地电压。在该非易失性存储器的该抹除模式且该存储器胞为该未选定存储器胞时，在二输出端提供该接地电压。在一读取模式时，在二输出端皆提供一读取电压。

Description

电压切换电路
技术领域
本发明涉及一种切换电路，且特别涉及一种运用于非易失性存储器的电压切换电路。
背景技术
众所周知，非易失性存储器可在电源消失之后，仍可保存数据，因此非易失性存储器已经广泛的运用于电子产品中。再者，非易失性存储器由多个存储器胞(memory cell，或称之为“记忆胞”)排列而成存储器胞阵列(memory cell array)，而每个存储器胞中皆包含一浮动栅晶体管(floating gate transistor)。
基本上，在编程模式(program mode)时，存储器胞阵列会接收一高电压(highvoltage)，使得选定存储器胞(selected memory cell)中浮动栅晶体管的浮动栅极(floating gate)被注入(inject)热载子(hot carrier)。
同理，在抹除模式(erase mode)时，存储器胞阵列也会接收高电压(highvoltage)，用以退出(eject)选定存储器胞内浮动栅晶体管的浮动栅极所存储的热载子。
由于在编程模式与抹除模式时，选定存储器胞皆需要接收高电压用来控制热载子的注入或者退出。因此，在非易失性存储器中需要有一电压切换电路(voltage switchcircuit)，并在不同的工作模式时提供各种操作电压至存储器胞阵列。
一般来说，上述的高电压(例如18V)远高于一般逻辑电路中5V、3.3V或1.8V的逻辑电平。因此，电压切换电路需要经过特别的设计才能够运用于非易失性存储器。例如美国专利US9,224,490公开一种运用于非易失性存储器的电压切换电路。
发明内容
本发明的主要目的是提出一种运用于非易失性存储器中的电压切换电路，根据非易失性存储器的工作模式，提供对应的操作电压至非易失性存储器的存储器胞阵列。
本发明涉及一种电压切换电路，连接至一非易失性存储器的一存储器胞，该电压切换电路包括：一第一晶体管，源极连接至一第一电压源，栅极连接至一节点a1；一第二晶体管，源极连接至该第一电压源，栅极连接至一节点b1；一第三晶体管，源极连接至该第一晶体管的漏极，栅极接收一致能信号，漏极连接至一节点a2；一第四晶体管，源极连接至该第二晶体管的漏极，栅极接收该致能信号，漏极连接至一节点b2；一第五晶体管，源极连接至该节点a2，栅极连接至一第二电压源，漏极连接至一第一输出端；一第六晶体管，源极连接至该节点b2，栅极连接至一第三电压源，漏极连接至一第二输出端；一第七晶体管，源极连接至一第四电压源，栅极连接至该第二输出端，漏极连接至该节点a2；一第一控制电路，连接至该节点a1、该节点b1与该节点a2；以及一第二控制电路，连接至该第一输出端与该第二输出端；其中，在该非易失性存储器的一编程模式以及一抹除模式时，该第一电压源提供一高电压、该第二电压源提供一中间电压或者一接地电压、该第三电压源提供一控制电压、且该第四电压源提供该中间电压；其中，在该非易失性存储器的一读取模式时，该第一电压源、该第二电压源、该第三电压源提供一逻辑高电平，该第四电压源提供该接地电压；其中，该高电压大于该中间电压，且该中间电压大于该逻辑高电平；以及该控制电压介于该高电压与该中间电压之间。
为了对本发明的上述及其他方面有更佳的了解，下文特举优选实施例，并配合附图，作详细说明如下：
附图说明
图1A与图1B所绘示为本发明电压切换电路的第一实施例及其相关表列信号示意图。
图2所绘示为本发明电压切换电路的第二实施例示意图。
【符号说明】
100、200：电压切换电路
110、210：第一控制电路
120：第二控制电路
具体实施方式
第一实施例
请参照图1A，其所绘示为本发明电压切换电路的第一实施例。电压切换电路100的二个输出端CL与EL连接至非易失性存储器的存储器胞。并且，根据非易失性存储器的操作模式，电压切换电路100的二个输出端CL与EL可供应对应的操作电压至非易失性存储器的存储器胞。
电压切换电路100包括第一控制电路110、第二控制电路以及多个p型晶体管Ml1、Ml2、Ml3、Mr1、Mr2、Mr3、Mx。第一控制电路110包括多个p型晶体管Mc1、Mc2、Mc3与Mc4。第二控制电路120包括N型晶体管Ml4、Ml5、Ml6、Mr4、Mr5与Mr6。其中，晶体管Ml4、Mr4为耐高压的轻掺杂N型晶体管(n lightly doped transistor)。
电压切换电路100中，晶体管Ml1源极连接至第一电压源Vpp1、栅极连接至节点a1；晶体管Ml2源极连接至晶体管Ml1漏极、栅极接收致能信号En、漏极连接至节点a2；晶体管Ml3源极连接至节点a2、栅极连接至第二电压源Vpp2、漏极连接至第一输出端CL。
再者，晶体管Mr1源极连接至第一电压源Vpp1、栅极连接至节点b1；晶体管Mr2源极连接至晶体管Mr1漏极、栅极接收致能信号En、漏极连接至节点b2；晶体管Mr3源极连接至节点b2、栅极连接至第三电压源Vpp3、漏极连接至第二输出端EL。
晶体管Mx源极连接至第四电压源Vpp4，漏极连接至节点a2，栅极连接至第二输出端EL。
再者，第一控制电路110中，晶体管Mc1源极连接至偏压电压Vbias、栅极接收第一控制信号Vc1、漏极连接至节点a1；晶体管Mc2源极连接至第一电压源Vpp1、栅极接收第二控制信号Vc2、漏极连接至节点a1；晶体管Mc3源极连接至偏压电压Vbias、栅极接收第三控制信号Vc3、漏极连接至节点b1；晶体管Mc4源极连接至节点a2、栅极接收第四控制信号Vc4、漏极连接至节点b1。
再者，第二控制电路120中，晶体管Ml4漏极连接至第一输出端CL、栅极接收逻辑高电平VDD、源极连接至节点a3；晶体管Ml5漏极连接至节点a3、栅极接收抹除信号Ers、源极接收反相抹除信号Ersb；晶体管Ml6漏极连接至节点a3、栅极接收读取信号Rd、源极接收读取电压VPR。再者，晶体管Mr4漏极连接至第二输出端EL、栅极接收逻辑高电平VDD、源极连接至节点b3；晶体管Mr5漏极连接至节点b3、栅极接收反相第一输入信号In1b、源极接收第一输入信号In1；晶体管Mr6漏极连接至节点b3、栅极接收读取信号Rd、源极接收读取电压VPR。
根据本发明的第一实施例，第二控制电路120中的第一输入信号In1、抹除信号Ers、读取信号Rd皆是操作在逻辑高电平以及逻辑低电平之间。例如，逻辑高电平为VDD(例如3.3V)，逻辑低电平为0V。
再者，第一控制电路110中的第一控制信号Vc1、第二控制信号Vc2、第三控制信号Vc3与第四控制信号Vc4操作在第一电平Vh与第二电平Vl之间。且第一电平Vh与第二电平Vl皆非逻辑电平，且第一电平Vh大于第二电平Vl，第二电平Vl大于逻辑高电平VDD。
请参照图1B，其所绘示为本发明第一实施例的相关表列信号示意图。根据本发明的第一实施例，在非易失性存储器的编程模式以及抹除模式时，电压切换电路100中的第一电压源Vpp1供应高电压VPP，第二电压源Vpp2供应中间电压VM(medium voltage)或者接地电压(0V)，第三电压源Vpp3供应控制电压(control voltage)Vctrl，第四电压源Vpp4供应中间电压VM。另外，在非易失性存储器的读取模式时，电压切换电路100中的第一电压源Vpp1、第二电压源Vpp2与第三电压源Vpp3供应逻辑高电平VDD，第四电压源Vpp4供应接地电压(0V)。其中，高电压VPP大于中间电压VM，且中间电压大于逻辑高电平VDD。再者，控制电压Vctrl介于高电压VPP与中间电压VM之间。举例来说，高电压VPP为20V，控制电压Vctrl为14V，中间电压VM为8V，逻辑高电平为3.3V。
当非易失性存储器处于编程模式，且电压切换电路100连接至选定存储器胞时，致能信号En为致能电压Ven使得晶体管Ml2与晶体管Mr2开启(turn on)；第二电压源Vpp2提供中间电压VM使得晶体管Ml3开启(turn on)；第三电压源Vpp3提供控制电压Vctrl使得晶体管Mr3开启(turn on)。其中，致能电压Ven小于高电压VPP。
再者，第一控制电路110中，第一控制信号Vc1为第二电平Vl、第二控制信号Vc2为第一电平Vh、第三控制信号Vc3为第二电平Vl、第四控制信号Vc4为第一电平Vh。因此，晶体管Mc1与晶体管Mc3开启(turn on)，晶体管Mc2与晶体管Mc4不开启(turn off)，使得节点a1与节点b1接收偏压电压Vbias，并使得晶体管Ml1与晶体管Mr1开启(turn on)。其中，第二电平Vl小于第一电平Vh；且第一电平Vh小于等于高电压VPP；且偏压电压Vbias小于高电压VPP。
再者，第二控制电路120中，第一输入信号In1为逻辑高电平VDD、抹除信号Ers为逻辑低电平0V、读取信号Rd为逻辑低电平0V。因此，晶体管Ml5、晶体管Ml6、晶体管Mr5、晶体管Mr6皆不开启(turn off)，使得第二控制电路120不动作(inactivate)。
由以上的说明可知，当非易失性存储器处于编程模式，且电压切换电路100连接至选定存储器胞时，晶体管Ml1、Ml2、Ml3、Mr1、Mr2、Mr3开启(turn on)，使得节点a2、节点b2、第一输出端CL、第二输出端EL皆为高电压VPP。因此，选定存储器胞接收第一输出端CL与第二输出端EL的高电压VPP作为操作电压。另外，由于第二输出端EL为高电压VPP，晶体管Mx不开启(turn off)。
当非易失性存储器处于编程模式，且电压切换电路100连接至非选定存储器胞时，致能信号En为禁能电压Vdis使得晶体管Ml2与晶体管Mr2不开启(turn off)；第二电压源Vpp2提供接地电压0V使得晶体管Ml3开启。其中，致能电压Ven小于禁能电压Vdis；且禁能电压Vdis小于等于高电压VPP。
再者，第一控制电路110中，第一控制信号Vc1为第二电平Vl、第二控制信号Vc2为第一电平Vh、第三控制信号Vc3为第二电平Vl、第四控制信号Vc4为第一电平Vh。因此，晶体管Mc1与晶体管Mc3开启(turn on)，晶体管Mc2与晶体管Mc4不开启(turn off)，使得节点a1与节点b1接收偏压电压Vbias，并使得晶体管Ml1与晶体管Mr1开启(turn on)。
再者，第二控制电路120中，第一输入信号In1为逻辑低电平0V、抹除信号Ers为逻辑低电平0V、读取信号Rd为逻辑低电平0V。因此，第二控制电路120中，仅有晶体管Mr5开启(turn on)，使得节点b2与第二输出端EL为接地电压0V。另外，由于第三电压源Vpp3提供控制电压Vctrl，使得晶体管Mr3不开启，节点b为浮接(floating，FL)。由于第二输出端EL为接地电压0V，晶体管Mx开启(turn on)，且第二电压源Vpp2为接地电压0V，晶体管Ml3开启。因此，节点a2与第一输出端CL为中间电压VM。
由以上的说明可知，当非易失性存储器处于编程模式，且电压切换电路100连接至非选定存储器胞时，由于晶体管Ml2与晶体管Mr2不开启(turn off)，且晶体管Mr5开启(turn on)，使得第二输出端EL为逻辑低电平0V。再者，由于晶体管Mx与晶体管Ml3开启，使得节点a2、第一输出端CL为中间电压VM。因此，非选定存储器胞接收第一输出端CL的中间电压VM与第二输出端EL的逻辑低电平0V作为操作电压。
当非易失性存储器处于抹除模式，且电压切换电路100连接至选定存储器胞时，致能信号En为致能电压Ven使得晶体管Ml2与晶体管Mr2开启(turn on)；第二电压源Vpp2提供中间电压VM使得晶体管Ml3不开启；第三电压源Vpp3提供控制电压Vctrl使得晶体管Mr3开启(turn on)。
再者，第一控制电路110中，第一控制信号Vc1为第一电平Vh、第二控制信号Vc2为第二电平Vl、第三控制信号Vc3为第一电平Vh、第四控制信号Vc4为第二电平Vl。因此，晶体管Mc1与晶体管Mc3不开启(turn off)，晶体管Mc2与晶体管Mc4开启(turn on)。由于晶体管Mc2开启(turn on)，使得节点a1接收高电压VPP，并使得晶体管Ml1不开启(turn off)。再者，由于晶体管Mc4开启(turn on)，节点b1与节点a2相互连接。
再者，第二控制电路120中，第一输入信号In1为逻辑高电平VDD、抹除信号Ers为逻辑高电平VDD、读取信号Rd为逻辑低电平0V。因此，第二控制电路120中，仅有晶体管Ml5开启(turn on)，使得第一输出端CL为逻辑低电平0V。另外，由于第二电压源Vpp2提供中间电压VM至晶体管Ml3栅极，由于栅极偶合效应(coupling effect)，将使得节点b1电压为中间电压VM，并开启晶体管Mr1。
由以上的说明可知，当非易失性存储器处于抹除模式，且电压切换电路100连接至选定存储器胞时，晶体管Mr1、晶体管Mr2、晶体管Mr3开启(turn on)，使得节点b2与第二输出端EL为高电压VPP。再者，由于晶体管Ml5开启(turn on)，使得第一输出端CL为逻辑低电平0V。因此，选定存储器胞接收第一输出端CL的逻辑低电平0V与第二输出端EL的高电压VPP作为操作电压。
当非易失性存储器处于抹除模式，且电压切换电路100连接至非选定存储器胞时，致能信号En为禁能电压Vdis使得晶体管Ml2与晶体管Mr2不开启(turn off)；第二电压源Vpp2提供中间电压VM使得晶体管Ml3不开启；第三电压源Vpp3提供控制电压Vctrl使得晶体管Mr3不开启。由于晶体管Mr2、Mr3皆不开启，节点b3为浮接(FL)。
再者，第一控制电路110中，第一控制信号Vc1为第一电平Vh、第二控制信号Vc2为第二电平Vl、第三控制信号Vc3为第一电平Vh、第四控制信号Vc4为第二电平Vl。因此，晶体管Mc1与晶体管Mc3不开启(turn off)，晶体管Mc2与晶体管Mc4开启(turn on)。由于晶体管Mc2开启(turn on)，使得节点a1接收高电压VPP，并使得晶体管Ml1不开启(turn off)。再者，由于晶体管Mc4开启(turn on)，节点b1连接至节点a2并接收中间电压VM，使得晶体管Mr1开启(turn on)。
再者，第二控制电路120中，第一输入信号In1为逻辑低电平0V、抹除信号Ers为逻辑高电平VDD、读取信号Rd为逻辑低电平0V。因此，晶体管Ml5与晶体管Mr5开启(turn on)，使得第一输出端CL与第二输出端EL为逻辑低电平0V。
另外，由于第二输出端EL为接地电压0V，晶体管Mx开启(turn on)，节点a2与节点b1为中间电压VM，使得晶体管Mr1开启(turn on)。
由以上的说明可知，当非易失性存储器处于抹除模式，且电压切换电路100连接至非选定存储器胞时，晶体管Ml5与晶体管Mr5开启(turn on)，使得第一输出端CL与第二输出端EL皆为逻辑低电平0V。因此，非选定存储器胞接收第一输出端CL与第二输出端EL的逻辑低电平0V作为操作电压。
当非易失性存储器处于读取模式，且电压切换电路100连接至选定存储器胞或者非选定存储器胞时，第一电压源Vpp1、第二电压源Vpp2、第三电压源Vpp3与致能信号En为逻辑高电平VDD，第四电压源Vpp4为接地电压0V。因此，晶体管Ml2、Mr2、Ml3、Mr3不开启(turnoff)。
再者，第一控制电路110中，第一控制信号Vc1、第二控制信号Vc2、第三控制信号Vc3与第四控制信号Vc4皆为浮接(floating，FL)。因此，晶体管Ml1与晶体管Mr1不开启(turn off)。因此，节点a1、节点a2、节点b1、节点b2皆为浮接(floating，FL)。
再者，第二控制电路120中，第一输入信号In1为逻辑高电平VDD、抹除信号Ers为逻辑低电平0V、读取信号Rd为高逻辑准VDD。因此，晶体管Ml6、晶体管Mr6开启(turn on)，使得第一输出端CL与第二输出端EL为读取电压VPR。
由以上的说明可知，当非易失性存储器处于读取模式，且电压切换电路100连接至选定存储器胞或者非选定存储器胞时，第一输出端CL与第二输出端EL皆为读取电压VPR。因此，选定存储器胞与非选定存储器胞接收第一输出端CL与第二输出端EL的读取电压VPR作为操作电压。
第二实施例
请参照图2，其所绘示为本发明电压切换电路的第二实施例示意图。相较于第一实施例，其差异仅在于第一控制电路210中的晶体管Mc2的连接关系，而其他晶体管的连接关系与第一实施例完全相同，不再赘述。亦即，第一控制电路210中，晶体管Mc2源极连接至节点b2、栅极接收第二控制信号Vc2、漏极连接至节点a1。
再者，第二实施例的电压切换电路200，其信号关系也相同于图1B。所以第二电压切换电路200在各种操作模式下的动作原理也不再赘述。
由以上说明可知，本发明的优点是提出一种运用于非易失性存储器中的电压切换电路，根据非易失性存储器的工作模式，提供对应的操作电压至存储器胞阵列。
综上所述，虽然本发明已以优选实施例公开如上，然其并非用以限定本发明。本发明所属领域技术人员在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视所附权利要求书界定范围为准。

Claims (19)

1.一种电压切换电路，连接至非易失性存储器的存储器胞，该电压切换电路包括：
第一晶体管，源极连接至第一电压源，栅极连接至节点a1；
第二晶体管，源极连接至该第一电压源，栅极连接至节点b1；
第三晶体管，源极连接至该第一晶体管的漏极，栅极接收致能信号，漏极连接至节点a2；
第四晶体管，源极连接至该第二晶体管的漏极，栅极接收该致能信号，漏极连接至节点b2；
第五晶体管，源极连接至该节点a2，栅极连接至第二电压源，漏极连接至第一输出端；
第六晶体管，源极连接至该节点b2，栅极连接至第三电压源，漏极连接至第二输出端；
第七晶体管，源极连接至第四电压源，栅极连接至该第二输出端，漏极连接至该节点a2；
第一控制电路，连接至该节点a1、该节点b1与该节点a2；以及
第二控制电路，连接至该第一输出端与该第二输出端；
其中，在该非易失性存储器的编程模式以及抹除模式时，该第一电压源提供高电压、该第二电压源提供中间电压或者接地电压、该第三电压源提供控制电压、且该第四电压源提供该中间电压；
其中，在该非易失性存储器的读取模式时，该第一电压源、该第二电压源、该第三电压源提供逻辑高电平，该第四电压源提供该接地电压；
其中，该高电压大于该中间电压，且该中间电压大于该逻辑高电平；以及该控制电压介于该高电压与该中间电压之间。
2.如权利要求1所述的电压切换电路，其中该第一控制电路包括：
第八晶体管，源极连接至偏压电压，栅极接收第一控制信号，漏极连接至该节点a1；
第九晶体管，源极连接至该第一电压源，栅极接收第二控制信号，漏极连接至该节点a1；
第十晶体管，源极连接至该偏压电压，栅极接收第三控制信号，漏极连接至该节点b1；以及
第十一晶体管，源极连接至该节点a2，栅极接收第四控制信号，漏极连接至该节点b1；
其中，该高电压大于该偏压电压。
3.如权利要求2所述的电压切换电路，其中在该非易失性存储器的该编程模式且该存储器胞为选定存储器胞时，该第一晶体管与该第二晶体管接收该偏压电压并开启；该致能信号为致能电压，使得该第三晶体管与该第四晶体管接收该致能电压并开启；该第五晶体管接收该中间电压并开启，该第六晶体管接收该控制电压并开启；以及，该第二控制电路不动作，使得该第一输出端与该第二输出端输出该高电压；其中，该致能电压小于该高电压。
4.如权利要求2所述的电压切换电路，其中在该非易失性存储器的该编程模式且该存储器胞为非选定存储器胞时，该第一晶体管与该第二晶体管接收该偏压电压并开启；该致能信号为禁能电压，使得该第三晶体管与该第四晶体管接收该禁能电压而不开启；该第五晶体管接收该接地电压并开启；该第六晶体管接收该控制电压而不开启；以及该第二控制电路提供逻辑低电平至该第二输出端；使得该第七晶体管开启，并提供该中电电压至该第一输出端；其中，该禁能电压小于等于该高电压。
5.如权利要求2所述的电压切换电路，其中在该非易失性存储器的该抹除模式且该存储器胞为选定存储器胞时，该第一晶体管接收该高电压而不开启；该第二晶体管开启；该致能信号为致能电压，使得该第三晶体管与该第四晶体管接收该致能电压并开启；该第五晶体管接收该中间电压而不开启；该第六晶体管接收该控制电压并开启，使得该第二输出端输出该高电压；以及，该第二控制电路提供逻辑低电平至该第一输出端，使得该第一输出端输出该逻辑低电平；其中，该致能电压小于该高电压。
6.如权利要求2所述的电压切换电路，其中在该非易失性存储器的该抹除模式且该存储器胞为非选定存储器胞时，该第一晶体管接收该高电压而不开启；该第二晶体管开启；该致能信号为禁能电压，使得该第三晶体管与该第四晶体管接收该禁能电压而不开启；该第五晶体管接收该中间电压而不开启；该第六晶体管接收该控制电压而不开启；以及，该第二控制电路提供逻辑低电平至该第一输出端与该第二输出端，使得该第一输出端与该第二输出端输出该逻辑低电平，且该第七晶体管开启；其中，该禁能电压小于等于该高电压。
7.如权利要求2所述的电压切换电路，其中在该非易失性存储器的该读取模式时，该第一晶体管与该第二晶体管不开启；该致能信号为该逻辑高电平，使得该第三晶体管与该第四晶体管不开启；该第五晶体管与该第六晶体管接收该该逻辑高电平而不开启；以及，该第二控制电路提供读取电压至该第一输出端与该第二输出端，使得该第一输出端与该第二输出端输出该读取电压。
8.如权利要求1所述的电压切换电路，其中该第二控制电路包括：
第十二晶体管，漏极连接至该第一输出端，栅极接收该逻辑高电平，源极连接至节点a3；
第十三晶体管，漏极连接至该第二输出端，栅极接收该逻辑高电平，源极连接至节点b3；
第十四晶体管，漏极连接至该节点a3，栅极接收抹除信号，源极接收反相的该抹除信号；
第十五晶体管，漏极连接至该节点a3，栅极接收读取信号，源极接收读取电压；
第十六晶体管，漏极连接至该节点b3，源极接收第一输入信号，栅极接收反相的该第一输入信号；以及
第十七晶体管，漏极连接至该节点b3，栅极接收该读取信号，源极接收该读取电压。
9.如权利要求8所述的电压切换电路，其中在该非易失性存储器的该编程模式且该存储器胞为选定存储器胞时，该第一输入信号为该逻辑高电平，该抹除信号与该读取信号为逻辑低电平，使得该十四晶体管、该第十五晶体管、该第十六晶体管与该第十七晶体管皆不开启。
10.如权利要求8所述的电压切换电路，其中在该非易失性存储器的该编程模式且该存储器胞为非选定存储器胞时，该第一输入信号、该抹除信号与该读取信号为逻辑低电平，使得该第十六晶体管开启，且该第十四晶体管、该第十五晶体管与该第十七晶体管不开启。
11.如权利要求8所述的电压切换电路，其中在该非易失性存储器的该抹除模式且该存储器胞为选定存储器胞时，该第一输入信号与该抹除信号为该逻辑高电平，该读取信号为逻辑低电平，使得该第十四晶体管开启，该第十五晶体管、该第十六晶体管与该第十七晶体管皆不开启。
12.如权利要求8所述的电压切换电路，其中该非易失性存储器在该抹除模式且该存储器胞为非选定存储器胞时，该抹除信号为该逻辑高电平，该第一输入信号与该读取信号为逻辑低电平，使得该第十四晶体管与该第十六晶体管开启，该第十五晶体管与该第十七晶体管不开启。
13.如权利要求8所述的电压切换电路，其中在该非易失性存储器的该读取模式时，该读取信号与该第一输入信号为该逻辑高电平，该抹除信号为逻辑低电平，使得该第十五晶体管与该第十七晶体管开启，该第十四晶体管与该第十六晶体管不开启。
14.如权利要求1所述的电压切换电路，其中该第一控制电路包括：
第八晶体管，源极连接至偏压电压，栅极接收第一控制信号，漏极连接至该节点a1；
第九晶体管，源极连接至该节点b2，栅极接收第二控制信号，漏极连接至该节点a1；
第十晶体管，源极连接至该偏压电压，栅极接收第三控制信号，漏极连接至该节点b1；以及
第十一晶体管，源极连接至该节点a2，栅极接收第四控制信号，漏极连接至该节点b1；
其中，该高电压大于该偏压电压。
15.如权利要求14所述的电压切换电路，其中在该非易失性存储器的该编程模式且该存储器胞为选定存储器胞时，该第一晶体管与该第二晶体管接收该偏压电压并开启；该致能信号为致能电压，使得该第三晶体管与该第四晶体管接收该致能电压并开启；该第五晶体管接收该中间电压并开启，该第六晶体管接收该控制电压并开启；以及，该第二控制电路不动作，使得该第一输出端与该第二输出端输出该高电压；其中，该致能电压小于该高电压。
16.如权利要求14所述的电压切换电路，其中在该非易失性存储器的该编程模式且该存储器胞为非选定存储器胞时，该第一晶体管与该第二晶体管接收该偏压电压并开启；该致能信号为禁能电压，使得该第三晶体管与该第四晶体管接收该禁能电压而不开启；该第五晶体管接收该接地电压并开启；该第六晶体管接收该控制电压而不开启；以及该第二控制电路提供逻辑低电平至该第二输出端；使得该第七晶体管开启，并提供该中间电压至该第一输出端；其中，该禁能电压小于等于该高电压。
17.如权利要求14所述的电压切换电路，其中在该非易失性存储器的该抹除模式且该存储器胞为选定存储器胞时，该第一晶体管接收该高电压而不开启；该第二晶体管开启；该致能信号为致能电压，使得该第三晶体管与该第四晶体管接收该致能电压并开启；该第五晶体管接收该中间电压而不开启；该第六晶体管接收该控制电压并开启，使得该第二输出端输出该高电压；以及，该第二控制电路提供逻辑低电平至该第一输出端，使得该第一输出端输出该逻辑低电平；其中，该致能电压小于该高电压。
18.如权利要求14所述的电压切换电路，其中在该非易失性存储器的该抹除模式且该存储器胞为非选定存储器胞时，该第一晶体管不开启；该第二晶体管开启；该致能信号为禁能电压，使得该第三晶体管与该第四晶体管接收该禁能电压而不开启；该第五晶体管接收该中间电压而不开启；该第六晶体管接收该控制电压而不开启；以及，该第二控制电路提供逻辑低电平至该第一输出端与该第二输出端，使得该第一输出端与该第二输出端输出该逻辑低电平，且该第七晶体管开启；其中，该禁能电压小于等于该高电压。
19.如权利要求14所述的电压切换电路，其中在该非易失性存储器的该读取模式时，该第一晶体管与该第二晶体管不开启；该致能信号为该逻辑高电平，使得该第三晶体管与该第四晶体管不开启；该第五晶体管与该第六晶体管接收该高逻辑电平而不开启；以及，该第二控制电路提供读取电压至该第一输出端与该第二输出端，使得该第一输出端与该第二输出端输出该读取电压。
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