TWI614763B - 記憶體裝置、其週邊電路及其單一位元組資料寫入方法 - Google Patents

記憶體裝置、其週邊電路及其單一位元組資料寫入方法 Download PDF

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TWI614763B
TWI614763B TW106100807A TW106100807A TWI614763B TW I614763 B TWI614763 B TW I614763B TW 106100807 A TW106100807 A TW 106100807A TW 106100807 A TW106100807 A TW 106100807A TW I614763 B TWI614763 B TW I614763B
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data
array
memory
decoder
memory array
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林義琅
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力旺電子股份有限公司
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Abstract

一種記憶體裝置、其週邊電路及其單一位元組資料寫入方法。週邊電路包括一Y解碼器、一分頁緩衝器及一寫入電路。寫入電路透過Y解碼器耦接一記憶體陣列及分頁緩衝器，並且接收一位元組的一程式化資料。寫入電路依據程式化資料對應的一記憶體位址透過Y解碼器讀取記憶體陣列所儲存的多位元組的一陣列資料，以將所讀取的陣列資料透過Y解碼器寫入至分頁緩衝器。接著，程式化資料透過寫入電路及Y解碼器寫入至記憶體陣列，並且陣列資料由分頁緩衝器寫入至記憶體陣列。

Description

記憶體裝置、其週邊電路及其單一位元組資料寫入方法
本發明是有關於一種記憶體裝置，且特別是有關於一種記憶體裝置、其週邊電路及其單一位元組資料寫入方法。
在目前，隨著科學與技術的快速發展，非揮發性記憶體已廣泛用於電子裝置中，並且非揮發性記憶體（例如，快閃記憶體）用以存儲電子裝置的資訊，且非揮發性記憶體對於電子裝置的重要的日益增加。然而，受限於非揮發性記憶體的半導體結構，非揮發性記憶體的寫入是以分頁為單位，而不是單一位元組，因此會影響非揮發性記憶體的寫入效能。
本發明提供一種記憶體裝置、其週邊電路及其單一位元組資料寫入方法，可接收單一位元組的程式化資料並且對應地對記憶體陣列進行資料更新。
本發明的記憶體裝置的週邊電路，包括一Y解碼器、一分頁緩衝器、一寫入電路及一感測放大器。Y解碼器耦接記憶裝置的一記憶體陣列。分頁緩衝器耦接記憶體陣列及Y解碼器。寫入電路透過Y解碼器耦接記憶體陣列及分頁緩衝器，並且接收一位元組的一程式化資料。感測放大器耦接於Y解碼器與寫入電路之間，以透過Y解碼器讀取記憶體陣列所儲存的多位元組的一陣列資料後提供陣列資料至寫入電路。所讀取的陣列資料是依據程式化資料對應的一記憶體位址，並且所讀取的陣列資料透過Y解碼器寫入至分頁緩衝器。接著，程式化資料透過寫入電路及Y解碼器寫入至記憶體陣列，並且陣列資料由分頁緩衝器寫入至記憶體陣列。
本發明的記憶體裝置，包括一記憶體陣列及如上所述的週邊電路。週邊電路耦接記憶體陣列，並且接收一位元組的一程式化資料，以將程式化資料寫入記憶體陣列。
本發明的記憶體裝置的單一位元組資料寫入方法，包括下列步驟。透過一寫入電路接收一位元組的一程式化資料。透過一感測放大器及一Y解碼器依據程式化資料對應的一記憶體位址讀取一記憶體陣列所儲存的多位元組的一陣列資料，並且透過寫入電路及Y解碼器將陣列資料寫入至一分頁緩衝器。透過寫入電路及Y解碼器將程式化資料寫入至記憶體陣列。透過分頁緩衝器將陣列資料寫入至記憶體陣列。
基於上述，本發明實施例的記憶體裝置、其週邊電路及其單一位元組資料寫入方法，其寫入電路讀取未選取的陣列資料並寫入至分頁緩衝器中，並且將選取的程式化資料直接寫入至記憶體陣列中，而陣列資料透過分頁緩衝器寫入記憶體陣列中。藉此，可在一分頁寫入的記憶體陣列中進行單一位元組資料的資料更新。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為依據本發明一實施例的記憶體裝置的系統示意圖。請參照圖1，在本實施例中，記憶體裝置100包括記憶體陣列110、分頁緩衝器120、Y解碼器130、感測放大器140、寫入電路150及字線解碼器160，其中記憶體裝置100可以是非揮發性記憶體裝置，並且記憶體陣列110例如包括多個陣列排列的記憶體胞（稍後說明），但本發明實施例不以此為限。並且，分頁緩衝器120、Y解碼器130、感測放大器140、寫入電路150及字線解碼器160可視為一週邊電路，耦接記憶體陣列110，並且接收由外部所提供的一位元組的程式化資料PDATA後，將程式化資料PDATA寫入記憶體陣列110。
記憶體陣列110耦接至分頁緩衝器120、Y解碼器130及字線解碼器160，其中記憶體陣列110、分頁緩衝器120及Y解碼器130相互耦接。感測放大器140耦接至Y解碼器130及寫入電路150，並且寫入電路150耦接至Y解碼器130。
寫入電路150接收程式化資料PDATA，並且感測放大器140透過Y解碼器130耦接至記憶體陣列110，以透過Y解碼器130依據程式化資料PDATA對應的記憶體位址讀取記憶體陣列110所儲存的多位元組的陣列資料ARDATA後，提供陣列資料ARDATA至寫入電路150。
接著，寫入電路150將所讀取的陣列資料ARDATA透過Y解碼器130寫入至分頁緩衝器120，並且接著程式化資料PDATA透過寫入電路150及Y解碼器130寫入至記憶體陣列110，但程式化資料PDATA不會經過分頁緩衝器120。然後，陣列資料ARDATA由分頁緩衝器120寫入至記憶體陣列110，但不會覆蓋程式化資料PDATA。
在本實施例中，記憶體位址包括字線位址及位元線位址，並且程式化資料PDATA與陣列資料ARDATA例如對應同一字線位址。一般來說，一分頁代表在一字線的記憶體胞。進一步來說，在感測放大器140讀取記憶體陣列110時，字線解碼器160會依據程式化資料PDATA對應的記憶體位址中的字線位址（亦即選定的字線位址）驅動記憶體陣列110，以致能記憶體陣列110中一分頁的記憶體胞（例如是控制邏輯上同一列的所有記憶體胞），接著位元線位址會遞增，以使感測放大器140可依序讀取此分頁的記憶體胞中所儲存的陣列資料ARDATA。
在本實施例中，當寫入電路150透過感測放大器140接收記憶體陣列110的陣列資料ARDATA時，開啟記憶體陣列110及Y解碼器130，並且關閉分頁緩衝器120；當寫入電路150將陣列資料ARDATA寫入分頁緩衝器120時，開啟Y解碼器130及分頁緩衝器120，並且關閉記憶體陣列110；當寫入電路150將程式化資料PDATA寫入記憶體陣列110時，開啟記憶體陣列110、分頁緩衝器120及Y解碼器130；當陣列資料ARDATA由分頁緩衝器120寫入記憶體陣列110時，開啟記憶體陣列110及分頁緩衝器120，並且關閉Y解碼器130。
在本發明的一實施例中，感測放大器140所讀取的陣列資料ARDATA可包含程式化資料PDATA所要寫入的記憶體胞中所儲存的資料，也可以不包含程式化資料PDATA所要寫入的記憶體胞中所儲存的資料。在寫入電路150將陣列資料ARDATA寫入至分頁緩衝器120後，可抹除程式化資料PDATA及陣列資料ARDATA的記憶體位址所對應的記憶體胞（亦即一分頁）。
圖2為依據本發明一實施例的記憶體陣列、Y解碼器、分頁緩衝器及寫入電路的線路示意圖。請參照圖1及圖2，其中相同或相似元件使用相同或相似標號。在本實施例中，記憶體陣列110具有多個記憶體胞111，Y解碼器130具有多個解碼單元131、分頁緩衝器120具有多個緩衝單元121，並且寫入電路150具有多個寫入單元151。
在本實施例中，Y解碼器130及分頁緩衝器120透過多條位元線（即BL 1、BL 2、…）耦接至記憶體陣列110。換言之，各個解碼單元131及各緩衝單元121透過對應的位元線（如BL 1、BL 2）耦接至對應的記憶體胞111。並且，Y解碼器130透過多條資料線（即DL 1、DL 2、…）耦接至感測放大器140及寫入電路150。在一實施例中，程式化資料PDATA為8位元（bit），寫入電路150具有8個寫入單元151，放大感測器140連接至資料線DL 1~DL 8，因此，當位元線位址遞增時，放大感測器140會依序送出8位元程式化資料PDATA至寫入電路150。
圖3為依據本發明一實施例的緩衝單元的電路示意圖。請參照圖1至圖3，在本實施例中，各個緩衝單元121包括第一傳輸閘TR1、第一反相器INV1及三態反相器310。第一傳輸閘TR1的第一端耦接對應的位元線BL 1，第一傳輸閘TR1的第二端耦接一內部栓鎖節點IN_LAT，第一傳輸閘TR1的正控制端接收頁面緩衝致能信號ENPGBUF，第一傳輸閘TR1的負控制端接收一反相頁面緩衝致能信號ZENPGBUF。第一反相器INV1的輸入端耦接內部栓鎖節點IN_LAT。三態反相器310的輸入端IE耦接第一反相器INV1的輸出端，三態反相器310的輸出端OE耦接內部栓鎖節點IN_LAT，其中三態反相器310受控於頁面緩衝致能信號ENPGBUF、反相頁面緩衝致能信號ZENPGBUF、Y解碼信號YD1及反相Y解碼信號ZYD1，頁面緩衝致能信號ENPGBUF與反相頁面緩衝致能信號ZENPGBUF互補，並且Y解碼信號YD1與反相Y解碼信號ZYD1互補。
三態反相器310包括電晶體M1~M6（對應第一電晶體至第六電晶體）。電晶體M1的源極（對應第一源/汲極）接收第一參考電壓VCC，電晶體M1的閘極（對應第一閘極）接收Y解碼信號YD1。電晶體M2的源極（對應第三源/汲極）耦接電晶體M1的汲極（對應第二源/汲極），電晶體M2的閘極（對應第二閘極）耦接三態反相器310的輸入端IE，電晶體M2的汲極（對應第四源/汲極）耦接三態反相器310的輸出端OE。
電晶體M3的汲極（對應第五源/汲極）耦接三態反相器310的輸出端OE，電晶體M3的閘極（對應第三閘極）耦接三態反相器310的輸入端IE。電晶體M4的汲極（對應第七源/汲極）耦接電晶體M3的源極（對應第六源/汲極），電晶體M4的閘極（對應第四閘極）接收反相Y解碼信號ZYD1，電晶體M4的源極（對應第八源/汲極）接收第二參考電壓GND。
電晶體M5的源極（對應第九源/汲極）接收第一參考電壓VCC，電晶體M5的閘極（對應第五閘極）接收頁面緩衝致能信號ENPGBUF，電晶體M五的汲極（對應第十源/汲極）耦接電晶體M1的汲極。電晶體M6的汲極（對應第十一源/汲極）耦接電晶體M3的源極（對應第六源/汲極），電晶體M6的閘極（對應第六閘極）接收反相頁面緩衝致能信號ZENPGBUF，電晶體M6的源極（對應第十二源/汲極）接收第二參考電壓GND。
在本實施例中，當頁面緩衝致能信號ENPGBUF致能時（例如為高電壓準位），亦即反相頁面緩衝致能信號ZENPGBUF為禁能（例如為低電壓準位），第一傳輸閘TR1會導通，亦即開啟分頁緩衝器120；反之，當頁面緩衝致能信號ENPGBUF禁能時，第一傳輸閘TR1會截止，亦即關閉分頁緩衝器120。並且，當Y解碼信號YD1及頁面緩衝致能信號ENPGBUF皆致能時，亦即寫入電路150寫入資料至分頁緩衝器120或記憶體陣列110，資料線DL 1連接至位元線BL 1，位元線BL 1連接至內部栓鎖節點IN_LAT，電晶體M1、M4~M6截止，並且位元線BL 1上的資料可易於寫入到三態反相器310的輸入端IE；當Y解碼信號YD1禁能且頁面緩衝致能信號ENPGBUF致能時，亦即分頁緩衝器120寫入資料至記憶體陣列110，資料線DL 1斷開與位元線BL 1的連接，位元線BL 1連接至內部栓鎖節點IN_LAT，電晶體M1、M4導通，並且栓鎖的資料將會透過位元線BL 1寫入至記憶體陣列110；一但頁面緩衝致能信號ENPGBUF禁能時，位元線BL 1斷開與內部栓鎖節點IN_LAT的連接，電晶體M5及M6導通，此時資料是閂鎖在緩衝單元121中的內部栓鎖節點IN_LAT。
圖4為依據本發明一實施例的解碼單元的電路示意圖。請參照圖1、圖2及圖4，在本實施例中，各個解碼單元131包括第二傳輸閘TR2。第二傳輸閘TR2的第一端耦接對應的位元線BL，第二傳輸閘TR2的第二端耦接對應的資料線DL 1，第二傳輸閘TR2的正控制端接收Y解碼信號YD1，第二傳輸閘TR2的負控制端接收反相Y解碼信號的ZYD1。當Y解碼信號YD1致能時（例如為高電壓準位），亦即反相Y解碼信號的ZYD1F為禁能（例如為低電壓準位），第二傳輸閘TR2會導通，亦即開啟Y解碼器130；反之，當Y解碼信號YD1禁能時，第二傳輸閘TR2會截止，亦即關閉Y解碼器130。在本發明的一實施例中，一分頁為M個位元組，位元線（如BL 1、BL 2）的數目N為M的8倍，亦即N=8Xm。因此，一條資料線（如DL 1、DL 2）連接至M個解碼單元131。並且，位元線會是BL 1~BL N，Y解碼信號會是YD1~YDN，並且反相Y解碼信號會是ZYD1~ZYDN。
在本發明一實施例中，各個位元線對應一Y解碼信號（如YD1~YDN）及一反相Y解碼信號（如ZYD1~ZYDN），並且解碼信號（如YD1~YDN）可以是部分致能、部分禁能、全部致能或全部禁能。緩衝單元（如121）的第一傳輸閘TR1接收同一頁面緩衝致能信號（如ENPGBUF）及同一反相頁面緩衝致能信號（如ZENPGBUF），亦即緩衝單元（如121）所接收的頁面緩衝致能信號（如ENPGBUF）為全部致能或全部禁能。
在本發明一實施例中，記憶體陣列110只能進行分頁抹除操作及分頁程式化操作，亦即在同一字線上的記憶體胞（如111）是同時抹除或同時程式化。當執行一位元組寫入方案時（亦即將程式化資料PDATA寫人至記憶體陣列110），用以傳送程式化資料PDATA的位元線（如BL 1~BL N）所對應的Y解碼信號（如YD1~YDN）為致能，其他Y解碼信號（如YD1~YDN）為禁能，並且頁面緩衝致能信號（如ENPGBUF）為致能。因此，程式化資料PDATA透過寫入電路150及Y解碼器130寫入至記憶體陣列110，同時陣列資料ARDATA由分頁緩衝器120寫入至記憶體陣列110。
圖5為依據本發明一實施例的寫入單元的電路示意圖。請參照圖1、圖2及圖4，在本實施例中，各個寫入單元151包括第三傳輸閘TR3、第四傳輸閘TR4、第二反相器INV2及第三反相器INV3。第三傳輸閘TR3的第一端接收陣列資料ARDATA，第三傳輸閘TR3的正控制端接收反相資料選信號ZDSL，第三傳輸閘TR3的負控制端接收資料選信號DSL。
第四傳輸閘TR4的第一端接收程式化資料PDATA，第四傳輸閘TR4的第二端耦接第三傳輸閘TR3的第二端，第四傳輸閘TR4的正控制端接收資料選信號DSL，第四傳輸閘TR4的負控制端接收反相資料選信號ZDSL。第二反相器INV2的輸入端耦接第三傳輸閘TR3的第二端。第三反相器INV3的輸入端耦接第二反相器INV2的輸出端，第三反相器INV3的輸出端耦接對應的資料線DL 1，第三反相器INV3的控制端接收寫入致能信號ENWR。
在本實施例中，當資料選信號DSL致能時（例如為高電壓準位），亦即反相資料選信號ZDSL為禁能（例如為低電壓準位），第四傳輸閘TR4會導通，第三傳輸閘TR3會截止，亦即程式化資料PDATA會提供至第二反相器INV2；反之，當資料選信號DSL禁能時，第三傳輸閘TR3會導通，第四傳輸閘TR4會截止，亦即陣列資料ARDATA會提供至第二反相器INV2。
圖6為依據本發明一實施例的記憶體裝置的單一位元組資料寫入方法的流程圖。請參照圖6，在本實施例中，單一位元組資料寫入方法包括下列步驟。在步驟S610中，會透過寫入電路接收一位元組的一程式化資料。在步驟S620中，會透過一感測放大器及Y解碼器依據程式化資料對應的一記憶體位址讀取記憶體陣列所儲存的多位元組的一陣列資料，並且透過寫入電路及Y解碼器將陣列資料寫入至分頁緩衝器。接著，在步驟S630中，在寫入電路將陣列資料寫入至分頁緩衝器後，抹除所讀取的陣列資料的記憶體位址所對應的記憶體陣列中的記憶體胞。在步驟S640中，透過寫入電路及Y解碼器將程式化資料寫入至記憶體陣列。此時，透過分頁緩衝器將陣列資料寫入至記憶體陣列。
圖7為依據本發明另一實施例的記憶體裝置的單一位元組資料寫入方法的流程圖。請參照圖7，在本實施例中，單一位元組資料寫入方法包括下列步驟。在步驟S710中，會設定選定的一字線位址及一位元線位址。在步驟S720中，會遞增位元線位址。在步驟S730中，會讀取記憶體陣列的一分頁中未選定的一位元組的陣列資料。接著，在步驟S740中，將陣列資料儲存於分頁緩衝器中。
在步驟S750中，會判斷位元線位址是否對應此分頁中最後一個未讀取且未選定的陣列資料。當位元線位址未對應此分頁中最後一個未讀取且未選定的陣列資料時，亦即步驟S750的判斷結果為“否”，則回到步驟S720；當位元線位址是對應此分頁中最後一個未讀取且未選定的陣列資料時，亦即步驟S750的判斷結果為“是”，則停止陣列資料的讀取，並且接著執行步驟S760。
在步驟S760中，會抹除此分頁。最後，在步驟S770中，將程式化資料（亦即選定的資料）直接寫入記憶體陣列中，以更新此分頁中所儲存的資料，並且透過分頁緩衝器將陣列資料（亦即未選定的資料）寫入記憶體陣列中，以回寫此分頁中所儲存的資料。
其中，上述步驟S610、S620、S630、S640、S710、S720、S730、S740、S750、S760及S770的順序為用以說明，本發明實施例不以此為限。並且，上述步驟S610、S620、S630、S640、S710、S720、S730、S740、S750、S760及S770的細節可參照圖1至圖5的實施例所示，在此則不再贅述。
在本發明的一實施例中，假設一分頁的大小為M位元組，而單一位元組資料寫入方法可由1計數至M，亦即分頁的陣列資料是逐位元組讀取，以判斷是否進行陣列資料的讀取。換言之，當計數結果小於M時，進行陣列資料的讀取，當計數結果大於等於M時，停止陣列資料的讀取。其中，M為一整數，並且陣列資料的讀取步驟參照圖7的步驟S720至S750，在此則不再贅述。
綜上所述，本發明實施例的記憶體裝置、其週邊電路及其單一位元組資料寫入方法，其寫入電路接收未選取的陣列資料並寫入至分頁緩衝器中，並且將選取的程式化資料直接寫入至記憶體陣列中，而陣列資料透過分頁緩衝器寫入記憶體陣列中。藉此，可在一分頁寫入的記憶體陣列中進行單一位元組資料的資料更新。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100：記憶體裝置 110：記憶體陣列 111：記憶體胞 120：分頁緩衝器 121：緩衝單元 130：Y解碼器 131：解碼單元 140：感測放大器 150：寫入電路 151：寫入單元 160：字線解碼器 310：三態反相器 ARDATA：陣列資料 BL 1、BL 2：位元線 DL 1、DL 2：資料線 DSL：資料選信號 ENPGBUF：頁面緩衝致能信號 ENWR：寫入致能信號 GND：第二參考電壓 IE：輸入端 IN_LAT：內部栓鎖節點 INV1：第一反相器 INV2：第二反相器 INV3：第三反相器 M1~M6：電晶體 OE：輸出端 PDATA：程式化資料 TR1：第一傳輸閘 TR2：第二傳輸閘 TR3：第三傳輸閘 TR4：第四傳輸閘 VCC：第一參考電壓 YD1：Y解碼信號 ZDSL：反相資料選信號 ZENPGBUF：反相頁面緩衝致能信號 ZYD1：反相Y解碼信號 S610、S620、S630、S640、S710、S720、S730、S740、S750、S760、S770：步驟
圖1為依據本發明一實施例的記憶體裝置的系統示意圖。 圖2為依據本發明一實施例的記憶體陣列、Y解碼器、分頁緩衝器及寫入電路的電路示意圖。 圖3為依據本發明一實施例的緩衝單元的電路示意圖。 圖4為依據本發明一實施例的解碼單元的電路示意圖。 圖5為依據本發明一實施例的寫入單元的電路示意圖。 圖6為依據本發明一實施例的記憶體裝置的單一位元組資料寫入方法的流程圖。 圖7為依據本發明一實施例的記憶體裝置的單一位元組資料寫入方法的流程圖。
100：記憶體裝置 110：記憶體陣列 120：分頁緩衝器 130：Y解碼器 140：感測放大器 150：寫入電路 160：字線解碼器 ARDATA：陣列資料 PDATA：程式化資料

Claims (20)

  1. 一種記憶體裝置的週邊電路，包括： 一Y解碼器，耦接該記憶裝置的一記憶體陣列； 一分頁緩衝器，耦接該記憶體陣列及該Y解碼器； 一寫入電路，透過該Y解碼器耦接該記憶體陣列及該分頁緩衝器，並且接收一位元組的一程式化資料；以及 一感測放大器，耦接於該Y解碼器與該寫入電路之間，以透過該Y解碼器讀取該記憶體陣列所儲存的多位元組的一陣列資料後提供至該寫入電路； 其中，所讀取的該陣列資料是依據該程式化資料對應的一記憶體位址，所讀取的該陣列資料是透過該Y解碼器寫入至該分頁緩衝器，並且接著該程式化資料透過該寫入電路及該Y解碼器寫入至該記憶體陣列，並且該陣列資料由該分頁緩衝器寫入至該記憶體陣列。
  2. 如申請專利範圍第1項所述的週邊電路，其中該記憶體位址包括一字線位址及一位元線位址，並且該程式化資料與該陣列資料對應同一字線位址。
  3. 如申請專利範圍第2項所述的週邊電路，更包括一字線解碼器，依據該字線位址驅動該記憶體陣列。
  4. 如申請專利範圍第1項所述的週邊電路，其中該記憶體陣列具有多個記憶體胞，並且在該寫入電路將該陣列資料寫入至該分頁緩衝器後，抹除該記憶體位址對應的該些記憶體胞及該陣列資料對應的該些記憶體胞。
  5. 如申請專利範圍第1項所述的週邊電路，其中該Y解碼器及該分頁緩衝器透過多條位元線耦接至該記憶體陣列。
  6. 如申請專利範圍第5項所述的週邊電路，其中該記憶體陣列具有多個記憶體胞，該Y解碼器具有多個解碼單元，並且該分頁緩衝器具有多個緩衝單元，其中各該些解碼單元及各該些緩衝單元透過對應的位元線耦接至對應的記憶體胞。
  7. 如申請專利範圍第6項所述的週邊電路，其中各該些緩衝單元包括： 一第一傳輸閘，具有耦接對應的位元線的一第一端、耦接一內部栓鎖節點的一第二端、接收一頁面緩衝致能信號的一正控制端、以及接收一反相頁面緩衝致能信號的一負控制端； 一第一反相器，具有耦接該內部栓鎖節點的一輸入端及一輸出端； 一三態反相器，具有耦接該第一反相器的該輸出端的一輸入端、以及耦接該內部栓鎖節點的的一輸出端，其中該三態反相器受控於該頁面緩衝致能信號及一Y解碼信號。
  8. 如申請專利範圍第7項所述的週邊電路，其中該三態反相器包括： 一第一電晶體，具有接收一第一參考電壓的一第一源/汲極、接收該Y解碼信號的一第一閘極、以及一第二源/汲極； 一第二電晶體，具有耦接該第二源/汲極的一第三源/汲極、耦接該輸入端的一第二閘極、以及耦接該輸出端的一第四源/汲極； 一第三電晶體，具有耦接該輸出端的一第五源/汲極、耦接該輸入端的一第三閘極、以及一第六源/汲極； 一第四電晶體，具有耦接該第六源/汲極的一第七源/汲極、接收一反相Y解碼信號的一第四閘極、以及接收一第二參考電壓的一第八源/汲極； 一第五電晶體，具有接收該第一參考電壓的一第九源/汲極、接收該頁面緩衝致能信號的一第五閘極、以及耦接該第二源/汲極的一第十源/汲極；以及 一第六電晶體，具有耦接該第六源/汲極的一第十一源/汲極、接收該反相頁面緩衝致能信號的一第六閘極、以及接收該第二參考電壓的一第十二源/汲極。
  9. 如申請專利範圍第8項所述的週邊電路，其中該Y解碼器透過多條資料線耦接至該寫入電路。
  10. 如申請專利範圍第9項所述的週邊電路，其中各該些解碼單元包括： 一第二傳輸閘，具有耦接對應的位元線的一第一端、耦接對應的資料線的一第二端、接收該Y解碼信號的一正控制端、以及接收該反相Y解碼信號的一負控制端。
  11. 如申請專利範圍第9項所述的週邊電路，其中該寫入電路具有多個寫入單元，並且各該些寫入單元包括： 一第三傳輸閘，具有接收該陣列資料的一第一端、一第二端、接收一反相資料選擇信號的一正控制端、以及接收一資料選信號的一負控制端； 一第四傳輸閘，具有接收該程式化資料的一第一端、耦接該第三傳輸閘的該第二端的一第二端、接收該資料選信號的一正控制端、以及接收該反相資料選擇信號的一負控制端； 一第二反相器，具有耦接該第三傳輸閘的該第二端的一輸入端及一輸出端；以及 一第三反相器，具有耦接該第二反相器的該輸出端的一輸入端、耦接對應的資料線的一輸出端以及接收一寫入致能信號的一控制端。
  12. 如申請專利範圍第1項所述的週邊電路，其中當該感測放大器讀取該記憶體陣列的該陣列資料時，開啟該記憶體陣列及該Y解碼器，並且關閉該分頁緩衝器，當該寫入電路將該陣列資料寫入該分頁緩衝器時，開啟該Y解碼器及該分頁緩衝器，並且關閉該記憶體陣列，當該寫入電路將該程式化資料寫入該記憶體陣列時，開啟該記憶體陣列、該分頁緩衝器及該Y解碼器，當該陣列資料由該分頁緩衝器寫入該記憶體陣列時，開啟該記憶體陣列及該分頁緩衝器，並且關閉該Y解碼器。
  13. 一種記憶體裝置，包括： 一記憶體陣列；以及 如申請專利範圍第1項所述的週邊電路，耦接該記憶體陣列，並且接收一位元組的一程式化資料，以將該程式化資料寫入該記憶體陣列。
  14. 一種記憶體裝置的單一位元組資料寫入方法，包括： 透過一寫入電路接收一位元組的一程式化資料； 透過一感測放大器及一Y解碼器依據該程式化資料對應的一記憶體位址讀取一記憶體陣列所儲存的多位元組的一陣列資料，並且透過該寫入電路及該Y解碼器將該陣列資料寫入至一分頁緩衝器； 透過該寫入電路及該Y解碼器將該程式化資料寫入至該記憶體陣列；以及 透過該分頁緩衝器將該陣列資料寫入至該記憶體陣列。
  15. 如申請專利範圍第14項所述的單一位元組資料寫入方法，其中該記憶體位址包括一字線位址及一位元線位址，並且該程式化資料與該陣列資料對應同一字元位址。
  16. 如申請專利範圍第14項所述的單一位元組資料寫入方法，其中該記憶體陣列具有多個記憶體胞，並且該單一位元組資料寫入方法更包括： 在該寫入電路將該陣列資料寫入至該分頁緩衝器後，抹除該記憶體位址對應的該些記憶體胞及該陣列資料對應的該些記憶體胞。
  17. 如申請專利範圍第14項所述的單一位元組資料寫入方法，更包括： 當該感測放大器讀取該記憶體陣列的該陣列資料時，開啟該記憶體陣列及該Y解碼器，並且關閉該分頁緩衝器； 當該寫入電路將該陣列資料寫入該分頁緩衝器時，開啟該Y解碼器及該分頁緩衝器，並且關閉該記憶體陣列； 當該寫入電路將該程式化資料寫入該記憶體陣列時，開啟該記憶體陣列、該分頁緩衝器及該Y解碼器：以及 當該陣列資料由該分頁緩衝器寫入該記憶體陣列時，開啟該記憶體陣列及該分頁緩衝器，並且關閉該Y解碼器。
  18. 如申請專利範圍第14項所述的單一位元組資料寫入方法，其中在透過該寫入電路及該Y解碼器將該程式化資料寫入至該記憶體陣列時，同時透過該分頁緩衝器將該陣列資料寫入至該記憶體陣列。
  19. 如申請專利範圍第14項所述的單一位元組資料寫入方法，其中“透過該感測放大器及該Y解碼器依據該程式化資料對應的該記憶體位址讀取該記憶體陣列所儲存的該多位元組的該陣列資料，並且透過該寫入電路及該Y解碼器將該陣列資料寫入至該分頁緩衝器”的步驟包括： A) 設定對應該程式化資料的該記憶體位址的一字線位址及一位元線位址； B) 遞增該位元線位址； C) 依據遞增的該位元線位址透過該感測放大器及該Y解碼器讀取在該記憶體陣列的一分頁中的一位元組的該陣列資料 D) 透過該寫入電路及該Y解碼器將該陣列資料寫入該分頁緩衝器；以及 E)當遞增的該位元線位址非對應該分頁中最後未讀取的該陣列資料時，重復步驟B至E，其中最後未讀取的該陣列資料非對應該記憶體位址的該位元線位址。
  20. 如申請專利範圍第14項所述的單一位元組資料寫入方法，其中在該記憶體陣列的一分頁的大小為M位元組，並且“依據該程式化資料對應的該記憶體位址讀取該記憶體陣列所儲存的該多位元組的該陣列資料”的步驟包括： 由1計數至N以產生一計數結果，其中M為一整數； 當該計數結果小於M時，讀取一位元組的該陣列資料；以及 當該計數結果等於M時，停止該陣列資料的讀取。
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