CN107017023A - 存储阵列 - Google Patents
存储阵列 Download PDFInfo
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- CN107017023A CN107017023A CN201710040607.6A CN201710040607A CN107017023A CN 107017023 A CN107017023 A CN 107017023A CN 201710040607 A CN201710040607 A CN 201710040607A CN 107017023 A CN107017023 A CN 107017023A
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- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 6
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- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G11C16/02—Erasable programmable read-only memories electrically programmable
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- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
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- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
本发明公开了一种存储阵列,包括多个存储分页,每一存储分页包括多个存储单元,每一存储单元包括浮接栅极模块、控制组件及清除组件。浮接栅极模块设置于第一井区、清除组件设置于第二井区,而控制组件设置于第三井区。第一井区、第二井区及第三井区设置于相同的深参杂区,且多个存储分页中的存储单元都设置于相同的深参杂区。因此,深参杂区之间的隔离空间规则就不会造成存储阵列的面积限制,使得存储阵列的面积能够降低。
Description
技术领域
本发明是有关于一种存储阵列,尤其是一种存储单元能够共享深参杂区的存储阵列。
背景技术
电子可重复写入的非挥发性存储器是一种在没有电源供应时仍然能够保存储存的信息,并且能够允许在电路板上被重复写入的存储器。由于这种非挥发性存储器所能应用的范围相当广泛,因此将非挥发性存储器与其他主要电路嵌入在同一芯片的需求也日益成长,尤其是在对电路面积要求相当严苛的个人电子装置,隔外需要将非挥发性存储器与其他电路嵌入在同一芯片中。
现有技术的非挥发性存储器包括用来储存数据的浮接栅极晶体管,以及一个或两个用来致能浮接栅极晶体管以执行对应操作的选择晶体管。浮接栅极的写入操作及清除操作可由耦合组件来控制。由于在不同存储分页的存储单元需能够独立控制,在不同存储分页的存储单元通常会被设置在不同的隔离区域。然而因为半导体制程的隔离空间规则(spacing rule),不同隔离区之间的隔离空间会显著地增加电路面积。此外,由于在隔离空间上不能设置任何组件,因此增加出来的电路面积也无法利用而造成浪费。
发明内容
本发明之一实施例提供一种存储阵列,存储阵列包括多个存储分页,每一存储分页包括多个存储单元,每一存储单元包括浮接栅极模块,控制组件,及清除组件。
浮接栅极模块包括浮接栅极晶体管,浮接栅极模块根据源极线、位线及字符线控制浮接栅极晶体管,浮接栅极晶体管具有第一端、第二端,及浮接栅极。
控制组件具有基极端耦接于控制线、第一端耦接于基极端、第二端耦接于基极端,及控制端耦接于浮接栅极。
清除组件具有基极端、第一端耦接于清除线、第二端耦接于清除组件的第一端或浮接,及控制端耦接于浮接栅极。清除组件的基极端在所述存储单元的写入操作或写入禁止操作期间接收第一电压,并在存储单元的清除操作期间接收第二电压。
浮接栅极模块是设置于第一井区,清除组件是设置于第二井区,而控制组件是设置于第三井区。第一井区、第二井区及第三井区是设置于深参杂区。多个存储分页的多个存储单元是设置于相同的深参杂区。在写入操作期间,控制线是处在第一电压,而在清除操作期间,清除线是处在第二电压。
附图说明
图1为本发明一实施例的存储阵列的示意图。
图2为本发明一实施例的存储阵列的布局图。
图3为图2中清除组件的剖面图。
图4为图1的存储单元在其写入操作期间所接收的信号电压示意图。
图5为图1的存储单元在其清除操作期间所接收的信号电压示意图。
图6为本发明另一实施例的存储阵列的示意图。
图7为图6的存储单元在其清除操作期间所接收的信号电压示意图。
图8为本发明另一实施例的存储阵列的示意图。
图9为图8的存储单元在其写入操作期间所接收的信号电压示意图。
图10为图8的存储单元在其清除操作期间所接收的信号电压示意图。
图11为本发明另一实施例的存储阵列的示意图。
图12为图11的存储单元在其清除操作期间所接收的信号电压示意图。
其中,附图标记说明如下:
10、20、30、40 存储阵列
MP1至MPM 存储分页
1001,1至100M,N、2001,1至200M,N、 存储单元
3001,1至300M,N、4001,1至400M,N
110、310 浮接栅极模块
112、312 浮接栅极晶体管
114、314 源极晶体管
116 位晶体管
120 控制组件
130 清除组件
132 清除组件的基极端
134 清除组件的第一端
136 清除组件的第二端
138 清除组件的控制端
SL1至SLN 源极线
BL1至BLN 位线
CL1至CLM 控制线
EL0、EL1至ELM 清除线
WL1至WLM 字符线
WBL 井偏压线
DR 深参杂区
PW1、PW2、PW3 P型井区
AAF1、AAF2、AAE1、AAE2、 主动区
AAC1
NW1、NW2、NW N型井区
P+ P型参杂区
DNW N型深井区
VPP 第一电压
VEE 第二电压
VEE’ 第三电压
VINH1 第四电压
VSS 第五电压
VPP’ 第六电压
VINH2 第七电压
具体实施方式
图1为本发明一实施例的存储阵列10的示意图。存储阵列10包括M个存储分页MP1至MPM。每一存储分页MP1至MPM包括N个存储单元。举例来说,存储分页MP1包括存储单元1001,1及1001,N,而存储分页MPM包括存储单元100M,1及100M,N。M及N为正整数。
在本发明的部分实施例中,同一存储分页中的存储单元可耦接至相同的控制线、相同的清除线及相同的字符线,并耦接至相异的源极线及相异的位线。举例来说,存储分页MP1中的存储单元1001,1及1001,N会耦接至相同的控制线CL1、相同的清除线EL1及相同的字符线WL1。然而存储单元1001,1会耦接至源极线SL1及位线BL1,而存储单元1001,N则会耦接至源极线SLN及位线BLN。
此外,在相异存储分页中但位于相同一行的存储单元则可耦接至相异的控制线、相异的清除线及相异的字符线,并可耦接至相同的源极线及相同的位线。举例来说,存储单元1001,1及100M,1是位于相同一行但相异存储分页中的两个存储单元,而存储单元1001,1及100M,1会耦接至相同的源极线SL1及相同的位线BL1。然而,存储单元1001,1会耦接至控制线CL1、清除线EL1及字符线WL1且存储单元100M,1会耦接至控制线CLM、清除线ELM及字符线WLM。
在图1中,存储单元1001,1至1001,N、…、及100M,1至100M,N可具有相同的结构。每一个存储单元可包括浮接栅极模块110、控制组件120及清除组件130。浮接栅极模块110可包括浮接栅极112、源极晶体管114及位晶体管116。浮接栅极模块110可以根据源极线、位线及字符线来控制浮接栅极晶体管112。
浮接栅极晶体管112具有第一端、第二端及浮接栅极。源极晶体管114具有第一端、第二端及控制端。源极晶体管114的第一端耦接于对应的源极线。举例来说,存储单元1001,1的源极晶体管114的第一端可耦接于源极线SL1,而存储单元1001,N的源极晶体管114的第一端可耦接于源极线SLN。源极晶体管114的第二端耦接于浮接栅极晶体管112的第一端,而源极晶体管114的控制端可耦接至对应的字符线WL1。举例来说,存储单元1001,1的源极晶体管114的控制端可耦接于源极线WL1,而存储单元100M,1的源极晶体管114的控制端可耦接于源极线WLM。
位晶体管116具有第一端、第二端及控制端。位晶体管116的第一端耦接于浮接栅极晶体管112的第二端,位晶体管116的第二端耦接于对应的位线,而位晶体管116的控制端耦接于对应的字符线。举例来说,存储单元1001,1的位晶体管116的第二端可耦接于位线BL1,而存储单元1001,N的位晶体管116的第二端可耦接于位线BLN。此外,存储单元1001,1的位晶体管116的控制端可耦接于字符线WL1,而存储单元100M,1的位晶体管116的控制端可耦接于字符线WLM。
控制组件120具有第一端、第二端、控制端及基极端,控制组件120的第一端及第二端耦接至基极端,控制组件120的控制端耦接至浮接栅极晶体管112的浮接栅极,而控制组件120的基极端耦接至对应的控制线。举例来说,存储单元1001,1的控制组件120的基极端可耦接于控制线CL1,而存储单元100M,1的控制组件120的基极端可耦接于控制线CLM。
清除组件130具有第一端、第二端、控制端及基极端。清除组件130的第一端134耦接于对应的清除线。举例来说,存储单元1001,1的清除组件130的第一端可耦接于清除线EL1,而存储单元100M,1的清除组件130的第一端可耦接于清除线ELM。清除组件130的第二端136可耦接至清除组件130的第一端或者浮接,清除组件130的控制端138可耦接至浮接栅极晶体管112的浮接栅极,而清除组件130的基极端132可耦接至井偏压线WBL。
图2为本发明一实施例的存储阵列10的布局图。存储单元1001,1的浮接栅极模块110可设置于第一P型井区PW1的主动区AAF1,存储单元1001,1的清除组件130可设置于第一N型井区NW1的主动区AAE1,而存储单元1001,1的控制组件120则可设置于第二P型井区PW2的主动区AAC1。第一P型井区PW1、第一N型井区NW1及第二P型井区PW2可设置于相同的深参杂区DR。在部分实施例中,深参杂区DR可为N型深井区(deep N-well)或N型埋层(N-typeburied layer)。
图3为图2中清除组件130的剖面图。在图3中,清除组件130的结构与P型金氧半晶体管的结构相似。也就是说,清除组件130的基极端132可为N型井区NW,清除组件130的第一端134及第二端136可为设置于N型井区NW中的两个P型参杂区P+。在图3中,井偏压线WBL可直接耦接至基极端132。然而在其他实施例中,井偏压线WBL也可例如经由接触点(contact)或是在N型井区NW中的N型参杂区来耦接至N型井区NW。浮接栅极晶体管112的浮接栅极可耦接至清除组件130的控制端138以形成栅极结构。由于清除线EL会耦接至清除组件130的第一端134,因此存储单元1001,1至1001,N、…、及100M,1至100M,N可以在其清除组件130的基极端132都耦接至相同的井偏压线WBL的情况下,维持正确的操作。也就是说,透过耦接至相同的井偏压线WBL,存储单元1001,1至1001,N、…、及100M,1至100M,N可以设置于相同的深参杂区DR。
举例来说,在图2中,存储单元1001,N的浮接栅极模块110可以设置在第三P型井区PW3的主动区AAF2,存储单元1001,N的清除组件130可设置于第二N型井区NW2的主动区AAE2,而存储单元1001,N的控制组件120可设置于第二P型井区PW2的主动区AAC1。然而第三P型井区PW3及第二N型井区NW2可设置在相同的深参杂区DR。
此外,虽然存储单元100M,1至100M,N的浮接栅极模块、控制组件及清除组件可如同图2所示设置于相异的井区当中,但是存储单元100M,1至100M,N仍然可同样设置在深参杂区DR中。也就是说,M个存储分页MP1至MPM中的存储单元1001,1至1001,N、…、及100M,1至100M,N可以设置在相同的深参杂区DR中。由于存储阵列10中相异的存储分页MP1至MPM可设置在同一个深参杂区DR中,深参杂区DR之间的隔离空间规则就不会造成存储阵列10的面积限制,因此存储阵列10的面积能够显著的降低。
在图2中,位于相同存储分页的存储单元的控制组件120,例如位于相同存储分页MP1的存储单元1001,1至1001,N的控制组件120,可设置于相同的第二P型井区PW2。存储单元1001,1至1001,N的浮接栅极模块110可设置在第二P型井区PW2的相对两侧的相异P型井区PW1及PW3。存储单元1001,1至1001,N的清除组件130也可设置在第二P型井区PW2的相对两侧的相异N型井区NW1及NW2。因此,存储阵列10的布局能够不沿着单一方向延伸,而可增加其布局安排的弹性。然而,在部分实施例中,根据实际系统的需求,位于相同存储分页的存储单元的浮接栅极模块110可接设置在同一个P型井区中,而位于相同存储分页的存储单元的清除组件130也可接设置在同一个N型井区中。
图4为存储阵列10的存储单元1001,1于其写入操作期间所接收的信号电压示意图。在图4中,第一电压VPP可实质上与第二电压VEE相等。第一电压VPP可大于第三电压VEE’,第三电压VEE’可大于第四电压VINH1,而第四电压VINH1可大于第五电压VSS。此外,第一电压VPP可大于第六电压VPP’,且第六电压VPP’可大于第五电压VSS。
在部分实施例中,第三电压VEE’与第五电压VSS之间的差值可大于第一电压VPP与第五电压VSS之间的差值的一半。第四电压VINH1与第五电压VSS之间的差值可小于第一电压VPP与第五电压VSS之间的差值的一半,而第六电压VPP’与第五电压VSS之间的差值可小于第一电压VPP与第五电压VSS之间的差值的一半。举例来说,若第一电压VPP为18V,第二电压VEE介于17V至18V,且第五电压VSS为0V,则第三电压VEE’可为13V,第四电压VINH1可为6V,而第六电压VPP’可为6V。
在图4中,在存储单元1001,1的写入操作期间,控制线CL1可处在第一电压VPP,清除线EL1可处在第三电压VEE’,字符线WL1可处在第四电压VINH1,源极线SL1可处在第五电压VSS,而位线BL1可处在第五电压VSS。
在此情况下,存储单元1001,1的控制组件120会透过控制线CL1耦接至高电压。源极晶体管114及位晶体管116都会被导通,使得存储单元1001,1的浮接栅极晶体管112的第一端及第二端会被拉至低电压。因此施加在浮接栅极晶体管112上的巨大电压差将会引致福诺(Fowler Nordheim)电子穿隧使得电子注入浮接栅极,使得存储单元1001,1被写入。此外。为避免存储阵列10中的P型井区及N型井区之间产生漏电流,井偏压线WBL可设定为不小于所有信号线中的最高电压。在此情况下,井偏压线WBL可处在第一电压VPP。
再者,在存储单元1001,1的写入操作期间,为避免与存储单元1001,1位于相同存储分页MP1的存储单元1001,N被写入,存储单元1001,N可在存储单元1001,1的写入操作期间执行禁止写入操作。在存储单元1001,N的禁止写入操作期间,控制线CL1可处在第一电压VPP,清除线EL1可处在第三电压VEE',字符线WL1可处在第四电压VINH1,源极线SLN可处在第四电压VINH1,而位线BLN可处在第四电压VINH1。
在此情况下,虽然存储单元1001,N会与存储单元1001,1耦接至相同的控制线CL1、清除线EL1及字符线WL1,但由于存储单元1001,N的源极晶体管114及位晶体管116所造成的通道抬升效应(channel boost effect),存储单元1001,N仍不会被写入。也就是说,浮接栅极晶体管112的第一端及第二端的电压会被抬升至高于第四电压VINH1的电压,使得存储单元1001,N的浮接栅极无法捕捉足够的电子,因此存储单元1001,N不会被写入。此外,由于控制线CL1为第一电压VPP,因此井偏压线WBL在存储单元1001,N的禁止写入期间仍会维持在第一电压VPP。
此外,在存储单元1001,1的写入操作期间,未被选定的存储分页中的存储单元,例如存储分页MPM中的存储单元也不应被写入。因此在图4中,耦接至未被选定的存储分页MPM的存储单元100M,1的控制线CLM可处在第六电压VPP’,耦接至未被选定的存储单元100M,1的清除线ELM可处在第三电压VEE’,而耦接至未被选定的存储单元100M,1的字符线WLM可处在第四电压VINH1。
由于存储单元100M,1的清除组件130的基极端会耦接至井偏压线WBL,且此时井偏压线WBL可处在第一电压VPP,因此清除线ELM电压不可过低,否则清除组件130将会崩溃。同时,清除线ELM的电压亦不得过高,否则存储单元100M,1的浮接栅极将会不预期地被写入。因此在存储单元1001,1的写入操作期间,清除线ELM可设定在第三电压VEE’。第三电压VEE’与第五电压VSS之间的差值可略大于第一电压VPP与第五电压VSS之间的差值的一半。在此情况下,清除组件130将不会崩溃,而存储单元100M,1也不会被误写入。
此外,控制线CLM的电压不应过低,否则存储单元100M,1可能会不稳定。因此在存储单元1001,1的写入操作期间,控制线CLM可为第六电压VPP’,且第六电压VPP’与第五电压VSS之间的差值可略小第一电压VPP与第五电压VSS之间的差值的一半。在此情况下,存储单元100M,1就能够保持稳定。
此外,由于位于同一行但不同存储分页的存储单元会耦接至相同的源极线及位线,因此字符线WLM可处在第四电压VINH1以减少栅极引致漏极漏电流(gate-induceddrain leakage,GIDL)。举例来说,在存储单元1001,1的写入操作期间,亦即存储单元1001,N的禁止写入操作期间,耦接至存储单元100M,N的源极线SLN及位线BLN可都为第四电压VINH1。此时若字符线WLM处在第五电压VSS,则第四电压VINH1与第五电压VSS之间的大电压差将可能导致存储单元100M,N的源极晶体管114及位晶体管116产生栅极引致漏极漏电流。然而,倘若字符线WLM同样是处在第四电压VINH1,就可以在不影响其他存储单元的操作的情况下,避免栅极引致漏极漏电流的产生。
图5为存储阵列10的存储单元1001,1于其清除操作期间所接收的信号电压示意图。在存储单元1001,1的清除操作期间,清除线EL1可处在第二电压VEE,字符线WL1可处在第四电压VINH1或第五电压VSS,源极线SL1可处在第四电压VINH1,位线BL1可处在第四电压VINH1,而控制线CL1可处在第五电压VSS。
在此情况下,清除线EL1的高电压可能会引致福诺穿隧,使得存储单元1001,1能够被清除。此外,在存储单元1001,1的清除操作期间,由于清除线EL1处在第二电压VEE,并为所有信号线中具有最高电压者,因此井偏压线WBL也可处在第二电压VEE。
在部分实施例中,存储阵列10可整页清除。也就是说,相同存储分页中的存储单元,例如存储分页MP1中的存储单元1001,1至1001,N,会同时被清除。在此情况下,耦接至存储单元1001,1至1001,N的源极线SL1至SLN及位线BL1至BLN可都处在较低的电压。举例来说,源极线SL1至SLN及位线BL1至BLN可都处在第四电压VINH1或第五电压VSS。第四电压VINH1与第五电压VSS之间的差值可小于第二电压VEE与第五电压VSS之间的差值的一半。
此外,在存储单元1001,1的清除操作期间,未被选定的存储分页的存储单元,例如存储分页MPM中的存储单元,则不应被清除。举例来说,为避免未被选定的存储分页MPM中的存储单元100M,1被清除,清除线ELM的电压不应过高。然而,由于井偏压线WBL会处在第二电压VEE,因此清除线ELM的电压亦不宜过低,否则存储单元100M,1的清除组件130可能会崩溃。因此,在图5中,清除线ELM可处在第三电压VEE'。第三电压VEE’与第五电压VSS之间的差值可略大于第二电压VEE与第五电压VSS之间的差值的一半。
在此情况下,清除线ELM的电压就不会高到足以清除存储单元100M,1,也不至于低到使清除组件130崩溃。控制线CLM可处在第六电压VPP’,使得存储单元100M,1不会因为清除线ELM的电压而不预期地被写入或清除。在图5中,第六电压VPP’与第五电压VSS之间的差值可小于第二电压VEE与第五电压VSS之间的差值的一半。相似地,字符线WLM、源极线SL1和位线BL1可处在相近的电压,因此可以避免存储单元100M,1因为清除线ELM的电压而不预期地被写入或清除,同时也可以避免栅极引致漏极漏电流。在部分实施例中,字符线WLM、源极线SL1及位线BL1可都处在第四电压VINH1。
在部分实施例中,存储阵列也可以整个区段(sector)一起清除。也就是说,存储阵列中的所有存储单元都可以同时清除。图6为本发明一实施例的存储阵列20的示意图。存储阵列10与存储阵列20具有相似的结构。两者的差异主要在于存储单元2001,1至2001,N、…、及200M,1至200M,N都会耦接至相同的清除线EL0,因此存储阵列20中的存储单元2001,1至2001,N、…、及200M,1至200M,N会同时被清除。
图7为存储阵列20的存储单元2001,1于其清除操作期间所接收的信号电压示意图。
在存储单元2001,1的清除操作期间,清除线EL0可处在第二电压VEE,控制线电压CL1可处在第五电压VSS,源极线SL1及位线BL1会同样处在第四电压VINH1或同样处在第五电压VSS,而字符线WL1则会处在第四电压VINH1或第五电压VSS。
在此情况下,清除线EL0上的高电压能够引致福诺电子穿隧,使得存储单元2001,1会被清除。为了同时清除存储阵列20中的存储单元2001,1至2001,N、…、及200M,1至200M,N,存储单元2001,1至2001,N、…、及200M,1至200M,N可以接收到相同的控制电压。
此外,在前述的操作过程中,存储单元的写入操作期间及禁止写入期间,清除线EL0会处在第三电压VEE’,因此存储阵列20在写入操作期间及禁止写入期间可以与存储阵列10根据相同的原理操作,如图4所示。
如此一来,存储阵列20的存储单元2001,1至2001,N、…、及200M,1至200M,N就能够设置在相同的深参杂区。由于存储阵列20中的存储分页MP1至MPM可以设置在同一个深参杂区,因此深参杂区之间的隔离空间规则就不会造成存储阵列20的面积限制,因此存储阵列20的面积能够显著的降低。此外,由于存储阵列20的存储单元2001,1至2001,N、…、及200M,1至200M,N会耦接至相同的清除线,因此还能够简化控制清除线电压的驱动电路,进而减少存储阵列20整体所需的面积。
图8为本发明一实施例的存储阵列30的示意图。存储阵列10与存储阵列30具有相似的结构。两者的差异主要在于存储单元3001,1至3001,N、…、及300M,1至300M,N的浮接栅极模块310、控制组件120及清除组件130。
浮接栅极模块310包括浮接栅极312及源极晶体管314。浮接栅极晶体管312具有第一端、第二端及浮接栅极。浮接栅极晶体管312的第二端耦接于对应的位线。举例来说,存储单元3001,1的浮接栅极晶体管312的第二端可耦接至位线BL1,而存储单元3001,N的浮接栅极晶体管312的第二端则会耦接至位线BLN。浮接栅极晶体管312的浮接栅极会耦接至控制组件120及清除组件130。
源极晶体管314具有第一端、第二端及控制端。源极晶体管314的第一端耦接于对应的源极线。举例来说,存储单元3001,1的源极晶体管314的第一端会耦接至源极线SL1,而存储单元3001,N的源极晶体管314的第一端会耦接至源极线SLN。源极晶体管314的第二端耦接于浮接栅极晶体管312的第一端,而源极晶体管314的控制端则会耦接至对应的字符线。举例来说,存储单元3001,1的源极晶体管314的控制端会耦接至字符线WL1,而存储单元300M,1的源极晶体管314的控制端会耦接至字符线WLM。
图9为存储阵列30的存储单元3001,1于其写入操作期间所接收的信号电压示意图。
在图9中,在存储单元3001,1的写入操作期间,控制线CL1可处在第一电压VPP,清除线EL1可处在第三电压VEE’,字符线WL1可处在第四电压VINH1,源极线SL1可处在第五电压VSS,而位线BL1可处在第五电压VSS。
在此情况下,存储单元3001,1的控制组件120会透过控制线CL1耦接至高电压。源极晶体管314会被导通,使得存储单元3001,1的浮接栅极晶体管312的第一端及第二端会被拉至低电压。因此施加在浮接栅极晶体管312上的巨大电压差将会引致福诺电子穿隧使得电子注入浮接栅极,使得存储单元3001,1被写入。此外。为避免存储阵列30中的P型井区及N型井区之间产生漏电流,井偏压线WBL可设定为不小于所有信号线中的最高电压。在此情况下,井偏压线WBL可处在第一电压VPP。
再者,在存储单元3001,1的写入操作期间,为避免与存储单元3001,1位于相同存储分页MP1的存储单元3001,N被写入,存储单元3001,N可在存储单元3001,1的写入操作期间执行禁止写入操作。在存储单元3001,N的禁止写入操作期间,控制线CL1可处在第一电压VPP,清除线EL1可处在第三电压VEE',字符线WL1可处在第四电压VINH1,源极线SLN可处在第七电压VINH2,而位线BLN可处在第七电压VINH2。
由于浮接栅极晶体管312的第二端会耦接至对应的位线,因此可透过让位元线BLN具有较高的电压来避免存储单元3001,N被写入。在此情况下,位线BLN可为第七电压VINH2。第七电压VINH2与第五电压VSS之间的电压差应小于浮接栅极晶体管312的源极/漏极的接面崩溃电压。举例来说,若浮接栅极晶体管312的源极/漏极的接面崩溃电压为9V,则第七电压VINH2可为8V。
在此情况下,虽然存储单元3001,N会与存储单元3001,1耦接至相同的控制线CL1、清除线EL1及字符线WL1,但由于存储单元3001,N的浮接栅极晶体管112的第一端及第二端的电压会被抬升至较高的电压,因此存储单元3001,N仍不会被写入。此外,由于控制线CL1为第一电压VPP,因此井偏压线WBL在存储单元3001,N的禁止写入期间仍会维持在第一电压VPP。
此外,在存储单元3001,1的写入操作期间,未被选定的存储分页中的存储单元,例如存储分页MPM中的存储单元也不应被写入。因此在图9中,耦接至未被选定的存储分页MPM的存储单元300M,1的控制线CLM可处在第六电压VPP’,耦接至未被选定的存储单元300M,1的清除线ELM可处在第三电压VEE’,而耦接至未选定的存储单元300M,1的字符线WLM可处在第四电压VINH1。在图9中,第六电压VPP’与第五电压VSS之间的差值可小于第一电压VPP与第五电压VSS之间的差值的一半。
由于在存储单元3001,1的写入操作期间,清除线ELM可设定在第三电压VEE’,因此清除组件130将不至于崩溃,而存储单元300M,1也不会被误写入。此外,控制线CLM则M可为第六电压VPP’,以确保存储单元300M,1不会被写入。
此外,由于位于同一行但不同存储分页的存储单元会耦接至相同的源极线及位线,因此字符线WLM可处在第四电压VINH1以减少栅极引致漏极漏电流(gate-induceddrain leakage,GIDL)。举例来说,在存储单元3001,1的写入操作期间,亦即存储单元3001,N的禁止写入操作期间,耦接至存储单元300M,N的源极线SLN及位线BLN可都为第七电压VINH2。此时若字符线WLM处在第五电压VSS,则逆向电压将可能导致存储单元300M,N的源极晶体管314产生栅极引致漏极漏电流。然而,倘若字符线WLM同样是处在第七电压VINH2,就可以在不影响其他存储单元的操作的情况下,避免栅极引致漏极漏电流的产生。
图10为存储阵列30的存储单元3001,1于其清除操作期间所接收的信号电压示意图。
在存储单元3001,1的清除操作期间,清除线EL1可处在第二电压VEE,控制线CL1可处在第五电压VSS,源极线SL1及位线BL1可同样处在第四电压VINH1或同样处在第五电压VSS,而字符线WL1可处在第四电压VINH1或第五电压VSS。
在此情况下,清除线EL1的高电压可能会引致福诺穿隧,使得存储单元3001,1能够被清除。此外,在存储单元3001,1的清除操作期间,由于清除线EL1处在第二电压VEE,并为所有信号线中具有最高电压者,因此井偏压线WBL也可处在第二电压VEE。
此外,在存储单元3001,1的清除操作期间,未被选定的存储分页的存储单元,例如存储分页MPM中的存储单元,则不应被清除。举例来说,为避免未被选定的存储分页MPM中的存储单元300M,1被清除,清除线ELM的电压不应过高。然而,由于井偏压线WBL会处在第二电压VEE,因此清除线ELM的电压亦不宜过低,否则存储单元300M,1的清除组件130可能会崩溃。因此,在图10中,清除线ELM可处在第三电压VEE'。
在此情况下,清除线ELM的电压就不会高到足以清除存储单元300M,1,也不至于低到使清除组件130崩溃。根据清除线ELM的电压,控制线CLM则可处在第六电压VPP。在图5中,第六电压VPP’与第五电压VSS之间的差值可小于第二电压VEE与第五电压VSS之间的差值的一半。此外,字符线WLM、源极线SL1和位线BL1可处在相近的电压,因此可以避免存储单元300M,1因为清除线ELM的电压而不预期地被写入或清除,同时也可以避免栅极引致漏极漏电流。在部分实施例中,字符线WLM、源极线SL1及位线BL1可都处在第四第电压VINH1。由于耦接至存储单元3001,1的清除线EL1会处在更高的电压,亦即第二电压VEE,而耦接至存储单元3001,1的控制线CL1会处在低电压,亦即第五第压VSS,因此在源极线SL1及位线SBL1处在第四电压VINH1的情况下,存储单元3001,1仍然可以正常清除。
此外,在部分实施例中,存储阵列30可整页清除。也就是说,相同存储分页中的存储单元,例如存储分页MP1中的存储单元3001,1至3001,N,会同时被清除。在此情况下,在清除操作期间,耦接至存储单元3001,1至3001,N的源极线SL1至SLN及位线BL1至BLN可都处在第四电压VINH1。
在部分实施例中,存储阵列也可以整个区段(sector)一起清除。也就是说,存储阵列中的所有存储单元都可以同时清除。图11为本发明一实施例的存储阵列40的示意图。存储阵列40与存储阵列30具有相似的结构。两者的差异主要在于存储单元4001,1至4001,N、…、及400M,1至400M,N都会耦接至相同的清除线EL0,因此存储阵列40中的存储单元4001,1至4001,N、…、及400M,1至400M,N会同时被清除。
图12为存储阵列40的存储单元4001,1于其清除操作期间所接收的信号电压示意图。
在存储单元4001,1的清除操作期间,清除线EL0可处在第二电压VEE,控制线电压CL1可处在第五电压VSS,源极线SL1及位线BL1会同样处在第四电压VINH1或同样处在第五电压VSS,而字符线WL1则会处在第四电压VINH1或第五电压VSS。在此情况下,清除线EL0的高电压将可引致福诺电子穿隧使得存储单元4001,1能被清除。
由于存储阵列40中的存储单元4001,1至4001,N、…、及400M,1至400M,N会同时被清除,因此存储单元4001,1至4001,N、…、及400M,1至400M,N可以接收到相同的控制电压。
此外,在前述的操作过程中,存储单元的写入操作期间及禁止写入期间,清除线EL0会处在第三电压VEE’,因此存储阵列40在写入操作期间及禁止写入期间可以与存储阵列30根据相同的原理操作,如图9所示。
如此一来,存储阵列40的存储单元4001,1至4001,N、…、及400M,1至400M,N就能够设置在相同的深参杂区。由于存储阵列40中的存储分页MP1至MPM可以设置在同一个深参杂区,因此深参杂区之间的隔离空间规则就不会造成存储阵列40的面积限制,因此存储阵列40的面积能够显著的降低。
综上所述,在本发明的实施例所提供的存储阵列中,位于相异存储阵列的存储单元可设置在相同的深参杂区。由于存储阵列中不同的存储分页可以设置在同一个深参杂区,因此深参杂区之间的隔离空间规则就不会造成存储阵列的面积限制,因此存储阵列的面积能够显著的降低。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (15)
1.一种存储阵列,其特征在于,包括:
多个存储分页,每一存储分页包括多个存储单元,每一存储单元包括:
浮接栅极模块,包括浮接栅极晶体管,所述浮接栅极模块用以根据源极线、位线及字符线控制所述浮接栅极晶体管,所述浮接栅极晶体管具有第一端、第二端,及浮接栅极;
控制组件,具有基极端耦接于控制线、第一端耦接于所述基极端、
第二端耦接于所述基极端,及控制端耦接于所述浮接栅极;及
清除组件,具有基极端、第一端耦接于清除线、第二端耦接于所述清除组件的所述第一端或浮接,及控制端耦接于所述浮接栅极,所述清除组件的基极端用以在所述存储单元的写入操作或写入禁止操作期间接收第一电压,及在所述存储单元的清除操作期间接收第二电压;
其中:
所述浮接栅极模块是设置于第一井区;
所述清除组件是设置于第二井区;
所述控制组件是设置于第三井区;
所述第一井区、所述第二井区及所述第三井区是设置于深参杂区;
所述多个存储分页的多个存储单元是设置于所述深参杂区;
在所述写入操作期间,所述控制线是处在所述第一电压;及
在所述清除操作期间,所述清除线是处在所述第二电压。
2.如权利要求1所述的存储阵列,其特征在于:
于相同的存储分页的多个存储单元是耦接于相同的控制线、相同的清除线,及相同的字符线;及
在相同的所述存储分页的所述多个存储单元是耦接于相异的源极线及相异的位线。
3.如权利要求1所述的存储阵列,其特征在于在所述存储单元的所述写入操作期间:
所述控制线是处在所述第一电压;
所述清除线是处在第三电压;
所述字符线是处在第四电压;
所述源极线是处在第五电压;
所述位线是处在所述第五电压;
所述第一电压大于所述第三电压,所述第三电压大于所述第四电压,所述第四电压大于所述第五电压;
所述第三电压与所述第五电压之间的差值大于所述第一电压与所述第五电压之间的差值的一半;及
所述第五电压与所述第四电压之间的差值小于所述第一电压与所述第五电压之间的所述差值的一半。
4.如权利要求3所述的存储阵列,其特征在于在所述存储单元的所述写入操作期间:
耦接于未选定存储分页的未选定存储单元的控制线是处在第六电压;
耦接于所述未选定存储单元的清除线是处在所述第三电压;及
耦接于所述未选定存储单元的字符线是处在所述第四电压;
所述第三电压是大于所述第六电压,且所述第六电压是大于所述第五电压;及
所述第六电压与所述第五电压之间的差值小于所述第一电压与所述第五电压之间的所述差值的一半。
5.如权利要求3所述的存储阵列,其特征在于在所述存储单元的所述写入禁止操作期间:
所述控制线是处在所述第一电压;
所述清除线是处在所述第三电压;
所述字符线是处在所述第四电压;
所述源极线是处在所述第四电压或第七电压;
所述位线是处在所述第四电压或所述第七电压;
所述第一电压是大于所述第七电压,且所述第七电压是大于或等于所述第四电压;及
所述第七电压与所述第五电压之间的差值小于所述浮接栅极晶体管的源极/漏极接口崩溃电压。
6.如权利要求1所述的存储阵列,其特征在于所述浮接栅极模块还包括:
源极晶体管,具有第一端耦接于所述源极线、第二端耦接于所述浮接栅极晶体管的所述第一端,及控制端耦接于所述字符线;及
位晶体管,具有第一端耦接于所述浮接栅极晶体管的所述第二端、第二端耦接于所述位线,及控制线耦接于所述字符线。
7.如权利要求6所述的存储阵列,其特征在于:
设置于相异存储分页的多个存储单元是耦接于复数条相异的控制线、复数条相异的字符线及所述清除线;
在所述存储单元的所述清除操作期间:
所述清除线是处在所述第二电压;
所述控制线是处在第五电压;及
所述源极线及所述位线是都处在第四电压或都处在所述第五电压,
而所述字符线是处在所述第四电压或所述第五电压;
所述第二电压大于所述第四电压,所述第四电压大于所述第五电压;及
所述第四电压与所述第五电压之间的差值小于所述第二电压及所述第五电压之间的差值的一半。
8.如权利要求6所述的存储阵列,其特征在于:
设置于相异存储分页的多个存储单元是耦接于复数条相异的控制线、复数条相异的字符线及复数条相异的清除线;
在所述存储单元的所述清除操作期间:
所述清除线是处在所述第二电压;
所述控制线是处在第五电压;及
所述源极线及所述位线是都处在第四电压或都处在所述第五电压,
而所述字符线是处在所述第四电压或所述第五电压;
所述第二电压大于所述第四电压,所述第四电压大于所述第五电压;及
所述第四电压与所述第五电压之间的差值小于所述第二电压及所述第五电压之间的差值的一半。
9.如权利要求8所述的存储阵列,其特征在于在所述存储单元的所述清除操作期间:
耦接于未选定存储分页的未选定存储单元的清除线是处在第三电压;
耦接于所述未选定存储单元的控制线是处在第六电压;
所述第二电压大于所述第三电压,所述第三电压大于所述第六电压,且所述第六电压大于所述第五电压;
所述第三电压与所述第五电压之间的差值大于所述第二电压与所述第五电压之间的所述差值的一半;及
所述第六电压与所述第五电压之间的差值小于所述第二电压与所述第五电压之间的所述差值的一半。
10.如权利要求1所述的存储阵列,其特征在于所述浮接栅极模块还包括:
源极晶体管,具有第一端耦接于所述源极线、第二端耦接于所述浮接栅极晶体管的所述第一端,及控制端耦接于所述字符线;
其中所述浮接栅极晶体管的所述第二端耦接于所述位线。
11.如权利要求10所述的存储阵列,其特征在于:
设置于相异存储分页的多个存储单元是耦接于复数条相异的控制线、复数条相异的字符线及所述清除线;
在所述存储单元的所述清除操作期间:
所述清除线是处在所述第二电压;
所述控制线是处在第五电压;
所述字符线是处在所述第四电压或所述第五电压;及
所述源极线及所述位线是都处在第四电压或都处在所述第五电压;
所述第二电压大于所述第四电压,所述第四电压大于所述第五电压;及
所述第四电压与所述第五电压之间的差值小于所述第二电压及所述第五电压之间的差值的一半。
12.如权利要求10所述的存储阵列,其特征在于:
设置于相异存储分页的多个存储单元是耦接于复数条相异的控制线、复数条相异的字符线及复数条相异的清除线;
在所述存储单元的所述清除操作期间:
所述清除线是处在所述第二电压;
所述控制线是处在第五电压;
所述字符线是处在所述第四电压或所述第五电压;及
所述源极线及所述位线是都处在第四电压或都处在所述第五电压;
所述第二电压大于所述第四电压,所述第四电压大于所述第五电压;及
所述第四电压与所述第五电压之间的差值小于所述第二电压及所述第五电压之间的差值的一半。
13.如权利要求12所述的存储阵列,其特征在于在所述存储单元的所述清除操作期间:
耦接于未选定存储分页的未选定存储单元的清除线是处在第三电压;
耦接于所述未选定存储单元的控制线是处在第六电压;
所述第二电压大于所述第三电压,所述第三电压大于所述第六电压,且所述第六电压大于所述第五电压;
所述第三电压与所述第五电压之间的差值大于所述第一电压与所述第五电压之间的所述差值的一半;及
所述第六电压与所述第五电压之间的差值小于所述第一电压与所述第五电压之间的所述差值的一半。
14.如权利要求1所述的存储阵列,其特征在于:
所述深参杂区是为N型深井区或N型埋层;
所述第一井区及所述第三井区是为设置于所述深参杂区的两个P型井区;
及
所述第二井区是为设置于所述深参杂区的N型井区。
15.如权利要求1所述的存储阵列,其特征在于:
相同的存储分页中多个存储单元的多个控制组件都设置于相同的第三井区。
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