CN106981492A - 非挥发性存储器结构和阵列 - Google Patents

非挥发性存储器结构和阵列 Download PDF

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CN106981492A
CN106981492A CN201610976441.4A CN201610976441A CN106981492A CN 106981492 A CN106981492 A CN 106981492A CN 201610976441 A CN201610976441 A CN 201610976441A CN 106981492 A CN106981492 A CN 106981492A
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volatile memory
memory structure
area
extension
active area
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CN106981492B (zh
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陈英哲
陈纬仁
孙文堂
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eMemory Technology Inc
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eMemory Technology Inc
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    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
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    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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Abstract

本发明公开一种非挥发性存储器结构和阵列，所述非挥发性存储器结构包括在基板中的第一有源区上的第一PMOS晶体管和第一浮置栅晶体管、在基板中的第二有源区上的第二PMOS晶体管和第二浮置栅晶体管、以及在基板中的n型抹除区。源极线连接第一和第二PMOS晶体管的源极。位线连接第一和第二浮置栅晶体管的漏极。字线分别连接位于第一和第二PMOS晶体管中的第一和第二选择栅极。抹除线连接n型抹除区。第一浮置栅晶体管包括具有在n型抹除区的第一部分上延伸的延伸部的第一浮置栅极。第二浮置栅晶体管包括具有在n型抹除区的第二部分上延伸的延伸部的第二浮置栅极。

Description

非挥发性存储器结构和阵列
技术领域
本发明涉及一种非挥发性存储器，且特别是涉及一种每位元采用两个电荷存储区(2-cells-per-bit)的非挥发性存储器结构和阵列。
背景技术
非挥发性存储器因为即使在没有供应电源的情况下，仍可以保留数据，故而广泛用于各种电子装置。依据写入次数的限制，非挥发性存储器分为可多次程序化(multi-timeprogrammable，MTP)和单次程序化(one-time programmable，OTP)。MTP是可多次读取和可多次写入的。一般而言，MTP具有用于写入和读取数据的单一电荷存储区域(即:1存储单元/位元)。
然而，随着存储器结构的发展，位于MTP的电荷存储区域底下的栅极氧化层会变得太薄，且因此在栅极氧化层出现缺陷时，数据保存能力(data retention capability)可能会恶化。因此，业界需要能改善非挥发性存储器的数据保存特性的方案。
发明内容
基于上述，本发明提供一种具有良好数据保存能力的非挥发性存储器结构，其具有两个用于写入和读取数据的电荷存储区域(即:2存储单元/位元)。
根据本发明的一实施例，一种非挥发性存储器结构包括基板、第一PMOS晶体管、第一浮置栅晶体管、第二PMOS晶体管、第二浮置栅晶体管、源极线、位线、字线以及抹除线。所述基板包括第一有源区、第二有源区以及n型抹除区。所述第一PMOS晶体管和所述第一浮置栅晶体管分别位于所述第一有源区上，其中所述第一PMOS晶体管包括第一选择栅极，所述第一浮置栅晶体管包括位于所述第一选择栅极和所述n型抹除区之间的第一浮置栅极，以及所述第一浮置栅极包括在所述n型抹除区的第一部分上延伸的延伸部。第二PMOS晶体管以及第二浮置栅晶体管分别位于所述第二有源区上，其中所述第二PMOS晶体管包括第二选择栅极，所述第二浮置栅晶体管包括位于所述第二选择栅极和所述n型抹除区之间的第二浮置栅极，且所述第二浮置栅极包括在所述n型抹除区的第二部分上延伸的延伸部。源极线连接所述第一和所述第二PMOS晶体管的源极。位线连接所述第一和所述第二浮置栅晶体管的漏极。字线连接所述第一和所述第二选择栅极。抹除线连接所述n型抹除区。
根据本发明的另一实施例，一种阵列包括数个上述的非挥发性存储器结构，其中两个所述非挥发性存储器结构共用一个所述n型抹除区。
在配合所附附图对以下较佳实施例进行详细说明后，将使本领域技术人员能清楚无疑虑地了解本发明的上述和其他特征。
附图说明
随附附图用以进一步理解本发明，且并入及构成本说明书的一部分。随附附图说明本发明的实施例，且与以下说明一起用于解释本发明的原理。
图1A是本发明的第一实施例的一种非挥发性存储器结构的布局的平面示意图；
图1B是沿图1A的线段B-B'的剖面示意图；
图1C是沿图1A的线段C-C'的一个实例的剖面示意图；
图1D是沿图1A的线段C-C'的另一个实例的剖面示意图；
图1E是图1A中的第一浮置栅极的放大图；
图2是说明如图1A中所述的非挥发性存储器结构的等效电路图；
图3和图4是本发明的第一实施例的非挥发性存储器结构的其他布局的平面示意图；
图5是如图1A中所述的非挥发性存储器结构的阵列的布局的平面示意图；
图6A是本发明的第二实施例的一种非挥发性存储器结构的布局的平面示意图；
图6B和图6C是本发明的第二实施例的非挥发性存储器结构的其他布局的平面示意图；
图7A和图7B是本发明的第三实施例的两种非挥发性存储器结构的布局的平面示意图；
图8是本发明的第四实施例的一种非挥发性存储器结构的阵列的布局的平面示意图；
图9是本发明的第五实施例的一种非挥发性存储器结构的阵列的布局的平面示意图。
符号说明
10、70a、70b、80、90：非挥发性存储器结构
100、800、900：基板
102、700、802、902：第一有源区
104、702、804、904：第二有源区
106、806a、806b、906：n型抹除区
106a：第一部分
106b：第二部分
108、808、908：第一PMOS晶体管
108a、112a、SG1、SG2：选择栅极
110、810、910：第一浮置栅晶体管
110a、114a、810a、814a、910a、914a、FG1、FG2：浮置栅极
110b、114b、300、302、600、602、810b、814b、910b、914b：延伸部
111：接触窗
112、812、912：第二PMOS晶体管
114、814、914：第二浮置栅晶体管
116：p型阱
118：隔离结构
120：N型阱
122：自行对准金属硅化物阻挡层
124：区域
126：自行对准金属硅化物层
604：槌状部分
606：耳状部分
704、816、916：金属线
A1、A2、A3、A4：重叠区域
B-B'、C-C'：线段
BL：位线
EL：抹除线
SL：源极线
WL：字线
具体实施方式
以下将详细地阐述本发明的较佳实施例，其实例在附图中示出。尽可能地，在附图中使用相同的元件符号，且指代相同或相似的元件。
图1A是根据本发明的第一实施例的一种非挥发性存储器结构的布局的示意性平面图。图1B是沿图1A的线段B-B'的剖面示意图。图1C是沿图1A的线段C-C'的一个实例的剖面示意图。图1D是沿图1A的线段C-C'的另一个实例的剖面示意图。
请参看图1A至图1D。本发明的第一实施例提供一种非挥发性存储器结构10，其包括基板100(具有第一有源区102、第二有源区104和n型抹除区106)、第一PMOS晶体管108、第一浮置栅晶体管110、第二PMOS晶体管112、第二浮置栅晶体管114、源极线SL、位线BL、字线WL以及抹除线EL。基板100例如是p型基板。n型抹除区106与所述第一有源区102和所述第二有源区104隔离，其中所述n型抹除区106可为如图1C所示的位于隔离结构118底下的由p型阱116所环绕的n+区。此外，p型阱116可如图1D所示进一步设置于n型抹除区106底下。
在图1A中，所述第一PMOS晶体管108以及所述第一浮置栅晶体管110分别设置于所述第一有源区102上，其中所述第一PMOS晶体管108包括第一选择栅极(SG1)108a，且所述第一浮置栅晶体管110包括位于所述第一选择栅极108a和所述n型抹除区106之间的第一浮置栅极(FG1)110a。所述第一浮置栅极110a还可包括在所述n型抹除区106的第一部分106a上延伸的延伸部110b，且所述延伸部110b具有平行于所述第一有源区102的延伸方向的延伸方向。所述第一浮置栅极110a的延伸部110b例如和所述第一有源区102的一部分重叠。所述第二PMOS晶体管112以及所述第二浮置栅晶体管114分别设置于所述第二有源区104上，其中所述第二PMOS晶体管112包括第二选择栅极(SG2)112a，且所述第二浮置栅晶体管114包括位于所述第二选择栅极112a和所述n型抹除区106之间的第二浮置栅极(FG2)114a。所述第二浮置栅极114a还可包括在所述n型抹除区106的第二部分106b上延伸的延伸部114b，且所述延伸部114b具有平行于所述第二有源区104的延伸方向的延伸方向。所述第二浮置栅极114a的延伸部114b例如和所述第二有源区104的一部分重叠。所述源极线SL通过接触窗111连接所述第一PMOS晶体管108和所述第二PMOS晶体管112的源极。所述位线BL通过接触窗111连接所述第一浮置栅晶体管110和所述第二浮置栅晶体管114的漏极。所述字线WL连接所述第一选择栅极108a和所述第二选择栅极112a。所述抹除线EL通过接触窗111连接所述n型抹除区106。由于所述非挥发性存储器结构10为每位元采用两个电荷存储区(2-cells-per-bit)的结构，可明显地降低所述存储器阵列的位元故障率(bit failurerate)。
在本发明的一个实施例中，所述第一浮置栅极110a和所述第二浮置栅极114a例如是经由福勒-诺德汉(Fowler-Nordheim，FN)穿隧来抹除，且例如是经由通道热电子(channel hot electron，CHE)程序化来进行程序化。此外，位于所述位线底下的所述第一有源区102和第二有源区104可如图1A所示彼此接触；然而，本发明并不限于此。
请再次参看图1C或图1D。N型阱120位于靠近所述p型阱116的基板100中，且所述延伸部110b设置于所述n型抹除区106的第一部分106a上。在本发明的一个实施例中，自行对准金属硅化物阻挡(salicide blocking，SAB)层122可形成于第一浮置栅极110a和所述延伸部110b上，用于改善数据保存能力。同理，SAB层122也可形成于第二浮置栅极114a及其延伸部114b上。因此，自行对准金属硅化物(self-aligned silicide)层可形成于图1A中的非挥发性存储器结构10的区域124内。
请再次参看图1B。自行对准金属硅化物层126形成于图1B中的区域124中。由于存储单元的尺寸因为SAB层122的关系可能会被放大，所以优选是将SAB层122形成于一部分的字线WL上。然而，本发明并不限于此。如果没有自行对准金属硅化物层的话，可以符合更小的设计法则。
图1E是图1A中的第一浮置栅极的放大图。
在图1E中，位于所述第一浮置栅极110a和所述第一有源区102之间的重叠区域设为A1，位于所述第一浮置栅极110a的延伸部110b和所述n型抹除区106之间的重叠区域设为A2，且有鉴于抹除效率，A1对A1和A2的总和的比值(即:A1/(A1+A2))例如大于75％。举例来说，若A1/(A1+A2)为90％且A2/(A1+A2)为10％，当施加10V的电压于n型抹除区106、施加0V的电压于N型阱(如图1C的120)时，自n型抹除区106至浮置栅极110a的电压差为10V-(0V×90％+10V×10％)＝9V。因此，在抹除操作期间，这样高的电压差可改善抹除效率。
同理，位于所述第二浮置栅极114a和所述第二有源区104之间的重叠区域如设为A3，位于所述第二浮置栅极114a的延伸部114b和所述n型抹除区106之间的重叠区域设为A4，且A3对A3和A4的总和的比值较佳也是大于75％。
图2说明如图1A中所述的非挥发性存储器结构的等效电路。所述源极线SL明显连接于两个PMOS晶体管的源极，所述位线BL明显连接于两个浮置栅晶体管的漏极，字线WL则连接两个选择栅极(SG1和SG2)，且所述抹除线EL连接至所述n型抹除区(即:n型电容)。
图3和图4是根据本发明的第一实施例的非挥发性存储器结构的其他布局的平面示意图，且为了清楚起见，部分必要构件并未绘示。
请参看图3。所述第一浮置栅极110a的延伸部300和所述第二浮置栅极114a的延伸部302各自独立地跨越所述n型抹除区106，以提升制作工艺的稳定度。
请参看图4。位于所述字线WL底下的第一有源区102和第二有源区104彼此接触，进而可扩大选择栅极的宽度。
图5是如图1A中所述的非挥发性存储器结构的阵列的布局的平面示意图。
请参看图5，其具有六个图1A的非挥发性存储器结构，但不限于此。在本发明的一个实施例中，n型抹除区106为非挥发性存储器结构的共通线(common line)，且一个字线WL可被用于三个非挥发性存储器结构中。此外，SAB层122形成于浮置栅极110a、浮置栅极114a、延伸部110b、延伸部114b以及半个字线WL上。因此，自行对准金属硅化物层不会形成于WL的靠近浮置栅极110a和浮置栅极114a的部分上。然而，本发明并不限于此。也可省略自行对准金属硅化物层。
由于图1A的非挥发性存储器结构可被排列于NOR型阵列中，所选择的存储器结构的操作条件可如下表1所列。
表1
在表1中，所施加的电压可因应不同的制作工艺技术而变更。举例来说，在0.13μm的制作工艺技术中，VPP约为6.5V、Vread约为2V、VEE约为11V，且视情况在读取操作中执行预充电，故施加于BL上的电压(例如0.4V)接近接地电压(GND)。此外，在读取操作中施加于EL的电压可介于0V和Vread之间，以获得较佳的Ion/Ioff范围。
图6A是根据本发明的第二实施例的一种非挥发性存储器结构的布局的平面示意图，且为清楚起见，部分必要构件未绘示。
请参看图6A。所述第一浮置栅极110a的延伸部600和所述第二浮置栅极114a的延伸部602不与第一有源区102和第二有源区104重叠。在第二实施例中，延伸部600和延伸部602设置于所述第一有源区102和所述第二有源区104之外。
图6B和图6C是根据本发明的第二实施例的非挥发性存储器结构的的其他布局的平面示意图，且为清楚起见，部分必要构件并未示出。
请参看图6B和图6C。所述第一浮置栅极110a的延伸部600可包括一个额外部分，所述额外部分例如是通过手控OPC(manual OPC)设在n型抹除区106的第一部分106a上的槌状部分604或耳状部分606。所述第二浮置栅极114a的延伸部602可包括额外部分，所述额外部分例如是通过手动OPC在n型抹除区106的第二部分106b上的槌状部分604或耳状部分606。通过手控OPC，可有助于稳定地形成延伸部600和602，并因此提升抹除稳定度。
图7A和图7B是根据本发明的第三实施例的两种非挥发性存储器结构的布局的平面示意图，且为清楚起见并未绘出部分必要构件。
请参看图7A。非挥发性存储器结构70a除了有源区的位置以外与第二实施例类似。在第三实施例中，第一有源区700和第二有源区702彼此间隔开。优选地，通过接触窗111设置金属线704来连接第一有源区700和第二有源区702。
请参看图7B。非挥发性存储器结构70b与图7A中的非挥发性存储器结构70a的差别在于第一浮置栅极110a的延伸部600和第二浮置栅极114a的延伸部602设置于第一有源区700和第二有源区702之间。因此，可消除邻近存储单元之间的多晶硅耦合问题(polycoupling issue)。
图8是根据本发明的第四实施例的一种非挥发性存储器结构的阵列的布局的平面示意图，且为清楚起见并未绘示部分必要构件。
请参看图8。本发明的第四实施例提供一种非挥发性存储器结构80，其包括基板800(具有第一有源区802、第二有源区804和两个分离的n型抹除区806a、806b)、第一PMOS晶体管808、第一浮置栅晶体管810、第二PMOS晶体管812、第二浮置栅晶体管814、金属线816以及字线WL。虽然没有画出源极线SL、抹除线EL和位线BL，但是本实施例仍需符合图2中的等效电路。举例来说，位线BL可为M2(即，在布局中的第二层金属层)，且抹除线EL可为M3(即，在布局中的第三层金属层)。
在第四实施例中，金属线816连接第一有源区802和第二有源区804。所述第一浮置栅极810a的延伸部810b在分离的n型抹除区806a上延伸，且第二浮置栅极814a的延伸部814b在分离的n型抹除区806b上延伸。延伸部810b具有垂直于第一有源区802的延伸方向的延伸方向。延伸部814b具有垂直于第二有源区804的延伸方向的延伸方向。
图9是根据本发明的第五实施例的一种非挥发性存储器结构的阵列的布局的平面示意图，且为清楚起见并未绘示部分必要构件。
请参看图9。本发明的第五实施例提供一种非挥发性存储器结构90，其包括基板900(具有第一有源区902、第二有源区904和n型抹除区906)、第一PMOS晶体管908、第一浮置栅晶体管910、第二PMOS晶体管912、第二浮置栅晶体管914、金属线916以及字线WL。虽然没有画出源极线SL、抹除线EL和位线BL，但是本实施例仍需依照图2中的等效电路被建构。
在第五实施例中，金属线916连接第一有源区902和第二有源区904。所述第一浮置栅极910a的延伸部910b和所述第二浮置栅极914a的延伸部914b两者在n型抹除区906上延伸。延伸部910b具有垂直于第一有源区902的延伸方向的延伸方向。延伸部914b具有垂直于第二有源区904的延伸方向的延伸方向。已知，若一个存储单元故障，则其他靠近故障存储单元的存储单元也容易故障。因此，因为第一PMOS晶体管908远离第二PMOS晶体管912，所以可进一步减少存储器阵列的位元故障率。在图9的阵列中，两个非挥发性存储器结构90明显是共用一个n型抹除区906。
综上所述，上述实施例的非挥发性存储器结构其特征在于降低读取故障率和提升数据保存能力。
虽然结合前述的实施例揭露了本发明，然而其并非用以限定本发明。在不脱离本发明的精神和范围内，所为之更动与润饰，均属本发明的专利保护范围。关于本发明所界定的保护范围请参考所附的权利要求。

Claims (24)

1.一种非挥发性存储器结构，其特征在于，包括:
基板，包括第一有源区、第二有源区以及n型抹除区，其中所述n型抹除区与所述第一有源区和所述第二有源区隔离；
第一PMOS晶体管和第一浮置栅晶体管，分别位于所述第一有源区上，其中所述第一PMOS晶体管包括第一选择栅极，所述第一浮置栅晶体管包括位于所述第一选择栅极和所述n型抹除区之间的第一浮置栅极，且所述第一浮置栅极包括在所述n型抹除区的第一部分上延伸的延伸部；
第二PMOS晶体管和第二浮置栅晶体管，分别位于所述第二有源区上，其中所述第二PMOS晶体管包括第二选择栅极，所述第二浮置栅晶体管包括位于所述第二选择栅极和所述n型抹除区之间的第二浮置栅极，且所述第二浮置栅极包括在所述n型抹除区的第二部分上延伸的延伸部；
源极线，连接所述第一PMOS晶体管和所述第二PMOS晶体管的多个源极；
位线，连接所述第一浮置栅晶体管和所述第二浮置栅晶体管的多个漏极；
字线，连接所述第一选择栅极和所述第二选择栅极；以及
抹除线，连接所述n型抹除区。
2.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极和所述第二浮置栅极经由福勒-诺德汉穿隧来抹除。
3.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极和所述第二浮置栅极经由通道热电子程序化来进行程序化。
4.如权利要求1所述的非挥发性存储器结构，其特征在于，还包括环绕所述n型抹除区的p型阱。
5.如权利要求1所述的非挥发性存储器结构，其特征在于，还包括位于所述n型抹除区底下且环绕所述n型抹除区的p型阱。
6.如权利要求1所述的非挥发性存储器结构，其特征在于，还包括自行对准金属硅化物阻挡层，位于所述第一浮置栅极和所述第二浮置栅极上。
7.如权利要求1所述的非挥发性存储器结构，其特征在于，位于所述第一浮置栅极和所述第一有源区之间的重叠区域为A1，位于所述第一浮置栅极和所述n型抹除区之间的重叠区域为A2，且A1对A1和A2的总和的比值大于75％。
8.如权利要求1所述的非挥发性存储器结构，其特征在于，位于所述第二浮置栅极和所述第二有源区之间的重叠区域为A3，位于所述第二浮置栅极和所述n型抹除区之间的重叠区域为A4，且A3对A3和A4的总和的比值大于75％。
9.如权利要求1所述的非挥发性存储器结构，其特征在于，还包括额外部分，位于所述n型抹除区的所述第一部分上的所述第一浮置栅极的所述延伸部中。
10.如权利要求1所述的非挥发性存储器结构，其特征在于，还包括额外部分，位于所述n型抹除区的所述第二部分上的所述第二浮置栅极的所述延伸部中。
11.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极的所述延伸部和所述第二浮置栅极的所述延伸部各自独立地跨越所述n型抹除区。
12.如权利要求1所述的非挥发性存储器结构，其特征在于，位于所述字线底下的所述第一有源区和所述第二有源区彼此接触。
13.如权利要求1所述的非挥发性存储器结构，其特征在于，位于所述位线底下的所述第一有源区和所述第二有源区彼此接触。
14.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一有源区和所述第二有源区彼此间隔开。
15.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极的所述延伸部与所述第一有源区的一部分重叠。
16.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第二浮置栅极的所述延伸部与所述第二有源区的一部分重叠。
17.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极的所述延伸部和所述第二浮置栅极的所述延伸部设置于所述第一有源区和所述第二有源区之间。
18.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极的所述延伸部和所述第二浮置栅极的所述延伸部设置于所述第一有源区和所述第二有源区之外。
19.如权利要求1所述的非挥发性存储器结构，其特征在于，所述n型抹除区包括分离的两个区，所述第一浮置栅极的所述延伸部在所述两个区的其中之一上延伸，以及所述第二浮置栅极的所述延伸部在所述两个区的其中另一上延伸。
20.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极的所述延伸部具有平行于所述第一有源区的延伸方向的延伸方向。
21.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第一浮置栅极的所述延伸部具有垂直于所述第一有源区的延伸方向的延伸方向。
22.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第二浮置栅极的所述延伸部具有平行于所述第二有源区的延伸方向的延伸方向。
23.如权利要求1所述的非挥发性存储器结构，其特征在于，所述第二浮置栅极的所述延伸部具有垂直于所述第二有源区的延伸方向的延伸方向。
24.一种阵列，包括多个如权利要求1所述的非挥发性存储器结构，其特征在于，两个所述非挥发性存储器结构共用一个所述n型抹除区。
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