TWI618072B - 電源切換電路 - Google Patents
電源切換電路 Download PDFInfo
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- TWI618072B TWI618072B TW106101257A TW106101257A TWI618072B TW I618072 B TWI618072 B TW I618072B TW 106101257 A TW106101257 A TW 106101257A TW 106101257 A TW106101257 A TW 106101257A TW I618072 B TWI618072 B TW I618072B
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- supply voltage
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- 238000006243 chemical reaction Methods 0.000 claims description 37
- 238000010586 diagram Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005086 pumping Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G11C16/20—Initialising; Data preset; Chip identification
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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Abstract
一電源切換電路包括:一第一電晶體、第二電晶體與一電流源。第一電晶體的一第一源汲端與一閘極端分別接收一第一供應電壓與一第二供應電壓,一第二源汲端與一體極端連接至一節點z,且該節點z產生一輸出信號。一第二電晶體的一第一源汲端與一閘極端分別接收該第二供應電壓與該第一供應電壓,一第二源汲端與一體極端連接至該節點z。一電流源連接於一偏壓電壓與該節點z之間。該第一供應電壓、該第二供應電壓或者該偏壓電壓可被選擇成為該輸出信號。
Description
本發明是有關於一種電源切換電路,且特別是有關於一種運用於非揮發性記憶體的電源切換電路。
眾所周知,非揮發性記憶體可在電源消失之後,仍可保存資料,因此非揮發性記憶體已經廣泛的運用於電子產品中。再者,非揮發性記憶體中包括多個非揮發性記憶胞(non-Volatile cell)排列而成非揮發性記憶胞陣列(non-Volatile cell array),而每個非揮發性記憶胞中皆包含一浮動閘電晶體(floating gate transistor)。
請參照第1圖,其所繪示為揮發性記憶體示意圖。非揮發性記憶體中包括一非揮發性記憶胞陣列110與一電源切換電路(power switch circuit)120。其中,電源切換電路120連接至非揮發性記憶胞陣列110。電源切換電路120接收多個供應電壓(supply voltage),並可在不同運作模式下輸出適當的供應電壓作為輸出信號Vs,並提供至非揮發性記憶胞陣列110。
舉例來說,電源切換電路120接收第一供應電壓與第二供應電壓。於非揮發性記憶胞陣列的抹除模式(erase mode)
時,電源切換電路120提供第一供應電壓至非揮發性記憶胞陣列110。再者,於編程模式(program mode)時,提供第二供應電壓至非揮發性記憶胞陣列110。
本發明係有關於一種電源切換電路,包括:一第一電晶體,具有一第一源汲端接收一第一供應電壓,一第二源汲端連接至一節點z,一閘極端接收一第二供應電壓,一體極端連接至該節點z,其中該節點z產生一輸出信號;一第二電晶體,具有一第一源汲端接收該第二供應電壓,一第二源汲端連接至該節點z,一閘極端接收該第一供應電壓,一體極端連接至該節點z;以及一電流源,連接於一偏壓電壓與該節點z之間;其中,當該第一供應電壓小於該第二供應電壓時,該輸出信號等於該第一供應電壓;當該第一供應電壓大於該第二供應電壓時,該輸出信號等於該第二供應電壓;當該第一供應電壓等於該第二供應電壓時,該輸出信號等於該偏壓電壓。
本發明係有關於一種電源切換電路,包括:一第一電晶體,具有一第一源汲端接收一第一供應電壓,一第二源汲端連接至一節點z,一閘極端接收一第二供應電壓,一體極端連接至該節點z,其中該節點z產生一輸出信號;一第二電晶體,具有一第一源汲端接收該第二供應電壓,一第二源汲端連接至該節點z,一閘極端接收該第一供應電壓,一體極端連接至該節點z;
一第三電晶體,具有一第一源汲端接收一偏壓電壓,一第二源汲端連接至該節點z,一閘極端接收一轉換信號,一體極端連接至該節點z;一自動選擇電路,接收該第一供應電壓與該第二供應電壓,並產生一輸出電壓,其中當該第一供應電壓小於該第二供應電壓時,該輸出電壓等於該第一供應電壓;以及當該第一供應電壓大於該第二供應電壓時,該輸出電壓等於該第二供應電壓;以及一準位轉換器,接收該輸出電壓,其中該準位轉換器根據該輸出電壓與一控制信號,將該控制信號轉換為該轉換信號。
本發明係有關於一種電源切換電路,包括:一第一電晶體,具有一第一源汲端接收一第一供應電壓,一第二源汲端連接至一節點w,一閘極端接收一第一轉換信號,其中該節點w產生一輸出信號;一第二電晶體,具有一第一源汲端接收該第二供應電壓,一第二源汲端連接至該節點w,一閘極端接收一第二轉換信號;一第一自動選擇電路,接收該第一供應電壓與該第二供應電壓,並產生一輸出電壓,其中當該第一供應電壓小於該第二供應電壓時,該輸出電壓等於該第一供應電壓;以及當該第一供應電壓大於該第二供應電壓時,該輸出電壓等於該第二供應電壓;一第一準位轉換器,接收該輸出電壓,其中該第一準位轉換器根據該輸出電壓與一第一控制信號,將該第一控制信號轉換為該第一轉換信號;以及一第二準位轉換器,接收該輸出電壓,其中該第二準位轉換器根據該輸出電壓與一第二控制信號,將該第二控制信號轉換為該第二轉換信號。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:
110‧‧‧非揮發性記憶胞
120、300、400、500、600、650、700、800‧‧‧電源切換電路
10、310、320、640、654、710、720‧‧‧自動選擇電路
330、620、630、652、810‧‧‧準位轉換器
410、910‧‧‧控制電路
412、912‧‧‧及閘
414、416、510、914、916、952‧‧‧電流源
900、950‧‧‧電源切換電路
第1圖所繪示為揮發性記憶體示意圖。
第2A圖所繪示為自動選擇電路。
第2B圖所繪示為自動選擇電路10的真值表。
第3A圖所繪示為本發明電源切換電路的第一實施例。
第3B圖所繪示為第一實施例電源切換電路的真值表。
第4圖所繪示為本發明電源切換電路的第二實施例。
第5A圖所繪示為本發明電源切換電路的第三實施例。
第5B圖所繪示為第三實施例切換電路的真值表。
第6A圖所繪示為本發明電源切換電路的第四實施例。
第6B圖所繪示為第四實施例準位轉換器的真值表。
第7圖所繪示為本發明電源切換電路的第五實施例。
第8圖所繪示為本發明電源切換電路的第六實施例。
第9圖所繪示為本發明電源切換電路的第七實施例。
第10圖所繪示為本發明電源切換電路的第八實施例。
第11圖所繪示為本發明電源切換電路的第九實施例。
請參照第2A圖,其所繪示為自動選擇電路。自動選擇電路10包括二個n型電晶體ma、mb。電晶體ma的第一源
汲端(source/drain terminal)連接至節點x、第二源汲端連接至節點z、閘極端連接至節點y、體極端(body terminal)連接至節點z。電晶體mb的第一源汲端連接至節點y、第二源汲端連接至節點z、閘極端連接至節點x、體極端連接至節點z。再者,節點x與節點y為自動選擇電路10的二輸入端,分別接收供應電壓Vp1與Vp2;節點z為為自動選擇電路10的輸出端,可以選擇性地將二個供應電壓Vp1與Vp2其中之一作為輸出信號Vs。
在本發明的實施例中,供應電壓Vp1與Vp2的電壓值小於等於零。而自動選擇電路10可以自動地選擇二個供應電壓Vp1與Vp2中較小的電壓做為輸出信號Vs。當然,自動選擇電路10的二個供應電壓Vp1與Vp2的電壓值也可大於零,而自動選擇電路10也可以自動地選擇二個供應電壓Vp1與Vp2中較小的電壓做為輸出信號Vs。
請參照第2B圖,其所繪示為自動選擇電路10的真值表。當供應電壓Vp1為0V且供應電壓Vp2為-4V時,電晶體mb開啟(turn on)且電晶體ma關閉(turn off),較低的供應電壓Vp2(-4V)即成為輸出信號Vs。再者,當供應電壓Vp1為-6V且供應電壓Vp2為-4V時,電晶體ma開啟且電晶體mb關閉,較低的供應電壓Vp1(-6V)即成為輸出信號Vs。
由於自動選擇電路10輸出信號Vs為二個供應電壓Vp1與Vp2中較小的電壓。因此,將輸出信號Vs作為電晶體ma與mb的體極端電壓,可以消除電晶體ma與mb的基體效應(body
effect)。
另外,當二供應電壓Vp1、Vp2皆相同,或者一個供應電壓未提供時,輸出信號Vs的電壓值可能約為0V的浮接狀態(floating)。在此狀況下,輸出信號Vs約為供應電壓減去Vtn。其中,Vtn為電晶體ma與mb的臨限電壓(threshold Voltage)。
如第2B圖所示,當供應電壓Vp1、Vp2皆為0V時,其輸出信號Vs為0-Vtn。當供應電壓Vp1為0V且節點y成為浮接狀態(意即,未提供供應電壓Vp2)時,其輸出信號Vs為0-Vtn。
請參照第3A圖,其所繪示為本發明電源切換電路的第一實施例。電源切換電路300包括:自動選擇電路310、320,一準位轉換器(level shifter)330與一n型電晶體mc。其中,自動選擇電路310、320的電路結構與第2A圖相同。
自動選擇電路310接收二個供應電壓Vp1與Vp2,並將較低的供應電壓作為輸出信號(output signal)Vs。另外,自動選擇電路320接收二個供應電壓Vp1與Vp2,並將較低的供應電壓作為輸出電壓(output voltage)Vx,並作為準位轉換器330的電壓源(voltage source)。
準位轉換器330接收邏輯準位的控制信號EN_mc並根據電壓源Vx與控制信號EN_mc來降轉(shift down)控制信號EN_mc成為轉換信號(shifted signal)Sc。舉例來說,當控制信號EN_mc為3.3V的邏輯高準位時,準位轉換器330產生3.3V的轉換信號Sc;當控制信號EN_mc為0V的邏輯低準位時,準位轉換
器330產生相同於電壓源Vx的轉換信號Sc。
根據本發明的實施例,當供應電壓Vp1與Vp2不相同時,控制信號EN_mc為邏輯低準位;當供應電壓Vp1與Vp2相同時,控制信號EN_mc為邏輯高準位;以及,當供應電壓Vp1與Vp2其中之一為浮接狀態時,控制信號EN_mc為邏輯高準位。
再者,電晶體mc的第一源汲端接收一偏壓電壓Vbias、第二源汲端與體極端連接至電源切換電路300的輸出端(亦即節點z),閘極端接收轉換信號Sc。其中,偏壓電壓Vbias可為供應電壓Vp1與Vp2其中之一。
請參照第3B圖,其所繪示為第一實施例電源切換電路300的真值表。當供應電壓Vp1為0V且供應電壓Vp2為-4V時,控制信號EN_mc為邏輯低準位(Lo=0V),轉換信號Sc為-4V,使得電晶體mc關閉。再者,電晶體mb開啟且電晶體ma關閉,較低的供應電壓Vp2(-4V)即成為輸出信號Vs。
再者,當供應電壓Vp1為-6V且供應電壓Vp2為-4V時,控制信號EN_mc為邏輯低準位(Lo=0V),轉換信號Sc為-6V,使得電晶體mc關閉。再者,電晶體ma開啟且電晶體mb關閉,較低的供應電壓Vp1(-6V)即成為輸出信號Vs。
當二供應電壓Vp1、Vp2相同時,電晶體ma與電晶體mb皆關閉。再者,控制信號EN_mc為邏輯高準位(Hi=3.3V),轉換信號Sc為3.3V,使得電晶體mc開啟,偏壓電壓Vbias即成為輸出信號Vs。
當供應電壓Vp2為浮接狀態時,電晶體ma與電晶體mb皆關閉。再者,控制信號EN_mc為邏輯高準位(Hi=3.3V),轉換信號Sc為3.3V,使得電晶體mc開啟,偏壓電壓Vbias即成為輸出信號Vs。其中,上述的偏壓電壓Vbias可為供應電壓Vp1與Vp2其中之一,例如0V。
換言之,本發明第一實施例的電源切換電路300可以自動地選擇較低的供應電壓作為輸出信號Vs。並且,也可以在二供應電壓Vp1、Vp2相同時,防止輸出信號Vs成為浮接狀態。
請參照第4圖,其所繪示為本發明電源切換電路的第二實施例。相較於第3A圖第一實施例的電源切換電路300,第二實施例電源切換電路400更包括一控制電路410用以產生邏輯準位的控制信號EN_mc。
控制電路410包括電晶體md、me,電流源(current source)414、416,及閘(AND gate)412。其中,電流源414連接於電壓源Vdd與節點a之間。電晶體md第一源汲端與體極端接收供應電壓Vp1,第二源汲端連接至節點a,閘極端接收供應電壓Vp2。電流源416連接於電壓源Vdd與節點b之間。電晶體me第一源汲端與體極端接收供應電壓Vp2,第二源汲端連接至節點b,閘極端接收供應電壓Vp1。及閘412的二輸入端分別連接至節點a、b,輸出端產生邏輯準位的控制信號EN_mc。其中,電壓源Vdd的電壓值為3.3V。再者,偏壓電壓Vbias可為供應電壓Vp1與Vp2其中之一。
當供應電壓Vp1與Vp2不相同時,電晶體md與me其中之一會開啟,另一個電晶體則關閉。舉例來說,當供應電壓Vp1為0V且供應電壓Vp2為-4V時,電晶體me開啟且電晶體md關閉。因此,節點a為邏輯高準位,節點b為邏輯低準位,及閘412輸出邏輯低準位的控制信號EN_mc。
當供應電壓Vp1與Vp2相同時,電晶體md與me皆關閉。舉例來說,當供應電壓Vp1為0V且供應電壓Vp2為0V時,電晶體me、md關閉。因此,節點a與節點b為邏輯高準位,及閘412輸出邏輯高準位的控制信號EN_mc。
同理,當供應電壓Vp1與Vp2其中之一為浮接狀態時,電晶體md與me皆關閉,且及閘412輸出邏輯高準位的控制信號EN_mc。
第二實施例的電源切換電路400的真值表相同於第3B圖,此處不再贅述。相同地,本發明第二實施例的電源切換電路400可以自動地選擇較低的供應電壓作為輸出信號Vs。並且,也可以在二供應電壓Vp1、Vp2相同時,防止輸出信號Vs成為浮接狀態。
請參照第5A圖,其所繪示為本發明電源切換電路的第三實施例。電源切換電路500包括:弱電流源(weak current source)510以及自動選擇電路310。其中,自動選擇電路310的電路結構與第2A圖相同。弱電流源510連接於偏壓電源Vbias與自動選擇電路310的輸出端(節點z)之間。第三實施例的電源切
換電路500也可以在二供應電壓Vp1、Vp2相同時,防止輸出信號Vs成為浮接狀態。
請參照第5B圖,其所繪示為第三實施例切換電路500的真值表。當供應電壓Vp1為0V且供應電壓Vp2為-4V時,電晶體mb開啟(turn on)且電晶體ma關閉(turn off),較低的供應電壓Vp2(-4V)即成為輸出信號Vs。
再者,當供應電壓Vp1為-6V且供應電壓Vp2為-4V時,電晶體ma開啟且電晶體mb關閉,較低的供應電壓Vp1(-6V)即成為輸出信號Vs。
另外,當二供應電壓Vp1、Vp2皆相同,或者一個供應電壓未提供時,電晶體ma、mb皆關閉。此時,弱電流源510所提供的弱電流可對節點z進行充電(charge),使得節點z維持在偏壓電源Vbias,而不會呈現浮接狀態。再者,偏壓電壓Vbias可以等於二個供應電壓Vp1、Vp2其中之一。
換言之,本發明第三實施例的電源切換電路500可以自動地選擇較低的供應電壓作為輸出信號Vs。並且,也可以在二供應電壓Vp1、Vp2相同時,防止輸出信號Vs成為浮接狀態。
請參照第6A圖,其所繪示為本發明電源切換電路的第四實施例。電源切換電路300包括:n型電晶體m1、m2,準位轉換器620、630,與自動選擇電路640。其中,電源切換電路接收二個控制信號EN_m1與EN_m2,並選擇性地將供應電壓Vp1或者供應電壓Vp2作為輸出信號Vs。其中,控制信號EN_m1與
EN_m2的邏輯高準位為3.3V,邏輯低準位為0V。
再者,自動選擇電路640接收二個供應電壓Vp1與供應電壓Vp2,並將較低的供應電壓作為輸出電壓Vx,並作為準位轉換器620、630的電壓源。其中,自動選擇電路640與第2A圖相同,詳細電路不再贅述。
準位轉換器620接收邏輯準位的控制信號EN_m1,並根據電壓源Vx與控制信號EN_m1來降轉(shift down)控制信號EN_m1。舉例來說,當控制信號EN_m1為3.3V的邏輯高準位時,準位轉換器620產生3.3V的轉換信號S1;當控制信號EN_m1為0V的邏輯低準位時,準位轉換器620產生相同於電壓源Vx的轉換信號S1。
再者,準位轉換器630接收邏輯準位的控制信號EN_m2,並根據電壓源Vx與控制信號EN_m2來降轉(shift down)控制信號EN_m2。舉例來說,當控制信號EN_m2為3.3V的邏輯高準位時,準位轉換器630產生3.3V的轉換信號S2;當控制信號EN_m2為0V的邏輯低準位時,準位轉換器330產生相同於電壓源Vx的轉換信號S2。
電源切換電路600中,電晶體m1的第一源汲端接收供應電壓Vp1、第二源汲端連接至節點w、閘極端接收轉換信號S1。電晶體m2的第一源汲端接收供應電壓Vp2、第二源汲端連接至節點w、閘極端接收轉換信號S2。再者,節點w產生輸出信號Vs。在此實施例中,電晶體m1與電晶體m2的體極端也可
以接收電壓源Vx。
根據本發明的第四實施例,供應電壓Vp1與Vp2為小於等於零的電壓。請參照第6B圖,其所繪示為第四實施例準位轉換器600的真值表。當供應電壓Vp1小於供應電壓Vp2時,自動選擇電路640的輸出電壓Vx等於供應電壓Vp1。例如,供應電壓Vp1為-4V且供應電壓Vp2為0V時,自動選擇電路640的輸出電壓Vx為-4V。再者,根據快閃記憶胞陣列的各種不同操作動作,例如抹除動作時,控制信號EN_m1為3.3V的邏輯高準位,且控制信號EN_m2為0V的邏輯低準位時,轉換信號S1為3.3V使得電晶體m1開啟,轉換信號S2為-4V使得電晶體m2關閉。因此,電源切換電路600將供應電壓Vp1作為輸出信號Vs,意即輸出信號Vs等於-4V。
再者,於快閃記憶胞陣列的另一種操作動作,例如讀取動作時,控制信號EN_m1為0V的邏輯低準位,且控制信號EN_m2為3.3V的邏輯高準位,轉換信號S1為-4V使得電晶體m1關閉,轉換信號S2為3.3V使得電晶體m2開啟。因此,電源切換電路600將供應電壓Vp2作為輸出信號Vs,意即輸出信號Vs等於0V。
當供應電壓Vp1大於供應電壓Vp2時,自動選擇電路640的輸出電壓Vx等於供應電壓Vp2。在其他的應用上,供應電壓Vp1與供應電壓Vp2其中之一是由內部泵浦電路(pumping circuit)所提供,而其中另一則是由外部所提供。例如,供應電壓
Vp1為-4V且供應電壓Vp2為-6V時,自動選擇電路640的輸出電壓Vx為-6V。再者,當控制信號EN_m1為3.3V的邏輯高準位,且控制信號EN_m2為0V的邏輯低準位時,轉換信號S1為3.3V使得電晶體m1開啟,轉換信號S2為-6V使得電晶體m2關閉。因此,電源切換電路600將供應電壓Vp1作為輸出信號Vs,意即輸出信號Vs等於-4V。
再者,當控制信號EN_m1為0V的邏輯低準位,且控制信號EN_m2為3.3V的邏輯高準位時,轉換信號S1為-6V使得電晶體m1關閉,轉換信號S2為3.3V使得電晶體m2開啟。因此,電源切換電路600將供應電壓Vp2作為輸出信號Vs,意即輸出信號Vs等於-6V。
請參照第7圖,其所繪示為本發明電源切換電路的第四實施例。電源切換電路650包括:一n型電晶體m1、一準位轉換器652與一自動選擇電路654。電源切換電路650接收邏輯準位的控制信號EN_m1並選擇性地將供應電壓Vp1作為輸出信號(output signal)Vs。控制信號EN_mc的邏輯高準位為3.3V,控制信號EN_mc的邏輯低準位為0V。
在此實施例中,自動選擇電路654接收供應電壓Vp1與輸出信號Vs,並選擇二者之中較低者為輸出電壓Vx,並作為電晶體m1的體極端電壓。當然,自動選擇電路654的輸出電壓Vx出電壓也作為準位轉換器652的電壓源。再者,自動選擇電路654的電路結構與第2A圖相同。
在此實施例中,自動選擇電路654接收供應電壓Vp1與輸出信號Vs,並選擇二者之中較低者為輸出電壓Vx作為體極端電壓,並傳遞至電晶體m1的體極端。因此,可以消除電晶體m1的基體效應。
請參照第8圖,其所繪示為本發明電源切換電路的第六實施例。相較於第6A圖第四實施例之電源切換電路600,第六實施例之電源切換電路700更增加自動選擇電路710、720。再者,自動選擇電路710、720的詳細電路與第2A圖相同。此處僅介紹第六實施例電源切換電路700內部自動選擇電路710、720的運作。
根據本發明的第六實施例,自動選擇電路710接收供應電壓Vp1與輸出信號Vs,並將較低的電壓傳遞至電晶體m1的體極端,作為電晶體m1的體極電壓Vm1b。而自動選擇電路720接收供應電壓Vp2與輸出信號Vs,並將較低的電壓傳遞至電晶體m2的體極端,作為電晶體m2的體極電壓Vm2b。因此,可以消除電晶體m1與m2的基體效應(body effect)。
再者,第六實施例電源切換電路700的真值表相同於第6B圖,此處不再贅述。
請參照第9圖,其所繪示為本發明電源切換電路的第七實施例。相較於第8圖的第六實施例電源切換電路700,第七實施例之電源切換電路800更增加一n型電晶體m3與一準位轉換器810。第七實施例的電源切換電路800係用來防止控制信
號EN_m1、EN_m2皆為邏輯低準位而造成節點w呈現浮接狀態(floating)。說明如下。
根據本發明的第七實施例,準位轉換器810接收控制信號EN_m3,並根據電壓源Vx來降轉控制信號EN_m3。舉例來說,當控制信號EN_m3為3.3V的邏輯高準位時,準位轉換器810產生3.3V的轉換信號S3;當控制信號EN_m3為0V的邏輯低準位時,準位轉換器810產生相同於電壓源Vx的轉換信號S3。
再者,電晶體m3的第一源汲端接收一偏壓電壓Vbias,第二源汲端連接至節點w,閘極端接收轉換信號S3,體極端接收自動選擇電路640的輸出電壓Vx。
當控制信號EN_m1與控制信號EN_m2為邏輯低準位時,控制信號EN_m3為邏輯高準位。因此,當控制信號EN_m1、EN_m2皆為邏輯低準位,並使得電晶體m1、m2皆關閉時,轉換信號S3開啟電晶體m3,使得節點w維持在偏壓電源Vbias,而不會呈現浮接狀態。再者,偏壓電壓Vbias可以等於二個供應電壓Vp1、Vp2其中之一。
請參照第10圖,其所繪示為本發明電源切換電路的第八實施例。相較於第九圖第七實施例的電源切換電路800,第八實施例電源切換電路900更包括一控制電路910用以產生邏輯準位的控制信號EN_m3。
控制電路910包括電晶體m4、m5,電流源(current source)914、916,及閘912。其中,電流源914連接於電壓源Vdd
與節點c之間。電晶體m4第一源汲端與體極端接收供應電壓Vp1,第二源汲端連接至節點c,閘極端接收供應電壓Vp2。電流源916連接於電壓源Vdd與節點d之間。電晶體m5第一源汲端與體極端接收供應電壓Vp2,第二源汲端連接至節點d,閘極端接收供應電壓Vp1。及閘912的二輸入端分別連接至節點c、d,輸出端產生邏輯準位的控制信號EN_mc。其中,電壓源Vdd的電壓值為3.3V。
當供應電壓Vp1與Vp2相同且控制信號EN_m1、EN_m2皆為邏輯低準位,電晶體m1、m2關閉。舉例來說,當供應電壓Vp1為0V且供應電壓Vp2為0V時,電晶體m4、m5關閉。因此,節點c與節點d為邏輯高準位,及閘912輸出邏輯高準位的控制信號EN_m3。
再者,當控制信號EN_m3為邏輯高準位時,轉換信號S3開啟電晶體m3,使得節點w維持在偏壓電源Vbias,而不會呈現浮接狀態。再者,偏壓電壓Vbias可以等於二個供應電壓Vp1、Vp2其中之一。
請參照第11圖,其所繪示為本發明電源切換電路的第九實施例。相較於第8圖第六實施例之的電源切換電路700,第九實施例之電源切換電路950更增加一弱電流源(weak current source)952。用以防止控制信號EN_m1、EN_m2皆為邏輯低準位而造成節點w呈現浮接狀態(floating)。說明如下。
根據本發明的第九實施例,弱電流源952連接於偏
壓電源Vbias與節點w之間。當控制信號EN_m1、EN_m2皆為邏輯低準位,並使得電晶體m1、m2皆關閉時,弱電流源952所提供的弱電流可對節點w進行充電(charge),使得節點w維持在偏壓電源Vbias,而不會呈現浮接狀態。再者,偏壓電壓Vbias可以等於二個供應電壓Vp1、Vp2其中之一。
由以上的說明可知,本發明係提出一種電源切換電路,在第一實施例至第三實施例中,電源切換電路可以自動地於多個供應電壓中選擇電壓值最低的供應電壓作為輸出信號,並且可以防止輸出信號呈現浮接狀態。在第四實施例至第九實施例中,電源切換電路可以根據控制信號來選擇多個供應電壓中之一,並作為輸出信號,並且也可以防止輸出信號呈現浮接狀態。
再者,在此領域的技術人員,可以根據以上的實施例所揭露的內容進行修改並達成本發明的目的。舉例來說,在此領域的技術人員可以省略第六實施例至第九實施例的自動選擇電路710、720,仍可以達成本發明的目的。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
300‧‧‧電源切換電路
310、320‧‧‧自動選擇電路
330‧‧‧準位轉換器
Claims (14)
- 一種電源切換電路,包括:一第一電晶體,具有一第一源汲端接收一第一供應電壓,一第二源汲端連接至一節點z,一閘極端接收一第二供應電壓,一體極端連接至該節點z,其中該節點z產生一輸出信號;一第二電晶體,具有一第一源汲端接收該第二供應電壓,一第二源汲端連接至該節點z,一閘極端接收該第一供應電壓,一體極端連接至該節點z;一第三電晶體,具有一第一源汲端接收一偏壓電壓,一第二源汲端連接至該節點z,一閘極端接收一轉換信號,一體極端連接至該節點z;一自動選擇電路,接收該第一供應電壓與該第二供應電壓,並產生一輸出電壓,其中當該第一供應電壓小於該第二供應電壓時,該輸出電壓等於該第一供應電壓;以及當該第一供應電壓大於該第二供應電壓時,該輸出電壓等於該第二供應電壓;以及一準位轉換器,接收該輸出電壓,其中該準位轉換器根據該輸出電壓與一控制信號,將該控制信號轉換為該轉換信號。
- 如申請專利範圍第1項所述之電源切換電路,其中該偏壓電壓等於該第一供應電壓或者該偏壓電壓等於該第二供應電壓。
- 如申請專利範圍第1項所述之電源切換電路,其中該第一 電晶體、該第二電晶體與該第三電晶體為n型電晶體。
- 如申請專利範圍第1項所述之電源切換電路,其中該自動選擇電路包括:一第四電晶體,具有一第一源汲端接收該第一供應電壓,一第二源汲端產生該輸出電壓,一閘極端接收該第二供應電壓,一體極端連接至該第二源汲端;以及一第五電晶體,具有一第一源汲端接收該第二供應電壓,一第二源汲端與一體極端連接至該第四電晶體的該第二源汲端,一閘極端接收該第一供應電壓。
- 如申請專利範圍第1項所述之電源切換電路,更包括:一第四電晶體,具有一第一源汲端與一體極端接收該第一供應電壓,一第二源汲端連接至一節點a,一閘極端接收該第二供應電壓;一第五電晶體,具有一第一源汲端與一體極端接收該第二供應電壓,一第二源汲端連接至一節點b,一閘極端接收該第一供應電壓;一第一電流源,連接於一電壓源與該節點a之間;一第二電流源,連接於該電壓源與該節點b之間;以及一及閘,具有二輸入端分別連接至該節點a與該節點b,並產生該控制信號。
- 一種電源切換電路,包括:一第一電晶體,具有一第一源汲端接收一第一供應電壓,一第二源汲端連接至一節點w,一閘極端接收一第一轉換信號,其中該節點w產生一輸出信號;一第二電晶體,具有一第一源汲端接收該第二供應電壓,一第二源汲端連接至該節點w,一閘極端接收一第二轉換信號;一第一自動選擇電路,接收該第一供應電壓與該第二供應電壓,並產生一輸出電壓,其中當該第一供應電壓小於該第二供應電壓時,該輸出電壓等於該第一供應電壓;以及當該第一供應電壓大於該第二供應電壓時,該輸出電壓等於該第二供應電壓;一第一準位轉換器,接收該輸出電壓,其中該第一準位轉換器根據該輸出電壓與一第一控制信號,將該第一控制信號轉換為該第一轉換信號;以及一第二準位轉換器,接收該輸出電壓,其中該第二準位轉換器根據該輸出電壓與一第二控制信號,將該第二控制信號轉換為該第二轉換信號。
- 如申請專利範圍第6項所述之電源切換電路,其中該第一電晶體與該第二電晶體為n型電晶體。
- 如申請專利範圍第6項所述之電源切換電路,其中該第一 自動選擇電路包括:一第三電晶體,具有一第一源汲端接收該第一供應電壓,一第二源汲端產生該輸出電壓,一閘極端接收該第二供應電壓,一體極端連接至該第二源汲端;以及一第四電晶體,具有一第一源汲端接收該第二供應電壓,一第二源汲端與一體極端連接至該三電晶體的該第二源汲端,一閘極端接收該第一供應電壓。
- 如申請專利範圍第6項所述之電源切換電路,更包括:一第二自動選擇電路,接收該第一供應電壓與該輸出信號,並產生一第一體極電壓傳送至該第一電晶體的一體極端,其中當該第一供應電壓小於該輸出信號時,該第一體極電壓等於該第一供應電壓;以及當該第一供應電壓大於該輸出信號時,該第一體極電壓等於該輸出信號;以及一第三自動選擇電路,接收該第二供應電壓與該輸出信號,並產生一第二體極電壓傳送至該第二電晶體的一體極端,其中當該第二供應電壓小於該輸出信號時,該第二體極電壓等於該第二供應電壓;以及當該第二供應電壓大於該輸出信號時,該第二體極電壓等於該輸出信號。
- 如申請專利範圍第6項所述之電源切換電路,更包括:一第三電晶體,具有一第一源汲端接收一偏壓電壓,一第二 源汲端連接至該節點w,一閘極端接收一第三轉換信號(S3);一第三準位轉換器,接收該輸出電壓,其中該第三準位轉換器根據該輸出電壓與一第三控制信號,將該第三控制信號轉換為該第三轉換信號;其中,當該第一控制信號與該第二控制信號為一第一邏輯準位時,該第三控制信號為一第二邏輯準位。
- 如申請專利範圍第10項所述之電源切換電路,其中該偏壓電壓等於該第一供應電壓或者該偏壓電壓等於該第二供應電壓。
- 如申請專利範圍第10項所述之電源切換電路,更包括:一第四電晶體,具有一第一源汲端與一體極端接收該第一供應電壓,一第二源汲端連接至一節點c,一閘極端接收該第二供應電壓;一第五電晶體,具有一第一源汲端與一體極端接收該第二供應電壓,一第二源汲端連接至一節點d,一閘極端接收該第一供應電壓;一第一電流源,連接於一電壓源與該節點c之間;一第二電流源,連接於該電壓源與該節點d之間;以及一及閘,具有二輸入端分別連接至該節點c與該節點d,並產生該第三控制信號。
- 如申請專利範圍第6項所述之電源切換電路,更包括:一弱電流源,連接於一偏壓電壓與該節點w之間。
- 如申請專利範圍第13項所述之電源切換電路,其中該偏壓電壓等於該第一供應電壓或者該偏壓電壓等於該第二供應電壓。
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