TW201727838A - 非揮發性記憶體結構 - Google Patents

非揮發性記憶體結構 Download PDF

Info

Publication number
TW201727838A
TW201727838A TW105133388A TW105133388A TW201727838A TW 201727838 A TW201727838 A TW 201727838A TW 105133388 A TW105133388 A TW 105133388A TW 105133388 A TW105133388 A TW 105133388A TW 201727838 A TW201727838 A TW 201727838A
Authority
TW
Taiwan
Prior art keywords
floating gate
volatile memory
region
memory structure
extension
Prior art date
Application number
TW105133388A
Other languages
English (en)
Other versions
TWI587455B (zh
Inventor
陳英哲
陳緯仁
孫文堂
Original Assignee
力旺電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力旺電子股份有限公司 filed Critical 力旺電子股份有限公司
Application granted granted Critical
Publication of TWI587455B publication Critical patent/TWI587455B/zh
Publication of TW201727838A publication Critical patent/TW201727838A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一種非揮發性記憶體結構包括在基板中的第一主動區上的第一PMOS電晶體和第一浮置閘電晶體、在基板中的第二主動區上的第二PMOS電晶體和第二浮置閘電晶體、以及在基板中的n型抹除區。源極線連接第一和第二PMOS電晶體的源極。位元線連接第一和第二浮置閘電晶體的汲極。字元線分別連接位於第一和第二PMOS電晶體中的第一和第二選擇閘極。抹除線連接n型抹除區。第一浮置閘電晶體包括具有在n型抹除區的第一部分上延伸的延伸部的第一浮置閘極。第二浮置閘電晶體包括具有在n型抹除區的第二部分上延伸的延伸部的第二浮置閘極。

Description

非揮發性記憶體結構
本發明是有關於一種非揮發性記憶體，且特別是有關於一種每位元採用兩個電荷儲存區(2-cells-per-bit)的非揮發性記憶體結構。
非揮發性記憶體因為即使在沒有供應電源的情況下，仍可以保留資料，故而廣泛用於各種電子裝置。依據寫入次數的限制，非揮發性記憶體分為可多次程式化(multi-time programmable，MTP)和單次程式化(one-time programmable，OTP)。MTP是可多次讀取和可多次寫入的。一般而言，MTP具有用於寫入和讀取資料的單一電荷儲存區域(即:1記憶胞/位元)。
然而，隨著記憶體結構的發展，位於MTP的電荷儲存區域底下的閘極氧化層會變得太薄，且因此在閘極氧化層出現缺陷時，資料保存能力(data retention capability)可能會惡化。因此，業界需要能改善非揮發性記憶體的資料保存特性的方案。
基於上述，本發明提供一種具有良好資料保存能力的非揮發性記憶體結構，其具有兩個用於寫入和讀取資料的電荷儲存區域(即:2記憶胞/位元)。
根據本發明的一實施例，一種非揮發性記憶體結構包括基板、第一PMOS電晶體、第一浮置閘電晶體、第二PMOS電晶體、第二浮置閘電晶體、源極線、位元線、字元線以及抹除線。所述基板包括第一主動區、第二主動區以及n型抹除區。所述第一PMOS電晶體和所述第一浮置閘電晶體分別位於所述第一主動區上，其中所述第一PMOS電晶體包括第一選擇閘極，所述第一浮置閘電晶體包括位於所述第一選擇閘極和所述n型抹除區之間的第一浮置閘極，以及所述第一浮置閘極包括在所述n型抹除區的第一部份上延伸的延伸部。第二PMOS電晶體以及第二浮置閘電晶體分別位於所述第二主動區上，其中所述第二PMOS電晶體包括第二選擇閘極，所述第二浮置閘電晶體包括位於所述第二選擇閘極和所述n型抹除區之間的第二浮置閘極，且所述第二浮置閘極包括在所述n型抹除區的第二部份上延伸的延伸部。源極線連接所述第一和所述第二PMOS電晶體的源極。位元線連接所述第一和所述第二浮置閘電晶體的汲極。字元線連接所述第一和所述第二選擇閘極。抹除線連接所述n型抹除區。
根據本發明的另一實施例，一種陣列包括數個上述的非揮發性記憶體結構，其中兩個所述非揮發性記憶體結構共用一個所述n型抹除區。
在配合所附圖式對以下較佳實施例進行詳細說明後，將使本領域技術人員能清楚無疑慮地了解本發明的上述和其他特徵。
以下將詳細地闡述本發明的較佳實施例，其實例在附圖中示出。盡可能地，在圖式中使用相同的元件符號，且指代相同或相似的元件。
圖1A是根據本發明的第一實施例的一種非揮發性記憶體結構的佈局的示意性平面圖。圖1B是沿圖1A的線段B-B'的剖面示意圖。圖1C是沿圖1A的線段C-C'的一個實例之剖面示意圖。圖1D是沿圖1A的線段C-C'的另一個實例之剖面示意圖。
請參看圖1A至圖1D。本發明的第一實施例提供一種非揮發性記憶體結構10，其包括基板100(具有第一主動區102、第二主動區104和n型抹除區106)、第一PMOS電晶體108、第一浮置閘電晶體110、第二PMOS電晶體112、第二浮置閘電晶體114、源極線SL、位元線BL、字元線WL以及抹除線EL。基板100例如是p型基板。n型抹除區106與所述第一主動區102和所述第二主動區104隔離，其中所述n型抹除區106可為如圖1C所示的位於隔離結構118底下的由p型井116所環繞的n+ 區。此外，p型井116可如圖1D所示進一步設置於n型抹除區106底下。
在圖1A中，所述第一PMOS電晶體108以及所述第一浮置閘電晶體110分別設置於所述第一主動區102上，其中所述第一PMOS電晶體108包括第一選擇閘極(SG1)108a，且所述第一浮置閘電晶體110包括位於所述第一選擇閘極108a和所述n型抹除區106之間的第一浮置閘極(FG1)110a。所述第一浮置閘極110a還可包括在所述n型抹除區106的第一部分106a上延伸的延伸部110b，且所述延伸部110b具有平行於所述第一主動區102的延伸方向的延伸方向。所述第一浮置閘極110a的延伸部110b例如和所述第一主動區102的一部分重疊。所述第二PMOS電晶體112以及所述第二浮置閘電晶體114分別設置於所述第二主動區104上，其中所述第二PMOS電晶體112包括第二選擇閘極(SG2)112a，且所述第二浮置閘電晶體114包括位於所述第二選擇閘極112a和所述n型抹除區106之間的第二浮置閘極(FG2)114a。所述第二浮置閘極114a還可包括在所述n型抹除區106的第二部分106b上延伸的延伸部114b，且所述延伸部114b具有平行於所述第二主動區104的延伸方向的延伸方向。所述第二浮置閘極114a的延伸部114b例如和所述第二主動區104的一部分重疊。所述源極線SL通過接觸窗111連接所述第一PMOS電晶體108和所述第二PMOS電晶體112的源極。所述位元線BL通過接觸窗111連接所述第一浮置閘電晶體110和所述第二浮置閘電晶體114的汲極。所述字元線WL連接所述第一選擇閘極108a和所述第二選擇閘極112a。所述抹除線EL通過接觸窗111連接所述n型抹除區106。由於所述非揮發性記憶體結構10為每位元採用兩個電荷儲存區(2-cells-per-bit)的結構，可明顯地降低所述記憶體陣列的位元故障率(bit failure rate)。
在本發明的一個實施例中，所述第一浮置閘極110a和所述第二浮置閘極114a例如是經由福勒-諾德漢(Fowler-Nordheim，FN)穿隧來抹除，且例如是經由通道熱電子(channel hot electron，CHE)程式化來進行程式化。此外，位於所述位元線底下的所述第一主動區102和第二主動區104可如圖1A所示彼此接觸；然而，本發明並不限於此。
請再次參看圖1C或圖1D。N型井120位於靠近所述p型井116的基板100中，且所述延伸部110b設置於所述n型抹除區106的第一部份106a上。在本發明的一個實施例中，自行對準金屬矽化物阻擋(salicide blocking，SAB)層122可形成於第一浮置閘極110a和所述延伸部110b上，用於改善資料保存能力。同理，SAB層122亦可形成於第二浮置閘極114a及其延伸部114b上。因此，自行對準金屬矽化物(self-aligned silicide)層可形成於圖1A中的非揮發性記憶體結構10的區域124內。
請再次參看圖1B。自行對準金屬矽化物層126形成於圖1B中的區域124中。由於記憶胞的尺寸因為SAB層122的關係可能會被放大，所以優選是將SAB層122形成於一部分的字元線WL上。然而，本發明並不限於此。如果沒有自行對準金屬矽化物層的話，可以符合更小的設計法則。
圖1E是圖1A中的第一浮置閘極的放大圖。
在圖1E中，位於所述第一浮置閘極110a和所述第一主動區102之間的重疊區域設為A1，位於所述第一浮置閘極110a的延伸部110b和所述n型抹除區106之間的重疊區域設為A2，且有鑑於抹除效率，A1對A1和A2的總和的比值(即:A1/(A1+A2))例如大於75%。舉例來說，若A1/(A1+A2)為90%且A2/(A1+A2)為10%，當施加10V的電壓於n型抹除區106、施加0V的電壓於N型井(如圖1C的120)時，自n型抹除區106至浮置閘極110a的電壓差為10V - (0V×90%+10V×10%) = 9V。因此，在抹除操作期間，這樣高的電壓差可改善抹除效率。
同理，位於所述第二浮置閘極114a和所述第二主動區104之間的重疊區域如設為A3，位於所述第二浮置閘極114a的延伸部114b和所述n型抹除區106之間的重疊區域設為A4，且A3對A3和A4的總和的比值較佳也是大於75%。
圖2說明如圖1A中所述的非揮發性記憶體結構的等效電路。所述源極線SL明顯連接於兩個PMOS電晶體的源極，所述位元線BL明顯連接於兩個浮置閘電晶體的汲極，字元線WL則連接兩個選擇閘極(SG1和SG2)，且所述抹除線EL連接至所述n型抹除區(即:n型電容)。
圖3和圖4是根據本發明的第一實施例的非揮發性記憶體結構的其他佈局的平面示意圖，且為了清楚起見，部分必要構件並未繪示。
請參看圖3。所述第一浮置閘極110a的延伸部300和所述第二浮置閘極114a的延伸部302各自獨立地跨越所述n型抹除區106，以提升製程的穩定度。
請參看圖4。位於所述字元線WL底下的第一主動區102和第二主動區104彼此接觸，進而可擴大選擇閘極的寬度。
圖5是如圖1A中所述的非揮發性記憶體結構的陣列的佈局的平面示意圖。
請參看圖5，其具有六個圖1A的非揮發性記憶體結構，但不限於此。在本發明的一個實施例中，n型抹除區106為非揮發性記憶體結構的共通線(common line)，且一個字元線WL可被用於三個非揮發性記憶體結構中。此外，SAB層122形成於浮置閘極110a、浮置閘極114a、延伸部110b、延伸部114b以及半個字元線WL上。因此，自行對準金屬矽化物層不會形成於WL的靠近浮置閘極110a和浮置閘極114a的部分上。然而，本發明並不限於此。也可省略自行對準金屬矽化物層。
由於圖1A的非揮發性記憶體結構可被排列於NOR型陣列中，所選擇的記憶體結構的操作條件可如下表1所列。
表1
在表1中，所施加的電壓可因應不同的製程技術而變更。舉例來說，在0.13μm的製程技術中，VPP約為6.5V、Vread約為2V、VEE約為11V，且視情況在讀取操作中執行預充電，故施加於BL上的電壓(例如0.4V)接近接地電壓(GND)。此外，在讀取操作中施加於EL的電壓可介於0V和Vread之間，以獲得較佳的Ion/Ioff範圍。
圖6A是根據本發明的第二實施例的一種非揮發性記憶體結構的佈局的平面示意圖，且為清楚起見，部分必要構件未繪示。
請參看圖6A。所述第一浮置閘極110a的延伸部600和所述第二浮置閘極114a的延伸部602不與第一主動區102和第二主動區104重疊。在第二實施例中，延伸部600和延伸部602設置於所述第一主動區102和所述第二主動區104之外。
圖6B和圖6C是根據本發明的第二實施例的非揮發性記憶體結構的的其他佈局的平面示意圖，且為清楚起見，部分必要構件並未示出。
請參看圖6B和圖6C。所述第一浮置閘極110a的延伸部600可包括一個額外部分，所述額外部分例如是藉由手控OPC(manual OPC)設在n型抹除區106的第一部分106a上的槌狀部分604或耳狀部分606。所述第二浮置閘極114a的延伸部602可包括額外部分，所述額外部分例如是藉由手動OPC在n型抹除區106的第二部分106b上的槌狀部分604或耳狀部分606。藉由手控OPC，可有助於穩定地形成延伸部600和602，並因此提升抹除穩定度。
圖7A和圖7B是根據本發明的第三實施例的兩種非揮發性記憶體結構的佈局的平面示意圖，且為清楚起見並未繪出部分必要構件。
請參看圖7A。非揮發性記憶體結構70a除了主動區的位置以外與第二實施例類似。在第三實施例中，第一主動區700和第二主動區702彼此間隔開。優選地，通過接觸窗111設置金屬線704來連接第一主動區700和第二主動區702。
請參看圖7B。非揮發性記憶體結構70b與圖7A中的非揮發性記憶體結構70a的差別在於第一浮置閘極110a的延伸部600和第二浮置閘極114a的延伸部602設置於第一主動區700和第二主動區702之間。因此，可消除鄰近記憶胞之間的多晶矽耦合問題(poly coupling issue)。
圖8是根據本發明的第四實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖，且為清楚起見並未繪示部分必要構件。
請參看圖8。本發明的第四實施例提供一種非揮發性記憶體結構80，其包括基板800(具有第一主動區802、第二主動區804和兩個分離的n型抹除區806a、806b)、第一PMOS電晶體808、第一浮置閘電晶體810、第二PMOS電晶體812、第二浮置閘電晶體814、金屬線816以及字元線WL。雖然沒有畫出源極線SL、抹除線EL和位元線BL，但是本實施例仍需符合圖2中的等效電路。舉例來說，位元線BL可為M2(即，在佈局中的第二層金屬層)，且抹除線EL可為M3(即，在佈局中的第三層金屬層)。
在第四實施例中，金屬線816連接第一主動區802和第二主動區804。所述第一浮置閘極810a的延伸部810b在分離的n型抹除區806a上延伸，且第二浮置閘極814a的延伸部814b在分離的n型抹除區806b上延伸。延伸部810b具有垂直於第一主動區802的延伸方向的延伸方向。延伸部814b具有垂直於第二主動區804的延伸方向的延伸方向。
圖9是根據本發明的第五實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖，且為清楚起見並未繪示部分必要構件。
請參看圖9。本發明的第五實施例提供一種非揮發性記憶體結構90，其包括基板900(具有第一主動區902、第二主動區904和n型抹除區906)、第一PMOS電晶體908、第一浮置閘電晶體910、第二PMOS電晶體912、第二浮置閘電晶體914、金屬線916以及字元線WL。雖然沒有畫出源極線SL、抹除線EL和位元線BL，但是本實施例仍需依照圖2中的等效電路被建構。
在第五實施例中，金屬線916連接第一主動區902和第二主動區904。所述第一浮置閘極910a的延伸部910b和所述第二浮置閘極914a的延伸部914b兩者在n型抹除區906上延伸。延伸部910b具有垂直於第一主動區902的延伸方向的延伸方向。延伸部914b具有垂直於第二主動區904的延伸方向的延伸方向。已知，若一個記憶胞故障，則其他靠近故障記憶胞的記憶胞也容易故障。因此，因為第一PMOS電晶體908遠離第二PMOS電晶體912，所以可進一步減少記憶體陣列的位元故障率。在圖9的陣列中，兩個非揮發性記憶體結構90明顯是共用一個n型抹除區906。
綜上所述，上述實施例的非揮發性記憶體結構其特徵在於降低讀取故障率和提升資料保存能力。
雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明。在不脫離本發明之精神和範圍內，所為之更動與潤飾，均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。
10、70a、70b、80、90‧‧‧非揮發性記憶體結構 100、800、900‧‧‧基板 102、700、802、902‧‧‧第一主動區 104、702、804、904‧‧‧第二主動區 106、806a、806b、906‧‧‧n型抹除區 106a‧‧‧第一部分 106b‧‧‧第二部分 108、808、908‧‧‧第一PMOS電晶體 108a、112a、SG1、SG2‧‧‧選擇閘極 110、810、910‧‧‧第一浮置閘電晶體 110a、114a、810a、814a、910a、914a、FG1、FG2‧‧‧浮置閘極 110b、114b、300、302、600、602、810b、814b、910b、914b‧‧‧延伸部 111‧‧‧接觸窗 112、812、912‧‧‧第二PMOS電晶體 114、814、914‧‧‧第二浮置閘電晶體 116‧‧‧p型井 118‧‧‧隔離結構 120‧‧‧N型井 122‧‧‧自行對準金屬矽化物阻擋層 124‧‧‧區域 126‧‧‧自行對準金屬矽化物層 604‧‧‧槌狀部分 606‧‧‧耳狀部分 704、816、916‧‧‧金屬線 A1、A2、A3、A4‧‧‧重疊區域 B-B'、C-C'‧‧‧線段 BL‧‧‧位元線 EL‧‧‧抹除線 SL‧‧‧源極線 WL‧‧‧字元線
隨附圖式用以進一步理解本發明，且併入及構成本說明書的一部分。隨附圖式說明本發明的實施例，且與以下說明一起用於解釋本發明的原理。 圖1A是根據本發明的第一實施例的一種非揮發性記憶體結構的佈局的平面示意圖。 圖1B是沿圖1A的線段B-B'的剖面示意圖。 圖1C是沿圖1A的線段C-C'的一個實例之剖面示意圖。 圖1D是沿圖1A的線段C-C'的另一個實例之剖面示意圖。 圖1E是圖1A中的第一浮置閘極的放大圖。 圖2是說明如圖1A中所述的非揮發性記憶體結構的等效電路圖。 圖3和圖4是根據本發明的第一實施例的非揮發性記憶體結構的其他佈局的平面示意圖。 圖5是如圖1A中所述的非揮發性記憶體結構的陣列的佈局的平面示意圖。 圖6A是根據本發明的第二實施例的一種非揮發性記憶體結構的佈局的平面示意圖。 圖6B和圖6C是根據本發明的第二實施例的非揮發性記憶體結構的其他佈局的平面示意圖。 圖7A和圖7B是根據本發明的第三實施例的兩種非揮發性記憶體結構的佈局的平面示意圖。 圖8是根據本發明的第四實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖。 圖9是根據本發明的第五實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖。
10‧‧‧非揮發性記憶體結構
102‧‧‧第一主動區
104‧‧‧第二主動區
106‧‧‧n型抹除區
106a‧‧‧第一部分
106b‧‧‧第二部分
108‧‧‧第一PMOS電晶體
108a‧‧‧第一選擇閘極
110‧‧‧第一浮置閘電晶體
110a、114a‧‧‧浮置閘極
110b、114b‧‧‧延伸部
111‧‧‧接觸窗
112‧‧‧第二PMOS電晶體
112a‧‧‧第二選擇閘極
114‧‧‧第二浮置閘電晶體
124‧‧‧區域
B-B'、C-C'‧‧‧線段
BL‧‧‧位元線
EL‧‧‧抹除線
SL‧‧‧源極線
WL‧‧‧字元線

Claims (24)

  1. 一種非揮發性記憶體結構，包括: 一基板，包括一第一主動區、一第二主動區以及一n型抹除區，其中所述n型抹除區與所述第一主動區和所述第二主動區隔離； 一第一PMOS電晶體和一第一浮置閘電晶體，分別位於所述第一主動區上，其中所述第一PMOS電晶體包括一第一選擇閘極，所述第一浮置閘電晶體包括位於所述第一選擇閘極和所述n型抹除區之間的一第一浮置閘極，且所述第一浮置閘極包括在所述n型抹除區的一第一部份上延伸的一延伸部； 一第二PMOS電晶體和一第二浮置閘電晶體，分別位於所述第二主動區上，其中所述第二PMOS電晶體包括一第二選擇閘極，所述第二浮置閘電晶體包括位於所述第二選擇閘極和所述n型抹除區之間的一第二浮置閘極，且所述第二浮置閘極包括在所述n型抹除區的一第二部份上延伸的一延伸部； 一源極線，連接所述第一PMOS電晶體和所述第二PMOS電晶體的多數個源極； 一位元線，連接所述第一浮置閘電晶體和所述第二浮置閘電晶體的多數個汲極； 一字元線，連接所述第一選擇閘極和所述第二選擇閘極；以及 一抹除線，連接所述n型抹除區。
  2. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極和所述第二浮置閘極經由福勒-諾德漢(FN)穿隧來抹除。
  3. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極和所述第二浮置閘極經由通道熱電子(CHE) 程式化來進行程式化。
  4. 如申請專利範圍第1項所述的非揮發性記憶體結構，更包括環繞所述n型抹除區的一p型井。
  5. 如申請專利範圍第1項所述的非揮發性記憶體結構，更包括位於所述n型抹除區底下且環繞所述n型抹除區的一p型井。
  6. 如申請專利範圍第1項所述的非揮發性記憶體結構，更包括一自行對準金屬矽化物阻擋(SAB)層，位於所述第一浮置閘極和所述第二浮置閘極上。
  7. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中位於所述第一浮置閘極和所述第一主動區之間的一重疊區域為A1，位於所述第一浮置閘極和所述n型抹除區之間的一重疊區域為A2，且A1對A1和A2的總和的比值大於75%。
  8. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中位於所述第二浮置閘極和所述第二主動區之間的一重疊區域為A3，位於所述第二浮置閘極和所述n型抹除區之間的一重疊區域為A4，且A3對A3和A4的總和的比值大於75%。
  9. 如申請專利範圍第1項所述的非揮發性記憶體結構，更包括一額外部分，位於所述n型抹除區的所述第一部份上的所述第一浮置閘極的所述延伸部中。
  10. 如申請專利範圍第1項所述的非揮發性記憶體結構，更包括一額外部分，位於所述n型抹除區的所述第二部份上的所述第二浮置閘極的所述延伸部中。
  11. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極的所述延伸部和所述第二浮置閘極的所述延伸部各自獨立地跨越所述n型抹除區。
  12. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中位於所述字元線底下的所述第一主動區和所述第二主動區彼此接觸。
  13. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中位於所述位元線底下的所述第一主動區和所述第二主動區彼此接觸。
  14. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一主動區和所述第二主動區彼此間隔開。
  15. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極的所述延伸部與所述第一主動區的一部分重疊。
  16. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第二浮置閘極的所述延伸部與所述第二主動區的一部分重疊。
  17. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極的所述延伸部和所述第二浮置閘極的所述延伸部設置於所述第一主動區和所述第二主動區之間。
  18. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極的所述延伸部和所述第二浮置閘極的所述延伸部設置於所述第一主動區和所述第二主動區之外。
  19. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述n型抹除區包括分離的兩個區，所述第一浮置閘極的所述延伸部在所述兩個區的其中之一上延伸，以及所述第二浮置閘極的所述延伸部在所述兩個區的其中另一上延伸。
  20. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極的所述延伸部具有平行於所述第一主動區的延伸方向的延伸方向。
  21. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第一浮置閘極的所述延伸部具有垂直於所述第一主動區的延伸方向的延伸方向。
  22. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第二浮置閘極的所述延伸部具有平行於所述第二主動區的延伸方向的延伸方向。
  23. 如申請專利範圍第1項所述的非揮發性記憶體結構，其中所述第二浮置閘極的所述延伸部具有垂直於所述第二主動區的延伸方向的延伸方向。
  24. 一種陣列，包括多數個如申請專利範圍第1項所述的非揮發性記憶體結構，其中兩個所述非揮發性記憶體結構共用一個所述n型抹除區。
TW105133388A 2016-01-19 2016-10-17 非揮發性記憶體結構 TWI587455B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201662280683P 2016-01-19 2016-01-19

Publications (2)

Publication Number Publication Date
TWI587455B TWI587455B (zh) 2017-06-11
TW201727838A true TW201727838A (zh) 2017-08-01

Family

ID=56137184

Family Applications (11)

Application Number Title Priority Date Filing Date
TW105121411A TWI578322B (zh) 2016-01-19 2016-07-06 電壓切換電路
TW105123524A TWI613672B (zh) 2016-01-19 2016-07-26 記憶體陣列
TW105133388A TWI587455B (zh) 2016-01-19 2016-10-17 非揮發性記憶體結構
TW106100743A TWI621123B (zh) 2016-01-19 2017-01-10 非揮發性記憶體的驅動電路
TW106100807A TWI614763B (zh) 2016-01-19 2017-01-11 記憶體裝置、其週邊電路及其單一位元組資料寫入方法
TW106101257A TWI618072B (zh) 2016-01-19 2017-01-13 電源切換電路
TW106101517A TWI630615B (zh) 2016-01-19 2017-01-17 記憶體陣列
TW106104042A TWI646665B (zh) 2016-01-19 2017-02-08 具有抹除元件的單層多晶矽非揮發性記憶胞結構
TW106108098A TWI613659B (zh) 2016-01-19 2017-03-13 記憶單元
TW106113346A TWI613654B (zh) 2016-01-19 2017-04-21 記憶體單元及記憶體陣列
TW106114486A TWI641115B (zh) 2016-01-19 2017-05-02 記憶體單元及記憶體陣列

Family Applications Before (2)

Application Number Title Priority Date Filing Date
TW105121411A TWI578322B (zh) 2016-01-19 2016-07-06 電壓切換電路
TW105123524A TWI613672B (zh) 2016-01-19 2016-07-26 記憶體陣列

Family Applications After (8)

Application Number Title Priority Date Filing Date
TW106100743A TWI621123B (zh) 2016-01-19 2017-01-10 非揮發性記憶體的驅動電路
TW106100807A TWI614763B (zh) 2016-01-19 2017-01-11 記憶體裝置、其週邊電路及其單一位元組資料寫入方法
TW106101257A TWI618072B (zh) 2016-01-19 2017-01-13 電源切換電路
TW106101517A TWI630615B (zh) 2016-01-19 2017-01-17 記憶體陣列
TW106104042A TWI646665B (zh) 2016-01-19 2017-02-08 具有抹除元件的單層多晶矽非揮發性記憶胞結構
TW106108098A TWI613659B (zh) 2016-01-19 2017-03-13 記憶單元
TW106113346A TWI613654B (zh) 2016-01-19 2017-04-21 記憶體單元及記憶體陣列
TW106114486A TWI641115B (zh) 2016-01-19 2017-05-02 記憶體單元及記憶體陣列

Country Status (5)

Country Link
US (13) US9847133B2 (zh)
EP (6) EP3196883B1 (zh)
JP (4) JP6122531B1 (zh)
CN (10) CN106981311B (zh)
TW (11) TWI578322B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI742880B (zh) * 2019-11-14 2021-10-11 力旺電子股份有限公司 唯讀式記憶胞及其相關的記憶胞陣列
TWI781281B (zh) * 2018-02-23 2022-10-21 南韓商Ｓｋ海力士系統集成電路有限公司 具有經提高程式化效率的一次性可程式化記憶體裝置及其製造方法

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9965267B2 (en) 2015-11-19 2018-05-08 Raytheon Company Dynamic interface for firmware updates
US9847133B2 (en) 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation
US9633734B1 (en) * 2016-07-14 2017-04-25 Ememory Technology Inc. Driving circuit for non-volatile memory
CN107768373B (zh) * 2016-08-15 2022-05-10 华邦电子股份有限公司 存储元件及其制造方法
US9882566B1 (en) * 2017-01-10 2018-01-30 Ememory Technology Inc. Driving circuit for non-volatile memory
TWI652683B (zh) * 2017-10-13 2019-03-01 力旺電子股份有限公司 用於記憶體的電壓驅動器
US10332597B2 (en) * 2017-11-08 2019-06-25 Globalfoundries Singapore Pte. Ltd. Floating gate OTP/MTP structure and method for producing the same
JP7143326B2 (ja) 2017-12-20 2022-09-28 タワー パートナーズ セミコンダクター株式会社 半導体装置
KR102422839B1 (ko) * 2018-02-23 2022-07-19 에스케이하이닉스 시스템아이씨 주식회사 수평 커플링 구조 및 단일층 게이트를 갖는 불휘발성 메모리 소자
US10522202B2 (en) * 2018-04-23 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and compensation method therein
US10964708B2 (en) * 2018-06-26 2021-03-30 Micron Technology, Inc. Fuse-array element
CN108986866B (zh) * 2018-07-20 2020-12-11 上海华虹宏力半导体制造有限公司 一种读高压传输电路
TWI659502B (zh) * 2018-08-02 2019-05-11 旺宏電子股份有限公司 非揮發性記憶體結構
CN110828464A (zh) * 2018-08-08 2020-02-21 旺宏电子股份有限公司 非易失性存储器结构
DE102019120605B4 (de) 2018-08-20 2022-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Speicherschaltung und verfahren zu deren herstellung
US11176969B2 (en) 2018-08-20 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit including a first program device
CN109147851B (zh) * 2018-08-31 2020-12-25 上海华力微电子有限公司 一种锁存电路
KR20200031894A (ko) * 2018-09-17 2020-03-25 에스케이하이닉스 주식회사 메모리 모듈 및 이를 포함하는 메모리 시스템
US10797064B2 (en) * 2018-09-19 2020-10-06 Ememory Technology Inc. Single-poly non-volatile memory cell and operating method thereof
CN109524042B (zh) * 2018-09-21 2020-03-17 浙江大学 一种基于反型模式阻变场效应晶体管的与非型存储阵列
TWI708253B (zh) 2018-11-16 2020-10-21 力旺電子股份有限公司 非揮發性記憶體良率提升的設計暨測試方法
CN111342541B (zh) * 2018-12-19 2021-04-16 智原微电子(苏州)有限公司 电源切换电路
KR20200104669A (ko) * 2019-02-27 2020-09-04 삼성전자주식회사 집적회로 소자
US10924112B2 (en) * 2019-04-11 2021-02-16 Ememory Technology Inc. Bandgap reference circuit
US11508719B2 (en) * 2019-05-13 2022-11-22 Ememory Technology Inc. Electrostatic discharge circuit
CN112086115B (zh) * 2019-06-14 2023-03-28 力旺电子股份有限公司 存储器系统
CN112131037B (zh) * 2019-06-24 2023-11-14 华邦电子股份有限公司 存储器装置
JP2021048230A (ja) * 2019-09-18 2021-03-25 キオクシア株式会社 半導体記憶装置
US11139006B1 (en) * 2020-03-12 2021-10-05 Ememory Technology Inc. Self-biased sense amplification circuit
JP6887044B1 (ja) * 2020-05-22 2021-06-16 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置および読出し方法
TWI739695B (zh) * 2020-06-14 2021-09-11 力旺電子股份有限公司 轉壓器
US11373715B1 (en) * 2021-01-14 2022-06-28 Elite Semiconductor Microelectronics Technology Inc. Post over-erase correction method with auto-adjusting verification and leakage degree detection
TWI819457B (zh) * 2021-02-18 2023-10-21 力旺電子股份有限公司 多次編程非揮發性記憶體的記憶胞陣列
US11854647B2 (en) * 2021-07-29 2023-12-26 Micron Technology, Inc. Voltage level shifter transition time reduction
US11972800B2 (en) * 2021-12-16 2024-04-30 Ememory Technology Inc. Non-volatile memory cell and non-volatile memory cell array
US12014783B2 (en) 2022-01-10 2024-06-18 Ememory Technology Inc. Driving circuit for non-volatile memory

Family Cites Families (170)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617652A (en) 1979-01-24 1986-10-14 Xicor, Inc. Integrated high voltage distribution and control systems
JP2685966B2 (ja) 1990-06-22 1997-12-08 株式会社東芝 不揮発性半導体記憶装置
US5331590A (en) 1991-10-15 1994-07-19 Lattice Semiconductor Corporation Single poly EE cell with separate read/write paths and reduced product term coupling
JP3180608B2 (ja) 1994-03-28 2001-06-25 松下電器産業株式会社 電源選択回路
JP3068752B2 (ja) 1994-08-29 2000-07-24 松下電器産業株式会社 半導体装置
US5648669A (en) * 1995-05-26 1997-07-15 Cypress Semiconductor High speed flash memory cell structure and method
US5742542A (en) * 1995-07-03 1998-04-21 Advanced Micro Devices, Inc. Non-volatile memory cells using only positive charge to store data
US5640344A (en) * 1995-07-25 1997-06-17 Btr, Inc. Programmable non-volatile bidirectional switch for programmable logic
US6005806A (en) * 1996-03-14 1999-12-21 Altera Corporation Nonvolatile configuration cells and cell arrays
JP4659662B2 (ja) 1997-04-28 2011-03-30 ペグレ・セミコンダクターズ・リミテッド・ライアビリティ・カンパニー 半導体装置及びその製造方法
FR2767219B1 (fr) * 1997-08-08 1999-09-17 Commissariat Energie Atomique Dispositif memoire non volatile programmable et effacable electriquement compatible avec un procede de fabrication cmos/soi
JP3037236B2 (ja) * 1997-11-13 2000-04-24 日本電気アイシーマイコンシステム株式会社 レベルシフタ回路
US5959889A (en) * 1997-12-29 1999-09-28 Cypress Semiconductor Corp. Counter-bias scheme to reduce charge gain in an electrically erasable cell
DE19808525A1 (de) 1998-02-27 1999-09-02 Siemens Ag Integrierte Schaltung
JP2000021183A (ja) 1998-06-30 2000-01-21 Matsushita Electric Ind Co Ltd 半導体不揮発性メモリ
US5999451A (en) 1998-07-13 1999-12-07 Macronix International Co., Ltd. Byte-wide write scheme for a page flash device
JP3344331B2 (ja) 1998-09-30 2002-11-11 日本電気株式会社 不揮発性半導体記憶装置
JP2000276889A (ja) 1999-03-23 2000-10-06 Toshiba Corp 不揮発性半導体メモリ
WO2001017030A1 (en) * 1999-08-27 2001-03-08 Macronix America, Inc. Non-volatile memory structure for twin-bit storage and methods of making same
JP2001068650A (ja) * 1999-08-30 2001-03-16 Hitachi Ltd 半導体集積回路装置
KR100338772B1 (ko) * 2000-03-10 2002-05-31 윤종용 바이어스 라인이 분리된 비휘발성 메모리 장치의 워드라인 드라이버 및 워드 라인 드라이빙 방법
US6370071B1 (en) * 2000-09-13 2002-04-09 Lattice Semiconductor Corporation High voltage CMOS switch
KR20040068552A (ko) * 2001-11-27 2004-07-31 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 반도체 디바이스
TW536818B (en) 2002-05-03 2003-06-11 Ememory Technology Inc Single-poly EEPROM
US6621745B1 (en) * 2002-06-18 2003-09-16 Atmel Corporation Row decoder circuit for use in programming a memory device
US6774704B2 (en) 2002-10-28 2004-08-10 Tower Semiconductor Ltd. Control circuit for selecting the greater of two voltage signals
US7038947B2 (en) * 2002-12-19 2006-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Two-transistor flash cell for large endurance application
CN1224106C (zh) * 2003-03-05 2005-10-19 力旺电子股份有限公司 只读存储器及其制作方法
JP2004326864A (ja) 2003-04-22 2004-11-18 Toshiba Corp 不揮発性半導体メモリ
FR2856185A1 (fr) 2003-06-12 2004-12-17 St Microelectronics Sa Memoire flash programmable par mot
US6963503B1 (en) 2003-07-11 2005-11-08 Altera Corporation. EEPROM with improved circuit performance and reduced cell size
JP2005051227A (ja) * 2003-07-17 2005-02-24 Nec Electronics Corp 半導体記憶装置
US7081774B2 (en) * 2003-07-30 2006-07-25 Semiconductor Energy Laboratory Co., Ltd. Circuit having source follower and semiconductor device having the circuit
US7169667B2 (en) * 2003-07-30 2007-01-30 Promos Technologies Inc. Nonvolatile memory cell with multiple floating gates formed after the select gate
US7145370B2 (en) 2003-09-05 2006-12-05 Impinj, Inc. High-voltage switches in single-well CMOS processes
US20050134355A1 (en) 2003-12-18 2005-06-23 Masato Maede Level shift circuit
US20050205969A1 (en) * 2004-03-19 2005-09-22 Sharp Laboratories Of America, Inc. Charge trap non-volatile memory structure for 2 bits per transistor
US7580311B2 (en) * 2004-03-30 2009-08-25 Virage Logic Corporation Reduced area high voltage switch for NVM
US7629640B2 (en) * 2004-05-03 2009-12-08 The Regents Of The University Of California Two bit/four bit SONOS flash memory cell
DE602004010795T2 (de) * 2004-06-24 2008-12-11 Stmicroelectronics S.R.L., Agrate Brianza Verbesserter Seitenspeicher für eine programmierbare Speichervorrichtung
US6992927B1 (en) 2004-07-08 2006-01-31 National Semiconductor Corporation Nonvolatile memory cell
US7209392B2 (en) * 2004-07-20 2007-04-24 Ememory Technology Inc. Single poly non-volatile memory
KR100633332B1 (ko) * 2004-11-09 2006-10-11 주식회사 하이닉스반도체 음의 전압 공급회로
KR100642631B1 (ko) * 2004-12-06 2006-11-10 삼성전자주식회사 전압 발생회로 및 이를 구비한 반도체 메모리 장치
US7369438B2 (en) 2004-12-28 2008-05-06 Aplus Flash Technology, Inc. Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
US7193265B2 (en) 2005-03-16 2007-03-20 United Microelectronics Corp. Single-poly EEPROM
US7263001B2 (en) 2005-03-17 2007-08-28 Impinj, Inc. Compact non-volatile memory cell and array system
US7288964B2 (en) 2005-08-12 2007-10-30 Ememory Technology Inc. Voltage selective circuit of power source
JP4800109B2 (ja) 2005-09-13 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置
JP2007149997A (ja) 2005-11-29 2007-06-14 Nec Electronics Corp 不揮発性メモリセル及びｅｅｐｒｏｍ
US7382658B2 (en) 2006-01-26 2008-06-03 Mosys, Inc. Non-volatile memory embedded in a conventional logic process and methods for operating same
US7391647B2 (en) * 2006-04-11 2008-06-24 Mosys, Inc. Non-volatile memory in CMOS logic process and method of operation thereof
US20070247915A1 (en) * 2006-04-21 2007-10-25 Intersil Americas Inc. Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide
US7773416B2 (en) * 2006-05-26 2010-08-10 Macronix International Co., Ltd. Single poly, multi-bit non-volatile memory device and methods for operating the same
JP4901325B2 (ja) 2006-06-22 2012-03-21 ルネサスエレクトロニクス株式会社 半導体装置
TWI373127B (en) * 2006-06-26 2012-09-21 Ememory Technology Inc Nonvolatile single-poly memory device
US20070296034A1 (en) 2006-06-26 2007-12-27 Hsin-Ming Chen Silicon-on-insulator (soi) memory device
US7768059B2 (en) 2006-06-26 2010-08-03 Ememory Technology Inc. Nonvolatile single-poly memory device
JP5005970B2 (ja) 2006-06-27 2012-08-22 株式会社リコー 電圧制御回路及び電圧制御回路を有する半導体集積回路
CN100508169C (zh) * 2006-08-02 2009-07-01 联华电子股份有限公司 单层多晶硅可电除可程序只读存储单元的制造方法
US7586792B1 (en) * 2006-08-24 2009-09-08 National Semiconductor Corporation System and method for providing drain avalanche hot carrier programming for non-volatile memory applications
KR100805839B1 (ko) * 2006-08-29 2008-02-21 삼성전자주식회사 고전압 발생기를 공유하는 플래시 메모리 장치
US7483310B1 (en) * 2006-11-02 2009-01-27 National Semiconductor Corporation System and method for providing high endurance low cost CMOS compatible EEPROM devices
KR100781041B1 (ko) * 2006-11-06 2007-11-30 주식회사 하이닉스반도체 플래시 메모리 장치 및 그 소거 동작 제어 방법
JP4863844B2 (ja) * 2006-11-08 2012-01-25 セイコーインスツル株式会社 電圧切替回路
US8378407B2 (en) 2006-12-07 2013-02-19 Tower Semiconductor, Ltd. Floating gate inverter type memory cell and array
US7755941B2 (en) * 2007-02-23 2010-07-13 Panasonic Corporation Nonvolatile semiconductor memory device
US7436710B2 (en) 2007-03-12 2008-10-14 Maxim Integrated Products, Inc. EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well
JP4855514B2 (ja) * 2007-03-16 2012-01-18 富士通セミコンダクター株式会社 電源スイッチ回路及び半導体集積回路装置
US7663916B2 (en) 2007-04-16 2010-02-16 Taiwan Semicondcutor Manufacturing Company, Ltd. Logic compatible arrays and operations
US7903465B2 (en) * 2007-04-24 2011-03-08 Intersil Americas Inc. Memory array of floating gate-based non-volatile memory cells
JP4455621B2 (ja) * 2007-07-17 2010-04-21 株式会社東芝 エージングデバイス
US8369155B2 (en) * 2007-08-08 2013-02-05 Hynix Semiconductor Inc. Operating method in a non-volatile memory device
JP2009049182A (ja) 2007-08-20 2009-03-05 Toyota Motor Corp 不揮発性半導体記憶素子
US7700993B2 (en) * 2007-11-05 2010-04-20 International Business Machines Corporation CMOS EPROM and EEPROM devices and programmable CMOS inverters
KR101286241B1 (ko) 2007-11-26 2013-07-15 삼성전자주식회사 최대 전압 선택회로
US7968926B2 (en) 2007-12-19 2011-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Logic non-volatile memory cell with improved data retention ability
CN101965638B (zh) * 2008-01-18 2012-12-05 夏普株式会社 非易失性随机存取存储器
US7639536B2 (en) 2008-03-07 2009-12-29 United Microelectronics Corp. Storage unit of single-conductor non-volatile memory cell and method of erasing the same
US7800426B2 (en) 2008-03-27 2010-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Two voltage input level shifter with switches for core power off application
JP5266443B2 (ja) * 2008-04-18 2013-08-21 インターチップ株式会社 不揮発性メモリセル及び不揮発性メモリセル内蔵データラッチ
US8344443B2 (en) 2008-04-25 2013-01-01 Freescale Semiconductor, Inc. Single poly NVM devices and arrays
US8218377B2 (en) * 2008-05-19 2012-07-10 Stmicroelectronics Pvt. Ltd. Fail-safe high speed level shifter for wide supply voltage range
US7894261B1 (en) 2008-05-22 2011-02-22 Synopsys, Inc. PFET nonvolatile memory
US8295087B2 (en) * 2008-06-16 2012-10-23 Aplus Flash Technology, Inc. Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS
KR101462487B1 (ko) * 2008-07-07 2014-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
US7983081B2 (en) 2008-12-14 2011-07-19 Chip.Memory Technology, Inc. Non-volatile memory apparatus and method with deep N-well
US8189390B2 (en) * 2009-03-05 2012-05-29 Mosaid Technologies Incorporated NAND flash architecture with multi-level row decoding
US8319528B2 (en) * 2009-03-26 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interconnected transistors and electronic device including semiconductor device
KR101020298B1 (ko) 2009-05-28 2011-03-07 주식회사 하이닉스반도체 레벨 시프터 및 반도체 메모리 장치
CN101650972B (zh) * 2009-06-12 2013-05-29 东信和平科技股份有限公司 智能卡的非易失性存储器数据更新方法
JP2011009454A (ja) * 2009-06-25 2011-01-13 Renesas Electronics Corp 半導体装置
FR2952227B1 (fr) 2009-10-29 2013-09-06 St Microelectronics Rousset Dispositif de memoire du type electriquement programmable et effacable, a deux cellules par bit
EP2323135A1 (en) * 2009-11-12 2011-05-18 SiTel Semiconductor B.V. Method and apparatus for emulating byte wise programmable functionality into sector wise erasable memory
KR101071190B1 (ko) * 2009-11-27 2011-10-10 주식회사 하이닉스반도체 레벨 쉬프팅 회로 및 이를 이용한 비휘발성 반도체 메모리 장치
IT1397229B1 (it) * 2009-12-30 2013-01-04 St Microelectronics Srl Dispositivo di memoria ftp programmabile e cancellabile a livello di cella
IN2012DN06399A (zh) * 2010-02-07 2015-10-02 Zeno Semiconductor Inc
US8284600B1 (en) 2010-02-08 2012-10-09 National Semiconductor Corporation 5-transistor non-volatile memory cell
KR101676816B1 (ko) * 2010-02-11 2016-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
US9082652B2 (en) 2010-03-23 2015-07-14 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate, and display device
KR101653262B1 (ko) * 2010-04-12 2016-09-02 삼성전자주식회사 멀티-비트 메모리의 프로그램 방법 및 그것을 이용한 데이터 저장 시스템
US8217705B2 (en) 2010-05-06 2012-07-10 Micron Technology, Inc. Voltage switching in a memory device
US8258853B2 (en) * 2010-06-14 2012-09-04 Ememory Technology Inc. Power switch circuit for tracing a higher supply voltage without a voltage drop
US9042174B2 (en) 2010-06-17 2015-05-26 Ememory Technology Inc. Non-volatile memory cell
US8355282B2 (en) 2010-06-17 2013-01-15 Ememory Technology Inc. Logic-based multiple time programming memory cell
US8958245B2 (en) 2010-06-17 2015-02-17 Ememory Technology Inc. Logic-based multiple time programming memory cell compatible with generic CMOS processes
US8279681B2 (en) 2010-06-24 2012-10-02 Semiconductor Components Industries, Llc Method of using a nonvolatile memory cell
US20120014183A1 (en) * 2010-07-16 2012-01-19 Pavel Poplevine 3 transistor (n/p/n) non-volatile memory cell without program disturb
US8044699B1 (en) * 2010-07-19 2011-10-25 Polar Semiconductor, Inc. Differential high voltage level shifter
KR101868332B1 (ko) * 2010-11-25 2018-06-20 삼성전자주식회사 플래시 메모리 장치 및 그것을 포함한 데이터 저장 장치
US8461899B2 (en) * 2011-01-14 2013-06-11 Stmicroelectronics International N.V. Negative voltage level shifter circuit
JP5685115B2 (ja) * 2011-03-09 2015-03-18 セイコーインスツル株式会社 電源切換回路
DE112012002622B4 (de) * 2011-06-24 2017-01-26 International Business Machines Corporation Aufzeichnungseinheit für lineare Aufzeichnung zum Ausführen optimalen Schreibens beim Empfangen einer Reihe von Befehlen, darunter gemischte Lese- und Schreibbefehle, sowie Verfahren und Programm für dessen Ausführung
US9455021B2 (en) 2011-07-22 2016-09-27 Texas Instruments Incorporated Array power supply-based screening of static random access memory cells for bias temperature instability
KR20130022743A (ko) * 2011-08-26 2013-03-07 에스케이하이닉스 주식회사 고전압 생성회로 및 이를 구비한 반도체 장치
US8999785B2 (en) * 2011-09-27 2015-04-07 Tower Semiconductor Ltd. Flash-to-ROM conversion
CN103078618B (zh) * 2011-10-26 2015-08-12 力旺电子股份有限公司 电压开关电路
JP2013102119A (ja) 2011-11-07 2013-05-23 Ememory Technology Inc 不揮発性メモリーセル
US8508971B2 (en) 2011-11-08 2013-08-13 Wafertech, Llc Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
US9165661B2 (en) * 2012-02-16 2015-10-20 Cypress Semiconductor Corporation Systems and methods for switching between voltages
US9048137B2 (en) 2012-02-17 2015-06-02 Flashsilicon Incorporation Scalable gate logic non-volatile memory cells and arrays
US8941167B2 (en) 2012-03-08 2015-01-27 Ememory Technology Inc. Erasable programmable single-ploy nonvolatile memory
TWI467744B (zh) * 2012-03-12 2015-01-01 Vanguard Int Semiconduct Corp 單層多晶矽可電抹除可程式唯讀記憶裝置
US8787092B2 (en) 2012-03-13 2014-07-22 Ememory Technology Inc. Programming inhibit method of nonvolatile memory apparatus for reducing leakage current
US9390799B2 (en) * 2012-04-30 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory cell devices and methods, having a storage cell with two sidewall bit cells
TWI469328B (zh) 2012-05-25 2015-01-11 Ememory Technology Inc 具可程式可抹除的單一多晶矽層非揮發性記憶體
TWI498901B (zh) * 2012-06-04 2015-09-01 Ememory Technology Inc 利用程式化禁止方法減少漏電流的非揮發性記憶體裝置
US9729145B2 (en) * 2012-06-12 2017-08-08 Infineon Technologies Ag Circuit and a method for selecting a power supply
KR101334843B1 (ko) * 2012-08-07 2013-12-02 주식회사 동부하이텍 전압 출력 회로 및 이를 이용한 네거티브 전압 선택 출력 장치
KR102038041B1 (ko) 2012-08-31 2019-11-26 에스케이하이닉스 주식회사 전원 선택 회로
CN104521146B (zh) * 2012-09-06 2017-09-22 松下知识产权经营株式会社 半导体集成电路
US9130553B2 (en) 2012-10-04 2015-09-08 Nxp B.V. Low/high voltage selector
JP5556873B2 (ja) * 2012-10-19 2014-07-23 株式会社フローディア 不揮発性半導体記憶装置
JP6053474B2 (ja) * 2012-11-27 2016-12-27 株式会社フローディア 不揮発性半導体記憶装置
JP2014116547A (ja) 2012-12-12 2014-06-26 Renesas Electronics Corp 半導体装置
JP6078327B2 (ja) * 2012-12-19 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置
US8963609B2 (en) * 2013-03-01 2015-02-24 Arm Limited Combinatorial circuit and method of operation of such a combinatorial circuit
US9275748B2 (en) * 2013-03-14 2016-03-01 Silicon Storage Technology, Inc. Low leakage, low threshold voltage, split-gate flash cell operation
KR102095856B1 (ko) * 2013-04-15 2020-04-01 삼성전자주식회사 반도체 메모리 장치 및 그것의 바디 바이어스 방법
US9197200B2 (en) 2013-05-16 2015-11-24 Dialog Semiconductor Gmbh Dynamic level shifter circuit
US9362374B2 (en) * 2013-06-27 2016-06-07 Globalfoundries Singapore Pte. Ltd. Simple and cost-free MTP structure
US9520404B2 (en) 2013-07-30 2016-12-13 Synopsys, Inc. Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
CN103456359A (zh) * 2013-09-03 2013-12-18 苏州宽温电子科技有限公司 基于串联晶体管型的改进的差分架构Nor flash存储单元
US9236453B2 (en) * 2013-09-27 2016-01-12 Ememory Technology Inc. Nonvolatile memory structure and fabrication method thereof
US9019780B1 (en) * 2013-10-08 2015-04-28 Ememory Technology Inc. Non-volatile memory apparatus and data verification method thereof
KR20150042041A (ko) * 2013-10-10 2015-04-20 에스케이하이닉스 주식회사 전압발생기, 집적회로 및 전압 발생 방법
FR3012673B1 (fr) * 2013-10-31 2017-04-14 St Microelectronics Rousset Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire
KR102072767B1 (ko) * 2013-11-21 2020-02-03 삼성전자주식회사 고전압 스위치 및 그것을 포함하는 불휘발성 메모리 장치
US9159425B2 (en) * 2013-11-25 2015-10-13 Stmicroelectronics International N.V. Non-volatile memory with reduced sub-threshold leakage during program and erase operations
KR102157875B1 (ko) * 2013-12-19 2020-09-22 삼성전자주식회사 불휘발성 메모리 장치 및 그것을 포함한 메모리 시스템
JP6235901B2 (ja) 2013-12-27 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置
US9331699B2 (en) 2014-01-08 2016-05-03 Micron Technology, Inc. Level shifters, memory systems, and level shifting methods
KR20160132405A (ko) * 2014-03-12 2016-11-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN103943570A (zh) * 2014-03-20 2014-07-23 上海华力微电子有限公司 一种一次性编程存储器中金属硅化物掩膜的制备方法
US9508396B2 (en) * 2014-04-02 2016-11-29 Ememory Technology Inc. Array structure of single-ploy nonvolatile memory
JP5745136B1 (ja) * 2014-05-09 2015-07-08 力晶科技股▲ふん▼有限公司 不揮発性半導体記憶装置とその書き込み方法
FR3021806B1 (fr) * 2014-05-28 2017-09-01 St Microelectronics Sa Procede de programmation d'une cellule memoire non volatile comprenant une grille de transistor de selection partagee
FR3021804B1 (fr) * 2014-05-28 2017-09-01 Stmicroelectronics Rousset Cellule memoire non volatile duale comprenant un transistor d'effacement
JP6286292B2 (ja) 2014-06-20 2018-02-28 株式会社フローディア 不揮発性半導体記憶装置
US20160006348A1 (en) 2014-07-07 2016-01-07 Ememory Technology Inc. Charge pump apparatus
US9431111B2 (en) * 2014-07-08 2016-08-30 Ememory Technology Inc. One time programming memory cell, array structure and operating method thereof
CN104112472B (zh) * 2014-07-22 2017-05-03 中国人民解放军国防科学技术大学 兼容标准cmos工艺的超低功耗差分结构非易失性存储器
CN104361906B (zh) * 2014-10-24 2017-09-19 中国人民解放军国防科学技术大学 基于标准cmos工艺的超低功耗非易失性存储器
US9514820B2 (en) * 2014-11-19 2016-12-06 Stmicroelectronics (Rousset) Sas EEPROM architecture wherein each bit is formed by two serially connected cells
JP6340310B2 (ja) 2014-12-17 2018-06-06 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびウェラブル装置
TWI546903B (zh) * 2015-01-15 2016-08-21 聯笙電子股份有限公司 非揮發性記憶體單元
JP6457829B2 (ja) 2015-02-05 2019-01-23 ルネサスエレクトロニクス株式会社 半導体装置
CN104900266B (zh) * 2015-06-10 2018-10-26 上海华虹宏力半导体制造有限公司 Eeprom存储单元门极控制信号产生电路
US9799395B2 (en) 2015-11-30 2017-10-24 Texas Instruments Incorporated Sense amplifier in low power and high performance SRAM
US9847133B2 (en) 2016-01-19 2017-12-19 Ememory Technology Inc. Memory array capable of performing byte erase operation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI781281B (zh) * 2018-02-23 2022-10-21 南韓商Ｓｋ海力士系統集成電路有限公司 具有經提高程式化效率的一次性可程式化記憶體裝置及其製造方法
TWI742880B (zh) * 2019-11-14 2021-10-11 力旺電子股份有限公司 唯讀式記憶胞及其相關的記憶胞陣列

Also Published As

Publication number Publication date
US20170206941A1 (en) 2017-07-20
EP3196883A1 (en) 2017-07-26
EP3410440B1 (en) 2020-05-13
CN106981307B (zh) 2020-04-07
CN108154898A (zh) 2018-06-12
US9812212B2 (en) 2017-11-07
TW201801084A (zh) 2018-01-01
CN106981307A (zh) 2017-07-25
CN106981492A (zh) 2017-07-25
US10096368B2 (en) 2018-10-09
TWI646665B (zh) 2019-01-01
US20170207230A1 (en) 2017-07-20
CN106981492B (zh) 2020-10-20
CN108320772B (zh) 2020-07-10
US20170206969A1 (en) 2017-07-20
TW201828302A (zh) 2018-08-01
CN106981311A (zh) 2017-07-25
JP2017130646A (ja) 2017-07-27
JP2017139045A (ja) 2017-08-10
TW201727632A (zh) 2017-08-01
CN106981309B (zh) 2020-02-14
US10121550B2 (en) 2018-11-06
JP2017130247A (ja) 2017-07-27
EP3196885A1 (en) 2017-07-26
CN108206186B (zh) 2020-10-13
US9847133B2 (en) 2017-12-19
CN108154898B (zh) 2021-02-02
TW201830665A (zh) 2018-08-16
CN107017023A (zh) 2017-08-04
JP6285001B2 (ja) 2018-02-28
US10262746B2 (en) 2019-04-16
TWI613654B (zh) 2018-02-01
EP3196883B1 (en) 2019-09-04
US20180190357A1 (en) 2018-07-05
EP3196886A1 (en) 2017-07-26
US10038003B2 (en) 2018-07-31
TWI587455B (zh) 2017-06-11
EP3197051B1 (en) 2020-01-15
US20170206975A1 (en) 2017-07-20
US20170206970A1 (en) 2017-07-20
TW201824520A (zh) 2018-07-01
US9653173B1 (en) 2017-05-16
US9941011B2 (en) 2018-04-10
JP2018101767A (ja) 2018-06-28
EP3196885B1 (en) 2019-03-27
TWI618072B (zh) 2018-03-11
US20170207228A1 (en) 2017-07-20
US9786340B2 (en) 2017-10-10
US20180261294A1 (en) 2018-09-13
EP3196886B1 (en) 2021-03-31
CN106981304A (zh) 2017-07-25
TWI578322B (zh) 2017-04-11
TW201727651A (zh) 2017-08-01
EP3410440A1 (en) 2018-12-05
CN106981311B (zh) 2019-08-30
US20170206968A1 (en) 2017-07-20
TW201822212A (zh) 2018-06-16
TW201727649A (zh) 2017-08-01
CN106981299A (zh) 2017-07-25
TWI630615B (zh) 2018-07-21
CN107017023B (zh) 2020-05-05
US10255980B2 (en) 2019-04-09
TWI613672B (zh) 2018-02-01
EP3197051A1 (en) 2017-07-26
US9520196B1 (en) 2016-12-13
TWI641115B (zh) 2018-11-11
US20170206976A1 (en) 2017-07-20
TW201740374A (zh) 2017-11-16
US9792993B2 (en) 2017-10-17
EP3196884B1 (en) 2021-08-04
CN106981309A (zh) 2017-07-25
CN106981299B (zh) 2019-10-18
US9805776B2 (en) 2017-10-31
CN108206186A (zh) 2018-06-26
TWI613659B (zh) 2018-02-01
TWI621123B (zh) 2018-04-11
TW201737256A (zh) 2017-10-16
JP6566975B2 (ja) 2019-08-28
JP6122531B1 (ja) 2017-04-26
US20170206945A1 (en) 2017-07-20
JP6392379B2 (ja) 2018-09-19
TWI614763B (zh) 2018-02-11
CN106981304B (zh) 2020-02-07
CN108320772A (zh) 2018-07-24
EP3196884A1 (en) 2017-07-26

Similar Documents

Publication Publication Date Title
TWI587455B (zh) 非揮發性記憶體結構
TWI582959B (zh) 具有輔助閘極之非揮發性記憶胞結構及其記憶體陣列
US11610630B2 (en) Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
JP5317742B2 (ja) 半導体装置
US9805806B2 (en) Non-volatile memory cell and method of operating the same
TWI681510B (zh) 單位元多記憶胞之非揮發性記憶體單元
JP3884397B2 (ja) 不揮発性半導体記憶装置
TWI705440B (zh) 單多晶非揮發性記憶單元
KR20160051175A (ko) 단일층 게이트를 갖는 불휘발성 메모리소자
JP5101085B2 (ja) 不揮発性メモリ素子
JPWO2006087796A1 (ja) 不揮発性半導体記憶装置
US7382653B2 (en) Electrically rewritable non-volatile semiconductor memory device
JP5483826B2 (ja) 不揮発性半導体記憶装置及びその書き込み方法
JP2012204435A (ja) 不揮発性半導体記憶装置