US10038003B2 - Single-poly nonvolatile memory cell structure having an erase device - Google Patents

Single-poly nonvolatile memory cell structure having an erase device Download PDF

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US10038003B2
US10038003B2 US15/384,323 US201615384323A US10038003B2 US 10038003 B2 US10038003 B2 US 10038003B2 US 201615384323 A US201615384323 A US 201615384323A US 10038003 B2 US10038003 B2 US 10038003B2
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region
floating gate
memory cell
nonvolatile memory
pmos
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US20170207230A1 (en
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Wein-Town Sun
Wei-Ren Chen
Ying-Je Chen
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eMemory Technology Inc
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eMemory Technology Inc
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Assigned to EMEMORY TECHNOLOGY INC. reassignment EMEMORY TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, WEI-REN, CHEN, YING-JE, SUN, WEIN-TOWN
Priority to JP2017000304A priority patent/JP6392379B2/en
Priority to TW106104042A priority patent/TWI646665B/en
Priority to CN201710135824.3A priority patent/CN108206186B/en
Publication of US20170207230A1 publication Critical patent/US20170207230A1/en
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    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
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    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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Definitions

  • the present invention relates to a nonvolatile memory and, more particularly, to a single-poly nonvolatile memory cell structure having an erase device on a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • FIG. 1 is a schematic layout diagram of a single-poly non-volatile memory cell.
  • the single-poly non-volatile memory cell 10 comprises two serially connected PMOS transistors 12 and 14 .
  • the PMOS transistor 12 includes a select gate 22 , a P + source doping region 32 and a P + drain/source doping region 34 .
  • the PMOS transistor 14 includes a floating gate 24 , the P + drain/source doping region 34 and a P + drain doping region 36 .
  • the two serially connected PMOS transistors 12 and 14 share the P + drain/source doping region 34 .
  • the single-poly non-volatile memory cell 10 is fully compatible with CMOS logic processes.
  • the select gate 22 of the PMOS transistor 12 is coupled to a select gate voltage V SG , the P + source doping region 32 of the PMOS transistor 12 is electrically coupled to a source line voltage V SL by way of a source line contact, the P + drain/source doping region 34 and the floating gate 24 are electrically floating, and the P + drain doping region 36 of the PMOS transistor 14 is electrically coupled to a bit line voltage V BL through a bit line contact.
  • the program mode electrons are selectively injected and stored in the floating gate 24 .
  • the memory structure is operated at low voltages.
  • the single-poly non-volatile memory is compatible with standard CMOS logic processes, it is usually applied in the field of embedded memory, embedded non-volatile memory in the mixed-mode circuits and micro-controllers (such as System on Chip, SOC).
  • MTP multi-time programmable
  • a single-poly nonvolatile memory cell includes a silicon-on-insulator (SOI) substrate comprising a silicon substrate, a buried oxide layer, and a semiconductor layer; a first oxide define (OD) region and a second oxide define (OD) region on the semiconductor layer; an isolation region in the semiconductor layer, the isolation region separating the first OD region from the second OD region; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor disposed on the first OD region, the PMOS floating gate transistor being serially connected to the PMOS select transistor, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and a floating gate extension continuously extended from the floating gate to the second OD region and being capacitively coupled to the second OD region.
  • SOI silicon-on-insulator
  • the PMOS select transistor comprises a select gate, a select gate oxide layer between the select gate and the semiconductor layer, a P + source doping region, and a P + drain/source doping region, wherein the P + source doping region is electrically connected to a source line.
  • the PMOS floating gate transistor comprises a floating gate, a floating gate oxide layer between the floating gate and the semiconductor layer, a P + drain doping region and the P + drain/source doping region, wherein the P + drain/source doping region is shared by the PMOS select transistor and the PMOS floating gate transistor.
  • an ion well such as an N well or a P well may be disposed in the semiconductor layer.
  • the ion well completely overlaps with the second OD region.
  • a heavily doped region such as N + or P + doping region is disposed in the ion well within the second OD region.
  • the second OD region, the heavily doped region, the floating gate oxide layer, and the floating gate extension that is capacitively coupled to the heavily doped region together constitute an erase device.
  • the single-poly nonvolatile memory cell further comprises a charge collecting region that is contiguous with the first OD region, wherein the charge collecting region collects redundant electrons and holes accumulated in the semiconductor layer during operation of the single-poly nonvolatile memory cell.
  • the charge collecting region comprises a third OD region, an N + doping region in the third OD region, abridge region connecting the N + doping region with the semiconductor layer directly under the floating gate.
  • the single-poly nonvolatile memory cell further comprises an N + doping region that is contiguous with the P + doping region on the same side of the select gate, thereby forming a butted contact region.
  • FIG. 1 is a schematic layout diagram showing a prior art single-poly non-volatile memory cell
  • FIG. 2 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to one embodiment of this invention
  • FIG. 3 is a cross-sectional view of a memory cell unit taken along line I-I′ in FIG. 2 ;
  • FIG. 4 is a cross-sectional view of a memory cell unit taken along line II-II′ in FIG. 2 ;
  • FIG. 5 to FIG. 7 show variants of the single-poly nonvolatile memory of FIG. 2 according to other embodiments of the invention.
  • FIG. 8 illustrates an exemplary operation conditions for programming (PGM), reading (READ) or erasing (ERS) operations of the memory cell unit as set forth through FIG. 2 to FIG. 7 ;
  • FIG. 9 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to another embodiment of this invention.
  • FIG. 10 is a cross-sectional view of a memory cell unit taken along line in FIG. 9 ;
  • FIG. 11 is a cross-sectional view of a memory cell unit taken along line IV-IV′ in FIG. 9 ;
  • FIG. 12 shows a variant of the single-poly nonvolatile memory of FIG. 9 according to still another embodiment of the invention.
  • FIG. 13 illustrates an exemplary operation conditions for programming (PGM), reading (READ) or erasing (ERS) operations of the memory cell unit as set forth in FIG. 9 and FIG. 12 .
  • the present invention pertains to a single-poly non-volatile memory having an erase device, which may function as a multi-time programmable memory (MTP).
  • the single-poly non-volatile memory is fabricated on an SOI (silicon-on-insulator or semiconductor-on-insulator) substrate.
  • the SOI substrate may comprises a silicon substrate, a buried oxide layer, and a silicon (or semiconductor) active layer on the buried oxide layer.
  • the single-poly non-volatile memory device is fabricated in or on the silicon (or semiconductor) active layer.
  • the SOI substrate may be any commercially available SOI products, which can be fabricated using conventional SIMOX method, but not limited thereto.
  • the single-poly non-volatile memory device may be a fully depleted SOI device or partially depleted SOI device.
  • FIG. 2 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to one embodiment of this invention.
  • FIG. 3 is a cross-sectional view taken along line I-I′ in FIG. 2 .
  • FIG. 4 is a cross-sectional view taken along line II-II′ in FIG. 2 .
  • the single-poly nonvolatile memory 1 comprises a plurality of memory cells including, for example, four memory cell units C 1 ⁇ C 4 .
  • the layout of the memory cells in FIG. 2 is for illustration purposes only. In FIG. 2 , for example, only three oxide define (OD) regions: OD 1 , OD 2 , and OD 3 are shown.
  • the memory cells C 1 and C 2 are fabricated on the oxide define region OD 1 and the memory cells C 3 and C 4 are fabricated on the oxide define region OD 2 .
  • the oxide define regions OD 1 , OD 2 , and OD 3 may be strip-shaped regions extending along a reference y-axis.
  • the oxide define regions OD 1 , OD 2 , and OD 3 are isolated from one another by the shallow trench isolation (STI) region 300 .
  • Only two word lines WL 1 and WL 2 are shown in FIG. 2 .
  • the two word lines WL 1 and WL 2 intersect the oxide define regions OD 1 , OD 2 and extend along a reference x-axis.
  • An erase device 250 may be fabricated on the oxide define region OD 3 .
  • the erase device 250 may be shared by the four memory cell units C 1 ⁇ C 4 .
  • the oxide define region OD 3 is interposed between the oxide define region OD 1 and the oxide define region OD 2 .
  • the oxide define region OD 3 is spaced apart from the two word lines WL 1 and WL 2 .
  • the oxide define region OD 3 does not overlap with the two word lines WL 1 and WL 2 when viewed from the above.
  • the memory cell unit C 1 and the memory cell unit C 2 share the same P + drain/source doping region and the same bit line contact.
  • the memory cell unit C 3 and the memory cell unit C 4 share the same P + drain doping region and the same bit line contact.
  • each of the four memory cell units (taking the memory cell unit C 1 as an example) comprises a PMOS select transistor 102 and a PMOS floating gate transistor 104 that is serially connected to the PMOS select transistor 102 .
  • the PMOS select transistor 102 and the PMOS floating gate transistor 104 are formed together on the oxide define region OD 1 that is defined in the semiconductor layer 230 of an SOI substrate 200 .
  • the cell structure of the memory cell units C 2 is mirror-symmetric to the memory cell unit C 1 .
  • the cell structures of the memory cell units C 3 and C 4 are mirror-symmetric to the memory cell units C 1 and C 2 , respectively.
  • the semiconductor layer 230 may be a single-crystalline silicon layer, but is not limited thereto.
  • the SOI substrate 200 may further comprise a buried oxide layer 220 and a silicon substrate 210 .
  • the semiconductor layer 230 is electrically isolated from the silicon substrate 210 by the buried oxide layer 220 .
  • the STI region 300 is contiguous with the buried oxide layer 230 .
  • the silicon substrate 210 may be a P type silicon substrate, but is not limited thereto.
  • an N well 310 which is completely overlapped with the oxide define region OD 1 , maybe formed by using ion implantation methods. In some embodiments, the N well 310 may be omitted so that the channel maybe formed in the intrinsic silicon.
  • the PMOS select transistor 102 comprises a select gate 110 , a select gate oxide layer 112 between the select gate 110 and the semiconductor layer 230 , a P + source doping region 132 , and a P + drain/source doping region 134 .
  • the PMOS floating gate transistor 104 comprises a floating gate 120 , a floating gate oxide layer 122 between the floating gate 120 and the semiconductor layer 230 , the P + drain/source doping region 134 , and a P + drain doping region 136 .
  • the PMOS select transistor 102 and the PMOS floating gate transistor 104 share the P + drain/source doping region 134 .
  • spacers on the sidewalls of the select gate 110 and the floating gate 120 are not illustrated.
  • the floating gate 120 includes an extended portion (or floating gate extension) 120 a that extends along the reference x direction to overlap with the oxide define region OD 3 .
  • the extended portion 120 a may have a width that is smaller than the width of the floating gate 120 .
  • the overlapping area between the extended portion 120 a and the oxide define region OD 3 is smaller than the overlapping area between the floating gate 120 and the oxide define region OD 1 .
  • a heavily doped region 138 is formed in the oxide define region OD 3 .
  • the heavily doped region 138 may be an N + doping region or a P + doping region.
  • An ion well 320 such as an N well or a P well may be formed in the semiconductor layer 230 and completely overlaps with the oxide define region OD 3 .
  • the heavily doped region 138 may be formed within the intrinsic silicon, and in such case, no ion well is formed in the oxide define region OD 3 . It is to be understood that the shape of the floating gate is only for illustration purposes.
  • the oxide define region OD 3 , the heavily doped region 138 , the floating gate oxide layer 122 , and the extended portion 120 a that is capacitively coupled to the heavily doped region 138 and the oxide define region OD 3 together constitute the erase device 250 .
  • the select gate 110 of the PMOS select transistor 102 is coupled to a select gate voltage V SG by way of a word line contact 510
  • the P + source doping region 132 of the PMOS select transistor 102 is electrically coupled to a source line voltage V SL by way of a source line (SL) contact
  • the P + drain/source doping region 134 and the floating gate 120 are electrically floating
  • the P + drain doping region 136 of the PMOS floating gate transistor 104 is electrically coupled to a bit line voltage V BL through a bit line (BL) contact.
  • the heavily doped region 138 is electrically coupled to an erase line voltage V EL through an erase line (EL) contact.
  • electrons are selectively injected into the floating gate 120 by channel hot electron (CHE) injection.
  • electrons may be erased from the floating gate 120 by Fowler-Nordheim (FN) tunneling.
  • CHE channel hot electron
  • FN Fowler-Nordheim
  • FIG. 5 to FIG. 7 show variants of the single-poly nonvolatile memory having an erase device according to other embodiments of the invention.
  • the difference between the single-poly nonvolatile memory 2 depicted in FIG. 5 and the single-poly nonvolatile memory 1 depicted in FIG. 2 is that the single-poly nonvolatile memory 2 further comprises a charge collecting region 50 that is contiguous with the oxide define region OD 1 .
  • the charge collecting region 50 is able to collect redundant electrons and holes accumulated in the semiconductor layer 230 during operation of the single-poly nonvolatile memory cell.
  • the charge collecting region 50 comprises an oxide define region OD 4 , an N + doping region 500 in the oxide define region OD 4 , a bridge region 520 connecting the N + doping region 500 with the semiconductor layer 230 directly under the floating gate 120 .
  • the N well 310 may overlap with the oxide define region OD 4 and the bridge region 520 .
  • An N well (NW) contact may be provided on the N + doping region 500 to electrically couple the charge collecting region 50 to an N well voltage V NW .
  • the two memory cells C 1 and C 2 share one charge collecting region and the two memory cells C 3 and C 4 share one charge collecting region.
  • the difference between the single-poly nonvolatile memory 3 depicted in FIG. 6 and the single-poly nonvolatile memory 3 depicted in FIG. 6 is that the single-poly nonvolatile memory 3 further comprises an N + doping region 162 that is contiguous with the P + doping region 132 on the same side of the select gate 110 , thereby forming a butted contact region 60 .
  • the N + doping region 162 and the P + doping region 132 are both electrically coupled to the source line voltage V SL .
  • the single-poly nonvolatile memory 4 comprises charge collecting region 50 that is contiguous with the oxide define region OD 1 .
  • the charge collecting region 50 is able to collect redundant electrons and holes accumulated in the semiconductor layer 230 during operation of the memory.
  • the charge collecting region 50 is described in FIG. 5 .
  • the single-poly nonvolatile memory 4 also comprises an N + doping region 162 that is contiguous with the P + doping region 132 on the same side of the select gate 110 , thereby forming a butted contact region 60 .
  • the N + doping region 162 and the P + doping region 132 are both electrically coupled to the source line voltage V SL .
  • FIG. 8 illustrates an exemplary operation conditions for programming (PGM) , reading (READ) or erasing (ERS) operations of the memory cell unit as set forth through FIG. 2 to FIG. 7 .
  • the source line (SL) is coupled to a voltage source V PP .
  • V PP may range between 5 ⁇ 9V.
  • the select gate (SG) 110 is provided with a voltage source between 0 ⁇ 1 ⁇ 2 V PP .
  • the erase line (EL) is provided with a voltage source between 0 ⁇ V PP .
  • the N + doping region 500 is coupled to a voltage source V PP .
  • the voltage conditions for the memory cells under program-inhibit (PGM-inhibit) operation or under program-unselect (PGM-unselect) operation are also listed in FIG. 8 .
  • the erase line (EL) is provided with a voltage source V EE .
  • V EE may range between 8 ⁇ 18V.
  • the source line (SL) may be coupled to a voltage source V BB .
  • V BB may range between ⁇ 4 ⁇ 8V.
  • the bit line (BL) is coupled to the voltage source V BB .
  • the select gate (SG) 110 is coupled to the voltage source V BB .
  • the erase line (EL) is provided with V EE .
  • V EE may range between 8 ⁇ 18V.
  • the N + doping region 500 is coupled to the voltage source V BB .
  • the source line (SL) is coupled to a voltage source V READ
  • V READ may range between 2 ⁇ 2.8V.
  • the N + doping region 500 is coupled to V READ .
  • the voltage conditions for the memory cells under read-unselect (READ-unselect) operation are also listed in FIG. 8 .
  • FIG. 9 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to another embodiment of this invention.
  • FIG. 10 is a cross-sectional view of a memory cell unit taken along line III-III′ in FIG. 9 .
  • FIG. 11 is a cross-sectional view of a memory cell unit taken along line IV-IV′ in FIG. 9 .
  • the single-poly nonvolatile memory 5 comprises a plurality of memory cells including, for example, four memory cell units C 1 ⁇ C 4 . It is understood that the layout of the memory cells in FIG. 9 is for illustration purposes only. In FIG.
  • the memory cells C 1 and C 2 are fabricated on the oxide define region OD 1 and the memory cells C 3 and C 4 are fabricated on the oxide define region OD 2 .
  • the oxide define regions OD 1 and OD 2 may be strip-shaped regions extending along a reference y-axis.
  • the oxide define regions OD 1 , OD 2 , and OD 3 are isolated from one another by the shallow trench isolation (STI) region 300 .
  • Only two word lines WL 1 and WL 2 are shown in FIG. 9 .
  • the two word lines WL 1 and WL 2 intersect the oxide define regions OD 1 , OD 2 and extend along a reference x-axis.
  • An erase device 450 may be fabricated on the oxide define region OD 3 .
  • the erase device 450 maybe shared by the four memory cell units C 1 ⁇ C 4 .
  • the oxide define region OD 3 is interposed between the oxide define region OD 1 and the oxide define region OD 2 .
  • the oxide define region OD 3 is spaced apart from the two word lines WL 1 and WL 2 .
  • the oxide define region OD 3 does not overlap with the two word lines WL 1 and WL 2 when viewed from the above.
  • the memory cell unit C 1 and the memory cell unit C 2 share the same P + drain/source doping region and the same bit line contact.
  • the memory cell unit C 3 and the memory cell unit C 4 share the same P + drain doping region and the same bit line contact.
  • each of the four memory cell units (taking the memory cell unit C 1 as an example) comprises a PMOS select transistor 102 and a PMOS floating gate transistor 104 that is serially connected to the PMOS select transistor 102 .
  • the PMOS select transistor 102 and the PMOS floating gate transistor 104 are formed together on the oxide define region OD 1 that is defined in the semiconductor layer 230 of an SOI substrate 200 .
  • the cell structure of the memory cell units C 2 is mirror-symmetric to the memory cell unit C 1 .
  • the cell structures of the memory cell units C 3 and C 4 are mirror-symmetric to the memory cell units C 1 and C 2 , respectively.
  • the semiconductor layer 230 may be a single-crystalline silicon layer, but is not limited thereto.
  • the SOI substrate 200 may further comprise a buried oxide layer 220 and a silicon substrate 210 .
  • the semiconductor layer 230 is electrically isolated from the silicon substrate 210 by the buried oxide layer 220 .
  • the STI region 300 is contiguous with the buried oxide layer 230 .
  • the silicon substrate 210 may be a P type silicon substrate, but is not limited thereto.
  • an N well 310 which is completely overlapped with the oxide define region OD 1 , maybe formed by using ion implantation methods. In some embodiments, the N well 310 may be omitted so that the channel maybe formed in the intrinsic silicon.
  • the PMOS select transistor 102 comprises a select gate 110 , a select gate oxide layer 122 between the select gate 110 and the semiconductor layer 230 , a P + source doping region 132 , and a P + drain/source doping region 134 .
  • the PMOS floating gate transistor 104 comprises a floating gate 120 , a floating gate oxide layer 122 between the floating gate 120 and the semiconductor layer 230 , the P + drain/source doping region 134 , and a P + drain doping region 136 .
  • the PMOS select transistor 102 and the PMOS floating gate transistor 104 share the P + drain/source doping region 134 .
  • spacers on the sidewalls of the select gate 110 and the floating gate 120 are not illustrated.
  • the floating gate 120 includes an extended portion 120 b that extends along the reference x direction to overlap with the oxide define region OD 3 .
  • the extended portion 120 b may have a width that is greater than the width of the floating gate 120 .
  • the overlapping area between the extended portion 120 b and the oxide define region OD 3 is greater than the overlapping area between the floating gate 120 and the oxide define region OD 1 .
  • a heavily doped region 138 is formed in the oxide define region OD 3 .
  • the heavily doped region 138 may be an N + doping region or a P + doping region.
  • An ion well 320 such as an N well or a P well may be formed in the oxide define region OD 3 .
  • the heavily doped region 138 is an N + doping region and the ion well 320 is an N well.
  • the heavily doped region 138 is a P + doping region and the ion well 320 is a P well. It is to be understood that the shape of the floating gate is only for illustration purposes.
  • the oxide define region OD 3 , the heavily doped region 138 , the floating gate oxide layer 122 , and the extended portion 120 b that is capacitively coupled to the heavily doped region 138 and the oxide define region OD 3 together constitute the erase device 450 .
  • the oxide define region OD 3 and the heavily doped region 138 may serve as a control gate.
  • the select gate 110 of the PMOS select transistor 102 is coupled to a select gate voltage V SG
  • the P + source doping region 132 of the PMOS select transistor 102 is electrically coupled to a source line voltage V BL by way of a source line (SL) contact
  • the P + drain/source doping region 134 and the floating gate 120 are electrically floating
  • the P + drain doping region 136 of the PMOS floating gate transistor 104 is electrically coupled to a bit line voltage V BL through a bit line (BL) contact.
  • the heavily doped region 138 is electrically coupled to a control gate voltage V CG .
  • electrons are selectively injected into the floating gate 120 by channel hot electron (CHE) injection.
  • CHE channel hot electron
  • erase mode ctor or chip erase
  • electrons may be erased from the floating gate 120 by Fowler-Nordheim (FN) tunneling.
  • FN Fowler-Nordheim
  • FIG. 12 shows a variant of the single-poly nonvolatile memory having an erase device according to still another embodiment of the invention.
  • the difference between the single-poly nonvolatile memory 6 depicted in FIG. 12 and the single-poly nonvolatile memory 5 depicted in FIG. 9 is that the single-poly nonvolatile memory 6 further comprises a charge collecting region 50 that is contiguous with the oxide define region OD 1 .
  • the charge collecting region 50 is able to collect redundant electrons and holes accumulated in the semiconductor layer 230 during operation of the memory.
  • the charge collecting region 50 comprises an oxide define region OD 4 , an N + doping region 500 in the oxide define region OD 4 , a bridge region 520 connecting the N + doping region 500 with the semiconductor layer 230 directly under the floating gate 120 .
  • the N well 310 may overlap with the oxide define region OD 4 and the bridge region 520 .
  • An N well (NW) contact may be provided on the N + doping region 500 to electrically couple the charge collecting region 50 to an N well voltage V NW .
  • the two memory cells C 1 and C 2 share one charge collecting region and the two memory cells C 3 and C 4 share one charge collecting region.
  • FIG. 13 illustrates an exemplary operation conditions for programming (PGM), reading (READ) or erasing (ERS) operations of the memory cell unit as set forth in FIG. 9 and FIG. 12 .
  • the source line (SL) is coupled to a voltage source V PP .
  • V PP may range between 5 ⁇ 9V.
  • the select gate (SG) 110 is provided with a voltage source between 0 ⁇ 1 ⁇ 2 V PP .
  • the control gate (CG) is provided with a voltage source between 0 ⁇ 1 ⁇ 2 V PP .
  • the N + doping region 500 is coupled to a voltage source V PP .
  • the voltage conditions for the memory cells under program-inhibit (PGM-inhibit) operation or under program-unselect (PGM-unselect) operation are also listed in FIG. 13 .
  • the source line (SL) is coupled to voltage source V EE (V EE may range between 8 ⁇ 18V).
  • the bit line (BL) is coupled to voltage source V EE .
  • the select gate (SG) 110 is coupled to voltage source V EE or V EE ⁇ V ( ⁇ V>Vt).
  • V EE may range between 8 ⁇ 18V.
  • the N + doping region 500 is grounded.
  • the source line (SL) is coupled to a voltage source V READ
  • V READ may range between 2 ⁇ 2.8V.
  • the N + doping region 500 is coupled to V READ .
  • the voltage conditions for the memory cells under read-unselect (READ-unselect) operation are also listed in FIG. 13 .

Abstract

A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. provisional application No. 62/280,683 filed Jan. 19, 2016.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory and, more particularly, to a single-poly nonvolatile memory cell structure having an erase device on a silicon-on-insulator (SOI) substrate.
2. Description of the Prior Art
Single-poly non-volatile memory is known in the art. FIG. 1 is a schematic layout diagram of a single-poly non-volatile memory cell. As shown in FIG. 1, the single-poly non-volatile memory cell 10 comprises two serially connected PMOS transistors 12 and 14. The PMOS transistor 12 includes a select gate 22, a P+ source doping region 32 and a P+ drain/source doping region 34. The PMOS transistor 14 includes a floating gate 24, the P+ drain/source doping region 34 and a P+ drain doping region 36. The two serially connected PMOS transistors 12 and 14 share the P+ drain/source doping region 34. The single-poly non-volatile memory cell 10 is fully compatible with CMOS logic processes.
In operation, the select gate 22 of the PMOS transistor 12 is coupled to a select gate voltage VSG, the P+ source doping region 32 of the PMOS transistor 12 is electrically coupled to a source line voltage VSL by way of a source line contact, the P+ drain/source doping region 34 and the floating gate 24 are electrically floating, and the P+ drain doping region 36 of the PMOS transistor 14 is electrically coupled to a bit line voltage VBL through a bit line contact. Under the program mode, electrons are selectively injected and stored in the floating gate 24. The memory structure is operated at low voltages.
Because the single-poly non-volatile memory is compatible with standard CMOS logic processes, it is usually applied in the field of embedded memory, embedded non-volatile memory in the mixed-mode circuits and micro-controllers (such as System on Chip, SOC).
There is a trend to make smaller and smaller NVM devices. As the NVM devices become smaller, it is anticipated that the cost per bit of a memory system will be reduced. However, the scalability of the prior art NVM cell is limited by the rule of implanting I/O ion wells that are implanted into the substrate to a junction depth that is deeper than the depth of the shallow trench isolation (STI) in the memory array region.
SUMMARY OF THE INVENTION
It is one object of the invention to provide an improved single-poly nonvolatile memory cell structure having an erase device formed in an SOI (silicon-on-insulator) substrate.
It is another objective of the invention to provide an improved single-poly, multi-time programmable (MTP) non-volatile memory cell that has reduced memory cell size.
According to one aspect of the invention, a single-poly nonvolatile memory cell includes a silicon-on-insulator (SOI) substrate comprising a silicon substrate, a buried oxide layer, and a semiconductor layer; a first oxide define (OD) region and a second oxide define (OD) region on the semiconductor layer; an isolation region in the semiconductor layer, the isolation region separating the first OD region from the second OD region; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor disposed on the first OD region, the PMOS floating gate transistor being serially connected to the PMOS select transistor, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and a floating gate extension continuously extended from the floating gate to the second OD region and being capacitively coupled to the second OD region.
The PMOS select transistor comprises a select gate, a select gate oxide layer between the select gate and the semiconductor layer, a P+ source doping region, and a P+ drain/source doping region, wherein the P+ source doping region is electrically connected to a source line.
The PMOS floating gate transistor comprises a floating gate, a floating gate oxide layer between the floating gate and the semiconductor layer, a P+ drain doping region and the P+ drain/source doping region, wherein the P+ drain/source doping region is shared by the PMOS select transistor and the PMOS floating gate transistor.
According to one embodiment, an ion well such as an N well or a P well may be disposed in the semiconductor layer. The ion well completely overlaps with the second OD region. A heavily doped region such as N+ or P+ doping region is disposed in the ion well within the second OD region. The second OD region, the heavily doped region, the floating gate oxide layer, and the floating gate extension that is capacitively coupled to the heavily doped region together constitute an erase device.
According to another embodiment, the single-poly nonvolatile memory cell further comprises a charge collecting region that is contiguous with the first OD region, wherein the charge collecting region collects redundant electrons and holes accumulated in the semiconductor layer during operation of the single-poly nonvolatile memory cell. The charge collecting region comprises a third OD region, an N+ doping region in the third OD region, abridge region connecting the N+ doping region with the semiconductor layer directly under the floating gate.
According to still another embodiment, the single-poly nonvolatile memory cell further comprises an N+ doping region that is contiguous with the P+ doping region on the same side of the select gate, thereby forming a butted contact region.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
FIG. 1 is a schematic layout diagram showing a prior art single-poly non-volatile memory cell;
FIG. 2 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to one embodiment of this invention;
FIG. 3 is a cross-sectional view of a memory cell unit taken along line I-I′ in FIG. 2;
FIG. 4 is a cross-sectional view of a memory cell unit taken along line II-II′ in FIG. 2;
FIG. 5 to FIG. 7 show variants of the single-poly nonvolatile memory of FIG. 2 according to other embodiments of the invention;
FIG. 8 illustrates an exemplary operation conditions for programming (PGM), reading (READ) or erasing (ERS) operations of the memory cell unit as set forth through FIG. 2 to FIG. 7;
FIG. 9 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to another embodiment of this invention;
FIG. 10 is a cross-sectional view of a memory cell unit taken along line in FIG. 9;
FIG. 11 is a cross-sectional view of a memory cell unit taken along line IV-IV′ in FIG. 9;
FIG. 12 shows a variant of the single-poly nonvolatile memory of FIG. 9 according to still another embodiment of the invention; and
FIG. 13 illustrates an exemplary operation conditions for programming (PGM), reading (READ) or erasing (ERS) operations of the memory cell unit as set forth in FIG. 9 and FIG. 12.
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size, for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
DETAILED DESCRIPTION
In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations or process steps are not disclosed in detail, as these should be well-known to those skilled in the art.
Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and some dimensions are exaggerated in the figures for clarity of presentation. Also, where multiple embodiments are disclosed and described as having some features in common, like or similar features will usually be described with like reference numerals for ease of illustration and description thereof.
The present invention pertains to a single-poly non-volatile memory having an erase device, which may function as a multi-time programmable memory (MTP). The single-poly non-volatile memory is fabricated on an SOI (silicon-on-insulator or semiconductor-on-insulator) substrate. The SOI substrate may comprises a silicon substrate, a buried oxide layer, and a silicon (or semiconductor) active layer on the buried oxide layer. The single-poly non-volatile memory device is fabricated in or on the silicon (or semiconductor) active layer. The SOI substrate may be any commercially available SOI products, which can be fabricated using conventional SIMOX method, but not limited thereto. The single-poly non-volatile memory device may be a fully depleted SOI device or partially depleted SOI device.
FIG. 2 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to one embodiment of this invention. FIG. 3 is a cross-sectional view taken along line I-I′ in FIG. 2. FIG. 4 is a cross-sectional view taken along line II-II′ in FIG. 2. As shown in FIG. 2, the single-poly nonvolatile memory 1 comprises a plurality of memory cells including, for example, four memory cell units C1˜C4. It is understood that the layout of the memory cells in FIG. 2 is for illustration purposes only. In FIG. 2, for example, only three oxide define (OD) regions: OD1, OD2, and OD3 are shown. According to the embodiment of the invention, the memory cells C1 and C2 are fabricated on the oxide define region OD1 and the memory cells C3 and C4 are fabricated on the oxide define region OD2.
According to the embodiment of the invention, the oxide define regions OD1, OD2, and OD3 may be strip-shaped regions extending along a reference y-axis. The oxide define regions OD1, OD2, and OD3 are isolated from one another by the shallow trench isolation (STI) region 300. Only two word lines WL1 and WL2 are shown in FIG. 2. The two word lines WL1 and WL2 intersect the oxide define regions OD1, OD2 and extend along a reference x-axis. An erase device 250 may be fabricated on the oxide define region OD3. According to the embodiment of the invention, the erase device 250 may be shared by the four memory cell units C1˜C4.
According to the embodiment of the invention, the oxide define region OD3 is interposed between the oxide define region OD1 and the oxide define region OD2. The oxide define region OD3 is spaced apart from the two word lines WL1 and WL2. The oxide define region OD3 does not overlap with the two word lines WL1 and WL2 when viewed from the above.
According to the embodiment of the invention, the memory cell unit C1 and the memory cell unit C2 share the same P+ drain/source doping region and the same bit line contact. According to the embodiment of the invention, the memory cell unit C3 and the memory cell unit C4 share the same P+ drain doping region and the same bit line contact.
As shown in FIG. 2, FIG. 3 and FIG. 4, each of the four memory cell units (taking the memory cell unit C1 as an example) comprises a PMOS select transistor 102 and a PMOS floating gate transistor 104 that is serially connected to the PMOS select transistor 102. The PMOS select transistor 102 and the PMOS floating gate transistor 104 are formed together on the oxide define region OD1 that is defined in the semiconductor layer 230 of an SOI substrate 200. The cell structure of the memory cell units C2 is mirror-symmetric to the memory cell unit C1. The cell structures of the memory cell units C3 and C4 are mirror-symmetric to the memory cell units C1 and C2, respectively.
The semiconductor layer 230 may be a single-crystalline silicon layer, but is not limited thereto. The SOI substrate 200 may further comprise a buried oxide layer 220 and a silicon substrate 210. The semiconductor layer 230 is electrically isolated from the silicon substrate 210 by the buried oxide layer 220. The STI region 300 is contiguous with the buried oxide layer 230. The silicon substrate 210 may be a P type silicon substrate, but is not limited thereto. In the semiconductor layer 230, an N well 310, which is completely overlapped with the oxide define region OD1, maybe formed by using ion implantation methods. In some embodiments, the N well 310 may be omitted so that the channel maybe formed in the intrinsic silicon.
The PMOS select transistor 102 comprises a select gate 110, a select gate oxide layer 112 between the select gate 110 and the semiconductor layer 230, a P+ source doping region 132, and a P+ drain/source doping region 134. The PMOS floating gate transistor 104 comprises a floating gate 120, a floating gate oxide layer 122 between the floating gate 120 and the semiconductor layer 230, the P+ drain/source doping region 134, and a P+ drain doping region 136. The PMOS select transistor 102 and the PMOS floating gate transistor 104 share the P+ drain/source doping region 134. For the sake of simplicity, spacers on the sidewalls of the select gate 110 and the floating gate 120 are not illustrated.
As can be seen in FIG. 2 and FIG. 4, the floating gate 120 includes an extended portion (or floating gate extension) 120 a that extends along the reference x direction to overlap with the oxide define region OD3. The extended portion 120 a may have a width that is smaller than the width of the floating gate 120. According to the embodiment of the invention, the overlapping area between the extended portion 120 a and the oxide define region OD3 is smaller than the overlapping area between the floating gate 120 and the oxide define region OD1.
In the oxide define region OD3, a heavily doped region 138 is formed. The heavily doped region 138 may be an N+ doping region or a P+ doping region. An ion well 320 such as an N well or a P well may be formed in the semiconductor layer 230 and completely overlaps with the oxide define region OD3. Alternatively, the heavily doped region 138 may be formed within the intrinsic silicon, and in such case, no ion well is formed in the oxide define region OD3. It is to be understood that the shape of the floating gate is only for illustration purposes.
According to the embodiment of the invention, the oxide define region OD3, the heavily doped region 138, the floating gate oxide layer 122, and the extended portion 120 a that is capacitively coupled to the heavily doped region 138 and the oxide define region OD3 together constitute the erase device 250.
In operation, the select gate 110 of the PMOS select transistor 102 is coupled to a select gate voltage VSG by way of a word line contact 510, the P+ source doping region 132 of the PMOS select transistor 102 is electrically coupled to a source line voltage VSL by way of a source line (SL) contact, the P+ drain/source doping region 134 and the floating gate 120 are electrically floating, and the P+ drain doping region 136 of the PMOS floating gate transistor 104 is electrically coupled to a bit line voltage VBL through a bit line (BL) contact. The heavily doped region 138 is electrically coupled to an erase line voltage VEL through an erase line (EL) contact.
Under the program mode, electrons are selectively injected into the floating gate 120 by channel hot electron (CHE) injection. Under the erase mode (sector or chip erase), electrons may be erased from the floating gate 120 by Fowler-Nordheim (FN) tunneling.
FIG. 5 to FIG. 7 show variants of the single-poly nonvolatile memory having an erase device according to other embodiments of the invention.
As shown in FIG. 5, the difference between the single-poly nonvolatile memory 2 depicted in FIG. 5 and the single-poly nonvolatile memory 1 depicted in FIG. 2 is that the single-poly nonvolatile memory 2 further comprises a charge collecting region 50 that is contiguous with the oxide define region OD1. The charge collecting region 50 is able to collect redundant electrons and holes accumulated in the semiconductor layer 230 during operation of the single-poly nonvolatile memory cell.
According to the embodiment of the invention, the charge collecting region 50 comprises an oxide define region OD4, an N+ doping region 500 in the oxide define region OD4, a bridge region 520 connecting the N+ doping region 500 with the semiconductor layer 230 directly under the floating gate 120. The N well 310 may overlap with the oxide define region OD4 and the bridge region 520. An N well (NW) contact may be provided on the N+ doping region 500 to electrically couple the charge collecting region 50 to an N well voltage VNW. In FIG. 5, the two memory cells C1 and C2 share one charge collecting region and the two memory cells C3 and C4 share one charge collecting region.
As shown in FIG. 6, the difference between the single-poly nonvolatile memory 3 depicted in FIG. 6 and the single-poly nonvolatile memory 3 depicted in FIG. 6 is that the single-poly nonvolatile memory 3 further comprises an N+ doping region 162 that is contiguous with the P+ doping region 132 on the same side of the select gate 110, thereby forming a butted contact region 60. The N+ doping region 162 and the P+ doping region 132 are both electrically coupled to the source line voltage VSL.
As shown in FIG. 7, the difference between the single-poly nonvolatile memory 4 depicted in FIG. 7 and the single-poly nonvolatile memory 1 depicted in FIG. 2 is that the single-poly nonvolatile memory 4 comprises charge collecting region 50 that is contiguous with the oxide define region OD1. The charge collecting region 50 is able to collect redundant electrons and holes accumulated in the semiconductor layer 230 during operation of the memory. The charge collecting region 50 is described in FIG. 5. The single-poly nonvolatile memory 4 also comprises an N+ doping region 162 that is contiguous with the P+ doping region 132 on the same side of the select gate 110, thereby forming a butted contact region 60. The N+ doping region 162 and the P+ doping region 132 are both electrically coupled to the source line voltage VSL.
FIG. 8 illustrates an exemplary operation conditions for programming (PGM) , reading (READ) or erasing (ERS) operations of the memory cell unit as set forth through FIG. 2 to FIG. 7. As shown in FIG. 8, during programming (PGM) operation, the source line (SL) is coupled to a voltage source VPP. For example, VPP may range between 5˜9V. The bit line (BL) is grounded (VBL=0V). The select gate (SG) 110 is provided with a voltage source between 0˜½ VPP. The erase line (EL) is provided with a voltage source between 0˜VPP. For the memory cells having the charge collecting region 50 as depicted in FIG. 5 and FIG. 7, the N+ doping region 500 is coupled to a voltage source VPP. The voltage conditions for the memory cells under program-inhibit (PGM-inhibit) operation or under program-unselect (PGM-unselect) operation are also listed in FIG. 8.
During erasing (ERS) operation, the source line (SL) is grounded (VSL=0V). The bit line (BL) is grounded (VBL=0V). The select gate (SG) 110 is grounded (VSG=0V). The erase line (EL) is provided with a voltage source VEE. For example, VEE may range between 8˜18V. For the memory cells having the charge collecting region 50 as depicted in FIG. 5 and FIG. 7, the N+ doping region 500 is grounded (VNW=0V). Alternatively, the source line (SL) may be coupled to a voltage source VBB. For example, VBB may range between −4˜−8V. The bit line (BL) is coupled to the voltage source VBB. The select gate (SG) 110 is coupled to the voltage source VBB. The erase line (EL) is provided with VEE. For example, VEE may range between 8˜18V. For the memory cells having the charge collecting region 50 as depicted in FIG. 5 and FIG. 7, the N+ doping region 500 is coupled to the voltage source VBB.
During READ operation, the source line (SL) is coupled to a voltage source VREAD For example, VREAD may range between 2˜2.8V. The bit line (BL) may be coupled to 0.4V (VBL=0.4V). The select gate (SG) 110 is grounded (VSB=0V). The erase line (EL) is grounded (VEL=0V). For the memory cells having the charge collecting region 50 as depicted in FIG. 5 and FIG. 7, the N+ doping region 500 is coupled to VREAD. The voltage conditions for the memory cells under read-unselect (READ-unselect) operation are also listed in FIG. 8.
Please refer to FIG. 9 and FIG. 11. FIG. 9 is a schematic layout diagram showing a portion of a single-poly nonvolatile memory according to another embodiment of this invention. FIG. 10 is a cross-sectional view of a memory cell unit taken along line III-III′ in FIG. 9. FIG. 11 is a cross-sectional view of a memory cell unit taken along line IV-IV′ in FIG. 9. As shown in FIG. 9, the single-poly nonvolatile memory 5 comprises a plurality of memory cells including, for example, four memory cell units C1˜C4. It is understood that the layout of the memory cells in FIG. 9 is for illustration purposes only. In FIG. 9, for example, only three oxide define regions OD1, OD2, and OD3 are shown. According to the embodiment of the invention, the memory cells C1 and C2 are fabricated on the oxide define region OD1 and the memory cells C3 and C4 are fabricated on the oxide define region OD2.
According to the embodiment of the invention, the oxide define regions OD1 and OD2 may be strip-shaped regions extending along a reference y-axis. The oxide define regions OD1, OD2, and OD3 are isolated from one another by the shallow trench isolation (STI) region 300. Only two word lines WL1 and WL2 are shown in FIG. 9. The two word lines WL1 and WL2 intersect the oxide define regions OD1, OD2 and extend along a reference x-axis. An erase device 450 may be fabricated on the oxide define region OD3. According to the embodiment of the invention, the erase device 450 maybe shared by the four memory cell units C1˜C4.
According to the embodiment of the invention, the oxide define region OD3 is interposed between the oxide define region OD1 and the oxide define region OD2. The oxide define region OD3 is spaced apart from the two word lines WL1 and WL2. The oxide define region OD3 does not overlap with the two word lines WL1 and WL2 when viewed from the above.
According to the embodiment of the invention, the memory cell unit C1 and the memory cell unit C2 share the same P+ drain/source doping region and the same bit line contact. According to the embodiment of the invention, the memory cell unit C3 and the memory cell unit C4 share the same P+ drain doping region and the same bit line contact.
As shown in FIG. 9, FIG. 10 and FIG. 11, each of the four memory cell units (taking the memory cell unit C1 as an example) comprises a PMOS select transistor 102 and a PMOS floating gate transistor 104 that is serially connected to the PMOS select transistor 102. The PMOS select transistor 102 and the PMOS floating gate transistor 104 are formed together on the oxide define region OD1 that is defined in the semiconductor layer 230 of an SOI substrate 200. The cell structure of the memory cell units C2 is mirror-symmetric to the memory cell unit C1. The cell structures of the memory cell units C3 and C4 are mirror-symmetric to the memory cell units C1 and C2, respectively.
The semiconductor layer 230 may be a single-crystalline silicon layer, but is not limited thereto. The SOI substrate 200 may further comprise a buried oxide layer 220 and a silicon substrate 210. The semiconductor layer 230 is electrically isolated from the silicon substrate 210 by the buried oxide layer 220. The STI region 300 is contiguous with the buried oxide layer 230. The silicon substrate 210 may be a P type silicon substrate, but is not limited thereto. In the semiconductor layer 230, an N well 310, which is completely overlapped with the oxide define region OD1, maybe formed by using ion implantation methods. In some embodiments, the N well 310 may be omitted so that the channel maybe formed in the intrinsic silicon.
The PMOS select transistor 102 comprises a select gate 110, a select gate oxide layer 122 between the select gate 110 and the semiconductor layer 230, a P+ source doping region 132, and a P+ drain/source doping region 134. The PMOS floating gate transistor 104 comprises a floating gate 120, a floating gate oxide layer 122 between the floating gate 120 and the semiconductor layer 230, the P+ drain/source doping region 134, and a P+ drain doping region 136. The PMOS select transistor 102 and the PMOS floating gate transistor 104 share the P+ drain/source doping region 134. For the sake of simplicity, spacers on the sidewalls of the select gate 110 and the floating gate 120 are not illustrated.
As can be seen in FIG. 9 and FIG. 11, the floating gate 120 includes an extended portion 120 b that extends along the reference x direction to overlap with the oxide define region OD3. The extended portion 120 b may have a width that is greater than the width of the floating gate 120. According to the embodiment of the invention, the overlapping area between the extended portion 120 b and the oxide define region OD3 is greater than the overlapping area between the floating gate 120 and the oxide define region OD1.
In the oxide define region OD3, a heavily doped region 138 is formed. The heavily doped region 138 may be an N+ doping region or a P+ doping region. An ion well 320 such as an N well or a P well may be formed in the oxide define region OD3. According to the embodiment, the heavily doped region 138 is an N+ doping region and the ion well 320 is an N well. According to another embodiment, the heavily doped region 138 is a P+ doping region and the ion well 320 is a P well. It is to be understood that the shape of the floating gate is only for illustration purposes.
According to the embodiment of the invention, the oxide define region OD3, the heavily doped region 138, the floating gate oxide layer 122, and the extended portion 120 b that is capacitively coupled to the heavily doped region 138 and the oxide define region OD3 together constitute the erase device 450. The oxide define region OD3 and the heavily doped region 138 may serve as a control gate.
In operation, the select gate 110 of the PMOS select transistor 102 is coupled to a select gate voltage VSG, the P+ source doping region 132 of the PMOS select transistor 102 is electrically coupled to a source line voltage VBL by way of a source line (SL) contact, the P+ drain/source doping region 134 and the floating gate 120 are electrically floating, and the P+ drain doping region 136 of the PMOS floating gate transistor 104 is electrically coupled to a bit line voltage VBL through a bit line (BL) contact. The heavily doped region 138 is electrically coupled to a control gate voltage VCG.
Under the program mode, electrons are selectively injected into the floating gate 120 by channel hot electron (CHE) injection. Under the erase mode (sector or chip erase) , electrons may be erased from the floating gate 120 by Fowler-Nordheim (FN) tunneling.
FIG. 12 shows a variant of the single-poly nonvolatile memory having an erase device according to still another embodiment of the invention.
As shown in FIG. 12, the difference between the single-poly nonvolatile memory 6 depicted in FIG. 12 and the single-poly nonvolatile memory 5 depicted in FIG. 9 is that the single-poly nonvolatile memory 6 further comprises a charge collecting region 50 that is contiguous with the oxide define region OD1. The charge collecting region 50 is able to collect redundant electrons and holes accumulated in the semiconductor layer 230 during operation of the memory.
According to the embodiment of the invention, the charge collecting region 50 comprises an oxide define region OD4, an N+ doping region 500 in the oxide define region OD4, a bridge region 520 connecting the N+ doping region 500 with the semiconductor layer 230 directly under the floating gate 120. The N well 310 may overlap with the oxide define region OD4 and the bridge region 520. An N well (NW) contact may be provided on the N+ doping region 500 to electrically couple the charge collecting region 50 to an N well voltage VNW. In FIG. 12, the two memory cells C1 and C2 share one charge collecting region and the two memory cells C3 and C4 share one charge collecting region.
FIG. 13 illustrates an exemplary operation conditions for programming (PGM), reading (READ) or erasing (ERS) operations of the memory cell unit as set forth in FIG. 9 and FIG. 12. As shown in FIG. 13, during programming (PGM) operation, the source line (SL) is coupled to a voltage source VPP. For example, VPP may range between 5˜9V. The bit line (BL) is grounded (VBL=0V). The select gate (SG) 110 is provided with a voltage source between 0˜½ VPP. The control gate (CG) is provided with a voltage source between 0˜½ VPP. For the memory cells having the charge collecting region 50 as depicted in FIG. 12, the N+ doping region 500 is coupled to a voltage source VPP. The voltage conditions for the memory cells under program-inhibit (PGM-inhibit) operation or under program-unselect (PGM-unselect) operation are also listed in FIG. 13.
During erasing (ERS) operation, the source line (SL) is coupled to voltage source VEE (VEE may range between 8˜18V). The bit line (BL) is coupled to voltage source VEE. The select gate (SG) 110 is coupled to voltage source VEE or VEE−ΔV (ΔV>Vt). The control gate (CG) is grounded (VCG=0V). For example, VEE may range between 8˜18V. For the memory cells having the charge collecting region 50 as depicted in FIG. 5 and FIG. 7, the N+ doping region 500 is grounded (VNW=0V). For the memory cells having the charge collecting region 50 as depicted in FIG. 12, the N+ doping region 500 is grounded.
During READ operation, the source line (SL) is coupled to a voltage source VREAD For example, VREAD may range between 2˜2.8V. The bit line (BL) may be coupled to 0.4V (VBL=0.4V). The select gate (SG) 110 is grounded (VSG=0V). The control gate (CG) is grounded (VCG=0V). For the memory cells having the charge collecting region 50 as depicted in FIG. 12, the N+ doping region 500 is coupled to VREAD. The voltage conditions for the memory cells under read-unselect (READ-unselect) operation are also listed in FIG. 13.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (13)

What is claimed is:
1. A single-poly nonvolatile memory cell, comprising:
a silicon-on-insulator (SOI) substrate comprising a silicon substrate, a buried oxide layer, and a semiconductor layer;
a first oxide define (OD) region and a second oxide define (OD) region on the semiconductor layer;
an isolation region in the semiconductor layer, the isolation region separating the first OD region from the second OD region;
a PMOS select transistor disposed on the first OD region;
a PMOS floating gate transistor disposed on the first OD region, the PMOS floating gate transistor being serially connected to the PMOS select transistor, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region;
a floating gate extension continuously extended from the floating gate to the second OD region and being capacitively coupled to the second OD region, wherein an overlapping area between the floating gate extension and the second OD region is smaller than an overlapping area between the floating gate and the first OD region;
a third oxide define (OD) region disposed on a side of the first OD region opposite to the second OD region;
an N well in the semiconductor layer, wherein the N well completely overlaps with the first OD region and the third OD region; and
a charge collecting region disposed in the third OD region and being contiguous with the first OD region, wherein the third OD region and the charge collecting region are situated within the N well.
2. The single-poly nonvolatile memory cell according to claim 1, wherein the PMOS select transistor comprises a select gate, a select gate oxide layer between the select gate and the semiconductor layer, a P+ source doping region, and a P+ drain/source doping region, wherein the P+ source doping region is electrically connected to a source line.
3. The single-poly nonvolatile memory cell according to claim 2, wherein the PMOS floating gate transistor comprises a floating gate, a floating gate oxide layer between the floating gate and the semiconductor layer, a P+ drain doping region and the P+ drain/source doping region, wherein the P+ drain/source doping region is shared by the PMOS select transistor and the PMOS floating gate transistor.
4. The single-poly nonvolatile memory cell according to claim 1 further comprising:
an ion well in the semiconductor layer and completely overlapping with the second OD region; and
a heavily doped region in the ion well within the second OD region.
5. The single-poly nonvolatile memory cell according to claim 4, wherein the ion well comprises N well or P well.
6. The single-poly nonvolatile memory cell according to claim 4, wherein the heavily doped region is an N+ doping region.
7. The single-poly nonvolatile memory cell according to claim 4, wherein the heavily doped region is a P+ doping region.
8. The single-poly nonvolatile memory cell according to claim 4, wherein the floating gate extension traverses the isolation region between the first OD region and the second OD region and partially overlaps with the second OD region to capacitively couple to the heavily doped region.
9. The single-poly nonvolatile memory cell according to claim 4, wherein the second OD region, the heavily doped region, the floating gate oxide layer, and the floating gate extension that is capacitively coupled to the heavily doped region together constitute an erase device.
10. The single-poly nonvolatile memory cell according to claim 4, wherein in operation, the select gate is coupled to a select gate voltage VSG, the P+ source doping region of the PMOS select transistor is electrically coupled to a source line voltage VSL, the P+ drain/source doping region and the floating gate are electrically floating, the P+ drain doping region of the PMOS floating gate transistor is electrically coupled to a bit line voltage VBL, and the heavily doped region is electrically coupled to an erase line voltage VEL.
11. The single-poly nonvolatile memory cell according to claim 1, wherein the charge collecting region comprises an N+ doping region in the third OD region, a bridge region connecting the N+ doping region with the semiconductor layer directly under the floating gate.
12. The single-poly nonvolatile memory cell according to claim 11, wherein the N well overlaps with the third OD region and the bridge region.
13. The single-poly nonvolatile memory cell according to claim 1 further comprising:
an N+ doping region that is contiguous with the P+ doping region on the same side of the select gate, thereby forming a butted contact region.
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