TWI587455B - 非揮發性記憶體結構 - Google Patents
非揮發性記憶體結構 Download PDFInfo
- Publication number
- TWI587455B TWI587455B TW105133388A TW105133388A TWI587455B TW I587455 B TWI587455 B TW I587455B TW 105133388 A TW105133388 A TW 105133388A TW 105133388 A TW105133388 A TW 105133388A TW I587455 B TWI587455 B TW I587455B
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- Taiwan
- Prior art keywords
- floating gate
- volatile memory
- region
- memory structure
- extension
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- 238000007667 floating Methods 0.000 claims description 99
- 239000002184 metal Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 239000002784 hot electron Substances 0.000 claims description 2
- 230000005641 tunneling Effects 0.000 claims description 2
- 230000014759 maintenance of location Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G11C16/00—Erasable programmable read-only memories
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
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- G11C16/20—Initialising; Data preset; Chip identification
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- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G11C8/00—Arrangements for selecting an address in a digital store
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Geometry (AREA)
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Description
本發明是有關於一種非揮發性記憶體,且特別是有關於一種每位元採用兩個電荷儲存區(2-cells-per-bit)的非揮發性記憶體結構。
非揮發性記憶體因為即使在沒有供應電源的情況下,仍可以保留資料,故而廣泛用於各種電子裝置。依據寫入次數的限制,非揮發性記憶體分為可多次程式化(multi-time programmable,MTP)和單次程式化(one-time programmable,OTP)。MTP是可多次讀取和可多次寫入的。一般而言,MTP具有用於寫入和讀取資料的單一電荷儲存區域(即:1記憶胞/位元)。
然而,隨著記憶體結構的發展,位於MTP的電荷儲存區域底下的閘極氧化層會變得太薄,且因此在閘極氧化層出現缺陷時,資料保存能力(data retention capability)可能會惡化。因此,業界需要能改善非揮發性記憶體的資料保存特性的方案。
基於上述,本發明提供一種具有良好資料保存能力的非揮發性記憶體結構,其具有兩個用於寫入和讀取資料的電荷儲存區域(即:2記憶胞/位元)。
根據本發明的一實施例,一種非揮發性記憶體結構包括基板、第一PMOS電晶體、第一浮置閘電晶體、第二PMOS電晶體、第二浮置閘電晶體、源極線、位元線、字元線以及抹除線。所述基板包括第一主動區、第二主動區以及n型抹除區。所述第一PMOS電晶體和所述第一浮置閘電晶體分別位於所述第一主動區上,其中所述第一PMOS電晶體包括第一選擇閘極,所述第一浮置閘電晶體包括位於所述第一選擇閘極和所述n型抹除區之間的第一浮置閘極,以及所述第一浮置閘極包括在所述n型抹除區的第一部份上延伸的延伸部。第二PMOS電晶體以及第二浮置閘電晶體分別位於所述第二主動區上,其中所述第二PMOS電晶體包括第二選擇閘極,所述第二浮置閘電晶體包括位於所述第二選擇閘極和所述n型抹除區之間的第二浮置閘極,且所述第二浮置閘極包括在所述n型抹除區的第二部份上延伸的延伸部。源極線連接所述第一和所述第二PMOS電晶體的源極。位元線連接所述第一和所述第二浮置閘電晶體的汲極。字元線連接所述第一和所述第二選擇閘極。抹除線連接所述n型抹除區。
根據本發明的另一實施例,一種陣列包括數個上述的非揮發性記憶體結構,其中兩個所述非揮發性記憶體結構共用一個所述n型抹除區。
在配合所附圖式對以下較佳實施例進行詳細說明後,將使本領域技術人員能清楚無疑慮地了解本發明的上述和其他特徵。
以下將詳細地闡述本發明的較佳實施例,其實例在附圖中示出。盡可能地,在圖式中使用相同的元件符號,且指代相同或相似的元件。
圖1A是根據本發明的第一實施例的一種非揮發性記憶體結構的佈局的示意性平面圖。圖1B是沿圖1A的線段B-B'的剖面示意圖。圖1C是沿圖1A的線段C-C'的一個實例之剖面示意圖。圖1D是沿圖1A的線段C-C'的另一個實例之剖面示意圖。
請參看圖1A至圖1D。本發明的第一實施例提供一種非揮發性記憶體結構10,其包括基板100(具有第一主動區102、第二主動區104和n型抹除區106)、第一PMOS電晶體108、第一浮置閘電晶體110、第二PMOS電晶體112、第二浮置閘電晶體114、源極線SL、位元線BL、字元線WL以及抹除線EL。基板100例如是p型基板。n型抹除區106與所述第一主動區102和所述第二主動區104隔離,其中所述n型抹除區106可為如圖1C所示的位於隔離結構118底下的由p型井116所環繞的n
+區。此外,p型井116可如圖1D所示進一步設置於n型抹除區106底下。
在圖1A中,所述第一PMOS電晶體108以及所述第一浮置閘電晶體110分別設置於所述第一主動區102上,其中所述第一PMOS電晶體108包括第一選擇閘極(SG1)108a,且所述第一浮置閘電晶體110包括位於所述第一選擇閘極108a和所述n型抹除區106之間的第一浮置閘極(FG1)110a。所述第一浮置閘極110a還可包括在所述n型抹除區106的第一部分106a上延伸的延伸部110b,且所述延伸部110b具有平行於所述第一主動區102的延伸方向的延伸方向。所述第一浮置閘極110a的延伸部110b例如和所述第一主動區102的一部分重疊。所述第二PMOS電晶體112以及所述第二浮置閘電晶體114分別設置於所述第二主動區104上,其中所述第二PMOS電晶體112包括第二選擇閘極(SG2)112a,且所述第二浮置閘電晶體114包括位於所述第二選擇閘極112a和所述n型抹除區106之間的第二浮置閘極(FG2)114a。所述第二浮置閘極114a還可包括在所述n型抹除區106的第二部分106b上延伸的延伸部114b,且所述延伸部114b具有平行於所述第二主動區104的延伸方向的延伸方向。所述第二浮置閘極114a的延伸部114b例如和所述第二主動區104的一部分重疊。所述源極線SL通過接觸窗111連接所述第一PMOS電晶體108和所述第二PMOS電晶體112的源極。所述位元線BL通過接觸窗111連接所述第一浮置閘電晶體110和所述第二浮置閘電晶體114的汲極。所述字元線WL連接所述第一選擇閘極108a和所述第二選擇閘極112a。所述抹除線EL通過接觸窗111連接所述n型抹除區106。由於所述非揮發性記憶體結構10為每位元採用兩個電荷儲存區(2-cells-per-bit)的結構,可明顯地降低所述記憶體陣列的位元故障率(bit failure rate)。
在本發明的一個實施例中,所述第一浮置閘極110a和所述第二浮置閘極114a例如是經由福勒-諾德漢(Fowler-Nordheim,FN)穿隧來抹除,且例如是經由通道熱電子(channel hot electron,CHE)程式化來進行程式化。此外,位於所述位元線底下的所述第一主動區102和第二主動區104可如圖1A所示彼此接觸;然而,本發明並不限於此。
請再次參看圖1C或圖1D。N型井120位於靠近所述p型井116的基板100中,且所述延伸部110b設置於所述n型抹除區106的第一部份106a上。在本發明的一個實施例中,自行對準金屬矽化物阻擋(salicide blocking,SAB)層122可形成於第一浮置閘極110a和所述延伸部110b上,用於改善資料保存能力。同理,SAB層122亦可形成於第二浮置閘極114a及其延伸部114b上。因此,自行對準金屬矽化物(self-aligned silicide)層可形成於圖1A中的非揮發性記憶體結構10的區域124內。
請再次參看圖1B。自行對準金屬矽化物層126形成於圖1B中的區域124中。由於記憶胞的尺寸因為SAB層122的關係可能會被放大,所以優選是將SAB層122形成於一部分的字元線WL上。然而,本發明並不限於此。如果沒有自行對準金屬矽化物層的話,可以符合更小的設計法則。
圖1E是圖1A中的第一浮置閘極的放大圖。
在圖1E中,位於所述第一浮置閘極110a和所述第一主動區102之間的重疊區域設為A1,位於所述第一浮置閘極110a的延伸部110b和所述n型抹除區106之間的重疊區域設為A2,且有鑑於抹除效率,A1對A1和A2的總和的比值(即:A1/(A1+A2))例如大於75%。舉例來說,若A1/(A1+A2)為90%且A2/(A1+A2)為10%,當施加10V的電壓於n型抹除區106、施加0V的電壓於N型井(如圖1C的120)時,自n型抹除區106至浮置閘極110a的電壓差為10V - (0V×90%+10V×10%) = 9V。因此,在抹除操作期間,這樣高的電壓差可改善抹除效率。
同理,位於所述第二浮置閘極114a和所述第二主動區104之間的重疊區域如設為A3,位於所述第二浮置閘極114a的延伸部114b和所述n型抹除區106之間的重疊區域設為A4,且A3對A3和A4的總和的比值較佳也是大於75%。
圖2說明如圖1A中所述的非揮發性記憶體結構的等效電路。所述源極線SL明顯連接於兩個PMOS電晶體的源極,所述位元線BL明顯連接於兩個浮置閘電晶體的汲極,字元線WL則連接兩個選擇閘極(SG1和SG2),且所述抹除線EL連接至所述n型抹除區(即:n型電容)。
圖3和圖4是根據本發明的第一實施例的非揮發性記憶體結構的其他佈局的平面示意圖,且為了清楚起見,部分必要構件並未繪示。
請參看圖3。所述第一浮置閘極110a的延伸部300和所述第二浮置閘極114a的延伸部302各自獨立地跨越所述n型抹除區106,以提升製程的穩定度。
請參看圖4。位於所述字元線WL底下的第一主動區102和第二主動區104彼此接觸,進而可擴大選擇閘極的寬度。
圖5是如圖1A中所述的非揮發性記憶體結構的陣列的佈局的平面示意圖。
請參看圖5,其具有六個圖1A的非揮發性記憶體結構,但不限於此。在本發明的一個實施例中,n型抹除區106為非揮發性記憶體結構的共通線(common line),且一個字元線WL可被用於三個非揮發性記憶體結構中。此外,SAB層122形成於浮置閘極110a、浮置閘極114a、延伸部110b、延伸部114b以及半個字元線WL上。因此,自行對準金屬矽化物層不會形成於WL的靠近浮置閘極110a和浮置閘極114a的部分上。然而,本發明並不限於此。也可省略自行對準金屬矽化物層。
由於圖1A的非揮發性記憶體結構可被排列於NOR型陣列中,所選擇的記憶體結構的操作條件可如下表1所列。
表1
<TABLE border="1" borderColor="#000000" width="_0002"><TBODY><tr><td> </td><td> BL </td><td> SL </td><td> NW (N型井) </td><td> WL </td><td> EL </td><td> PW (p型井) </td></tr><tr><td> 程式化 </td><td> 0V </td><td> VPP </td><td> VPP/2 </td><td> VPP/2 </td><td> 0V </td></tr><tr><td> 抹除 </td><td> 0V </td><td> 0V </td><td> 0V </td><td> VEE </td><td> 0V </td></tr><tr><td> 讀取 </td><td> 接近接地 </td><td> Vread </td><td> 0V </td><td> 0V-Vread </td><td> 0V </td></tr></TBODY></TABLE>
在表1中,所施加的電壓可因應不同的製程技術而變更。舉例來說,在0.13μm的製程技術中,VPP約為6.5V、Vread約為2V、VEE約為11V,且視情況在讀取操作中執行預充電,故施加於BL上的電壓(例如0.4V)接近接地電壓(GND)。此外,在讀取操作中施加於EL的電壓可介於0V和Vread之間,以獲得較佳的Ion/Ioff範圍。
圖6A是根據本發明的第二實施例的一種非揮發性記憶體結構的佈局的平面示意圖,且為清楚起見,部分必要構件未繪示。
請參看圖6A。所述第一浮置閘極110a的延伸部600和所述第二浮置閘極114a的延伸部602不與第一主動區102和第二主動區104重疊。在第二實施例中,延伸部600和延伸部602設置於所述第一主動區102和所述第二主動區104之外。
圖6B和圖6C是根據本發明的第二實施例的非揮發性記憶體結構的的其他佈局的平面示意圖,且為清楚起見,部分必要構件並未示出。
請參看圖6B和圖6C。所述第一浮置閘極110a的延伸部600可包括一個額外部分,所述額外部分例如是藉由手控OPC(manual OPC)設在n型抹除區106的第一部分106a上的槌狀部分604或耳狀部分606。所述第二浮置閘極114a的延伸部602可包括額外部分,所述額外部分例如是藉由手動OPC在n型抹除區106的第二部分106b上的槌狀部分604或耳狀部分606。藉由手控OPC,可有助於穩定地形成延伸部600和602,並因此提升抹除穩定度。
圖7A和圖7B是根據本發明的第三實施例的兩種非揮發性記憶體結構的佈局的平面示意圖,且為清楚起見並未繪出部分必要構件。
請參看圖7A。非揮發性記憶體結構70a除了主動區的位置以外與第二實施例類似。在第三實施例中,第一主動區700和第二主動區702彼此間隔開。優選地,通過接觸窗111設置金屬線704來連接第一主動區700和第二主動區702。
請參看圖7B。非揮發性記憶體結構70b與圖7A中的非揮發性記憶體結構70a的差別在於第一浮置閘極110a的延伸部600和第二浮置閘極114a的延伸部602設置於第一主動區700和第二主動區702之間。因此,可消除鄰近記憶胞之間的多晶矽耦合問題(poly coupling issue)。
圖8是根據本發明的第四實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖,且為清楚起見並未繪示部分必要構件。
請參看圖8。本發明的第四實施例提供一種非揮發性記憶體結構80,其包括基板800(具有第一主動區802、第二主動區804和兩個分離的n型抹除區806a、806b)、第一PMOS電晶體808、第一浮置閘電晶體810、第二PMOS電晶體812、第二浮置閘電晶體814、金屬線816以及字元線WL。雖然沒有畫出源極線SL、抹除線EL和位元線BL,但是本實施例仍需符合圖2中的等效電路。舉例來說,位元線BL可為M2(即,在佈局中的第二層金屬層),且抹除線EL可為M3(即,在佈局中的第三層金屬層)。
在第四實施例中,金屬線816連接第一主動區802和第二主動區804。所述第一浮置閘極810a的延伸部810b在分離的n型抹除區806a上延伸,且第二浮置閘極814a的延伸部814b在分離的n型抹除區806b上延伸。延伸部810b具有垂直於第一主動區802的延伸方向的延伸方向。延伸部814b具有垂直於第二主動區804的延伸方向的延伸方向。
圖9是根據本發明的第五實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖,且為清楚起見並未繪示部分必要構件。
請參看圖9。本發明的第五實施例提供一種非揮發性記憶體結構90,其包括基板900(具有第一主動區902、第二主動區904和n型抹除區906)、第一PMOS電晶體908、第一浮置閘電晶體910、第二PMOS電晶體912、第二浮置閘電晶體914、金屬線916以及字元線WL。雖然沒有畫出源極線SL、抹除線EL和位元線BL,但是本實施例仍需依照圖2中的等效電路被建構。
在第五實施例中,金屬線916連接第一主動區902和第二主動區904。所述第一浮置閘極910a的延伸部910b和所述第二浮置閘極914a的延伸部914b兩者在n型抹除區906上延伸。延伸部910b具有垂直於第一主動區902的延伸方向的延伸方向。延伸部914b具有垂直於第二主動區904的延伸方向的延伸方向。已知,若一個記憶胞故障,則其他靠近故障記憶胞的記憶胞也容易故障。因此,因為第一PMOS電晶體908遠離第二PMOS電晶體912,所以可進一步減少記憶體陣列的位元故障率。在圖9的陣列中,兩個非揮發性記憶體結構90明顯是共用一個n型抹除區906。
綜上所述,上述實施例的非揮發性記憶體結構其特徵在於降低讀取故障率和提升資料保存能力。
雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。
10、70a、70b、80、90‧‧‧非揮發性記憶體結構
100、800、900‧‧‧基板
102、700、802、902‧‧‧第一主動區
104、702、804、904‧‧‧第二主動區
106、806a、806b、906‧‧‧n型抹除區
106a‧‧‧第一部分
106b‧‧‧第二部分
108、808、908‧‧‧第一PMOS電晶體
108a、112a、SG1、SG2‧‧‧選擇閘極
110、810、910‧‧‧第一浮置閘電晶體
110a、114a、810a、814a、910a、914a、FG1、FG2‧‧‧浮置閘極
110b、114b、300、302、600、602、810b、814b、910b、914b‧‧‧延伸部
111‧‧‧接觸窗
112、812、912‧‧‧第二PMOS電晶體
114、814、914‧‧‧第二浮置閘電晶體
116‧‧‧p型井
118‧‧‧隔離結構
120‧‧‧N型井
122‧‧‧自行對準金屬矽化物阻擋層
124‧‧‧區域
126‧‧‧自行對準金屬矽化物層
604‧‧‧槌狀部分
606‧‧‧耳狀部分
704、816、916‧‧‧金屬線
A1、A2、A3、A4‧‧‧重疊區域
B-B'、C-C'‧‧‧線段
BL‧‧‧位元線
EL‧‧‧抹除線
SL‧‧‧源極線
WL‧‧‧字元線
隨附圖式用以進一步理解本發明,且併入及構成本說明書的一部分。隨附圖式說明本發明的實施例,且與以下說明一起用於解釋本發明的原理。 圖1A是根據本發明的第一實施例的一種非揮發性記憶體結構的佈局的平面示意圖。 圖1B是沿圖1A的線段B-B'的剖面示意圖。 圖1C是沿圖1A的線段C-C'的一個實例之剖面示意圖。 圖1D是沿圖1A的線段C-C'的另一個實例之剖面示意圖。 圖1E是圖1A中的第一浮置閘極的放大圖。 圖2是說明如圖1A中所述的非揮發性記憶體結構的等效電路圖。 圖3和圖4是根據本發明的第一實施例的非揮發性記憶體結構的其他佈局的平面示意圖。 圖5是如圖1A中所述的非揮發性記憶體結構的陣列的佈局的平面示意圖。 圖6A是根據本發明的第二實施例的一種非揮發性記憶體結構的佈局的平面示意圖。 圖6B和圖6C是根據本發明的第二實施例的非揮發性記憶體結構的其他佈局的平面示意圖。 圖7A和圖7B是根據本發明的第三實施例的兩種非揮發性記憶體結構的佈局的平面示意圖。 圖8是根據本發明的第四實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖。 圖9是根據本發明的第五實施例的一種非揮發性記憶體結構的陣列的佈局的平面示意圖。
10‧‧‧非揮發性記憶體結構
102‧‧‧第一主動區
104‧‧‧第二主動區
106‧‧‧n型抹除區
106a‧‧‧第一部分
106b‧‧‧第二部分
108‧‧‧第一PMOS電晶體
108a‧‧‧第一選擇閘極
110‧‧‧第一浮置閘電晶體
110a、114a‧‧‧浮置閘極
110b、114b‧‧‧延伸部
111‧‧‧接觸窗
112‧‧‧第二PMOS電晶體
112a‧‧‧第二選擇閘極
114‧‧‧第二浮置閘電晶體
124‧‧‧區域
B-B'、C-C'‧‧‧線段
BL‧‧‧位元線
EL‧‧‧抹除線
SL‧‧‧源極線
WL‧‧‧字元線
Claims (24)
- 一種非揮發性記憶體結構,包括: 一基板,包括一第一主動區、一第二主動區以及一n型抹除區,其中所述n型抹除區與所述第一主動區和所述第二主動區隔離; 一第一PMOS電晶體和一第一浮置閘電晶體,分別位於所述第一主動區上,其中所述第一PMOS電晶體包括一第一選擇閘極,所述第一浮置閘電晶體包括位於所述第一選擇閘極和所述n型抹除區之間的一第一浮置閘極,且所述第一浮置閘極包括在所述n型抹除區的一第一部份上延伸的一延伸部; 一第二PMOS電晶體和一第二浮置閘電晶體,分別位於所述第二主動區上,其中所述第二PMOS電晶體包括一第二選擇閘極,所述第二浮置閘電晶體包括位於所述第二選擇閘極和所述n型抹除區之間的一第二浮置閘極,且所述第二浮置閘極包括在所述n型抹除區的一第二部份上延伸的一延伸部; 一源極線,連接所述第一PMOS電晶體和所述第二PMOS電晶體的多數個源極; 一位元線,連接所述第一浮置閘電晶體和所述第二浮置閘電晶體的多數個汲極; 一字元線,連接所述第一選擇閘極和所述第二選擇閘極;以及 一抹除線,連接所述n型抹除區。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極和所述第二浮置閘極經由福勒-諾德漢(FN)穿隧來抹除。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極和所述第二浮置閘極經由通道熱電子(CHE) 程式化來進行程式化。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,更包括環繞所述n型抹除區的一p型井。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,更包括位於所述n型抹除區底下且環繞所述n型抹除區的一p型井。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,更包括一自行對準金屬矽化物阻擋(SAB)層,位於所述第一浮置閘極和所述第二浮置閘極上。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中位於所述第一浮置閘極和所述第一主動區之間的一重疊區域為A1,位於所述第一浮置閘極和所述n型抹除區之間的一重疊區域為A2,且A1對A1和A2的總和的比值大於75%。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中位於所述第二浮置閘極和所述第二主動區之間的一重疊區域為A3,位於所述第二浮置閘極和所述n型抹除區之間的一重疊區域為A4,且A3對A3和A4的總和的比值大於75%。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,更包括一額外部分,位於所述n型抹除區的所述第一部份上的所述第一浮置閘極的所述延伸部中。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,更包括一額外部分,位於所述n型抹除區的所述第二部份上的所述第二浮置閘極的所述延伸部中。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極的所述延伸部和所述第二浮置閘極的所述延伸部各自獨立地跨越所述n型抹除區。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中位於所述字元線底下的所述第一主動區和所述第二主動區彼此接觸。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中位於所述位元線底下的所述第一主動區和所述第二主動區彼此接觸。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一主動區和所述第二主動區彼此間隔開。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極的所述延伸部與所述第一主動區的一部分重疊。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第二浮置閘極的所述延伸部與所述第二主動區的一部分重疊。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極的所述延伸部和所述第二浮置閘極的所述延伸部設置於所述第一主動區和所述第二主動區之間。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極的所述延伸部和所述第二浮置閘極的所述延伸部設置於所述第一主動區和所述第二主動區之外。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述n型抹除區包括分離的兩個區,所述第一浮置閘極的所述延伸部在所述兩個區的其中之一上延伸,以及所述第二浮置閘極的所述延伸部在所述兩個區的其中另一上延伸。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極的所述延伸部具有平行於所述第一主動區的延伸方向的延伸方向。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第一浮置閘極的所述延伸部具有垂直於所述第一主動區的延伸方向的延伸方向。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第二浮置閘極的所述延伸部具有平行於所述第二主動區的延伸方向的延伸方向。
- 如申請專利範圍第1項所述的非揮發性記憶體結構,其中所述第二浮置閘極的所述延伸部具有垂直於所述第二主動區的延伸方向的延伸方向。
- 一種陣列,包括多數個如申請專利範圍第1項所述的非揮發性記憶體結構,其中兩個所述非揮發性記憶體結構共用一個所述n型抹除區。
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