TWI613654B - 記憶體單元及記憶體陣列 - Google Patents
記憶體單元及記憶體陣列 Download PDFInfo
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- TWI613654B TWI613654B TW106113346A TW106113346A TWI613654B TW I613654 B TWI613654 B TW I613654B TW 106113346 A TW106113346 A TW 106113346A TW 106113346 A TW106113346 A TW 106113346A TW I613654 B TWI613654 B TW I613654B
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- voltage
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- 230000015654 memory Effects 0.000 title claims abstract description 258
- 238000009792 diffusion process Methods 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 claims 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 24
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G11C16/00—Erasable programmable read-only memories
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- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
記憶體單元包含讀取選擇電晶體、第一浮接閘極電晶體、寫入選擇電晶體、第二浮接閘極電晶體及共同浮接閘極。共同浮接閘極耦接於第一浮接閘極電晶體及第二浮接閘極電晶體。記憶體單元利用第二浮接閘極電晶體上方的共同浮接閘極進行寫入及清除操作,並透過第一浮接閘極及讀取選擇電晶體進行讀取操作。
Description
本發明是有關於一種記憶體單元,特別是一種能夠承受高壓操作的多次寫入記憶體單元。
非揮發性記憶體(Non-volatile memory,NVM)是一種能夠在記憶體區塊無電源供應時,仍能保存儲存訊息的記憶體。
由於非揮發性記憶體能夠應用在各種領域中,因此將非揮發性記憶體嵌入於與主電路相同晶片的需求也成為趨勢,特別是在對於晶片空間要求嚴格的個人電子裝置應用中尤為普遍。
根據寫入次數限制的不同,非揮發性記憶體可分為多次寫入(multi-time programmable,MTP)記憶體和單次寫入(one-time programmable,OTP)記憶體。先前技術中的多次寫入非揮發性記憶體可包含用來儲存資料的浮接閘極電晶體,以及一或兩個用來致能浮接閘極電晶體以進行對應操作的選擇電晶體。浮接閘極電晶體係由兩個不同的耦合元件所控制,一個用來控制寫入操作,另一個則用來控制清除操作。
由於在寫入操作和清除操作期間,電子會被注入浮接閘極或是自浮接閘極退出(eject),因此隨著寫入次數增加,浮接閘極也會隨著受損。浮接閘極的缺陷將使得記憶體單元退化,導致記憶體單元所產生的讀取電流難以辨識。
本發明之一實施例提供一種記憶體單元,記憶體單元包含讀取選擇電晶體、第一浮接閘極電晶體、寫入選擇電晶體、第二浮接閘極電晶體及共同浮接閘極。
讀取選擇電晶體具有第一端、第二端、控制端及基極端。讀取選擇電晶體的第一端耦接於位元線,讀取選擇電晶體的控制端耦接於字元線,而讀取選擇電晶體的基極端耦接於源極線。
第一浮接閘極電晶體具有第一端、第二端、控制端及基極端。第一浮接閘極電晶體的第一端耦接於讀取選擇電晶體之第二端,第一浮接閘極電晶體的第二端耦接於源極線,而第一浮接閘極電晶體的基極端耦接於源極線。
寫入選擇電晶體具有第一端、第二端、控制端及基極端,寫入選擇電晶體的第一端耦接於清除控制線,寫入選擇電晶體的控制端耦接於操作控制線,而寫入選擇電晶體的基極端耦接於清除控制線。
第二浮接閘極電晶體具有第一端、第二端、控制端及基極端,第二浮接閘極電晶體的第一端耦接於寫入選擇電晶體之第二端,而第二浮接閘極電晶體的基極端耦接於清除控制線。
共同浮接閘極耦接於第一浮接閘極電晶體及第二浮接閘極電晶體。
本發明之另一實施例提供一種記憶體陣列,記憶體陣列包含複數條位元線、複數條字元線、複數條操作控制線、複數條清除控制線、複數條源極線及複數列記憶體單元。每一記憶體單元包含讀取選擇電晶體、第一浮接閘極電晶體、寫入選擇電晶體、第二浮接閘極電晶體及共同浮接閘極。
讀取選擇電晶體具有第一端、第二端、控制端及基極端,讀取選擇電晶體的第一端耦接於對應之位元線,讀取選擇電晶體的控制端耦接於對應之字元線,而讀取選擇電晶體之基極端耦接於對應之源極線。第一浮接閘極電晶體具有第一端、第二端及基極端,第一浮接閘極電晶體的第一端耦接於讀取選擇電晶體之第二端,第一浮接閘極電晶體的第二端耦接於源極線,而第一浮接閘極電晶體的基極端耦接於對應之源極線。寫入選擇電晶體具有第一端、第二端、控制端及基極端,寫入選擇電晶體的第一端耦接於對應之清除控制線,寫入選擇電晶體的控制端耦接於對應之操作控制線,而寫入選擇電晶體的基極端耦接於對應之清除控制線。第二浮接閘極電晶體具有第一端、第二端及基極端,第二浮接閘極電晶體的第一端耦接於寫入選擇電晶體之第二端,而第二浮接閘極電晶體的基極端耦接於清除控制線。共同浮接閘極耦接於第一浮接閘極電晶體及第二浮接閘極電晶體。
位於相同一列之複數個記憶體單元是耦接於相同的字元線,相同的源極線,及相同的清除控制線,而位於相同一行之複數個記憶體單元是耦接於相同的位元線及相同的操作控制線。
第1圖為本發明一實施例之記憶體單元100的示意圖。記憶體單元100包含讀取選擇電晶體110、第一浮接閘極電晶體120、寫入選擇電晶體130、第二浮接閘極電晶體140及共同浮接閘極FG。
讀取選擇電晶體110具有第一端、第二端、控制端及基極端。讀取選擇電晶體110的第一端耦接於位元線BL,讀取選擇電晶體110的控制端耦接於字元線WL,而讀取選擇電晶體110的基極端耦接於源極線SL。
第一浮接閘極電晶體120具有第一端、第二端、控制端及基極端。第一浮接閘極電晶體120的第一端耦接於讀取選擇電晶體110的第二端,第一浮接閘極電晶體120的第二端耦接於源極線SL,第一浮接閘極電晶體120的基極端耦接於源極線SL。
寫入選擇電晶體130具有第一端、第二端、控制端及基極端。寫入選擇電晶體130的第一端耦接於清除控制線EL,寫入選擇電晶體130的控制端耦接於操作控制線OL,而寫入選擇電晶體130的基極端耦接於清除控制線EL。
第二浮接閘極電晶體140具有第一端、第二端、控制端及基極端。第二浮接閘極電晶體140的第一端耦接於寫入選擇電晶體的第二端,第二浮接閘極電晶體140的第二端為浮接狀態,而第二浮接閘極電晶體140的基極端耦接於清除控制線EL。此外,共同浮接閘極FG耦接至第一浮接閘極電晶體120及第二浮接閘極電晶體140。
第2圖為記憶體單元100的布局圖,而第3圖為寫入選擇電晶體130及第二浮接閘極電晶體140的結構圖。
在第2及3圖中,讀取選擇電晶體110、第一浮接閘極電晶體120、寫入選擇電晶體130及第二浮接閘極電晶體140可由P型金氧半電晶體(P-type metal-oxide-semiconductor,PMOS)實作。此外,讀取選擇電晶體110及第一浮接閘極電晶體120可形成於第一N型井NW1中的氧化擴散區OD1中,而寫入選擇電晶體130及第二浮接閘極電晶體140可形成於第二N型井NW2的氧化擴散區OD2。在本實施例中,讀取選擇電晶體110及第一浮接閘極電晶體120的第一端和第二端可皆為第一N型井NW1之氧化擴散區OD1中的P型參雜區P+,而讀取選擇電晶體110及第一浮接閘極電晶體120的基極端可為其他未受參雜部分的氧化擴散區OD1。在部分實施例中,氧化擴散區OD1的範圍可如第3圖所示,由淺溝槽絕緣層STI來界定。
相似地,寫入選擇電晶體130及第二浮接閘極電晶體140的第一端和第二端可皆為第二N型井NW2之氧化擴散區OD2中的P型參雜區P+,而寫入選擇電晶體130及第二浮接閘極電晶體140的基極端可為其他未受P型參雜部分的氧化擴散區OD2。第一N型井NW1和第二N型井NW2之間可利用P型基底P-sub上的P型井PW相隔離。
在第3圖中,寫入選擇電晶體130的基極端可經由接觸窗132耦接至清除控制線EL,且接觸窗132可形成於氧化擴散區OD2中的N型參雜區N+上方。在第2及3圖中,N型參雜區N+可設置在鄰近於寫入選擇電晶體130的位置。然而在其他實施例中,N型參雜區N+也可設置在N型井NW2之氧化擴散區OD2的其他位置。由於第二浮接閘極電晶體140及寫入選擇電晶體130是設置於相同的N型井NW2中,因此第二浮接閘極電晶體140基極端也會耦接至清除控制線EL。
相似地,讀取選擇電晶體110及第一浮接閘極電晶體120可與第3圖所示的寫入選擇電晶體130及第二浮接閘極電晶體140具有相似的結構。由於第一浮接閘極電晶體120及讀取選擇電晶體110皆設置於相同之N型井NW1的氧化擴散區OD1中,因此讀取選擇電晶體110及第一浮接閘極電晶體120的基極端可皆經由N型井NW1之氧化擴散區OD1中的N型參雜區N+上的接觸窗耦接至源極線SL。
共同浮接閘極FG可為設置於第一浮接閘極電晶體120及第二浮接閘極電晶體140上方的多晶矽層。因此,共同浮接閘極FG的電壓能夠由第一浮接閘極電晶體120之基極端的電壓以及第二浮接閘極電晶體140之基極端的電壓來控制。
此外,如第2圖所示,氧化擴散區OD1與共同浮接閘極FG重疊的區域可定義為重疊區域A1,而氧化擴散區OD2與共同浮接閘極FG重疊的區域可定義為重疊區域A2。在本實施例中,重疊區域A1的面積會大於重疊區域A2的面積。因此,共同浮接閘極FG的電壓會由第一浮接閘極電晶體120的基極端的電壓所主導。在部分實施例中,為確保第一浮接閘極電晶體120的主導地位,重疊區域A1的面積可為重疊區域A2的面積的9倍。
第4圖為本發明一實施例之記憶體單元100之寫入操作期間,記憶體單元100之訊號線所接收的電壓示意圖。
在第4圖中,在記憶體單元100之寫入操作期間,源極線SL、位元線BL及字元線WL可皆處於第一電壓V1。此外,操作控制線OL可處於第二電壓V2,而清除控制線EL可處於第三電壓V3。第三電壓V3大於第二電壓V2,且第二電壓V2大於第一電壓V1。在部分實施例中,第一電壓V1可為系統地電壓,第二電壓V2可例如為10V,而第三電壓V3可例如為18V。
在記憶體單元100之寫入操作期間,共同浮接閘極FG可經由第一浮接閘極電晶體120耦合至第一電壓V1。在此情況下,由於第二浮接閘極電晶體140的基極端是處於第三電壓V3,因此施加在第二浮接閘極電晶體140上的巨大電壓差將引致電子退出。因此原先儲存在共同浮接閘極FG中的電子會退出至第二浮接閘極電晶體140的基極端。同時,寫入選擇電晶體130會被導通以確保第二浮接閘極電晶體140不會進入空乏狀態。如此一來,第二浮接閘極電晶體140就能夠對應的被寫入。
第5圖為本發明一實施例之記憶體單元100之清除操作期間,記憶體單元100之訊號線所接收的電壓示意圖。
在記憶體單元100之清除操作期間,源極線SL和字元線WL可皆處於第三電壓V3,位元線BL可處於第二電壓V2,操作控制線OL可處於第一電壓V1或第二電壓V2,而清除控制線EL可處於第一電壓V1。
也就是說,在記憶體單元100之清除操作期間,第二浮接閘極電晶體140的基極端會處於較低的第一電壓V1,而共同浮接閘極FG會經由第一浮接閘極電晶體120耦合至較高的第三電壓V3。因此,施加於第二浮接閘極電晶體140上的巨大電壓差將引致電子穿隧,使得第二浮接閘極電晶體140之基極端中的電子會注入至共同浮接閘極FG以達成清除操作。
第6圖為本發明一實施例之記憶體單元100之讀取操作期間,記憶體單元100之訊號線所接收的電壓示意圖。
在記憶體單元100之讀取操作期間,源極線SL可處於第四電壓V4,位元線BL可處於第五電壓V5,而字元線WL、操作控制線OL、清除控制線EL可皆處於第一電壓V1。第二電壓V2大於第四電壓V4,第四電壓V4大於第五電壓V5,而第五電壓V5大於第一電壓V1。舉例來說,第一電壓V1可為系統的地電壓,第二電壓V2可為10V,第三電壓V3可為18V,第四電壓V4可為5V,而第五電壓V5可為3.8V。
也就是說,在記憶體單元100之讀取操作期間,讀取選擇電晶體110會被導通,而寫入選擇電晶體130會被截止。此外,第一浮接閘極電晶體120及第二浮接閘極電晶體140會保持在其先前的狀態。因此,讀取選擇電晶體110可根據共同浮接閘極FG的狀態產生讀取電流。舉例來說,若記憶體單元100係在寫入狀態(programmed state),則共同浮接閘極FG中的電子可能已退出。在此情況下,可能不會有讀取電流產生,或是僅產生微小的讀取電流。相對地,若記憶體單元100係在清除狀態(erased state),則將產生足以辨識的讀取電流。因此,透過判斷讀取電流的強度,就能夠辨識出儲存在記憶體單元100中的資訊。
此外,由於電子退出及電子注入都是發生在第二浮接閘極電晶體140,而讀取電流則是流經讀取選擇電晶體110及第一浮接閘極電晶體120,因此在寫入及清除過程中所造成第二浮接閘極電晶體140的缺陷將不會影響到讀取電流的產生。也就是說,由於記憶體單元100的寫入/清除路徑和讀取路徑是分別的兩條路徑,因此記憶體單元100能夠承受夠多次數的寫入及清除操作,而不會使讀取的能力退化。
雖然第1至6圖中的記憶體單元100可皆由P型電晶體實作,然而在其他實施例中,讀取選擇電晶體、第一浮接閘極電晶體、寫入選擇電晶體及第二浮接閘極電晶體也皆可由N型金氧半電晶體(N-type metal-oxide-semiconductor,NMOS)來實作。
第7圖為本發明一實施例之記憶體單元200的示意圖,而第8圖為記憶體單元200的布局圖。記憶體單元200與記憶體單元100具有相似的結構。然而記憶體單元200的讀取選擇電晶體210、第一浮接閘極電晶體220、寫入選擇電晶體230、第二浮接閘極電晶體240皆由N型電晶體來實作。如第8圖所示,讀取選擇電晶體210及第一浮接閘極電晶體220可形成於第一P型井PW1。寫入選擇電晶體230及第二浮接閘極電晶體240可形成於第二P型井PW2。
也就是說,讀取選擇電晶體210、第一浮接閘極電晶體220、寫入選擇電晶體230、第二浮接閘極電晶體240的基極端可皆形成於P型參雜的井區。在本實施例中,第一P型井PW1和第二P型井PW2可設置於深N型井DNW,因此讀取選擇電晶體210、第一浮接閘極電晶體220、寫入選擇電晶體230、第二浮接閘極電晶體240的基極端不會產生漏電流。
第9圖為本發明一實施例之記憶體陣列10的示意圖。記憶體陣列10包含N條位元線BL1至BLN,M條字元線WL1至WLM,N條操作控制線OL1至OLN,M條清除控制線EL1至ELM,M條源極線SL1至SLM,及M列記憶體單元100(1,1)至100(N,1),…,以及 100(1,M)至(N,M),其中M及N為大於1的正整數。
每一個記憶體單元100(1,1)至100(N,1),…,以及 100(1,M)至(N,M)可與第1圖之記憶體單元100具有相同的結構。此外,在第9圖中,同一列的記憶體單元可耦接至相同的字元線、相同的源極線及相同的清除控制線,而同一行的記憶體單元可耦接至相同的位元線及相同的操作控制線。
舉例來說,記憶體單元100(1,1)及100(N,1)為設置於相同一列的記憶體單元。記憶體單元100(1,1)及100(N,1)會耦接至相同的字元線WL1,相同的源極線SL1,及相同的清除控制線EL1。然而,記憶體單元100(1,1)會耦接於位元線BL1及操作控制線OL1,而記憶體單元100(N,1)會耦接於位元線BLN及操作控制線OLN。相似地,記憶體單元100(1,M)及100(N,M)為設置於相同一列的記憶體單元。記憶體單元100(1,M)及100(N,M)會耦接至相同的字元線WLM,相同的源極線SLM,及相同的清除控制線ELM。然而,記憶體單元100(1,M)會耦接於位元線BL1及操作控制線OL1,而記憶體單元100(N,M)會耦接於位元線BLN及操作控制線OLN。
此外,記憶體單元100(1,1)及100(1,M)為設置於相同一行的記憶體單元。記憶體單元100(1,1)及100(1,M)耦接於相同的位元線BL1及相同的操作控制線OL1。然而記憶體單元100(1,1)會耦接至字元線WL1、源極線SL1及清除控制線EL1,而記憶體單元100(1,M)會耦接至字元線WLM、源極線SLM及清除控制線ELM。相似地,記憶體單元100(N,1)及100(N,M)為設置於相同一行的記憶體單元。記憶體單元100(N,1)及100(N,M)耦接於相同的位元線BLN及相同的操作控制線OLN。然而記憶體單元100(N,1)會耦接至字元線WL1、源極線SL1及清除控制線EL1,而記憶體單元100(N,M)會耦接至字元線WLM、源極線SLM及清除控制線ELM。
第10圖為本發明一實施例之記憶體單元100(1,1)的寫入操作期間,記憶體陣列10之訊號線所接收到的電壓示意圖。
在第10圖中,在記憶體單元100(1,1)的寫入操作期間,源極線SL1、位元線BL1和字元線WL1可皆處於第一電壓V1。此外,操作控制線OL1可處於第二電壓V2,而清除控制線EL1可處於第三電壓V3。第三電壓V3大於第二電壓V2,而第二電壓V2大於第一電壓V1。在部分實施例中,第一電壓V1可為系統的地電壓,第二電壓V2可為10V,而第三電壓V3可為18V。
在此情況下,施加在記憶體單元100(1,1)之第二浮接閘極電晶體140上的巨大電壓差將引致電子自共同浮接閘極FG中退出至第二浮接閘極電晶體140。因此,原先儲存在記憶體單元100(1,1)之共同浮接閘極FG中的電子會退出至記憶體單元100(1,1)之第二浮接閘極電晶體140的基極端。使得記憶體單元100(1,1)的第二浮接閘極電晶體140能夠被寫入。
然而,在記憶體單元100(1,1)的寫入操作期間,記憶體陣列10中的其他記憶體單元並未被選取,因此也不應被寫入。舉例來說,記憶體單元(N,1)及記憶體單元100(1,M)即不應被寫入。
記憶體單元100(N,1)與記憶體單元100(1,1)位於相同一列。在第10圖中,在記憶體單元100(1,1)的寫入操作期間,耦接至未被選取之記憶體單元100(N,1)的位元線BLN會處於第一電壓V1,而耦接至未被選取之記憶體單元100(N,1)的操作控制線OLN則會處於第三電壓V3。
亦即,在記憶體單元100(1,1)的寫入操作期間,記憶體單元100(N,1)的寫入選擇電晶體130會被截止。因此,施加在記憶體單元100(N,1)之第二浮接閘極電晶體140上的高電壓會導致通道空乏,而不致於使電子自共同浮接閘極FG退出至第二浮接閘極電晶體140的基極端。如此一來,就能夠防止記憶體單元100(N,1)在記憶體單元100(1,1)的寫入操作期間被寫入。
記憶體單元100(1,M)與記憶體單元100(1,1)位於相同一行。由於記憶體單元100(1,M)也會耦接至操作控制線OL1,且在記憶體單元100(1,1)的寫入操作期間,操作控制線OL1是處於第二電壓V2,因此耦接至未被選取之記憶體單元100(1,M)的清除控制線ELM不得過低,否則將導致記憶體單元100(1,M)的寫入選擇電晶體130因為操作控制線OL1及清除控制線ELM之間的巨大電壓差而導致崩潰。然而清除控制線ELM亦不得過高,否則記憶體單元100(1,M)的第二浮接閘極電晶體140將被不預期地被寫入。
因此,在第10圖中,在記憶體單元100(1,1)的寫入操作期間,耦接至未被選取之記憶體單元100(1,M)的字元線WLM及源極線SLM可皆處於第一電壓V1,而耦接至未被選取之記憶體單元100(1,M)的清除控制線ELM可皆處於第二電壓V2。在此情況下,為了讓施加在記憶體單元100(1,M)之寫入選擇電晶體130上的電壓保持在可接受的範圍內,第二電壓V2可為10V,而第三電壓V3可為18V。如此一來,施加在記憶體單元100(1,M)之第二浮接閘極電晶體140的電壓就不至於過高而引致電子退出。因此能夠防止記憶體單元100(1,M)在記憶體單元100(1,1)的寫入操作期間被寫入。此外,記憶體單元100(1,M)的寫入選擇電晶體130也不至於損壞。
第11圖為本發明一實施例之記憶體單元100(1,1)的清除操作期間,記憶體陣列10之訊號線所接收到的電壓示意圖。
在記憶體單元100(1,1)之清除操作期間,源極線SL1和字元線WL1可皆處於第三電壓V3,位元線BL1可處於第二電壓V2,操作控制線OL1可處於第一電壓V1或第二電壓V2,而清除控制線EL1可處於第一電壓V1。因此,施加於記憶體單元100(1,1)之第二浮接閘極電晶體140上的巨大電壓差將引致福諾電子穿隧,使得記憶體單元100(1,1)被清除。
然而,在記憶體單元100(1,1)的清除操作期間,記憶體陣列10中的其他記憶體單元並未被選取,因此也不應被清除。在本發明的部分實施例中,記憶體陣列10是依列清除。舉例來說,在第11圖中,當記憶體單元100(1,1)被清除時,與記憶體單元100(1,1)設置於相同一列的其他記憶體單元,例如記憶體單元100(N,1),也將同步被清除。然而,與記憶體單元100(1,1)設置於相異列的記憶體單元則不應被清除。
舉例來說,記憶體單元100(1,M)與記憶體單元100(1,1)設置於相異列。由於記憶體單元100(1,M)也同樣會耦接至位元線BL1,且在記憶體單元100(1,1)的清除操作期間,位元線BL1會處於第二電壓V2,因此耦接至記憶體單元100(1,M)之源極線SLM的電壓不應過低,否則記憶體單元100(1,M)之讀取選擇電晶體110會因承受過大電壓而受損。此外,源極線SLM的電壓也不應過高,否則記憶體單元100(1,M)將被不預期地清除。
因此,在第11圖中,在記憶體單元100(1,1)的清除操作期間,耦接至未被選取之記憶體單元100(1,M)的字元線WLM可處於第三電壓V3,耦接至未被選取之記憶體單元100(1,M)的源極線SLM可處於第二電壓V2,而耦接至未被選取之記憶體單元100(1,M)的清除控制線ELM可處於第一電壓V1。
在此情況下,為了讓施加在記憶體單元100(1,M)之讀取選擇電晶體110上的電壓保持在可接受的範圍內,第二電壓V2可為10V,而第三電壓V3可為18V。如此一來,施加在記憶體單元100(1,M)之第一浮接閘極電晶體120的電壓就不至於過高而引致福諾電子穿隧。因此能夠防止記憶體單元100(1,M)在記憶體單元100(1,1)的寫入操作期間被清除。此外,記憶體單元100(1,M)的讀取選擇電晶體110也不至於受損。
第12圖為本發明一實施例之記憶體單元100(1,1)的讀取操作期間,記憶體陣列10之訊號線所接收到的電壓示意圖。
在記憶體單元100(1,1)的讀取操作期間,源極線SL1可處於第四電壓V4,位元線BL1可處於第五電壓V5,而字元線WL1、操作控制線OL1、清除控制線EL1可皆處於第一電壓V1。
由於第四電壓V4大於第五電壓V5,且第五電壓V5大於第一電壓V1,因此在記憶體單元100(1,1)的讀取操作期間,記憶體單元100(1,1)的讀取選擇電晶體110會被導通。在部分實施例中,第四電壓V4可為5V,第五電壓V5可為3.8V,而第一電壓V1可為0V。因此,可透過偵測讀取電流來判斷記憶體單元100(1,1)之共同浮接閘極FG的狀態。
然而,在記憶體單元100(1,1)的讀取操作期間,記憶體陣列10中其他未被選取的記憶體單元則不應被讀取。舉例來說,記憶體單元100(N,1)及記憶體單元100(1,M)就不應被讀取。
記憶體單元100(N,1)與記憶體單元100(1,1)位於相同一列。在第12圖中,在記憶體單元100(1,1)的讀取操作期間,耦接至未被選取之記憶體單元100(N,1)的位元線BLN及操作控制線OLN可皆為第一電壓V1。在此情況下,記憶體單元100(N,1)的讀取選擇電晶體110會被截止,使得記憶體單元100(N,1)不會被存取。
此外,記憶體單元100(1,M)與記憶體單元100(1,1)位於相異列。在第12圖中,在記憶體單元100(1,1)的讀取操作期間,耦接至未被選取之記憶體單元100(1,M)的字元線WLM可處於第四電壓V4,而耦接至未被選取之記憶體單元100(1,M)的源極線SLM可處於第一電壓V1。在此情況下,記憶體單元100(1,M)的讀取選擇電晶體110會被截止,使得記憶體單元100(1,M)不會被存取。
在記憶體陣列10中,由於電子退出及電子注入都是發生在記憶體單元100(1,1)至100(N,M)的第二浮接閘極電晶體140,而讀取電流則是經由記憶體單元100(1,1)至100(N,M)的讀取選擇電晶體110及第一浮接閘極電晶體120來感測,因此在寫入及清除過程中所造成記憶體單元100(1,1)至100(N,M)之第二浮接閘極電晶體140的缺陷將不會影到讀取電流。也就是說,由於記憶體陣列10之記憶體單元的寫入/清除路徑和讀取路徑是分別的兩條路徑,因此記憶體陣列10能夠承受夠多次數的寫入及清除操作,而不會使讀取的能力退化。
此外,在部分實施例中,記憶體陣列10也可將原先所使用之記憶體單元100改為第7圖所示的記憶體單元200來實作。透過適當的控制訊號,利用記憶體單元200來實作的記憶體陣列仍然能夠正常的操作,且同樣可較先前技術更加耐用。
綜上所述,根據本發明之實施例所提供的記憶體單元及記憶體陣列,其共同浮接閘極可透過第二浮接閘極電晶體來進行寫入及清除操作,並可透過第一浮接閘極電晶體及讀取選擇電晶體來進行讀取操作。因此,在第二浮接閘極電晶體或共同浮接閘極的缺陷將不會影響到第一浮接閘極電晶體和讀取選擇電晶體判斷讀取電流。也就是說,由於本發明之記憶體陣列及記憶體單元能夠承受夠多次數的寫入及清除操作,同時不會導致讀取能力退化。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100、200、100(1,1)至100(N,M)‧‧‧記憶體單元
110、210‧‧‧讀取選擇電晶體
120、220‧‧‧第一浮接閘極電晶體
130、230‧‧‧寫入選擇電晶體
140、240‧‧‧第二浮接閘極電晶體
FG‧‧‧共同浮接閘極
WL、WL1至WLM‧‧‧字元線
BL、BL1至BLN‧‧‧位元線
SL、SL1至SLM‧‧‧源極線
OL、OL1至OLN‧‧‧操作控制線
EL、EL1至ELM‧‧‧清除控制線
NW1、NW2‧‧‧N型井
PW、PW1、PW2‧‧‧P型井
P+‧‧‧P型參雜區
N+‧‧‧N型參雜區
OD1、OD2‧‧‧氧化擴散區
A1、A2‧‧‧重疊區域
P-Sub‧‧‧P型基底
STI‧‧‧淺溝槽絕緣層
132‧‧‧接觸窗
V1‧‧‧第一電壓
V2‧‧‧第二電壓
V3‧‧‧第三電壓
V4‧‧‧第四電壓
V5‧‧‧第五電壓
DNW‧‧‧深N型井
10‧‧‧記憶體陣列
110、210‧‧‧讀取選擇電晶體
120、220‧‧‧第一浮接閘極電晶體
130、230‧‧‧寫入選擇電晶體
140、240‧‧‧第二浮接閘極電晶體
FG‧‧‧共同浮接閘極
WL、WL1至WLM‧‧‧字元線
BL、BL1至BLN‧‧‧位元線
SL、SL1至SLM‧‧‧源極線
OL、OL1至OLN‧‧‧操作控制線
EL、EL1至ELM‧‧‧清除控制線
NW1、NW2‧‧‧N型井
PW、PW1、PW2‧‧‧P型井
P+‧‧‧P型參雜區
N+‧‧‧N型參雜區
OD1、OD2‧‧‧氧化擴散區
A1、A2‧‧‧重疊區域
P-Sub‧‧‧P型基底
STI‧‧‧淺溝槽絕緣層
132‧‧‧接觸窗
V1‧‧‧第一電壓
V2‧‧‧第二電壓
V3‧‧‧第三電壓
V4‧‧‧第四電壓
V5‧‧‧第五電壓
DNW‧‧‧深N型井
10‧‧‧記憶體陣列
第1圖為本發明一實施例之記憶體單元的示意圖。 第2圖為第1圖之記憶體單元的布局圖。 第3圖為第1圖之寫入選擇電晶體及第二浮接閘極電晶體的結構圖。 第4圖為第1圖之記憶體單元在寫入操作期間所接收的電壓示意圖。 第5圖為第1圖之記憶體單元在清除操作期間所接收的電壓示意圖。 第6圖為第1圖之記憶體單元在讀取操作期間所接收的電壓示意圖。 第7圖為本發明另一實施例之記憶體單元的示意圖。 第8圖為第7圖之記憶體單元的布局圖。 第9圖為本發明一實施例之記憶體陣列的示意圖。 第10圖為第9圖之記憶體陣列在其記憶體單元的寫入操作期間所接收到的電壓示意圖。 第11圖為第9圖之記憶體陣列在其記憶體單元的清除操作期間所接收到的電壓示意圖。 第12圖為第9圖之記憶體陣列在其記憶體單元的讀取操作期間所接收到的電壓示意圖。
10‧‧‧記憶體陣列
100(1,1)至100(N,M)‧‧‧記憶體單元
110‧‧‧讀取選擇電晶體
120‧‧‧第一浮接閘極電晶體
130‧‧‧寫入選擇電晶體
140‧‧‧第二浮接閘極電晶體
FG‧‧‧共同浮接閘極
WL1至WLM‧‧‧字元線
BL1至BLN‧‧‧位元線
SL1至SLM‧‧‧源極線
OL1至OLN‧‧‧操作控制線
EL1至ELM‧‧‧清除控制線
Claims (23)
- 一種記憶體單元,包含: 一讀取選擇電晶體,具有一第一端耦接於一位元線,一第二端,一控制端耦接於一字元線,及一基極端耦接於一源極線; 一第一浮接閘極電晶體,具有一第一端耦接於該讀取選擇電晶體之該第二端,一第二端耦接於該源極線,及一基極端耦接於該源極線; 一寫入選擇電晶體,具有一第一端耦接於一清除控制線,一第二端,一控制端耦接於一操作控制線,及一基極端耦接於該清除控制線; 一第二浮接閘極電晶體,具有一第一端耦接於該寫入選擇電晶體之該第二端,一第二端,及一基極端耦接於該清除控制線;及 一共同浮接閘極,耦接於該第一浮接閘極電晶體及該第二浮接閘極電晶體。
- 如請求項1所述之記憶體單元,其中該第一浮接閘極電晶體之一第一氧化擴散層與該共同浮接閘極相重疊之一第一重疊區域大於該第二浮接閘極電晶體之一第二氧化擴散層與該共同浮接閘極相重疊之一第二重疊區域。
- 如請求項1所述之記憶體單元,其中該讀取選擇電晶體,該第一浮接閘極電晶體,該寫入選擇電晶體,及該第二浮接閘極電晶體是由P型金氧半電晶體形成。
- 如請求項3所述之記憶體單元,其中: 該讀取選擇電晶體及該第一浮接閘極電晶體是形成於一第一N型井;及 該寫入選擇電晶體及該第二浮接閘極電晶體是形成於一第二N型井。
- 如請求項3所述之記憶體單元,其中在該記憶體單元的一寫入操作期間: 該源極線是處於一第一電壓; 該位元線是處於該第一電壓; 該字元線是處於該第一電壓; 該操作控制線是處於一第二電壓;及 該清除控制線是處於一第三電壓; 其中該第三電壓大於該第二電壓,且該第二電壓大於該第一電壓。
- 如請求項5所述之記憶體單元,其中在該記憶體單元的一讀取操作期間: 該源極線是處於一第四電壓; 該位元線是處於一第五電壓; 該字元線是處於該第一電壓; 該操作控制線是處於該第一電壓;及 該清除控制線是處於該第一電壓; 其中該第二電壓大於該第四電壓,該第四電壓大於該第五電壓,且該第五電壓大於該第一電壓。
- 如請求項3所述之記憶體單元,其中在該記憶體單元的一清除操作期間: 該源極線是處於一第三電壓; 該位元線是處於一第二電壓; 該字元線是處於該第三電壓; 該操作控制線是處於一第一電壓或該第二電壓;及 該清除控制線是處於該第一電壓; 其中該第三電壓大於該第二電壓,且該第二電壓大於該第一電壓。
- 如請求項1所述之記憶體單元,其中該讀取選擇電晶體、該第一浮接閘極電晶體、該寫入選擇電晶體及該第二浮接閘極電晶體是由N型金氧半電晶體形成。
- 如請求項8所述之記憶體單元,其中: 該讀取選擇電晶體及該第一浮接閘極電晶體是形成於一第一P型井; 該寫入選擇電晶體及該第二浮接閘極電晶體是形成於一第二P型井;及 該第一P型井及該第二P型井係設置於一深N型井。
- 一種記憶體陣列,包含: 複數條位元線; 複數條字元線; 複數條操作控制線; 複數條清除控制線; 複數條源極線;及 複數列記憶體單元,每一記憶體單元包含: 一讀取選擇電晶體,具有一第一端耦接於該些位元線之一位元線,一第二端,一控制端耦接於該些字元線之一字元線,及一基極端耦接於該些源極線之一源極線; 一第一浮接閘極電晶體,具有一第一端耦接於該讀取選擇電晶體之該第二端,一第二端耦接於該源極線,及一基極端耦接於該源極線; 一寫入選擇電晶體,具有一第一端耦接於該些清除控制線之一清除控制線,一第二端,一控制端耦接於該些操作控制線之一操作控制線,及一基極端耦接於該清除控制線; 一第二浮接閘極電晶體,具有一第一端耦接於該寫入選擇電晶體之該第二端,一第二端,及一基極端耦接於該清除控制線;及 一共同浮接閘極,耦接於該第一浮接閘極電晶體及該第二浮接閘極電晶體; 其中: 位於相同一列之複數個記憶體單元皆耦接於相同之一字元線,相同之一源極線,及相同之一清除控制線;及 位於相同一行之複數個記憶體單元皆耦接於相同之一位元線,及相同之一操作控制線。
- 如請求項10所述之記憶體陣列,其中該第一浮接閘極電晶體之一第一氧化擴散層與該共同浮接閘極相重疊之一第一重疊區域大於該第二浮接閘極電晶體之一第二氧化擴散層與該共同浮接閘極相重疊之一第二重疊區域。
- 如請求項10所述之記憶體陣列,其中該讀取選擇電晶體,該第一浮接閘極電晶體,該寫入選擇電晶體,及該第二浮接閘極電晶體是由P型金氧半電晶體形成。
- 如請求項12所述之記憶體單元,其中: 該讀取選擇電晶體及該第一浮接閘極電晶體是形成於一第一N型井;及 該寫入選擇電晶體及該第二浮接閘極電晶體是形成於一第二N型井。
- 如請求項12所述之記憶體陣列,其中在該記憶體單元的一寫入操作期間: 該源極線是處於一第一電壓; 該位元線是處於該第一電壓; 該字元線是處於該第一電壓; 該操作控制線是處於一第二電壓;及 該清除控制線是處於一第三電壓; 其中該第三電壓大於該第二電壓,且該第二電壓大於該第一電壓。
- 如請求項14所述之記憶體陣列,其中在該記憶體單元的該寫入操作期間: 耦接至與該記憶體單元位於同一列之一未選定記憶體單元之一位元線是處於該第一電壓;及 耦接至該未選定記憶體單元之一操作控制線是處於該第三電壓。
- 如請求項14所述之記憶體陣列,其中在該記憶體單元的該寫入操作期間: 耦接至與該記憶體單元位於同一行之一未選定記憶體單元之一字元線是處於該第一電壓; 耦接至該未選定記憶體單元之一源極線是處於該第一電壓;及 耦接至該未選定記憶體單元之一清除控制線是處於該第二電壓。
- 如請求項14所述之記憶體陣列,其中在該記憶體單元的一讀取操作期間: 該源極線是處於一第四電壓; 該位元線是處於一第五電壓; 該字元線是處於該第一電壓; 該操作控制線是處於該第一電壓;及 該清除控制線是處於該第一電壓; 其中該第二電壓大於該第四電壓,該第四電壓大於該第五電壓,且該第五電壓大於該第一電壓。
- 如請求項17所述之記憶體陣列,其中在該記憶體單元的該讀取操作期間: 耦接至與該記憶體單元位於同一列之一未選定記憶體單元之一位元線是處於該第一電壓;及 耦接至該未選定記憶體單元之一操作控制線是處於該第一電壓。
- 如請求項17所述之記憶體陣列,其中在該記憶體單元的該讀取操作期間: 耦接至與該記憶體單元位於同一行之一未選定記憶體單元之一字元線是處於該第四電壓; 耦接至該未選定記憶體單元之一源極線是處於該第一電壓;及 耦接至該未選定記憶體單元之一清除控制線是處於該第一電壓。
- 如請求項12所述之記憶體陣列,其中在該記憶體單元的一清除操作期間: 該源極線是處於一第三電壓; 該位元線是處於一第二電壓; 該字元線是處於該第三電壓; 該操作控制線是處於一第一電壓或該第二電壓;及 該清除控制線是處於該第一電壓; 其中該第三電壓大於該第二電壓,且該第二電壓大於該第一電壓。
- 如請求項20所述之記憶體陣列,其中在該記憶體單元的該清除操作期間: 耦接至與該記憶體單元位於同一行之一未選定記憶體單元之一字元線是處於該第三電壓; 耦接至該未選定記憶體單元之一源極線是處於該第二電壓;及 耦接至該未選定記憶體單元之一清除控制線是處於該第一電壓。
- 如請求項10所述之記憶體陣列,其中該讀取選擇電晶體、該第一浮接閘極電晶體、該寫入選擇電晶體及該第二浮接閘極電晶體是由N型金氧半電晶體形成。
- 如請求項22所述之記憶體單元,其中: 該讀取選擇電晶體及該第一浮接閘極電晶體是形成於一第一P型井; 該寫入選擇電晶體及該第二浮接閘極電晶體是形成於一第二P型井;及 該第一P型井及該第二P型井是設置於一N型深井區。
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