CN104517966A - 单层多晶硅非易失性存储器单元 - Google Patents

单层多晶硅非易失性存储器单元 Download PDF

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CN104517966A
CN104517966A CN201410341709.8A CN201410341709A CN104517966A CN 104517966 A CN104517966 A CN 104517966A CN 201410341709 A CN201410341709 A CN 201410341709A CN 104517966 A CN104517966 A CN 104517966A
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layer
volatile memory
memory unit
unit according
drain electrode
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CN104517966B (zh
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李翊宏
赖妍心
罗明山
黄士展
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eMemory Technology Inc
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    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
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    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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Abstract

本发明公开了一种单层多晶硅非易失性存储器(nonvolatile memory,NVM)单元包含一PMOS选择晶体管,位于一半导体基材上,以及一PMOS浮栅晶体管,串接上述PMOS选择晶体管。上述PMOS浮栅晶体管包含一浮栅以及一栅极氧化层介于上述浮栅及上述半导体基材间。一保护氧化层覆盖并且直接接触上述浮栅。一接触蚀刻停止层设置在上述保护氧化层上,通过上述保护氧化层使上述浮栅与上述接触蚀刻停止层相互分隔。

Description

单层多晶硅非易失性存储器单元
技术领域
本发明涉及一种非易失性存储器单元,特别是涉及一种单层多晶硅非易失性存储器单元,具有较佳的数据保存特性。
背景技术
非易失性存储器(nonvolatile memory,NVM)为一种在无电力供应时也可保留储存数据的存储器装置,例如,磁器件(magnetic devices)、光盘(opticaldiscs)、快闪存储器(flash memory)及其他半导体类的存储器。
例如,美国专利第6,678,190号公开了一种单层多晶硅非易失性存储器,其具有两个串联连接的PMOS晶体管,其中,在编程时,浮栅不需施加偏置,且在此布图结构中,控制栅已被省略。第一PMOS晶体管是作为一选择晶体管。第二PMOS晶体管是连接至上述第一PMOS晶体管。上述第二PMOS晶体管的栅极是作为一浮栅。上述浮栅被选择性的编程或抹除以存储电荷。
在该技术领域中,如何使储存于浮栅中的电荷能被长时间的保留,以增加非易失性存储器的数据保存特性,仍为现今的研究课题。
发明内容
本发明的主要目的涉及提供改良的单层多晶硅非易失性存储器单元,其具有更佳的数据保存特性。
在一实施例中,单层多晶硅非易失性存储器包含选择晶体管,例如是一PMOS选择晶体管,位于一半导体基材的第一井上,例如是一N型井上,以及一PMOS浮栅晶体管,是串接上述PMOS选择晶体管。上述PMOS选择栅晶体管包含一选择栅、一第一栅极氧化层介于上述选择栅及上述半导体基材间、一第一间隙壁位于上述选择栅的任一侧壁上、一第一有源极/漏极掺杂区,例如是第一P型有源极/漏极掺杂区位于上述N型井中,以及一第二P型有源极/漏极掺杂区是与上述第一P型有源极/漏极掺杂区相间隔。上述PMOS浮栅晶体管包含一浮栅、一第二栅极氧化层介于上述选择栅及上述半导体基材间、一第二间隙壁位于上述浮栅的任一侧壁上、与上述PMOS选择晶体管共享的上述第二P型有源极/漏极掺杂区,以及一第三P型有源极/漏极掺杂区是与上述第二P型有源极/漏极掺杂区相间隔。
一第一金属硅化物层,例如是一第一自对准金属硅化物层,设置在上述第一P型有源极/漏极掺杂区上。一第二金属硅化物层,位于上述P型第二有源极/漏极掺杂区上。上述第二金属硅化物层与上述第一间隙壁底部的边缘接壤,但与上述第二间隙壁底部的边缘间保持一预定距离。一保护氧化层,覆盖并且直接接触上述浮栅。一接触蚀刻停止层,位于上述保护氧化层上,通过上述保护氧化层使上述浮栅与上述接触蚀刻停止层相互分隔。
附图说明
图1为本发明一实施例的部分非易失性存储器布图示意图。
图2为图1沿着Ⅰ-Ⅰ’切线的切面示意图。
图3为本发明另一实施例的部分非易失性存储器布图示意图,其具有额外的UV阻挡层。
图4为本发明另一实施例的部分非易失性存储器布图示意图。
图5为图4沿着Ⅱ-Ⅱ’切线的切面示意图。
图6及图7为本发明单层多晶硅非易失性存储器单元的剖视示意图,其与高压制作工艺相容。
图8为本发明另一实施例的布图示意图。
图9例示制作单层多晶硅非易失性存储器的主要阶段的步骤流程。
其中，附图标记说明如下：
1、1a、1c、1d              单层多晶硅非易失性存储器
12                         字符线
14                         浮栅段
100                        半导体基材
101、101’、101”          有源区
102                        隔离凹槽区
110                        N型井
112、114、116              P型有源极/漏极掺杂区
112a、114a、114b、116a     P型轻掺杂区
120、140                   栅极氧化层
122、142                   间隙壁
2                          多次编程存储器
210、212、214、216         自对准金属硅化物层
300                        保护氧化层
312                        接触蚀刻停止层
320                        层间介电层
321                        源线接触孔
322                        位线接触孔
400                        UV阻挡层
610                        深N型井
612                        高压P型井
620                        STI区
710                        高压P型井
712                        N型埋层
91-96                      步骤
BC                         位线接触区
C1、C2                     非易失性存储器单元
CG                         控制栅区
EG                         抹除栅区
FT、FT1、FT2               浮栅晶体管
FG                         浮栅
ML1                        第一金属层
ST、ST1、ST2               选择晶体管
SG                         选择栅
WLx-1、WLx                 字符线
具体实施方式
为使熟习本技术领域的技术人员能更进一步了解本发明,下文特详细说明本发明的构成内容及希望实现的效果。下文已公开足够的细节使该领域的一般技术人员得以具以实施。此外,一些本领域已公知的对象结构及操作流程将不再重复描述。当然,本发明中也可实行其他的实施例,或是在不违反文中所述实施例的前提下作出任何结构性、逻辑性及电性上的改变。
同样地,如下所述的优选实施方式与附图仅供参考与说明用,并非用来对本发明加以限制,且为清楚呈现本发明,部分对象尺寸已被放大。此外,各实施例中相同或相似的对象将以相同标号标记,以便更容易了解本发明。
请参照图1及图2所示。图1为本发明一实施例的单层多晶硅非易失性存储器布图示意图。图2为图1沿着Ⅰ-Ⅰ’切线的剖面示意图。如图1及图2所示,多个直线型有源区101沿一第一方向延伸于一半导体基材100中,半导体基材100例如是P型硅基材(P-Sub)。通过数个位于有源区101间的隔离凹槽(STI)区102将上述有源区101彼此相互分离。在图1中,仅绘示两列有源区101。多条字符线12(例如图1的WLx-1及WLx)形成于半导体基材100的主表面上。字符线12沿一第二方向延伸(例如参考y轴)且与有源区101相交以在交会处形成数个选择晶体管(ST)。各字符线12可作为相对应选择晶体管的选择栅(SG)。为简化说明,在图1中仅绘示两行字符线12。根据上述实施例,上述第一方向是垂直于上述第二方向。
单层多晶硅非易失性存储器1进一步包含多个用以储存电荷的浮栅段14,是沿着各有源区101设置,且位于字符线12间,借此使两相邻字符线12间仅具有两浮栅段14或两浮栅晶体管(FT)。例如,两镜像对称NVM胞:如图1及图2所示位于有源区101上方同列的C1及C2。NVM胞C1包含一选择晶体管ST1以及串接于选择晶体管ST1的一浮栅晶体管FT1。同样地,NVM胞C2包含一选择晶体管ST2以及串接于选择晶体管ST2的一浮栅晶体管FT2。NVM胞C1及NVM胞C2共享同一位线接触(bit line contact,BC)区。
如图2所示,例如选择晶体管ST1包含一选择栅(SG)12(即所述之字符线，在各NVM胞中称为选择栅)、一栅极氧化层120介于选择栅(SG)12及半导体基材100间、一间隙壁122,位于选择栅(SG)12的一侧壁上、一第一有源极/漏极掺杂区,例如是一P型有源极/漏极掺杂区112位于一第一井中,例如是一N型井(NW)110中、一P型轻掺杂(PLDD)区112a与P型有源极/漏极掺杂区112相合并、一第二有源极/漏极掺杂区,例如是一P型有源极/漏极掺杂区114与P型有源极/漏极掺杂区112相间隔,以及一PLDD区114a与P型有源极/漏极掺杂区114相合并。在操作时,一P型通道区可形成于PLDD区112a与PLDD区114a间,且位于选择栅(SG)12的下方。浮栅晶体管FT1包含一浮栅(FG)14、一栅极氧化层140介于浮栅(FG)14(即所述之浮栅段，在各NVM胞中称为浮栅)及上述半导体基材100间、一间隙壁142,位于浮栅(FG)14的一侧壁上、P型有源极/漏极掺杂区114、一PLDD区114b与P型有源极/漏极掺杂区114相合并、一第三有源极/漏极掺杂区,例如是一P型有源极/漏极掺杂区116与P型有源极/漏极掺杂区114相间隔,以及一PLDD区116a与P型有源极/漏极掺杂区116相合并。选择晶体管ST1与浮栅晶体管FT1共享P型有源极/漏极掺杂区114。根据上述实施例,选择栅(SG)12与浮栅(FG)14是由单层的多晶硅层所制成,其完全与逻辑制作工艺兼容。
根据上述实施例,浮栅晶体管FT1的栅极氧化层140的厚度可较逻辑晶体管装置的栅极氧化层的厚度更厚,例如是位于相同存储器芯片的周边电路的上述晶体管装置。较厚的栅极氧化层140可改善单层多晶硅非易失性存储器1的资料保存能力。在另一实施例中,栅极氧化层140的厚度可以等同于栅极氧化层120的厚度。
一第一金属硅化物层,例如是自对准金属硅化物(salicide)层212,设置在P型有源极/漏极掺杂区112上。自对准金属硅化物层212延伸至间隙壁122底部的边缘。在选择栅(SG)12的相对侧上,一第二金属硅化物层,例如是自对准金属硅化物层214,设置在P型有源极/漏极掺杂区114上。自对准金属硅化物层212与间隙壁122底部的边缘接壤,但与间隙壁142底部的边缘间保持一预定距离。换句话说,自对准金属硅化物层212覆盖P型有源极/漏极掺杂区112的整个表面区域,自对准金属硅化物层214仅覆盖P型有源极/漏极掺杂区114与间隙壁122邻接部分的表面区域,且自对准金属硅化物层214与间隙壁142的上述边缘相互间隔。同样地,在浮栅(FG)14的相对侧上,一第三金属硅化物层,例如是一自对准金属硅化物层216,设置在P型有源极/漏极掺杂区116上。自对准金属硅化物层216与间隙壁142底部的边缘保持一预定距离。一第四金属硅化物层,例如是一自对准金属硅化物层210位于选择栅(SG)12的顶表面上。值得注意的是,浮栅(FG)14的顶表面上并未形成金属硅化物层。
一保护氧化层300,覆盖于浮栅(FG)14上。根据上述实施例,上述保护氧化层300可包含氧化硅,但不限于此。保护氧化层300覆盖浮栅(FG)14的顶表面、间隙壁142的表面、P型有源极/漏极掺杂区114的部分表面,以及P型有源极/漏极掺杂区116的部分表面。前述自对准金属硅化物层214及216仅形成在P型有源极/漏极掺杂区114及116未被保护氧化层300覆盖的表面区域上。保护氧化层300预定覆盖的区域则如图1的虚线所标示。
位于P型有源极/漏极掺杂区114中且介于间隙壁142与自对准金属硅化物层214间的非金属硅化区,以及位于P型有源极/漏极掺杂区116中且介于间隙壁142与自对准金属硅化物层216间的非金属硅化区可减少缺陷诱发的带间隧穿干扰(band to band tunneling disturbance)。
一共形的接触蚀刻停止层(conformal contact etch stop layer,CESL)312接着形成在保护氧化层300的上方以覆盖选择栅(SG)12、浮栅(FG)14,以及自对准金属硅化物层212、214及216。根据上述实施例,共形的接触蚀刻停止层(CESL)312为一氮化硅层,且可以通过等离子体增强化学气相沉积(plasmaenhanced chemical vapor deposition,PECVD)制作工艺进行沉积。通过调整上述共形的接触蚀刻停止层(CESL)312中的硅对氮比例(例如,调整SiH4/NH3在反应槽中的比例)以降低其电子捕阱能力。值得注意的是,由于保护氧化层300的关系,接触蚀刻停止层(CESL)312并未直接接触浮栅(FG)14或间隙壁142。由于保护氧化层300使浮栅(FG)14与上述接触蚀刻停止层(CESL)312相互分隔,可有效改善单层多晶硅非易失性存储器单元1的数据保存特性。
一层间介电(inter-layer dielectric layer,ILD)层320沉积在接触蚀刻停止层(CESL)312上。层间介电层320较接触蚀刻停止层(CESL)312厚,且完全地填充于选择栅(SG)12与浮栅(FG)14间的间隙中。若有需要时,可进行一化学机械抛光制作工艺(chemical mechanical polish,CMP)以平坦化层间介电层320的表面。一源线接触孔321及一位线接触孔322形成于层间介电层320中。一源线(source line,SL)以及一位线(bit line,BL)可被定义于一第一金属层(ML1)中,以分别连接源线接触孔321及位线接触孔322。
请参照图3所示,图3为本发明另一实施例的非易失性存储器布图示意图。如图3所示,上述存储器单元的布图近似于图1所示布图,差别在于额外增设一UV阻挡层400,当非易失性存储器作为单次编程(one-time programmable,OTP)存储器时,可进一步强化其资料保存能力。UV阻挡层400位于存储器数组区,至少完全地覆盖或是直接设置在浮栅(FG)14上方。UV阻挡层400可以是任何位于半导体基材100上的介电层中的膜层,其具有阻挡或分散UV辐射的能力。例如,UV阻挡层400可以是位于钝化结构的一氮化硅层或者是一冗余金属层。前述位于钝化结构中的上述硅氮层可以利用PECVD或是LPCVD方法沉积形成,且可具有大于一预定值的折射率。
请参照图4及图5所示,图4为本发明另一实施例的非易失性存储器布图示意图。图5为图4沿着Ⅱ-Ⅱ’切线的剖面示意图。如图4及图5所示,同样地,多个直线型有源区101沿一第一方向(例如x参考轴)延伸于一半导体基材100中,半导体基材100例如P型硅基材(P-Sub)。通过数个位于有源区101间的隔离凹槽区(STI)102将上述有源区101彼此相互分离。在图4中,仅绘示出两列有源区101。多条字符线12(例如图4的WLx-1及WLx)形成于半导体基材100的主表面上。字符线12沿一第二方向延伸(例如参考y轴)且与有源区101相交,在交会处形成数个选择晶体管(ST)。各字符线12可作为相对应选择晶体管的选择栅(SG)。为简化说明,在图4中仅绘示两行字符线12。根据上述实施例,上述第一方向垂直于上述第二方向。
单层多晶硅非易失性存储器1a更进一步包含多个用以储存电荷的浮栅段14,是沿着各有源区101设置,且位于字符线12间,借此使两相邻字符线12间仅具有两浮栅段14或两浮栅晶体管(FT)。例如,两镜像对称两NVM胞:如图4及图5所示位于有源区101上方同列的C1及C2。NVM胞C1包含一选择晶体管ST1以及串接于选择晶体管ST1的一浮栅晶体管FT1。同样地,NVM胞C2包含一选择晶体管ST2以及串接于选择晶体管ST2的一浮栅晶体管FT2。NVM胞C1及NVM胞C2共享同一位线接触(BC)区。
如图5所示,选择晶体管ST1包含一选择栅(SG)12、一栅极氧化层120介于选择栅(SG)12及半导体基材100间、一间隙壁122,位于选择栅(SG)12的一侧壁上、一P型有源极/漏极掺杂区112位于一N型井(NW)110中、一P型轻掺杂(PLDD)区112a与P型有源极/漏极掺杂区112相合并、一P型有源极/漏极掺杂区114与P型有源极/漏极掺杂区112相间隔,以及一PLDD区114a与P型有源极/漏极掺杂区114相合并。在操作时,一P型通道区可形成于PLDD区112a与PLDD区114a间,且位于选择栅(SG)12的下方。浮栅晶体管FT1包含一浮栅(FG)14、一栅极氧化层140介于浮栅(FG)14及上述半导体基材100间、一间隙壁142,位于浮栅(FG)14的一侧壁上、P型有源极/漏极掺杂区114、一PLDD区114b与P型有源极/漏极掺杂区114相合并、一P型有源极/漏极掺杂区116与P型有源极/漏极掺杂区114相间隔,以及一PLDD区116a与P型有源极/漏极掺杂区116相合并。选择晶体管ST1与浮栅晶体管FT1共享P型有源极/漏极掺杂区114。根据上述实施例,选择栅(SG)12与浮栅(FG)14是由单层的多晶硅层所制成,其完全与逻辑制作工艺兼容。
一自对准金属硅化物层212,设置在P型有源极/漏极掺杂区112上。自对准金属硅化物层212延伸至间隙壁122底部的边缘。在选择栅(SG)12的相对侧上,P型有源极/漏极掺杂区114上方并未设置自对准金属硅化物层。一自对准金属硅化物层216,设置在P型有源极/漏极掺杂区116上。自对准金属硅化物层216与间隙壁142底部的边缘保持一预定距离。一自对准金属硅化物层210位于选择栅(SG)12的顶表面上。值得注意的是,浮栅(FG)14的顶表面上并未形成金属硅化物层。
一保护氧化层300,覆盖于浮栅(FG)14上。根据上述实施例,上述保护氧化层300可包含氧化硅,但不限于此。保护氧化层300覆盖且直接接触浮栅(FG)14的上述顶表面、间隙壁142的表面、P型有源极/漏极掺杂区114的整个表面,以及P型有源极/漏极掺杂区的部分表面116。前述自对准金属硅化物层216仅形成在P型有源极/漏极掺杂区116未被保护氧化层300覆盖的表面区域上。保护氧化层300预定覆盖的区域则如图4的虚线所标示。如上述实施例所示,P型有源极/漏极掺杂区114完全地被保护氧化层300覆盖。
一共形的接触蚀刻停止层(CESL)312接着形成在保护氧化层300的上方以覆盖选择栅(SG)12、浮栅(FG)14,以及自对准金属硅化物层212及216。根据上述实施例,共形的接触蚀刻停止层(CESL)312为一硅氮层且可以等离子体增强化学气相沉积(PECVD)制作工艺进行沉积。通过调整上述共形的接触蚀刻停止层(CESL)312中的硅对氮比例(例如,调整SiH4/NH3在反应槽中的比例)以降低其电子捕阱能力。可以理解的是,共形的接触蚀刻停止层(CESL)312可以是任何具有降低电子陷阱能力的材质,且并不以前述举例为限。需注意的是,由于保护氧化层300的关系,接触蚀刻停止层(CESL)312并未直接接触浮栅(FG)14或间隙壁142。通过以保护氧化层300使浮栅(FG)14与上述接触蚀刻停止层(CESL)312相互分隔的手段,可有效改善单层多晶硅非易失性存储器1a的数据保存功能。
一层间介电(ILD)层320是沉积在接触蚀刻停止层(CESL)312上。层间介电层320较接触蚀刻停止层(CESL)312厚,且完全地填充于选择栅(SG)12与浮栅(FG)14间的间隙中。若有需要时,可进行一化学机械研磨制作工艺(CMP)以平坦化层间介电层320的表面。一源线接触孔321及一位线接触孔322形成于层间介电层320中,以分别电性连接P型有源极/漏极掺杂区112及P型有源极/漏极掺杂区116。一源线(SL)以及一位线(BL)可被定义于第一金属层(ML1)中,以分别连接源线接触孔321及位线接触孔322。
请参照图6及图7所示,图6及图7例示其他实施例的单层多晶硅非易失性存储器单元的剖视图,其与高压制作工艺相容。如图6所示,单层多晶硅非易失性存储器1c包含一深N型井(deep N well,DNW)610,增设于N型井110的下方。根据上述实施例,N型井110可以是一中压N型井(medium-voltage N well,MVNW)。一高压N型井(high-voltage N well,HVNW)612形成于半导体基材100中,且与深N型井610相合并。高压N型井(HVNW)612是通过一STI区620而与单层多晶硅非易失性存储器单元分隔开。
如图7所示,单层多晶硅非易失性存储器1d与图6的单层多晶硅非易失性存储器1c差异在于一N型埋层(N-type buried layer,NBL)712是设置在一高压N型井(HVNW)612的下方。一高压P型井(HVPW)710是形成于N型埋层712与中压N型井110间。
图8例示本发明另一实施例的存储器布图示意图。如图8所示,其绘示一种多次编程(multiple time programmable,MTP)存储器范例。多次编程(MTP)存储器2的浮栅(FG)可延伸于一第二方向(例如参考y轴)以电容耦接相邻的有源区101’及101”,借此分别形成一控制栅(control gate,CG)区以及一抹除栅(erase gate,EG)区。同样地,保护氧化层300,完全地覆盖于浮栅(FG)14上、控制栅(CG)区,以及抹除栅(EG)区。前述延伸装置可以是一N型金氧半场效晶体管(NMOSFET)、P型金氧半场效晶体管(PMOSFET)、N型金氧半电容(N-typeMOS capacitor)或P型金氧半电容(P-type MOS capacitor)。将前述浮栅(FG)、控制栅(CG)区,以及抹除栅(EG)区沿同一条浮置多晶硅联带(floating poly strip)设置,可利用前述技术改善电荷保存能力。
图9例示制作单层多晶硅非易失性存储器的主要阶段的步骤流程。如图9所示,在步骤91中,在半导体基材形成数个STI区及数个有源区。之后,进行井掺杂,以在上述半导体基材形成井结构。在步骤92中,一多晶硅层是被沉积且图案化,以形成单层多晶硅浮栅。在步骤93中,在栅极的侧壁上形成数个间隙壁。在步骤94中,在存储器数组中的上述单层多晶硅浮栅的上方形成一保护氧化层。在步骤95中,在有源极/漏极区的上方形成一硅化金属层。在步骤96中,接着沉积一接触蚀刻停止层。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (22)

1.一种单层多晶硅非易失性存储器单元,其特征在于,包含:
一选择晶体管,位于一半导体基材的一第一井上,其中该选择晶体管包含一选择栅、一第一栅极氧化层介于该选择栅及该半导体基材间、一第一有源极/漏极掺杂区位于该第一井中,以及一第二有源极/漏极掺杂区与该第一有源极/漏极掺杂区相间隔；
一浮栅晶体管,位于该第一井上且串接该选择晶体管,其中该浮栅晶体管包含一浮栅、一第二栅极氧化层介于该浮栅及该半导体基材间、与该选择晶体管共享的该第二有源极/漏极掺杂区,以及一第三有源极/漏极掺杂区与该第二有源极/漏极掺杂区相间隔；
一第一金属硅化物层,位于该第一有源极/漏极掺杂区上；
一保护氧化层,覆盖并且直接接触该浮栅；以及
一接触蚀刻停止层,位于该保护氧化层上,通过该保护氧化层使该浮栅与该接触蚀刻停止层相互分隔。
2.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一第一间隙壁,位于该选择栅的任一侧壁上,以及一第二间隙壁,位于该浮栅的任一侧壁上。
3.根据权利要求2所述的单层多晶硅非易失性存储器单元,其特征在于,该第一金属硅化物层延伸至该第一间隙壁底部的边缘。
4.根据权利要求2所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一第二金属硅化物层,位于该第二有源极/漏极掺杂区上,其中该第二金属硅化物层与该第一间隙壁底部的边缘接壤,但与该第二间隙壁底部的边缘间保持一预定距离。
5.根据权利要求4所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一第三金属硅化物层,位于该第三有源极/漏极掺杂区上,其中,该第三金属硅化物层与该第二间隙壁底部的边缘保持一预定距离。
6.根据权利要求5所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一第四金属硅化物层,位于该选择栅的一顶表面上。
7.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,该浮栅的一顶表面上未形成一金属硅化物层。
8.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一层间介电层,位于该接触蚀刻停止层下面。
9.根据权利要求8所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一源线接触孔及位线接触孔,位于该层间介电层中以分别电连接该第一有源极/漏极掺杂区及该第三有源极/漏极掺杂区。
10.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,该保护氧化层为一硅氧层。
11.根据权利要求2所述的单层多晶硅非易失性存储器单元,其特征在于,该保护氧化层覆盖且直接接触该浮栅的一顶表面、该第二间隙壁的表面、该第二有源极/漏极掺杂区的一部分,以及该第三有源极/漏极掺杂区的一部分。
12.根据权利要求2所述的单层多晶硅非易失性存储器单元,其特征在于,该保护氧化层覆盖且直接接触该浮栅的一顶表面、该第二间隙壁的表面、该第二有源极/漏极掺杂区的整个表面,以及该第三有源极/漏极掺杂区的一部分。
13.根据权利要求5所述的单层多晶硅非易失性存储器单元,其特征在于,该第三金属硅化物层仅形成在该第三有源极/漏极掺杂区未被该保护氧化层覆盖的表面区域上。
14.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一UV阻挡层,完全覆盖或直接设置在该浮栅的上方。
15.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一深N井区,设置在该第一井的下方。
16.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,该第一井是一中压N型井。
17.根据权利要求16所述的单层多晶硅非易失性存储器单元,其特征在于,更包含一高压P型井,设置在该中压N型井的下方,且一N型埋层设置在该高压P型井的下方。
18.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,该第二栅极氧化层较该第一栅极氧化层厚。
19.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,该浮栅可延伸至与一抹除栅区电容耦合。
20.根据权利要求19所述的单层多晶硅非易失性存储器单元,其特征在于,该保护氧化层更完全地覆盖该抹除栅区。
21.根据权利要求1所述的单层多晶硅非易失性存储器单元,其特征在于,该浮栅更电容耦合至一控制栅区及一抹除栅区。
22.根据权利要求21所述的单层多晶硅非易失性存储器单元,其特征在于,该保护氧化层更完全地覆盖该控制栅区及该抹除栅区。
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