TWI584414B - 非揮發性記憶體結構及製造方法 - Google Patents

非揮發性記憶體結構及製造方法 Download PDF

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TWI584414B
TWI584414B TW103121255A TW103121255A TWI584414B TW I584414 B TWI584414 B TW I584414B TW 103121255 A TW103121255 A TW 103121255A TW 103121255 A TW103121255 A TW 103121255A TW I584414 B TWI584414 B TW I584414B
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layer
volatile memory
gate
polycrystalline germanium
region
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TW201513269A (zh
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李翊宏
賴妍心
羅明山
黃士展
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力旺電子股份有限公司
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    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
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    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
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Description

非揮發性記憶體結構及製造方法
本發明有關一種非揮發性記憶體裝置，特別是有關一種單層多晶非揮發性記憶體結構，具有較佳的資料保存特性。
非揮發性記憶體(nonvolatile memory，NVM)為一種在無電力供應時亦可保留儲存資料的記憶體裝置，例如，磁性裝置(magnetic devices)、光碟(optical discs)、快閃記憶體(flash memory)及其他半導體類的記憶體。
例如，美國專利第6,678,190號公開了一種單層多晶非揮發性記憶體，其具有兩個串聯連接的PMOS電晶體，其中，在編程時，浮置閘極不需施加偏壓，且在此佈局結構中，控制柵極已被省略。第一PMOS電晶體係作為一選擇電晶體。第二PMOS電晶體係連接至該第一PMOS電晶體。該第二PMOS電晶體的閘極係作為一浮置閘極。該浮置閘極被選擇性的編程或抹除以存儲電荷。
在該技術領域中，如何使儲存於浮置閘極中的電荷能被長時間的保留，以增加非揮發性記憶體的數據保存特性，仍為現今的研究課題。
本發明的主要目的在於提供改良的單層多晶非揮發性記憶體結構，其具有更佳的資料保存特性。
在一實施例中，單層多晶非揮發性記憶體包含一PMOS選擇電晶體，位於一半導體基底的一N型井上，以及一PMOS浮置閘極電晶體，係串接該PMOS選擇電晶體。該PMOS選擇閘極電晶體包含一選擇閘極、一第一 閘極氧化層介於該選擇閘極及該半導體基底之間、一第一側壁子位在該選擇閘極的任一側壁上、一第一P型源極/汲極摻雜區位在該N型井中，以及一第二P型源極/汲極摻雜區係與該第一P型源極/汲極摻雜區相間隔。該PMOS浮置閘極電晶體包含一浮置閘極、一第二閘極氧化層介於該選擇閘極及該半導體基底之間、一第二側壁子位在該浮置閘極的任一側壁上、與該PMOS選擇電晶體共用的該第二P型源極/汲極摻雜區，以及一第三P型源極/汲極摻雜區係與該第二P型源極/汲極摻雜區相間隔。
一第一自對準金屬矽化物層，設置在該第一P型源極/汲極摻雜區上。一第二金屬矽化物層，位於該P型第二源極/汲極摻雜區上。該第二金屬矽化物層與該第一側壁子底部的邊緣接壤，但與該第二側壁子底部的邊緣之間保持一預定距離。一保護氧化層，覆蓋並且直接接觸該浮置閘極。一接觸蝕刻停止層，位在該保護氧化層上，藉由該保護氧化層使該浮置閘極與該接觸蝕刻停止層相互分隔。
1、1a、1c、1d‧‧‧單層多晶矽非揮發性記憶體
12‧‧‧字元線
14‧‧‧浮置閘極段
100、100’、100”‧‧‧半導體基底
101‧‧‧主動區
102‧‧‧淺溝絕緣區
110‧‧‧N型井
112、114、116‧‧‧P型源極/汲極摻雜區
112a、114a、116a‧‧‧P型輕摻雜區
120、140‧‧‧閘極氧化層
122、142‧‧‧側壁子
140‧‧‧閘極氧化層
210、212、214、216‧‧‧自對準金屬矽化物層
300‧‧‧保護氧化層
312‧‧‧接觸蝕刻停止層
320‧‧‧層間介電層
321‧‧‧源線接觸孔
322‧‧‧位線接觸孔
400‧‧‧UV阻擋層
610‧‧‧深N型井
612‧‧‧高壓P型井
620‧‧‧STI區
710‧‧‧高壓P型井
712‧‧‧N型障壁層
91-96‧‧‧步驟
BC‧‧‧位元接觸區
C1、C2‧‧‧非揮發性記憶體單元
CG‧‧‧控制閘極區
EG‧‧‧抹除閘極區
FT、FT1、FT2‧‧‧浮置閘極電晶體
FG‧‧‧浮置閘極
ML1‧‧‧第一金屬層
ST、ST1、ST2‧‧‧選擇電晶體
SG‧‧‧選擇閘極
WLx-1、WLx‧‧‧字元線
為使能進一步理解本實施例，特提供圖式，該些圖式已被併入並且已構成本說明書的一部分。該些圖式繪示一些實施例，係配合說明書一併用以解釋其原理。在該些圖式中：
第1圖為本發明一實施例的部分非揮發性記憶體佈局示意圖。
第2圖為第1圖沿著I-I’切線的剖面示意圖。
第3圖為本發明另一實施例的部分非揮發性記憶體佈局示意圖，其具有額外的UV阻擋層。
第4圖為本發明另一實施例的部分非揮發性記憶體佈局示意圖。
第5圖為第4圖沿著Ⅱ-Ⅱ’切線的切面示意圖。
第6圖及第7圖為本發明單層多晶矽非揮發性記憶體單元的剖面示意圖， 其與高壓製程相容。
第8圖為本發明另一實施例的佈局示意圖。
第9圖例示製作單層多晶矽非揮發性記憶體的主要階段的步驟流程。
應注意的是，所有圖式皆為示意圖。為求清楚和方便呈現，部分附圖中部件的相對尺寸和比例已被放大或縮小。在改良或不同的實施例中，相對應的或相似的特徵將會使用相同的附圖標記標示。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特詳細說明本發明的構成內容及所欲達成之功效。下文已揭露足夠的細節俾使該領域之一般技藝人士得以具以實施。此外，一些本領域已熟知之物件結構及操作流程將不再贅述。當然，本發明中亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性及電性上的改變。
同樣地，如下所述之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者，且為清楚呈現本發明，部分物件尺寸已被放大。再者，各實施例中相同或相似的物件將以相同標號標記，以便更容易了解本發明。
請參照第1圖及第2圖所示。第1圖為本發明一實施例的單層多晶矽非揮發性記憶體佈局示意圖。第2圖為第1圖沿著I-I’切線的剖面示意圖。如第1圖及第2圖所示，複數個直線型主動區101沿一第一方向延伸於一半導體基底100中，半導體基底100例如是P型矽基底(P-Sub)。藉由數個位於主動區101之間的淺溝絕緣(STI)區102將該些主動區101彼此相互分離。在第1圖中，僅繪示兩列主動區101。複數條字元線12(例如第1圖的WLx-1及WLx)形成於半導體基底100的主表面上。字元線12沿一第二方向延伸(例如參考y軸)且與主動區101相交以在交會處形成數個選擇 電晶體(ST)。各字元線12可作為相對應選擇電晶體的選擇閘極(SG)。為簡化說明，在第1圖中僅繪示兩行字元線12。根據該實施例，該第一方向是垂直於該第二方向。
單層多晶矽非揮發性記憶體1進一步包含複數個用以儲存電荷的浮置閘極段14，係沿著各主動區101設置，且位於字元線12之間，藉此使兩相鄰字元線12之間僅具有兩浮置閘極段14或兩浮置閘極電晶體(FT)。例如，兩鏡像對稱NVM胞：如第1圖及第2圖所示位在主動區101上方同列的C1及C2。NVM胞C1包含一選擇電晶體ST1以及串接於選擇電晶體ST1的一浮置閘極電晶體FT1。同樣地，NVM胞C2包含一選擇電晶體ST2以及串接於選擇電晶體ST2的一浮置閘極電晶體FT2。NVM胞C1及NVM胞C2共用同一位元接觸(bit line contact，BC)區。
如第2圖所示，例如選擇電晶體ST1包含一選擇閘極(SG)12、一閘極氧化層120介於選擇閘極(SG)12及半導體基底100之間、一側壁子122，位於選擇閘極(SG)12的一側壁上、一P型源極/汲極摻雜區112位於一N型井(NW)110中、一P型輕摻雜(PLDD)區112a與P型源極/汲極摻雜區112相合併、一P型源極/汲極摻雜區114與P型源極/汲極摻雜區112相間隔，以及一PLDD區114a與P型源極/汲極摻雜區114相合併。在操作時，一P型通道區可形成於PLDD區112a與PLDD區114a之間，且位在選擇閘極(SG)12的下方。浮置閘極電晶體FT1包含一浮置閘極(FG)14、一閘極氧化層140介於浮置閘極(FG)14及該半導體基底100之間、一側壁子142，位於浮置閘極(FG)14的一側壁上、P型源極/汲極摻雜區114、一PLDD區114b與P型源極/汲極摻雜區114相合併、一P型源極/汲極摻雜區116與P型源極/汲極摻雜區114相間隔，以及一PLDD區116a與P型源極/汲極摻雜區116相合併。選擇電晶體ST1與浮置閘極電晶體FT1共用P型源極/汲極摻雜區114。根據該實施例，選擇閘極(SG)12與浮置閘極(FG)14是由單層的多晶矽層所製成，其完全與邏輯製程相容。
根據該實施例，浮置閘極電晶體FT1的閘極氧化層140的厚度可較邏輯電晶體裝置的閘極氧化層的厚度更厚，例如是位於相同記憶體晶片的周邊電路的該些電晶體裝置。較厚的閘極氧化層140可改善單層多晶矽非揮發性記憶體1的資料保存能力。在另一實施例中，閘極氧化層140的厚度可以等同於閘極氧化層120的厚度。
一自對準金屬矽化物(salicide)層212，設置在P型源極/汲極摻雜區112上。自對準金屬矽化物層212延伸至側壁子122底部的邊緣。在選擇閘極(SG)12的相對側上，一自對準金屬矽化物層214，設置在P型源極/汲極摻雜區114上。自對準金屬矽化物層212與側壁子122底部的邊緣接壤，但與側壁子142底部的邊緣之間保持一預定距離。換言之，自對準金屬矽化物層212覆蓋P型源極/汲極摻雜區112的整個表面區域，自對準金屬矽化物層214僅覆蓋P型源極/汲極摻雜區114與側壁子122鄰接部分的表面區域，且自對準金屬矽化物層214與側壁子142的該邊緣相互間隔。同樣地，在浮置閘極(FG)14的相對側上，一自對準金屬矽化物層216，設置在P型源極/汲極摻雜區116上。自對準金屬矽化物層216與側壁子142底部的邊緣保持一預定距離。一自對準金屬矽化物層210位在選擇閘極(SG)12的頂表面上。值得注意的是，浮置閘極(FG)14的頂表面上並未形成金屬矽化物層。
一保護氧化層300，覆蓋於浮置閘極(FG)14上。根據該實施例，該保護氧化層300可包含氧化矽，但不限於此。保護氧化層300覆蓋浮置閘極(FG)14的頂表面、側壁子142的表面、P型源極/汲極摻雜區114的部分表面，以及P型源極/汲極摻雜區116的部分表面。前述自對準金屬矽化物層214及216僅形成在P型源極/汲極摻雜區114及116未被保護氧化層300覆蓋的表面區域上。保護氧化層300預定覆蓋的區域則如第1圖的虛線所標示。
位於P型源極/汲極摻雜區114中且介於側壁子142與自對準矽化物層214之間的非金屬矽化區，以及位於P型源極/汲極摻雜區116中且介於側壁子142與自對準矽化物層216之間的非金屬矽化區可減少缺陷誘發的帶 間穿隧干擾(band to band tunneling disturbance)。
一共形的接觸蝕刻停止層(conformal contact etch stop layer，CESL)312接著形成在保護氧化層300的上方以覆蓋選擇閘極(SG)12、浮置閘極(FG)蓋14，以及自對準金屬矽化物層212、214及216。根據該實施例，共形的接觸蝕刻停止層(CESL)312為一氮化矽層，且可以藉由電漿輔助化學氣相沈積(plasma enhanced chemical vapor deposition，PECVD)製程進行沉積。藉由調整該共形的接觸蝕刻停止層(CESL)312中的矽對氮比例(例如，調整SiH4/NH3在反應槽中的比例)以降低其電子捕阱能力。值得注意的是，由於保護氧化層300的關係，接觸蝕刻停止層(CESL)312並未直接接觸浮置閘極(FG)14或側壁子142。由於保護氧化層300使浮置閘極(FG)14與該接觸蝕刻停止層(CESL)312相互分隔，可有效改善單層多晶矽非揮發性記憶體單元1的資料保存特性。
一層間介電(inter-layer dielectric layer，ILD)層320沉積在接觸蝕刻停止層(CESL)312上。層間介電層320較接觸蝕刻停止層(CESL)312厚，且完全地填充於選擇閘極(SG)12與浮置閘極(FG)14之間的間隙中。若有需要時，可進行一化學機械研磨製程(chemical mechanical polish，CMP)以平坦化層間介電層320的表面。一源線接觸孔321及一位線接觸孔322形成於層間介電層320中。一源線(source line，SL)以及一位線(bit line，BL)可被定義於一第一金屬層(ML1)中，以分別連接源線接觸孔321及位線接觸孔322。
請參照第3圖所示，第3圖為本發明另一實施例的非揮發性記憶體佈局示意圖。如第3圖所示，該記憶體單元的佈局近似於第1圖所示佈局，差別在於額外增設一UV阻擋層400，當非揮發性記憶體作為單次編程(one-time programmable，OTP)記憶體時，可進一步強化其資料保存能力。UV阻擋層400位於記憶體陣列區，至少完全地覆蓋或是直接設置在浮置閘極(FG)14上方。UV阻擋層400可以是任何位於基底100上的介電層中的膜 層，其具有阻擋或分散UV輻射的能力。例如，UV阻擋層400可以是位在鈍化結構的一氮化矽層或者是一冗餘金屬層。前述位在鈍化結構中的該矽氮層可以利用PECVD或是LPCVD方法沉積形成，且可具有大於一預定值的折射率。
請參照第4圖及第5圖所示，第4圖為本發明另一實施例的非揮發性記憶體佈局示意圖。第5圖為第4圖沿著Ⅱ-Ⅱ’切線的剖面示意圖。如第4圖及第5圖所示，同樣地，複數個直線型主動區101沿一第一方向(例如x參考軸)延伸於一半導體基底100中，半導體基底100例如P型矽基底(P-Sub)。藉由數個位於主動區101之間的淺溝絕緣區(STI)102將該些主動區101彼此相互分離。在第4圖中，僅繪示出兩列主動區101。複數條字元線12(例如第4圖的WLx-1及WLx)形成於半導體基底100的主表面上。字元線12沿一第二方向延伸(例如參考y軸)且與主動區101相交，在交會處形成數個選擇電晶體(ST)。各字元線12可作為相對應選擇電晶體的選擇閘極(SG)。為簡化說明，在第4圖中僅繪示兩行字元線12。根據該實施例，該第一方向垂直於該第二方向。
單層多晶矽非揮發性記憶體1a更進一步包含複數個用以儲存電荷的浮置閘極段14，係沿著各主動區101設置，且位於字元線12之間，藉此使兩相鄰字元線12之間僅具有兩浮置閘極段14或兩浮置閘極電晶體(FT)。例如，兩鏡像對稱兩NVM胞：如第4圖及第5圖所示位在主動區101上方同列的C1及C2。NVM胞C1包含一選擇電晶體ST1以及串接於選擇電晶體ST1的一浮置閘極電晶體FT1。同樣地，NVM胞C2包含一選擇電晶體ST2以及串接於選擇電晶體ST2的一浮置閘極電晶體FT2。NVM胞C1及NVM單元C2共用同一位元接觸(BC)區。
如第5圖所示，選擇電晶體ST1包含一選擇閘極(SG)12、一閘極氧化層120介於選擇閘極(SG)12及半導體基底100之間、一側壁子122，位於選擇閘極(SG)12的一側壁上、一P型源極/汲極摻雜區112位於一N 型井(NW)110中、一P型輕摻雜(PLDD)區112a與P型源極/汲極摻雜區112相合併、一P型源極/汲極摻雜區114與P型源極/汲極摻雜區112相間隔，以及一PLDD區114a與P型源極/汲極摻雜區114相合併。在操作時，一P型通道區可形成於PLDD區112a與PLDD區114a之間，且位在選擇閘極(SG)12的下方。浮置閘極電晶體FT1包含一浮置閘極(FG)14、一閘極氧化層140介於浮置閘極(FG)14及該半導體基底100之間、一側壁子142，位於浮置閘極(FG)14的一側壁上、P型源極/汲極摻雜區114、一PLDD區114b與P型源極/汲極摻雜區114相合併、一P型源極/汲極摻雜區116與P型源極/汲極摻雜區114相間隔，以及一PLDD區116a與P型源極/汲極摻雜區116相合併。選擇電晶體ST1與浮置閘極電晶體FT1共用P型源極/汲極摻雜區114。根據該實施例，選擇閘極(SG)12與浮置閘極(FG)14是由單層的多晶矽層所製成，其完全與邏輯製程相容。
一自對準金屬矽化物層212，設置在P型源極/汲極摻雜區112上。自對準金屬矽化物層212延伸至側壁子122底部的邊緣。在選擇閘極(SG)12的相對側上，P型源極/汲極摻雜區114上方並未設置自對準金屬矽化物層。一自對準金屬矽化物層216，設置在P型源極/汲極摻雜區116上。自對準金屬矽化物層216與側壁子142底部的邊緣保持一預定距離。一自對準金屬矽化物層210位在選擇閘極(SG)12的頂表面上。值得注意的是，浮置閘極(FG)14的頂表面上並未形成金屬矽化物層。
一保護氧化層300，覆蓋於浮置閘極(FG)14上。根據該實施例，該保護氧化層300可包含氧化矽，但不限於此。保護氧化層300覆蓋且直接接觸浮置閘極(FG)14的該頂表面、側壁子142的表面、P型源極/汲極摻雜區114的整個表面，以及P型源極/汲極摻雜區的部分表面116。前述自對準金屬矽化物層216僅形成在P型源極/汲極摻雜區116未被保護氧化層300覆蓋的表面區域上。保護氧化層300預定覆蓋的區域則如第4圖的虛線所標示。如該實施例所示，P型源極/汲極摻雜區114完全地被保護氧化層300覆蓋。
一共行的接觸蝕刻停止層(CESL)312接著形成在保護氧化層300的上方以覆蓋選擇閘極(SG)12、浮置閘極(FG)14，以及自對準金屬矽化物層212及216。根據該實施例，共形的接觸蝕刻停止層(CESL)312為一矽氮層且可以電漿輔助化學氣相沈積(PECVD)製程進行沉積。藉由調整該共形的接觸蝕刻停止層(CESL)312中的矽對氮比例(例如，調整SiH4/NH3在反應槽中的比例)以降低其電子捕阱能力。可以理解的是，共形的接觸蝕刻停止層(CESL)312可以是任何具有降低電子陷阱能力的材質，且並不以前述舉例為限。需注意的是，由於保護氧化層300的關係，接觸蝕刻停止層(CESL)312並未直接接觸浮置閘極(FG)14或側壁子142。藉由以保護氧化層300使浮置閘極(FG)14與該接觸蝕刻停止層(CESL)312相互分隔之手段，可有效改善單層多晶矽非揮發性記憶體單元1a的資料保存功能。
一層間介電(ILD)層320是沉積在接觸蝕刻停止層(CESL)312上。層間介電層320較接觸蝕刻停止層(CESL)312厚，且完全地填充於選擇閘極(SG)12與浮置閘極(FG)14之間的間隙中。若有需要時，可進行一化學機械研磨製程(CMP)以平坦化層間介電層320的表面。一源線接觸孔321及一位線接觸孔322形成於層間介電層320中，以分別電性連接P型源極/汲極摻雜區112及P型源極/汲極摻雜區116。一源線(SL)以及一位線(BL)可被定義於第一金屬層(ML1)中，以分別連接源線接觸孔321及位線接觸孔322。
請參照第6圖及第7圖所示，第6圖及第7圖例示其他實施例的單層多晶矽非揮發性記憶體單元的剖面圖，其與高壓製程相容。如第6圖所示，單層多晶矽非揮發性記憶體1c包含一深N型井(deep N well，DNW)610，增設於N型井110的下方。根據該實施例，N型井110可以是一中壓N型井(medium-voltage N well，MVNW)。一高壓P型井(high-voltage N well，HVNW)612形成於半導體基底100中，且與深N型井610相合併。高壓P型井(HVNW)612是透過一STI區620而與單層多晶矽非揮發性記憶體單 元分隔開。
如第7圖所示，單層多晶矽非揮發性記憶體1d與第6圖的單層多晶矽非揮發性記憶體1c差異在於一N型障壁層(N-type buried layer，NBL)712係設置在一高壓N型井(HVNW)612的下方。一高壓P型井(HVPW)710是形成於N型障壁層712與中壓N型井110之間。
第8圖例示本發明另一實施例的記憶體佈局示意圖。如第8圖所示，其繪示一種多次編程(multiple time programmable，MTP)記憶體範例。多次編程(MTP)記憶體的浮置閘極(FG)可延伸於一第二方向(例如參考y軸)以電容耦接相鄰的主動區101’及101”，藉此分別形成一控制閘極(control gate，CG)區以及一抹除閘極(erase gate，EG)區。同樣地，保護氧化層300，完全地覆蓋於浮置閘極(FG)14上、控制閘極(CG)區，以及抹除閘極(EG)區。前述延伸裝置可以是一N型金氧半場效電晶體(NMOSFET)、P型金氧半場效電晶體(PMOSFET)、N型金氧半電容(N-type MOS capacitor)或P型金氧半電容(P-type MOS capacitor)。將前述浮置閘極(FG)、控制閘極(CG)區，以及抹除閘極(EG)區沿同一條浮置多晶矽聯帶(floating poly strip)設置，可利用前述技術改善電荷保存能力。
第9圖例示製作單層多晶矽非揮發性記憶體的主要階段的步驟流程。如第9圖所示，在步驟91中，在半導體基底形成數個STI區及數個主動區。之後，進行井摻雜，以在該半導體基底形成井結構。在步驟92中，一多晶矽層是被沉積且圖案化，以形成單層多晶矽浮置閘極。在步驟93中，在閘極的側壁上形成數個側壁子。在步驟94中，在記憶體陣列中的該單層多晶矽浮置閘極的上方形成一保護氧化層。在步驟95中，在源極/汲極區的上方形成一矽化金屬層。在步驟96中，接著沉積一接觸蝕刻停止層。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧單層多晶矽非揮發性記憶體
101‧‧‧主動區
102‧‧‧淺溝絕緣區
12‧‧‧字元線
14‧‧‧浮置閘極段
212、214、216‧‧‧自對準金屬矽化物層
300‧‧‧保護氧化層
BC‧‧‧位元接觸區
FG‧‧‧浮置閘極
WLx-1、WLx‧‧‧字元線

Claims (20)

  1. 一種單層多晶矽非揮發性記憶體單元，包含：一選擇電晶體，位於一半導體基底的一第一井上，其中該選擇電晶體包含一選擇閘極、一第一閘極氧化層介於該選擇閘極及該半導體基底之間、一第一源極/汲極摻雜區位於該第一井中，以及一第二源極/汲極摻雜區係與該第一源極/汲極摻雜區相間隔；一浮置閘極電晶體，位於該第一井上且串接該選擇電晶體，其中該浮置閘極電晶體包含一浮置閘極、一第二閘極氧化層介於該浮置閘極及該半導體基底之間、與該選擇電晶體共用的該第二源極/汲極摻雜區，以及一第三源極/汲極摻雜區係與該第二源極/汲極摻雜區相間隔；一第一金屬矽化物層，位於該第一源極/汲極摻雜區上；一保護氧化層，覆蓋並且直接接觸該浮置閘極的一頂表面、該第二源極/汲極摻雜區的整個表面，以及該第三源極/汲極摻雜區的一部分；以及一接觸蝕刻停止層，位於該保護氧化層上，藉由該保護氧化層使該浮置閘極與該接觸蝕刻停止層相互分隔。
  2. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中更包含一第一側壁子，位於該選擇閘極的任一側壁上，以及一第二側壁子，位於該浮置閘極的任一側壁上。
  3. 如申請專利範圍第2項所述之單層多晶矽非揮發性記憶體單元，其中該第一金屬矽化物層係延伸至該第一側壁子底部的邊緣。
  4. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中更包含一第二金屬矽化物層，位於該第三源極/汲極摻雜區上，其中，該第二 金屬矽化物層與該第二側壁子底部的邊緣保持一預定距離。
  5. 如申請專利範圍第4項所述之單層多晶矽非揮發性記憶體單元，其中更包含一第三金屬矽化物層，位於該選擇閘極的一頂表面上。
  6. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中該浮置閘極的一頂表面上未形成一金屬矽化物層。
  7. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中更包含一層間介電層，位於該接觸蝕刻停止層上面。
  8. 如申請專利範圍第7項所述之單層多晶矽非揮發性記憶體單元，其中更包含一源線接觸孔及位線接觸孔，位於該層間介電層中以分別電連接該第一源極/汲極摻雜區及該第三源極/汲極摻雜區。
  9. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中該保護氧化層為一矽氧層。
  10. 如申請專利範圍第2項所述之單層多晶矽非揮發性記憶體單元，其中該保護氧化層還覆蓋該第二側壁子的表面。
  11. 如申請專利範圍第4項所述之單層多晶矽非揮發性記憶體單元，其中該第二金屬矽化物層僅形成在該第三源極/汲極摻雜區未被該保護氧化層覆蓋的表面區域上。
  12. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中更包含一UV阻擋層，完全覆蓋或直接設置在該浮置閘極的上方。
  13. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中更包含一深N井區，設置在該第一井的下方。
  14. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中該第一井是一中壓N型井。
  15. 如申請專利範圍第14項所述之單層多晶矽非揮發性記憶體單元，其中更包含一高壓P型井，設置在該中壓N型井的下方，且一N型障壁層係設置在該高壓P型井的下方。
  16. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中該第二閘極氧化層較該第一閘極氧化層厚。
  17. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中該浮置閘極可延伸至與一抹除閘極區電容耦合。
  18. 如申請專利範圍第17項所述之單層多晶矽非揮發性記憶體單元，其中該保護氧化層更完全地覆蓋該抹除閘極區。
  19. 如申請專利範圍第1項所述之單層多晶矽非揮發性記憶體單元，其中，該浮置閘極更電容耦合至一控制閘極區及一抹除閘極區。
  20. 如申請專利範圍第19項所述之單層多晶矽非揮發性記憶體單元，其中該保護氧化層更完全地覆蓋該控制閘極區及該抹除閘極區。
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