1306256 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種NAND型快閃記憶體元件（nand以让 memory device)之寫入及讀取方法（pr〇gram and “以 methods)及用以執行該寫入及該讀取方法之頁緩衝器（㈣。 buffer)，尤指一種應用於一多層次胞（咖出七⑽-“⑴ NAND型快閃記憶體元件之寫入及讀取方法及用以執行該 寫入方法之頁緩衝器。 【先前技術】 在一傳統NAND型快問記憶體中，每一記憶胞可儲存兩 種資料狀態，意即可儲存「開」狀態（”〇N" state)或「關」 狀悲（OFF state)。資訊的每一位元（bh)係由個別的記憶胞 之「開」、「關」狀態所定義。在傳統NAND型快閃記憶體中， 為了能儲存N個位元資料（N為大於或等於2之整數），必須使 用N個個別的§己憶胞。因此，若是使用傳統型快閃記 憶體，當所要儲存的資料位元個數增加時，記憶胞的個數 也必須跟著增加。儲存在單一位元（〇ne_bit)記憶胞之資訊係 決疋於一 5己憶胞之寫入狀態（pr〇grammed status)，而該資料 係利用寫入（program)動作儲存至該記憶胞。存有記憶胞狀 悲之資訊係由一位於該記憶胞中之電晶體之門檻電壓 (threshold voltage)所決定。門檻電壓係施予在該電晶體之 閘極及源極間，可將該電晶體導通（turn 〇n)之最小電壓。 為了增加儲存容量而不增加記憶胞之數目，儲存在每一 記憶胞之資訊可被增加至超過兩個狀態，而非僅上述的 109329.doc 1306256 開」及關」兩個狀態。如此一個「多狀態」或「多層 次胞」可以儲存超過一位元（onebit)的資訊。目前最常使用 的多層次胞結構係在一個記憶胞中儲存二位元（tw〇以⑷的 資訊’其中係有四個可區別的不同狀態（four distinctly different states)需要被定義，而通常係利用以下將敍述的門 檻電壓加以定義。 圖U’、員示根據所寫入的資料，一記憶胞之四種門植電壓分 佈圖。如圖1所示，所寫入的資料可以以下四種電壓分佈之 一來表示：（1)小於-2.0V之門檻電壓分佈，係代表（11)之二 位元資料；（2)介於〇.3V及〇.7V之門檻電壓分佈，係代表（1〇) 之二位元資料；（3)介於1.3V及1.7V之門檻電壓分佈，係代 表（01)之二位元資料及（4)介於2.3V及2.7V之門檻電壓分 佈，係代表（00)之二位元資料。資料可基於上述四種不同門 檻電壓分佈而儲存於一記憶胞中。 圖2係應用在一 NAND型快閃記憶體中之記憶胞陣列 20(memory cell array)中之二記憶胞串（string)示意圖，其中 每一記憶胞10係儲存二位元資訊。該記憶胞陣列2〇包含串 接於一位元線BL1或BL2 (bit line)及一地選擇線 GSL(ground select line)之間之複數個記憶胞1〇。一組與位 元線（BL1或 BL2)、串選擇電晶體ssT(string select transistor) 及地選擇電晶體GST(ground select transistor)相串接之記 憶胞10稱為記憶胞串’其中該串選擇電晶體SST及該地選擇 電晶體GST係用以選定用來進行寫入之記憶胞1〇，而串選 擇電晶體SST之導通（turn on)或關閉（turn off)則由一串選擇 109329.doc 1306256 線SSL(string select line)之狀態所決定。該串選擇電晶體 SST被選擇性地切換以耦合相關的記憶胞串及位元線；該地 選擇電晶體GST則被選擇性地切換每一記憶胞串及一共源 線 CSL(common source line)之間之電連接（eiectrical connection)。每一字元線WL1〜WL16橫向連結相應記憶胞 10之閘極，係施加一適當電位以進行寫入、讀取或確認之 操作。 關於應用於一多層次胞NAND型快閃記憶體之寫入及讀 取方法已有一些方法被提出，將於下文陸續介紹。美國專 利公開號US2005/0018488(合併作為參考資料，以下稱，488) 揭示一種以兩頁資料寫入記憶胞的方法。首先，第一頁之 資料係被寫入記憶胞之最低有效位元（Least Significant Bit . LSB);之後，第二頁之資料係寫入記憶胞之最高有效 位元（Most Significant Bit : MSB)。圖3係顯示，488中之寫入 方法中之記憶胞狀態轉換示意圖。參圖3，首先於第一頁寫 入操作時，記憶胞之最低有效位元係由（1丨）狀態被寫入 (programmed)至（11)狀態或（1 〇)狀態（以箭號a表示）。接著， 於第二頁寫入操作時，記憶胞之最高有效位元被寫入。於 寫入最高有效位元時，處於（11)狀態之記憶胞將被寫入至 (11)狀態或（01)狀態（以箭號B1表示）；處於（1〇)狀態之記憶 胞將被寫入至（00)狀態（以箭號B2表示）^以箭號]81及]52表 示之最南有效位元之寫入操作係同時進行。進行箭號Μ所 示之寫入操作時，位元線電壓位準係為〇v;然而，進行箭 號B2所示之寫入操作時，位元線電壓位準係可調整介於一 109329.doc 1306256 接地電位（即ον)及一電源電位（例vcc)之間，係用以減緩箭 號B2所示寫入操作之速度，以配合箭號B1所示之寫入操 作。'488同時揭示一種記憶胞讀取方法，其包含一兩階段式 最低有效位元讀取（two-phase LSB read)及 --階段式最高 有效位元讀取（one-phase MSB read)。該兩階段式最低有效 位元讀取又包含一 LSB1讀取及一 LSB2讀取。於該LSB1讀 取期間、該LSB2讀取期間及該一階段式最高有效位元讀取 期間’選定字元線（selected word line)係分別被施予電壓 Vrd3’ Vrcjl，及 Vrd2 ’ 其中 VrU > Vrcj2 > Vrdl(參圖 3)。 美國專利US 6,937,510(合併作為參考資料，以下稱，51〇) 亦揭示一種以兩頁資料寫入記憶胞的方法。圖4顯示一記憶 胞可能具有的4種狀態，（0)、（1)、（2)及（3)狀態，其係顯 示於’510中所揭示之寫入操作中之記憶胞狀態轉換圖。圖4 中之門檻電壓分佈係與圖3之門檻電壓分佈相同。參圖4, 於第一頁寫入操作時，記憶胞之最低有效位元係由（〇)狀態 被寫入至（0)或（1)狀態（以箭號c表示）；於第二頁寫入操作 時，記憶胞之最高有效位元則被寫入。於最高有效位元之 寫入操作時’處於（0)狀態之記憶胞係被寫入至（〇)或（2)狀態 (以箭號D1表示）；處於⑴狀態之記憶胞係被寫入至⑴或⑺ 狀態（以箭號D2表示）。以箭號〇1及〇2表示之最高有效位元 之寫入操作係同時進行。進行箭號D2所示之寫入操作時， 位元線電Μ位準係為〇V;然而，進行箭號叫所示之寫入操 作時’位元線電壓位準係可調整介於__接地電位（即〇v)及 -電源電位（例Vcc)之間，係用以減緩箭號叫所示寫入操作 109329.doc -9. 1306256 之速度’以配合箭號D2所示之寫入操作。·51〇同時揭示一 種記憶胞讀取方法，其使用一三階段讀取（three_phase read) 並施加電壓vrd3，vrd2,及vrdl於選定字元線（selected w〇rd line)上以分別區別（0)、（1)、（2)及（3)四種不同狀態之記憶 胞’其中其中Vrd3 > Vrd2 > Vrdl(參圖4) 0 【發明内容】 本發明之第一目的係提供一種多層次胞1306256 IX. Description of the Invention: [Technical Field] The present invention relates to a NAND type flash memory component (nand for memory device) writing and reading method (pr〇gram and "methods") A page buffer ((4). buffer) for performing the writing and the reading method, especially for writing and reading a multi-layer cell (Cake Seven (10)-"(1) NAND type flash memory device The method and the page buffer for executing the writing method. [Prior Art] In a conventional NAND type fast memory, each memory cell can store two data states, meaning that the "on" state can be stored (" 〇N" state) or "OFF". Each bit (bh) of information is defined by the "on" and "off" states of individual memory cells. In traditional NAND flash memory In the body, in order to store N bit data (N is an integer greater than or equal to 2), N individual § cells must be used. Therefore, if using conventional flash memory, when the data bit to be stored When the number of elements increases, the number of memory cells must also follow The information stored in a single bit (〇ne_bit) memory cell is determined by a pr〇grammed status, and the data is stored into the program by a program action. Memory cell. The information of memory cell sorrow is determined by the threshold voltage of a transistor located in the memory cell. The threshold voltage is applied between the gate and the source of the transistor. The minimum voltage at which the transistor is turned on. In order to increase the storage capacity without increasing the number of memory cells, the information stored in each memory cell can be increased to more than two states, instead of only the above 109329. Doc 1306256 "On" and "Off" states. Such a "multi-state" or "multi-level cell" can store more than one bit (onebit) of information. The most commonly used multi-level cell structure is in a memory cell. The storage of two bits (twf (4) of information 'four distinctly different states' needs to be defined, and is usually defined by the threshold voltages described below. U', the member shows the four gate voltage distribution maps of a memory cell according to the written data. As shown in Figure 1, the written data can be expressed by one of the following four voltage distributions: (1) less than -2.0V threshold voltage distribution, representing the two-dimensional data of (11); (2) threshold voltage distribution between 〇.3V and 〇.7V, representing the two-dimensional data of (1〇); (3) The threshold voltage distribution between 1.3V and 1.7V represents the two-bit data of (01) and (4) the threshold voltage distribution between 2.3V and 2.7V, which represents the two-dimensional data of (00). The data can be stored in a memory cell based on the four different threshold voltage distributions described above. 2 is a schematic diagram of two memory strings used in a memory cell array in a NAND type flash memory, wherein each memory cell 10 stores binary information. The memory cell array 2 includes a plurality of memory cells 1 串 connected in series between a bit line BL1 or BL2 (bit line) and a ground select line (GSL). A set of memory cells 10 connected in series with a bit line (BL1 or BL2), a string select transistor, and a ground select transistor (GST) is called a memory string. The transistor SST and the ground selection transistor GST are used to select the memory cell for writing, and the turn-on or turn-off of the string selection transistor SST is selected by a string 109329. Doc 1306256 Determined by the state of the line SSL (string select line). The string selection transistor SST is selectively switched to couple the associated memory cell string and bit line; the ground selection transistor GST is selectively switched between each memory cell string and a common source line CSL (common source line) Electrical connection between them. Each of the word lines WL1 WL WL16 is laterally coupled to the gate of the corresponding memory cell 10, and an appropriate potential is applied for writing, reading or confirming. There have been some methods for writing and reading methods applied to a multi-layer cell NAND type flash memory, which will be introduced later. U.S. Patent Publication No. US2005/0018488 (incorporated by reference, hereinafter referred to as 488) discloses a method of writing two-page data into memory cells. First, the first page of data is written to the Least Significant Bit (LSB) of the memory cell; after that, the second page of data is written to the most significant bit of the memory cell (Most Significant Bit: MSB) . Fig. 3 is a diagram showing the state transition of the memory cell in the writing method in 488. Referring to Figure 3, first in the first page write operation, the least significant bit of the memory cell is programmed (1) state to (11) state or (1 〇) state (with arrow a Express). Then, at the second page write operation, the most significant bit of the memory cell is written. When the most significant bit is written, the memory cell in the (11) state will be written to the (11) state or the (01) state (indicated by the arrow B1); the memory cell in the (1〇) state will be The write operation to the (00) state (indicated by the arrow B2) ^ the write operation of the most south effective bit indicated by the arrows 81 and 52 is performed simultaneously. When performing the write operation shown by the arrow Μ, the bit line voltage level is 〇v; however, when the write operation indicated by the arrow B2 is performed, the bit line voltage level can be adjusted between one and 109329. .doc 1306256 The ground potential (ie ον) and a power supply potential (eg vcc) are used to slow down the write operation indicated by arrow B2 to match the write operation indicated by arrow B1. '488 also discloses a memory cell reading method that includes a two-phase LSB read and a one-phase MSB read. The two-stage least significant bit read further includes an LSB1 read and an LSB2 read. During the LSB1 reading period, the LSB2 reading period, and the one-stage most significant bit reading period, the selected word lines are respectively applied with voltages Vrd3' Vrcjl, and Vrd2 'where VrU > ; Vrcj2 > Vrdl (see Figure 3). U.S. Pat. 4 shows four states (0), (1), (2), and (3) states that a memory cell may have, which is a memory cell state transition diagram shown in the write operation disclosed in '510. . The threshold voltage distribution in Figure 4 is the same as the threshold voltage distribution in Figure 3. Referring to FIG. 4, during the first page write operation, the least significant bit of the memory cell is written to the (0) or (1) state (indicated by the arrow c) by the (〇) state; At the time of the write operation, the most significant bit of the memory cell is written. In the write operation of the most significant bit, the memory cell in the (0) state is written to the (〇) or (2) state (indicated by the arrow D1); the memory cell in the (1) state is written. To the (1) or (7) state (indicated by the arrow D2). The writing operations of the most significant bits indicated by arrows 〇1 and 〇2 are simultaneously performed. When the write operation indicated by arrow D2 is performed, the bit line power level is 〇V; however, when the arrow is called the write operation, the bit line voltage level can be adjusted between _ _ ground potential (ie 〇v) and - power supply potential (example Vcc), used to slow down the arrow called write operation 109329.doc -9. 1306256 speed 'to match the arrow D2 Into the operation. 51〇 also discloses a memory cell reading method that uses a three-phase read (three_phase read) and applies voltages vrd3, vrd2, and vrdl on the selected word line (selected w〇rd line) to distinguish (0 , (1), (2), and (3) memory cells of four different states, wherein Vrd3 > Vrd2 > Vrdl (see Fig. 4) 0 [Summary] The first object of the present invention is to provide a multi-layer Hierarchical cell
(multi-level-cell)NAND型快閃記憶體元件之寫入方法，係 先寫入記憶胞之最高有效位元，再寫入寫入記憶胞之最低 有效位元，藉以減少寫入時間（pr〇gramming time)。 本發明之第二目的提供一種多層次胞NAND型快閃記憶 體元件之讀取方法’藉由執行—三階段最低有效位元讀取 (three-phase LSB read)及一 一階段最高有效位元讀取 (嶋-phase MSB read)，以減少讀取時間（reading Ume)。 本發明之第二目的係提供一種頁緩衝區（pagebuf㈣用 以實施該寫入及讀取方法，以減少寫入及讀取之時間。 為達上述之目的，本發明揭示一種NAND型快閃記憶體 元件之寫入讀取方法及一種用以實施該寫入及讀取方法之 頁緩衝區。本發明揭示之寫人方法係應用在—包含複數個 零記憶胞、複數個第一記憶胞、複數個第二記憶胞及複數 個第三記憶胞之NAND型快閃記憶體元件。該寫入方法包含 以下步驟：⑷將該零記憶胞、該第—記憶胞、該第二記憶 胞及該第三記憶胞寫人至_零狀態；⑻藉由切換該第二記 憶胞之最高有效位元將該第二記憶胞自該零狀態寫入至一 109329.doc •10, 1306256 i · 第二狀態；以及（C)藉由切換該第一記憶胞之最低有效位元 將該第一記憶胞自該零狀態寫入至一第一狀態，同時藉由 切換該第三記憶胞之最低有效位元將該第三記憶胞自該第 一狀態寫入至一第三狀態。其中每該記憶胞均搭配一第一 栓鎖電路及一第二栓鎖電路。 本發明揭示之讀取方法係應用在一包含複數個零記憶 胞、複數個第一記憶胞、複數個第二記憶胞及複數個第三 記憶胞之NAND型快閃記憶體元件。該讀取方法包含以下步 驟：（a)藉由施加一第一確認訊號及一第二確認訊號至該第 一栓鎖電路以讀取該零記憶胞、該第一記憶胞、該第二記 憶胞及a亥第二g己憶胞之最咼有效位元；以及（b)藉由施加該 第一確認訊號至一第一栓鎖電路及施加一第三確認訊號至 該一二栓鎖電路以讀取該零記憶胞、該第一記憶胞、該第 一 S己憶胞及該第三記憶胞之最低有效位元。其中每該記憶 胞均搭配一第一栓鎖電路及一第二栓鎖電路。 注意本文所述之零記憶胞、第一記憶胞、第二記憶胞及 第三記憶胞係分別代表預定被寫入至（11)狀態、（10)狀 態、（01)狀態及（00)狀態之記憶胞。 本發明同時揭示一種頁緩衝區，係應用在一包含複數個 記憶胞之NAND型快問記憶體元件以實施本發明之寫入及 讀取方法。該頁緩衝區包含：一第一栓鎖電路、一第二栓 鎖電路、一位元線電源電路、一輸入電路及一預充電路 (precharge circuit)。該第一栓鎖電路係藉由一第一確認訊 號及一第二確認訊號以確認該記憶胞《該第二栓鎖電路係 109329.doc -11- 1306256 藉由一第三確認訊號以讀取該記憶胞之最低有效位元。該 位元線電源電路係提供一位元線電源至一選定位元線 (selected bit line)，其中該選定字元線係搭配預定寫入之記 憶胞。該輸入電路係接收預定寫入之資料（information to be programmed)至該記憶胞。該預充電路係預充（precharge)該 選定位元線。 【實施方式】 圖5係本發明一實施例之頁緩衝區5之電路示意圖。該頁 ® 缓衝區5包含第一栓鎖電路5 1、第二栓鎖電路52、位元線電 源電路53、輸入電路55、預充電路56及位元線選擇電路54。 位元線選擇電路54係用以決定選定位元線及遮藪位元線。 〜 第一栓鎖電路5丨及第二栓鎖電路52分別包含一栓鎖511及 521 ° 圖6係本發明之兩頁式寫入方法（tw〇_page method)之記憶胞狀態轉換示意圖。於本實施例中，施加在 φ 選定字兀線之讀取電壓（read voltage)Vrdl，Vw及Vrd3可分 別設定為0V、IV及2V ;而施加在選定字元線之寫入電壓 (program voltage)PGMVT0、PGMVT1 及 PGMVT2 可分別設 疋為 0.3V、1.3V及 2.3V，其中寫入電壓 pGMVT()、pGMVT1 及PGMVT2又可分別稱為第一寫入電壓、第二寫入電壓及 第三寫入電壓。此外，零狀態、第一狀態、第二狀態及第 二狀態係分別表不圖6中之（1”、（1〇)、（〇1)及（〇〇)狀態；且 零記憶胞、第-記憶胞、第二記憶胞及第三記憶胞係分別 代表將被寫入至零狀態、第一狀態、第二狀態及第三狀態 109329.doc •12- 1306256 之記憶胞。 同時參考圖5及圖6。於第一頁寫入操作（first page operation)時（意即由圊6中箭號E所表不的最南有效位元寫 入操作），該第一栓鎖電路5 1中之節點C及D以及該第二栓鎖 電路52中之節點B及A在資料輸入之前’係分別設定在低位 準、高位準、高位準及低位準。處於低位準之節點A係觸發 訊號RESET2以導通NM0S電晶體T17 ;處於低位準之節點C 係觸發訊號PLOAD至低位準以導通PM0S電晶體T1 ’同時 觸發一第一確認訊號S 11以導通NM0S電晶體T4。藉此，節 點SO將被拉至一高位準（即Vcc)且NMOS電晶體T5、T3及T4 被導通以將節點C拉至低位準。在資料輸入期間，訊號ENDI 一直保持在高位準。若輸入資料為「〇」（即低位準，此時 訊號ENI則為高位準），NM0S電晶體T20及T21被導通，使 得節點D及C分別處於低位準及高位準。若輸入資料為「1」 (即高位準，此時訊號ENI則為低位準），NMOS電晶體T20 被關閉（turn off)，使得節點C處於低位準。之後’訊號VBL1 及VBL2被分別設定至低位準及高位準，以導通PM0S電晶 體T9及NMOS電晶體T12。在最高有效位元寫入操作期間， 若輸入資料為「〇 J，將導致節點C處於高位準且NMOS電晶 體T10、T11及T12均被導通。因此在最高有效位元寫入操作 期間，節點SO將被拉至一位元線電源BLPWR，此時該位元 線電源BLPWR係一接地電位Vss(ground voltage)。節點SO 係藉由導通NMOS電晶體T22以電連接位元線BLE，使得位 109329.doc •13- 1306256 元線BLE處於該接地電位Vss;藉此即可進行寫入操作。注 意此時另一條位元線BLO係接地，以作為—遮蔽位元線 (shielding bit line)。然而，若輸入資料為「丨」，將導致節 點C處於低位準且PMOS電晶體T8及T9將被導通.接著，節 點SO將被拉至一電源電位vee(source voltage)，使得位元線 BLE也處於該電源電位Vec ;藉此禁止寫入操作之進行。注 意’第二記憶胞之最尚有效位元、第一記憶胞之最低有效 位元及第二記憶胞之最低有效位元係由高位準切換至低位 準。 圖7係選定字元線電壓SWLV、第一確認訊號S1丨及節點c 之狀態於最高有效位元寫入操作之時序圖，該時序圖包含 二寫入期間（MP1及MP2)及二確認期間（MV1及MV2)。在 MP1期間，一寫入電壓PGMV(例如19V，其係大於圖6中之 PGMVT0、PGMVT1及PGMVT2)被施加在一與被存取記憶 胞（accessed memory cells)搭配之選定字元線，其中該被存 取記憶胞之最高有效位元係預定被寫入。於Μ V1及M V2期 間’寫入電壓PGMVT1 (例1.3 V)被施加在選定字元線上且第 一確認訊號S11被觸發以感測存取記憶胞之狀態。在MV1 期間’節點C維持在高位準意謂著最高有效位元寫入操作尚 未完成。因此，寫入操作在MP2期間内持續進行。在MV2 期間’存取記憶胞之門檻電壓達到目標值（即最高有效位元 寫入操作已完成）且節點C在第一確認訊號S 11被觸發時由 高位準切換至低位準。當（01)狀態達到時（即（11)狀態之最 109329.doc • 14- 1306256(multi-level-cell) NAND-type flash memory device writing method, which is first written to the most significant bit of the memory cell, and then written to the least significant bit of the memory cell, thereby reducing the write time ( Pr〇gramming time). A second object of the present invention is to provide a method for reading a multi-layer cell NAND type flash memory device by performing a three-phase LSB read and a one-stage most significant bit. Read (嶋-phase MSB read) to reduce the reading time (reading Ume). A second object of the present invention is to provide a page buffer (pagebuf (4) for implementing the writing and reading method to reduce the writing and reading time. To achieve the above purpose, the present invention discloses a NAND type flash memory. a method for writing and reading a body element and a page buffer for implementing the writing and reading method. The method for writing a person disclosed in the present invention is applied to include a plurality of zero memory cells, a plurality of first memory cells, a plurality of NAND type flash memory elements of the second memory cell and the plurality of third memory cells. The writing method comprises the following steps: (4) the zero memory cell, the first memory cell, the second memory cell, and the The third memory cell writes the _zero state; (8) writes the second memory cell from the zero state to a 109329.doc •10, 1306256 i · second by switching the most significant bit of the second memory cell And (C) writing the first memory cell from the zero state to a first state by switching the least significant bit of the first memory cell while switching the least significant bit of the third memory cell The third memory cell from the first The state is written to a third state, wherein each of the memory cells is coupled with a first latch circuit and a second latch circuit. The reading method disclosed in the present invention is applied to a plurality of zero memory cells and a plurality of a NAND flash memory component of the first memory cell, the plurality of second memory cells, and the plurality of third memory cells. The reading method comprises the steps of: (a) applying a first confirmation signal and a second Confirming a signal to the first latch circuit to read the zero memory cell, the first memory cell, the second memory cell, and the last significant bit of the second cell; and (b) Applying the first confirmation signal to a first latch circuit and applying a third acknowledge signal to the one or two latch circuits to read the zero memory cell, the first memory cell, the first S memory cell, and the The least significant bit of the third memory cell, wherein each of the memory cells is matched with a first latch circuit and a second latch circuit. Note that the zero memory cell, the first memory cell, the second memory cell and The third memory cell system respectively represents a predetermined write to the (11) state, (10) a memory cell of a state, a (01) state, and a (00) state. The present invention also discloses a page buffer applied to a NAND-type fast memory device element including a plurality of memory cells to implement the writing of the present invention. The page buffer includes: a first latch circuit, a second latch circuit, a bit line power circuit, an input circuit, and a precharge circuit. The first latch circuit Determining the memory cell by using a first acknowledgement signal and a second acknowledgement signal. The second latch circuit is 109329.doc -11- 1306256. The third valid signal is used to read the least effective memory cell. The bit line power supply circuit provides a bit line power supply to a selected bit line, wherein the selected word line is matched with a predetermined written memory cell. The input circuit receives an information to be programmed to the memory cell. The precharge path precharges the selected location line. [Embodiment] FIG. 5 is a circuit diagram of a page buffer 5 according to an embodiment of the present invention. The page ® buffer 5 includes a first latch circuit 51, a second latch circuit 52, a bit line power circuit 53, an input circuit 55, a precharge path 56, and a bit line selection circuit 54. The bit line selection circuit 54 is used to determine the selected bit line and the conceal bit line. The first latch circuit 5A and the second latch circuit 52 respectively include a latch 511 and 521 °. FIG. 6 is a schematic diagram of the memory cell state transition of the two-page writing method (tw〇_page method) of the present invention. In the present embodiment, the read voltages Vrd1, Vw, and Vrd3 applied to the selected word line of φ can be set to 0V, IV, and 2V, respectively; and the write voltage applied to the selected word line (program voltage) PGMVT0, PGMMV1, and PGMVT2 can be set to 0.3V, 1.3V, and 2.3V, respectively. The write voltages pGMVT(), pGMVT1, and PGMVT2 can be referred to as the first write voltage, the second write voltage, and the third, respectively. Write voltage. In addition, the zero state, the first state, the second state, and the second state respectively indicate the (1", (1〇), (〇1), and (〇〇) states in FIG. 6; and the zero memory cell, the first - the memory cell, the second memory cell, and the third memory cell represent memory cells to be written to the zero state, the first state, the second state, and the third state 109329.doc • 12-1306256, respectively. And Figure 6. In the first page operation (meaning the most south significant bit write operation indicated by the arrow E in 圊6), the first latch circuit 5 1 Nodes C and D and nodes B and A in the second latch circuit 52 are respectively set to low level, high level, high level and low level before data input. Node A is triggered signal RESET2 at low level. To turn on the NM0S transistor T17; the node C at the low level triggers the signal PLOAD to the low level to turn on the PM0S transistor T1' while triggering a first acknowledge signal S11 to turn on the NM0S transistor T4. Thereby, the node SO will be Pulled to a high level (ie Vcc) and NMOS transistors T5, T3 and T4 are turned on to pull node C Low level. During data input, the signal ENDI remains at a high level. If the input data is “〇” (ie, the low level, the signal ENI is high), the NM0S transistors T20 and T21 are turned on, making node D And C are at a low level and a high level respectively. If the input data is "1" (ie, the high level, the signal ENI is low), the NMOS transistor T20 is turned off, so that the node C is at a low level. After that, the signals VBL1 and VBL2 are respectively set to the low level and the high level to turn on the PM0S transistor T9 and the NMOS transistor T12. During the most significant bit write operation, if the input data is "〇J, the node C will be caused. At the high level and the NMOS transistors T10, T11 and T12 are all turned on. Therefore, during the most significant bit write operation, the node SO will be pulled to the one-bit line power supply BLPWR, at which time the bit line power supply BLPWR is one. Grounding potential Vss (ground voltage). The node SO is electrically connected to the bit line BLE by turning on the NMOS transistor T22, so that the bit 109329.doc • 13 - 1306256 element line BLE is at the ground potential Vss; Into the operation. Note It is intended that the other bit line BLO is grounded as a shielding bit line. However, if the input data is "丨", node C will be at a low level and PMOS transistors T8 and T9 will Turned on. Next, the node SO will be pulled to a power supply potential vee (source voltage) such that the bit line BLE is also at the power supply potential Vec; thereby prohibiting the writing operation from proceeding. Note that the most significant bit of the second memory cell, the least significant bit of the first memory cell, and the least significant bit of the second memory cell are switched from the high level to the low level. 7 is a timing diagram of the state of the selected word line voltage SWLV, the first acknowledge signal S1丨, and the node c in the most significant bit write operation, the timing diagram including two write periods (MP1 and MP2) and two acknowledge periods (MV1 and MV2). During MP1, a write voltage PGMV (eg, 19V, which is greater than PGMVT0, PGMMV1, and PGMVT2 in FIG. 6) is applied to a selected word line collocated with the accessed memory cells, where The most significant bit of the accessed memory cell is scheduled to be written. During the V1 and M V2 periods, the write voltage PGMMV1 (example 1.3 V) is applied to the selected word line and the first acknowledge signal S11 is triggered to sense the state of accessing the memory cell. During MV1, node C is maintained at a high level, meaning that the most significant bit write operation has not yet completed. Therefore, the write operation continues during the MP2 period. During the MV2 period, the threshold voltage of the access memory cell reaches the target value (i.e., the most significant bit write operation has been completed) and the node C switches from the high level to the low level when the first acknowledge signal S 11 is triggered. When the (01) state is reached (ie, the (11) state is the most 109329.doc • 14-1306256
馬有效位元「丨」切換至（G1)之最高有效位元之 點so將被保持在高位準且節點c將被設定至低位準。PThe point "so" at which the horse valid bit "丨" switches to the most significant bit of (G1) will be held at the high level and the node c will be set to the low level. P
於第二頁寫入操作（即最低有效位元之寫入操作）時’係 使用與在最高有效位元之寫入操作時相同之字元線或存取 錢胞。參考圖5及圖6,節點A、B、QD之啟始狀態盘最 :有效位元“操作時相同。在資料輸人期間，訊號肋出 直保持在馬位準。若輸人資料為「G」（即低位準，此時 讯號ENI則為高位準），NM〇s電晶體丁2〇及丁21被導通，使 得節點D及C分別處於低位準及高位$。若輸入資料為「卜 (即高位準，此時訊號ENI則為低位準），NM〇s電晶體τ2〇 被關閉，使得節點C處於低位準。此時，讀取電壓V…或 (其係小於（01)狀態之門檻電壓分佈）被施加在選定字元線 上且一第三確認訊號S 2被觸發以感測存取記憶胞之狀態。 右存取記憶胞處於（11)狀態，節點s〇將處於低位準且節點B 將保持在高位準。若存取記憶胞處於（〇1)狀態，節點8〇將 處於高位準且節點B將切換至低位準。藉此，第二記憶胞之 最南有效位元將被讀至第二栓鎖電路52且被栓鎖在其中。 意即’處於（11)狀態（即零狀態）及處於（01)狀態（即第二狀態） 之存取記憶胞之最高有效位元之訊息係被栓鎖在第二栓鎖 電路52中。之後，訊號VBL1及VBL2將分別被設定至低位 準及高位準’以導通PMOS電晶體T9及NM0S電晶體T12。 最低有效位元寫入操作可進一步分成LSB1寫入及LSB2 寫入，其分別以圖6中之箭號fi及F2表示。於LSB1寫入期 109329.doc -15· 1306256 間’輸入為「ο」之資料將使得節點c處於高位準。若存取 記憶胞處於（11)狀態，則節點Β將保持在高位準且1^1^〇8電 晶體Τ10、Τ11及Τ12將被導通，使得節點s〇將被拉至一位 元線電源BLPWR。因節點SO於NMOS電晶體T22導通時係 電連接位元線BLE ’位元線BLE將處於該位元線電源 BLPWR之電壓位準。此時該位元線電源BLpWR之電壓位準 係可調整於該接地電位vss及該電源電位Vce之間，以減缓自 (11)狀態寫入至（10)狀態（參考箭號F1)之寫入速度並配合自 (01)狀態寫入至（00)狀態（參考箭號F2)之寫入時間。LSB1 寫入將一直進行直到存取記憶胞均已達到（i 0)狀態。於 LSB2寫入期間，輸入為「〇」之資料將使得節點c處於高位 準。差存取記憶胞處於（〇1)狀態，則節點B將保持在低位準 且NMOS電晶體T1 0、T13及T14將被導通，使得節點s〇將被 拉至該接地電位vss ;藉此，位元線BLE也被拉至該接地電 位Vss。LSB2寫入將一直進行直到存取記憶胞均已達到（〇〇) 狀態。注意，於最低有效位元寫入操作時，輸入為「丨」之 資料將使得節點c處於低位準。參考圖5，PM〇s電晶體T8 及T9將被導通。結果，節點s〇將被拉至該電源電位ν^，同 時位元線BLE也被拉至該電源電位；因此，將禁止最低 有效位元寫入操作之進行。 圖8係選疋子元線電壓s WLV、第一確認訊號$ 1〗、第二確 認訊號S12及節點C之狀態於最低有效位元寫人操作之時序 圖 一 P白 #又確3忍程序（tow-phase verification，即 LV1 及 LV2 109329.doc -16- 1306256 期間或者LV3及LV4期間）係用以確認該LSB 1寫入（即LV1或 LV3)及該LSB2寫入（即LV2或LV4)。為了確認該LSB1寫入， 寫入電壓PGMVT0(例如0.3V)被施加在選定字元線上且該 第一確認訊號S11被觸發以感測存取記憶胞之狀態（此時， 節點B係處於高位準）。為了確認該LSB2寫入，寫入電壓 PGMVT2(例如2.3V)被施加在選定字元線上且該第二確認 訊號S12被觸發以感測存取記憶胞之狀態（此時，節點A係處 於高位準）。當（10)狀態及（00)狀態達到時，節點C將被設定 至低位準，因此進一步的寫入操作將被禁止。注意，寫入 電壓PGMV(例如19V)在LP1及LP2期間係施加在選定字元 線上，使得該LSB1寫入及該LSB2寫入可同時在LP1及LP2 每一期間進行。 圖9係使用單階段讀取（one phase reading)之最高有效位 元讀取之時序圖。於MR1期間，第一栓鎖電路51之節點C 及D係藉由觸發訊號RESET1以導通NMOS電晶體T2而分別 被重置至高位準及低位準。在最高有效位元讀取時，僅有 第一栓鎖電路51被使用。在MR2期間，讀取電壓Vrd2(例如 1V)被施加在選定字元線以確認存取記憶胞之狀態。因為第 二栓鎖電路52沒有被重置且節點A可能處在高位準或低位 準，因此第一及第二確認訊號S11及S12被觸發用以感測存 取記憶胞之狀態。若存取記憶胞處於（01)或（00)狀態，則節 點SO將處於高位準且節點C則藉由導通NMOS電晶體T5、 T3及T4(或T5、T6及T7)而被設定至低位準。若存取記憶胞 109329.doc 17· 1306256 處於（11)或（10)狀態，則節點so將處於低位準且節點C將保 持在高位準。在MR3期間，節點C之四種狀態即為存取記憶 胞分別處於（11)、（10)、（01)及（00)狀態之最高有效位元。 圖10係使用二階段讀取（three-phase reading)之最低有效 位元讀取之時序圊。該三階段讀取係用以感測存取記憶胞 之最低有效位元，其包含LSB1讀取、LSB2讀取及LSB3讀 取三個階段。參考圖1〇及圖6，節點A、B、C及D首先藉由 觸發訊號RESET1及RESET2以導通NMOS電晶體T2及T17 而分別被設定為低位準、高位準、高位準及低位準（即重置 該第一栓鎖電路5 1及該第二栓鎖電路52)。於LSB 1讀取期 間，係利用第一栓鎖電路51。讀取電壓Vrd3(例如2V)被施加 在選定字元線上用以區別處於（〇〇)狀態之存取記憶胞及處 於（01)、（ 10)及（11)狀態之存取記憶胞。該第一確認訊號S i i 被觸發以感測存取記憶胞之狀態。若存取記憶胞處於（00) 狀態’則節點C藉由導通NMOS電晶體T5、T3及T4而切換至 低位準。若存取記憶胞處於（11)、（1〇)或（〇1)狀態，則節點 SO將切換至低位準且節點c保持在高位準。於LSB2讀取期 間’係利用第二拴鎖電路52。讀取電壓Vrd2(例如IV)被施加 在選定字元線上用以區別處於（1〇)或（U)狀態之存取記憶 胞及處於（01)或（00)狀態之存取記憶胞。該第三確認訊號S2 被觸發以感測存取記憶胞之狀態。若存取記憶胞處於（01) 或（〇〇)狀態’則節點SO為高位準且節點B切換至低位準。若 存取記憶胞處於（11)或（10)狀態，則節點SO被拉至低位準且 109329.doc -18· 1306256 節點B保持在高位準。於LSB3讀取期間，係利用第—拴鎖 電路5 1。讀取電壓Vrdl (例如〇v)被施加在選定字元線上用以 區別處於（11)狀態之存取記憶胞及處於其他狀態之存取記 憶胞。該LSB2讀取之結果係被回授以控制該LSB3讀取中之 感測動作。再次地，該第一確認訊號S11係用以感測存取記 憶胞之狀態。有關存取記憶胞之最低有效位元之感測動作 摘要如下。若存取記憶胞處於（00)狀態，節點c係已在該lsb 讀取期間被設定為低位準。若存取記憶胞處於（〇1)狀態，節 點SO在該LSB3讀取期間處於高位準，然而節點B在該LSB2 讀取期間被設為低位準；因此，節點c將保持在高位準。若 存取記憶胞處於（10)狀態，節點S〇在該LSB3讀取期間處於 高位準且節點B在該LSB2讀取期間及該LSB 1讀取時間被設 為高位準；因此，節點C被設為低位準。若存取記憶胞處於 (11)狀態，節點SO在該LSB3讀取期間處於低位準且節點B 在該LSB2讀取期間及該LSB1讀取時間均為高位準；因此， 節點C將保持在高位準。結果，當存取記憶胞處於（〇〇)、 (01)、（10)及（11)狀態時，節點c之狀態分別為「〇」、「丨」、 「〇」及「1」。意即，節點c之輸出即為存取記憶體之最低 有效位元。此外，記憶胞之每一最高有效位元及每一最低 有效位70係經由第—栓鎖電路5丨中之栓鎖（latch)5丨丨輸出 (參圖5)。 經由上述關於本發明多層次胞N AND型快閃記憶體元件 寫入及讀取方法之詳細說明之後，以下簡述各確認訊號 109329.doc •19- 1306256 S11、S12及S2之技術特徵。第一確認訊號s 11係用以確認處 於第二狀態記憶胞之最高有效位元（參圖7之MV1及MV2期 間），且用以確認處於第一狀態記憶胞之最低有效位元（參圖 8之LV1及LV3期間）。第二確認訊號S12係用以確認處於第 三狀態記憶胞之最低有效位元（參圖8之LV2及LV4期間）。第 三確認訊號S2係用以讀取處於第二及第三狀態之記憶胞之 最低有效位元（參圖10之LSB2讀取及LSB3讀取期間）。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1係一記憶胞之四種門檻電壓分佈圖； 圖2係應用在一 NAND型快閃記憶體中之記憶胞陣列中 之二記憶胞串示意圖； 圖3係顯示第一習知技藝之寫入方法之記憶胞狀態轉換 不意圖； 圖4係顯示第二習知技藝之寫入方法之記憶胞狀態轉換 示意圖； 圖5係本發明一實施例之頁緩衝區之電路示意圖； 圖6係本發明之兩頁式寫入方法之記憶胞狀態轉換示意 圖； 圖7係本發明最高有效位元寫入操作之相關訊號時序圖； 109329.doc -20, 1306256 圖8係本發明最低有效位元寫入操作之相關訊號時序圖； 圖9係使用單階段讀取之最高有效位元讀取之時序圖；以 及 圖1 〇係使用三階段讀取之最低有效位元讀取之時序圖。 【主要元件符號說明】When the second page write operation (i.e., the write operation of the least significant bit) is performed, the same word line or access cell as the write operation at the most significant bit is used. Referring to FIG. 5 and FIG. 6, the starting state of the nodes A, B, and QD is the most: the effective bit "is the same during operation. During the data input period, the signal ribs are kept at the horse level. If the input data is " G" (ie, low level, at this time the signal ENI is high), NM〇s transistor D2 and D21 are turned on, so that nodes D and C are at low level and high level, respectively. If the input data is "Bu (ie, the high level, then the signal ENI is low), the NM〇s transistor τ2〇 is turned off, so that the node C is at a low level. At this time, the reading voltage V... or (the system) A threshold voltage distribution less than (01) state is applied to the selected word line and a third acknowledge signal S 2 is triggered to sense the state of accessing the memory cell. The right access memory cell is in the (11) state, node s 〇 will be at a low level and node B will remain at a high level. If the access memory cell is in the (〇1) state, node 8〇 will be at a high level and node B will switch to a low level. Thereby, the second memory cell The southernmost significant bit will be read to the second latch circuit 52 and latched therein. That is, the access is in the (11) state (ie, the zero state) and the (01) state (ie, the second state). The message of the most significant bit of the memory cell is latched in the second latch circuit 52. Thereafter, the signals VBL1 and VBL2 are respectively set to the low level and the high level to turn on the PMOS transistor T9 and the NM0S transistor T12. The least significant bit write operation can be further divided into LSB1 write and LSB2 write Which are indicated by the arrows in Figure 6 fi and F2. LSB1 to write on 109329.doc -15 · 1306256 Jian 'input data' ο 'will make the node c at a high level. If the access memory cell is in the (11) state, the node Β will remain at the high level and the transistor Τ10, Τ11, and Τ12 will be turned on, so that the node s〇 will be pulled to the one-bit line power supply. BLPWR. When the node SO is turned on when the NMOS transistor T22 is turned on, the bit line BLE' BLE line BLE will be at the voltage level of the bit line power source BLPWR. At this time, the voltage level of the bit line power supply BLpWR can be adjusted between the ground potential vss and the power supply potential Vce to slow the writing from the (11) state to the (10) state (refer to the arrow F1). The write speed is matched with the write time from the (01) state to the (00) state (refer to arrow F2). The LSB1 write will continue until the access memory cell has reached the (i 0) state. During the LSB2 write, the data entered as “〇” will cause node c to be at a high level. When the differential access memory cell is in the (〇1) state, the node B will remain at the low level and the NMOS transistors T1 0, T13 and T14 will be turned on, so that the node s 〇 will be pulled to the ground potential vss; The bit line BLE is also pulled to the ground potential Vss. The LSB2 write will continue until the access memory cell has reached the (〇〇) state. Note that when writing to the least significant bit, the data entered as "丨" will cause node c to be at a low level. Referring to Figure 5, the PM〇s transistors T8 and T9 will be turned on. As a result, the node s 〇 will be pulled to the power supply potential ν^, and the bit line BLE is also pulled to the power supply potential; therefore, the least significant bit write operation will be inhibited. Figure 8 is a timing diagram of the selection of the sub-element voltage s WLV, the first acknowledgment signal $1, the second acknowledgment signal S12, and the state of the node C in the least significant bit write operation. (tow-phase verification, ie LV1 and LV2 109329.doc -16-1306256 or during LV3 and LV4) is used to confirm the LSB 1 write (ie LV1 or LV3) and the LSB2 write (ie LV2 or LV4) . In order to confirm the LSB1 write, a write voltage PGMMV0 (eg, 0.3V) is applied to the selected word line and the first acknowledge signal S11 is triggered to sense the state of accessing the memory cell (at this time, the Node B is in the high position) quasi). In order to confirm the LSB2 write, a write voltage PGMMV2 (eg, 2.3V) is applied to the selected word line and the second acknowledge signal S12 is triggered to sense the state of accessing the memory cell (at this time, node A is in a high position) quasi). When the (10) state and the (00) state are reached, node C will be set to the low level, so further write operations will be disabled. Note that the write voltage PGMV (e.g., 19V) is applied to the selected word line during LP1 and LP2 so that the LSB1 write and the LSB2 write can be performed simultaneously during each of LP1 and LP2. Figure 9 is a timing diagram of the most significant bit read using one phase reading. During MR1, nodes C and D of the first latch circuit 51 are reset to the high level and the low level, respectively, by the trigger signal RESET1 to turn on the NMOS transistor T2. Only the first latch circuit 51 is used when the most significant bit is read. During MR2, a read voltage Vrd2 (e.g., 1V) is applied to the selected word line to confirm the state of accessing the memory cell. Since the second latch circuit 52 is not reset and the node A may be at a high or low level, the first and second acknowledge signals S11 and S12 are triggered to sense the state of the memory cell. If the access memory cell is in the (01) or (00) state, the node SO will be at a high level and the node C is set to a low level by turning on the NMOS transistors T5, T3, and T4 (or T5, T6, and T7). quasi. If the access memory cell 109329.doc 17· 1306256 is in the (11) or (10) state, the node so will be at a low level and the node C will remain at a high level. During MR3, the four states of node C are the most significant bits of the access memory cells in the states of (11), (10), (01), and (00), respectively. Figure 10 is a timing diagram using the least significant bit read of a three-phase reading. The three-phase read is used to sense the least significant bit of the access memory cell, which includes three stages of LSB1 read, LSB2 read, and LSB3 read. Referring to FIG. 1A and FIG. 6, nodes A, B, C, and D are first set to low level, high level, high level, and low level by triggering signals RESET1 and RESET2 to turn on NMOS transistors T2 and T17, respectively. The first latch circuit 51 and the second latch circuit 52) are reset. During the LSB 1 reading, the first latch circuit 51 is utilized. A read voltage Vrd3 (e.g., 2V) is applied to the selected word line to distinguish between the access memory cells in the (〇〇) state and the access memory cells in the (01), (10), and (11) states. The first acknowledgement signal S i i is triggered to sense the state of accessing the memory cell. If the access memory cell is in the (00) state, the node C switches to the low level by turning on the NMOS transistors T5, T3, and T4. If the access memory cell is in the (11), (1〇) or (〇1) state, the node SO will switch to the low level and node c will remain at the high level. The second latch circuit 52 is utilized during the LSB2 read period. A read voltage Vrd2 (e.g., IV) is applied to the selected word line to distinguish between an access memory cell in the (1) or (U) state and an access memory cell in the (01) or (00) state. The third acknowledge signal S2 is triggered to sense the state of accessing the memory cell. If the access memory cell is in the (01) or (〇〇) state, the node SO is at a high level and the node B is switched to a low level. If the access memory cell is in the (11) or (10) state, node SO is pulled to the low level and 109329.doc -18·1306256 node B remains at the high level. During the LSB3 reading, the first shackle circuit 51 is utilized. A read voltage Vrd1 (e.g., 〇v) is applied to the selected word line to distinguish between the access memory cells in the (11) state and the access memory cells in other states. The result of the LSB2 reading is fed back to control the sensing action in the LSB3 reading. Again, the first confirmation signal S11 is used to sense the state of the access memory cell. The sensing actions for accessing the least significant bits of the memory cell are summarized below. If the access memory cell is in the (00) state, node c is already set to a low level during the lsb read. If the access memory cell is in the (〇1) state, the node SO is at a high level during the LSB3 read, however, the Node B is set to a low level during the LSB2 read; therefore, the node c will remain at a high level. If the access memory cell is in the (10) state, the node S is at a high level during the LSB3 read and the node B is set to a high level during the LSB2 read and the LSB 1 read time; therefore, the node C is Set to low level. If the access memory cell is in the (11) state, the node SO is in the low level during the LSB3 read and the node B is in the high level during the LSB2 read and the LSB1 read time; therefore, the node C will remain at the high level. quasi. As a result, when the access memory cells are in the (〇〇), (01), (10), and (11) states, the states of the node c are "〇", "丨", "〇", and "1", respectively. That is, the output of node c is the least significant bit of the access memory. In addition, each of the most significant bits of the memory cell and each of the least significant bits 70 are output via a latch 5 in the first latch circuit 5 (see Figure 5). After the above detailed description of the multi-level cell N AND type flash memory device writing and reading method of the present invention, the technical features of each of the confirmation signals 109329.doc • 19-1306256 S11, S12 and S2 will be briefly described below. The first acknowledgement signal s 11 is used to confirm the most significant bit in the second state memory cell (refer to MV1 and MV2 in FIG. 7), and is used to confirm the least significant bit in the first state memory cell (refer to the figure). 8 during LV1 and LV3). The second acknowledge signal S12 is used to confirm the least significant bit in the third state memory cell (refer to LV2 and LV4 of Figure 8). The third acknowledge signal S2 is used to read the least significant bits of the memory cells in the second and third states (refer to the LSB2 read and LSB3 read of Figure 10). The technical contents and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a four-thickness voltage distribution diagram of a memory cell; FIG. 2 is a schematic diagram of two memory cell strings used in a memory cell array in a NAND-type flash memory; FIG. 4 is a schematic diagram showing the memory cell state transition of the writing method of the second conventional technique; FIG. 5 is a circuit diagram of the page buffer of an embodiment of the present invention; FIG. 6 is a schematic diagram of memory cell state transition of the two-page writing method of the present invention; FIG. 7 is a timing diagram of related signals of the most significant bit writing operation of the present invention; 109329.doc -20, 1306256 FIG. Invented the least significant bit write operation related signal timing diagram; Figure 9 is the timing diagram of the most significant bit read using single-phase read; and Figure 1 is the least significant bit read using three-stage read Timing diagram. [Main component symbol description]
5 頁緩衝區 10 記憶胞 20 記憶胞陣列 51 第一栓鎖電路 52 第二栓鎖電路 53 位元線電源電路 54 位元線選擇電路 55 輸入電路 56 預充電路 511 、521 栓鎖 A、B、C、D、SO 節點 BL1 ' BL2 > BLE > BL0 位元線 BLPWR 位元線電源 CSL 共源線 GSL 地選擇線 GST 地選擇電晶體 SSL 串選擇線 SST 串選擇電晶體 T1〜 T17 、 T20 、 T21 電 晶體 Vcc 電源電位 WL1 〜WL16 字元線 109329.doc •21 -5 page buffer 10 memory cell 20 memory cell array 51 first latch circuit 52 second latch circuit 53 bit line power circuit 54 bit line selection circuit 55 input circuit 56 precharge path 511, 521 latch A, B , C, D, SO node BL1 'BL2 > BLE > BL0 bit line BLPWR bit line power CSL common source line GSL ground selection line GST ground selection transistor SSL string selection line SST string selection transistor T1 ~ T17, T20, T21 transistor Vcc power supply potential WL1 ~ WL16 word line 109329.doc • 21 -