KR100739251B1 - Page Buffer in flash memory device - Google Patents

Abstract

The present invention relates to a page buffer of a flash memory device, which omits the process of transferring data from a first latch to a second latch during a program operation by adding a program data input switch to a register and directly inputs data from the second latch. A page buffer of a flash memory device that can prevent program time and malfunction of a program is disclosed.

Nand Flash, Page Buffers, Data Transfer

Description

Page buffer in flash memory device

1 is a circuit diagram illustrating a conventional page buffer.

2 is a circuit diagram illustrating a page buffer according to the present invention.

3 is a timing diagram of a circuit for explaining a page buffer according to the present invention.

Description of the main parts of the drawing

10, 100: memory cell array 20, 110: bit line selector

30, 120: precharge section 40, 130: register

41, 131: first latch 42, 132: second latch

The present invention relates to a page buffer of a flash memory device, and more particularly to a page buffer of a programmable flash memory device without a data transfer operation for transferring data from the first latch to the second latch.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function to rewrite data at regular intervals. In order to develop a large-capacity memory device capable of storing a larger amount of data, technical research on high integration of memory devices has been actively studied.

For high integration of memory cells, a NAND type flash memory device has been developed in which a plurality of memory cells are connected in series to form a string. The NAND type flash memory device is programmed and erased by injecting or extracting electrons into the floating gate of the NAND type flash memory device by a Fowler-Nordheim Tunneling method.

NAND-type flash memory devices use a page buffer to store large amounts of information in a short time and to verify normal program and erase.

1 is a configuration diagram of a page buffer of a general NAND type flash memory device. The program operation is performed by using the first latch 41 and the second latch 42 of the register 40. A program operation of a flash memory device using a conventional page buffer will be briefly described as follows.

1) Initialization stage

The reset signal CSET is applied to the NMOS transistor N44 of the register 40 to turn on the NMOS transistor N44. Therefore, the ground power source Vss is applied to the node QBb of the first latch 41 so that the node QBb is initialized to a low level.

2) data latch phase

The reset signal MRST is applied to the NMOS transistor N43 of the register 40 so that the NMOS transistor N43 is turned on. Therefore, the ground power source Vss is applied to the node QA of the second latch 42 so that the node QA is initialized to the low level. The precharge signal PRECHb is applied to the precharge unit 30. Therefore, the power supply voltage Vcc is applied to the sensing node SO, and the sensing node SO is precharged to the power supply voltage Vcc level. Data to be programmed is input to the input / output terminal YA. In response to the data input signal nDI, the NMOS transistor N47 of the register 40 is turned on to connect the node QB of the first latch 41 and the input / output terminal YA. Thus, data is stored in the first latch 41.

3) Data transfer step

The data transfer signal PDUMP is input to the NMOS transistor N49 of the register 40 so that the NMOS transistor N49 is turned on. Therefore, the sensing node SO and the node QB of the first latch are connected so that the potential of the sensing node SO is maintained at the power supply voltage Vcc level or discharged to the ground power supply Vss level according to the data to be programmed. . The NMOS transistor N41 of the resistor 40 is turned on or off depending on the potential of the sense node SO. Thereafter, the latch signal LATCH is input to the NMOS transistor N42 to turn on the NMOS transistor N42. When the NMOS transistor N41 is turned on, the node QAb of the second latch 42 is connected to the ground power supply Vss and discharged to the ground power supply Vss level. On the other hand, when the NMOS transistor N41 is turned off, the node QAb maintains an initialization state, that is, a logic high.

4) Data program step

The bit line selection signal BSLe or BSLo is applied to the NMOS transistors N23 or N24 of the bit line selector 20 to select the bit lines BLe or BLo to be programmed. If the even bit line BLe is selected, the bit line selection signal BSLe is applied to the NMOS transistor N23 to connect the even bit line BLe and the sensing node SO. Thereafter, the program signal PGM is applied to the register 40 so that the NMOS transistor N50 is turned on. Therefore, the sensing node SO and the node QA of the second latch are connected. Therefore, the data stored in the second latch is input to the bit line BLe or BLo connected to the sensing node SO, and the word line program signal WL is input to the memory cell array 10 so that the data is input to the memory cell array 10. Is programmed.

As described above, in the conventional program method using the page buffer, data to be programmed is stored in a first latch and then transferred to a second latch. Due to such a day transmission process, there is a high possibility that a malfunction occurs in the program operation and the program time increases, thereby decreasing the efficiency of the program operation.

Therefore, the page buffer of the flash memory device according to the present invention omits the process of transferring data from the first latch to the second latch during a program operation by adding a program data input switch and directly inputs data from the second latch. Prevents time and program malfunctions.

A page buffer of a flash memory device according to the present invention is connected to an even bit line and an odd bit line of a memory cell array to precharge the even bit line or the odd bit line, and selects the even bit line or the odd bit line. A bit line selector connected to the sensing node, a precharge unit connected between a power supply terminal and the sensing node to maintain the predetermined potential by the precharge signal, and between the sensing node and the input / output terminal. A first and second latches connected to the first and second latches to temporarily store data, and a program first switching unit to connect the input / output terminal and the first node of the first latch in response to a program data input signal during a program operation. Only the first latch is activated to store program data, and then In response to the program data to the sense node and said bit line or Ibn includes a register to transfer to the memory cell array via the odd bit lines.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

FIG. 2 is a detailed circuit diagram of a page buffer of a flash memory device according to an exemplary embodiment of the present invention. The bit line selection unit 110 selects a memory cell array 100 capable of storing data and a bit line of the memory cell array 100. And a precharge unit 120 for precharging the sensing node and a register 130 for storing data to be programmed.

The bit line selector 120 includes a plurality of NMOS transistors N111 to N114. In the NMOS transistors N111 and N112 connected in series between the even bit line BLe and the odd bit line BLo, the NMOS transistors N111 and N112 are turned on in response to the discharge signals DISCHe and DISCHo to turn on the verification signal. VIRPWR is applied to the bit lines BLe and BLo. The NMOS transistors N303 and N304 connected between the bit lines BLe and BLo and the sensing node SO are turned on in response to the bit line selection signals BSLe and BSLo so that the NMOS transistors N113 and N114 are turned on. And BLo) and the sense node SO are connected.

The precharge unit 120 is connected between the power supply voltage terminal Vcc and the sensing node SO, and is composed of a PMOS transistor P121 connected between the power supply voltage terminal Vcc and the sensing node SO. The PMOS transistor P121 is turned on in response to the precharge signal PRECHb to apply the power supply voltage Vcc to the sensing node SO.

The register 130 is connected between the sensing node SO and the input / output terminal YA, and includes a first latch 131 and a second latch 132 for temporarily storing data. A detailed configuration thereof will be described. Is as follows.

The NMOS transistors N131 and N132 are connected in series between the node QAb of the second latch 132 and the ground power supply Vss. The NMOS transistor N131 is turned on in response to the latch signal LATCH, and the NMOS transistor N132 is turned on / off according to the potential of the sensing node SO to connect the node QAb and the ground power source Vss, or Separate. The PMOS transistor P131 is connected between the power supply voltage terminal Vcc and the detection signal terminal nWDO_L, and the PMOS transistor P131 is turned on in accordance with the node QA potential of the second latch 132 to supply the power supply voltage Vcc. Is applied to the detection signal terminal nWDO_L. The NMOS transistor N133 is connected between the node QA of the second latch 132 and the ground power supply terminal Vss, and the NMOS transistor N133 is turned on in response to the reset signal MRST so that the ground power supply Vss is turned on. Is applied to this node QA. Thus, the second latch 132 is initialized. The NMOS transistor N135 is connected between the node QA and the input / output terminal YA, and in response to the program data input signal PGM_IN, the NMOS transistor N135 is turned on so that the node QA and the input / output terminal YA are turned on. Connected. The NMOS transistor N134 is connected between the node QA and the input / output terminal YA, and the NMOS transistor N134 is turned on in response to the data read signal PBDO to connect the input / output terminal YA and the node QA. do. The NMOS transistor N136 is connected between the node QA and the sensing node SO, and the NMOS transistor N136 is turned on in response to the program signal PGM to connect the node QA and the sensing node SO. . The NMOS transistor N137 is connected between the node QBb of the first latch 131 and the ground power supply Vss, and the NMOS transistor N137 is turned on in response to the reset signal CRST to turn off the ground power supply Vss. Applied to node QBb. Thus, the first latch 131 is initialized. The NMOS transistor N138 is connected between the node QB of the first latch 131 and the input / output terminal YA, and the NMOS transistor N138 is turned on in response to the cache program signal CACHEPRGM so that the NMOS transistor N138 is connected to the node QB. The input / output terminal YA is connected. The NMOS transistors N139 and 140 are connected in series between the ground power supply Vss and the node QB. The NMOS transistor N139 is turned on in response to the first latch signal CLCH, and the NMOS transistor N140 is turned on / off in accordance with the potential of the sensing node SO, so that the node QB and the ground power supply Vss are turned on. ) Or connect it. The NMOS transistor N141 is connected between the node QB and the sense node SO, and the NMOS transistor N141 is turned on in response to the dump signal PDUMP to connect the sense node SO and the node QB. . The first latch 131 and the second latch 132 each consist of two inverters connected in parallel in the reverse direction to store program data.

3 is a timing diagram of page buffer signals according to the present invention. For example, the operation of the flash memory device according to the present invention configured as described above with reference to FIG. 3 is programmed in an even bit line BLe. The explanation is as follows.

1) T1 section in FIG. 3: precharge and data input section

First, the precharge signal PRECHb is applied to the PMOS transistor P31 of the precharge unit 30 to turn on the PMOS transistor P31. Therefore, the power supply voltage Vcc is applied to the sensing node SO, and the sensing node SO is precharged to the power supply voltage Vcc level. The NMOS transistor N132 is turned on in accordance with the sensing node SO potential of the power supply voltage Vcc level. At this time, the latch signal LATCH is applied to the register 130 to turn on the NMOS transistor N131. Due to the turn-on of the NMOS transistor N132 and the NMOS transistor N131, the node QAb of the second latch 132 and the ground power source Vss are connected so that the node QAb is logic low, and the node QA is Logic high. Thereafter, the program data input signal PGM_IN is input to the register 130 to connect the node QA of the second latch 132 and the input / output terminal YA. If '1' data is input, node QA is maintained at logic high, and if '0' data is input, node QA is at logic low.

2) T2 section in FIG. 3: Bit line precharge section

The even discharge signal DISe is applied to the NMOS transistor N111 of the bit line selector 120 to turn on the NMOS transistor N111. Accordingly, the bias voltage VIRPWR is applied to the even bit line BLe so that the even bit line BLe is precharged. In addition, the odd discharge signal DISo is applied to the NMOS transistor N112 to turn on the NMOS transistor N112. Accordingly, the bias voltage VIRPWR is applied to the odd bit line BLo to precharge the odd bit line BLo. Thereafter, the even discharge signal DISe is blocked to separate the bias voltage VIRPWR and the even bit line BLe. On the other hand, the odd discharge signal DISo is continuously applied so that the odd bit line BLo is continuously connected to the bias voltage VIRPWR to maintain the bias voltage VIRPWR level.

3) T3 section in FIG. 3: Program section

An even bit line select signal BSLe is applied to the NMOS transistor N113 of the bit line selector 110 to turn on the NMOS transistor N113. Therefore, the sensing node SO is connected to the even bit line BLe. Thereafter, the program signal PGM is sequentially applied to the NMOS transistor N136 of the register 130 to turn on the NMOS transistor N136. Therefore, the sensing node SO is connected to the node QA of the second latch 132. Since the potential of the node QA is at the high level when programming the '1' data, the potential of the even bit line BLe is maintained at the high level. On the other hand, since the potential of the node QA is at the low level during the zero data program, the potential of the even bit line BLe is discharged to the low level. Thereafter, high voltages 15 to 19V are applied to the word line WL to program the cells of the memory cell array 100. For reference, the reason why the program signal PGM is applied in stages is that in the case of a large-capacity flash memory device, a large amount of current discharged during programming may cause a malfunction of the device. Adjust the amount of current discharged by applying.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

Therefore, the page buffer of the flash memory device according to the present invention omits the process of transferring data from the first latch to the second latch during a program operation by adding a program data input switch and immediately inputs data from the second latch so that the program time Malfunctions of programs and programs are prevented.

Claims (6)

A bit line selector connected to an even bit line and an odd bit line of the memory cell array to precharge the even bit line or the odd bit line, and select the even bit line or the odd bit line to connect with a sensing node; A precharge unit connected between a power supply terminal and the sense node to maintain the sense node at a predetermined potential by a precharge signal; First and second latches connected between the sensing node and the input / output terminal for temporarily storing data, and a program first connecting the input / output terminal and the first node of the first latch in response to a program data input signal during a program operation; And a switching unit, wherein only the first latch is activated to store program data during a program operation, and then the program data is transmitted through the sensing node and the even bit line or the odd bit line in response to a program signal. Page buffer of a flash memory device containing registers to transfer to. The method of claim 1, The bit line selector may include a first switch configured to precharge by applying a verify signal to the even bit line and the odd bit line in response to a discharge signal; And And a second switching unit for connecting the even bit line or the odd bit line to the sensing node in response to a bit line selection signal. The method of claim 1, The precharge unit may include a switching unit connecting a power terminal and the sensing node in response to a precharge signal. The method of claim 1, The register unit includes a first latch initialization circuit for initializing the first latch; A second latch initialization circuit for initializing the second latch; And And a program second switching unit configured to connect the first node of the first latch and the sensing node in response to a program signal during a program operation. The method of claim 4, wherein And the second latch is inactivated during a program operation. The method of claim 4, wherein And the first and second latches comprise two inverters connected in parallel in a reverse direction to store data.

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