KR100576485B1 - Method of program verify of flash memory device - Google Patents

Abstract

The present invention relates to a method for verifying a program of a flash memory device, the method for verifying a program of a flash memory device having a page buffer of a dual register structure having a main register and a cache register, wherein program data is stored in a main register and a cache register, respectively. Doing; Programming a selected cell using program data stored in the main register and then performing program verification using the main register; Resetting the main register and reading state data of the program cell when it is determined that the program is successful as a result of the program verification of the main register; And comparing the data of the programmed cell with the program data stored in the cache register and outputting a verification signal according to the result. The program verification method of the NAND type flash memory device capable of improving program verification reliability is presented. do.

Page Buffer, Dual Registers, Program Verification, Reliability

Description

Method of program verify of flash memory device             

1 is a configuration diagram of a page buffer for explaining a program verification method of a NAND type flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101: memory cell array 102: main register

103: cache registers 104 and 105: latch

The present invention relates to a program verification method of a flash memory device, and more particularly, to a program verification method of a NAND flash memory device using a page buffer of a dual register structure.

Recently, the demand for semiconductor memory devices that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, research into a high integration technology of the memory device has been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of erasing data written to the memory cell.

NAND type flash memory device (NAND) in which a plurality of memory cells are connected in series (that is, a structure in which adjacent cells share drain or source with each other) to form a string for high integration of the memory device. -type flash memory device) has been developed. Unlike a NOR-type flash memory device, a NAND type flash memory device is a memory device that reads information sequentially. Programming and erasing of such a NAND type flash memory device is performed by controlling the threshold voltage of the memory cell while injecting or emitting electrons into a floating gate using an F-N tunneling method.

A NAND type flash memory device uses a page buffer to store a large amount of information in a short time. The page buffer receives a large amount of data from input / output pads and provides the memory cells. In general, a page buffer is generally composed of a single register to temporarily store data. However, in recent years, a NAND-type flash memory device has a dual register to increase program speed when programming large data.

In a NAND flash memory device using a page buffer of a dual register structure, program data is loaded into a main register for a program, and then data is stored in a selected memory cell. At this time, the program verification is repeated after the program is executed, and the program and the program verification are repeated for the set maximum number of times. During program verification, if the PMOS transistor is turned off by the potential of the output terminal of the main register and the PMOS transistor is turned off and the verification signal remains floating, it is determined that the program is successful. However, since the output terminal of the main resistor is unstable for various reasons, such as a change in power supply voltage and coupling with peripheral devices, the verification signal output according to this potential is also unstable. Therefore, there is a lot of problems in terms of reliability since it is not reliable whether the program succeeds.

An object of the present invention is to provide a program verification method of a flash memory device capable of improving program verification reliability.

Another object of the present invention is to improve the program verification reliability by storing the program data in the cache register at the time of programming, by performing the final program verification by comparing the program data stored in the cache register with the verification data after the program verification using the main register. A program verification method of a flash memory device is provided.

In the program verifying method of a flash memory device according to an embodiment of the present invention, in the program verifying method of a flash memory device having a page buffer of a dual register structure having a main register and a cache register, program data is stored in the main register and the cache register. Storing each; Programming a selected cell using program data stored in the main register and then performing program verification using the main register; Resetting the main register and reading state data of the program cell when it is determined that the program is successful as a result of the program verification of the main register; And comparing the data of the programmed cell with the program data stored in the cache register and outputting a verification signal according to the result.

The verification signal maintains a floating state when the program is successful and maintains the potential of the power supply voltage level when the program fails.

On the other hand, the program verification method of a flash memory device according to another embodiment of the present invention includes a first switch for connecting the even bit line and the odd bit line and the sensing node connected to the memory cell array, respectively, according to the bit line selection signal; A second switch for supplying a predetermined voltage to the sensing node according to a precharge signal so that the sensing node maintains a predetermined potential; A main register for storing program data according to a control signal activated during programming and for storing output data from selected cells of the memory cell array according to a potential of the sensing node and a first read signal; A cache register for storing the program data according to a control signal activated during the programming, and comparing the program data with data stored in the main register and data from the main register according to a second read signal; Providing a page buffer including a third switch for outputting a verify signal according to the output signal of the cache register; Initializing the main register and the cache register; Storing the program data in the main register and the cache register, respectively, according to the control signal; Programming a selected cell using program data stored in the main register and then performing program verification using the main register; Resetting the main register and reading state data of the program cell when it is determined that the program is successful as a result of the program verification of the main register; And a potential of the output terminal of the cache register is changed according to the state data of the program cell read by the main register and the second read signal, and the third switch is driven according to the potential of the output terminal of the cache register. Outputting the verification signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of a page buffer having dual registers of a NAND type flash memory device. The page buffer is a memory cell after receiving and storing data from a cash register 103 and a cache register 103. It includes a main register (102) provided to the array 101, and performs a program operation using the cache register 103 and the main register (102).

The NMOS transistors N101 and N102 are driven in accordance with the discharge signals DISCHe and DISCHo, respectively, for example, a memory connected to the even bit line BLe or the odd bit line BLO by applying a voltage of, for example, 0 V according to the signal VIRPWR. It is applied to the memory cells of the cell array 101. The NMOS transistors N103 and N104 are driven according to the bit line selection signals BSLe and BSLo to connect the memory cell array 101 to the page buffer.

The PMOS transistor P101 is driven according to the precharge signal PRECHARGE_L to supply predetermined power to the node S0. The NMOS transistor N105 supplies data from the cache register 103 to the latch 104 of the main register 102 in accordance with the copyback programming signal COPYBACK. Inverters I101 and I102 invert the potentials of nodes QAb and QBb, respectively. The latches 104 and 105 store output data output from the memory cell array 101 and data supplied from the outside. The NMOS transistors N106 and N113 are driven according to the potential of the node SO, and the NMOS transistors N107 and N114 are driven according to the read signals READ_L and READ_R to invert the potentials of the nodes QAb and QBb. The NMOS transistors N108 and N115 are driven according to the signals DI_L and DI_R activated during programming to supply program data to the nodes QAb and QBb, and the NMOS transistors N109 and N116 activate the signals nDI_L when erased. And nDI_R to supply erase data to the nodes QA and QB. The NMOS transistors N110 and N117 are driven according to the reset signals RESET_L and RESET_R to initialize the nodes QA and QB. The PMOS transistors P102 and P103 are driven according to the potentials of the nodes QA and QB to output the verification signals nWDO_L and nWDO_R in the power supply voltage Vcc level or the floating state. The NMOS transistors N111 and N118 are driven according to the signals PROGRAM_L and PROGRAM_R during a program operation so that the information to be programmed is transmitted to the selected bit line. The NMOS transistors N112 and N119 are driven according to the signals PBDO_L and PBDO_R to output the potentials of the nodes QAb and QBb inverted by the inverters I201 and I202. The NMOS transistor N120 is driven according to the signal CON to connect the node SO and the input / output terminal YA.

A program and a program verification method of a NAND type flash memory device using the page buffer configured as described above will be described below.

The NMOS transistors N110 and N117 are turned on according to the reset signals RESET_L and RESET_R to initialize the main latch 104 of the main register 102 and the cache latch 105 of the cache register 103. When the program data is input through the YA pad YA, the NMOS transistors N108 and N115 are turned on according to the signals DI_L and DI_R, so that low-level program data is stored in the node QAb and the main latch 104. Each is passed to node QBb of cache latch 105. Thus, node QA of main latch 104 and node QB of cache latch 105 each maintain a high level. The program data transferred to the node QAb of the main latch 104 is inverted to a high level through the inverter I101, and according to the program signal PROGRAM_L, the NMOS transistor N111 is turned on to program the selected cell. do.

After the program is executed, program verification is performed using the main latch 104. For example, when the discharge signal DISCHe is applied at a low level, the NMOS transistor N101 is turned off and the signal DISCHo is used. ) Is applied at a high level, the NMOS transistor N102 is turned on, and a signal VIRPWR, which maintains a potential of 0 V, is supplied to the odd bit line BLo to read the state of the selected cell. Therefore, the even bit line BLe is selected and the odd bit line BLO is not selected. In addition, the signal RESET_L is applied to the high level to turn on the NMOS transistor N110 to initialize the output terminal QA of the latch 104 to the low level, and then apply the signal PRECHAGGE to the low level to apply the PMOS transistor ( P101 is turned on to maintain the node SO at the high level. After that, the signal BSLe is applied to the potential of the first voltage V1 so that the selected bit line BLe is precharged to V1 -Vt, and then the signal BSLe is applied at a low level, thereby evaluating the cell. ) At this time, the word lines are all applied at 0V. Then, the signal PRECHAGGE is applied to the high level to turn off the PMOS transistor P101, the signal BSLe is applied to the potential of the second voltage V2, and the signal READ_L is applied to the high level to NMOS. The transistor N107 is turned on. Therefore, the potential of the node SO changes according to the state of the cell, and thus the potential of the input terminal QAb and the output terminal QA of the latch 104 changes. That is, in the case of a program cell, the node SO maintains a high level potential, and in the case of an unprogrammed cell, the node SO maintains a low level potential. Therefore, when the node SO maintains the low level, the NMOS transistor N106 is turned off and the potential of the nodes QAb and QA does not change, so that the node QA maintains the low level. In contrast, when the node SO maintains a high level, the NMOS transistor N106 is turned on. At this time, since the transistor N107 is turned on, the potential of the node QAb is turned low, and the node QA is at a high level. Becomes Accordingly, the node QAb maintains a high level when the node is not a program cell, and the node QA maintains a low level. In contrast, in the case of a program cell, node QAb maintains a low level and node QA maintains a high level. Accordingly, the PMOS transistor P102 is turned off and the verify signal nWDO_L remains in a floating state according to the potential of the node QA at the high level, thereby determining that the program has been successfully performed.

After the program and program verification are repeated for the set maximum loop as described above, if the verification signal nWDO_L remains in the floating state, the NMOS transistor N110 is turned on according to the reset signal RESET_L to turn on the main register 102. Initialize the main latch 104 of. Accordingly, node QA maintains a low level and node QAb maintains a high level. In this state, the state of the selected cell is read in the same manner as the program verifying operation. If the read state of the cell is a program state, the node QAb maintains a low level. The potential of the low level node QAb is inverted to a high level through the inverter I101, and the NMOS transistor N111 is turned on according to the program signal PROGRAM_L to supply a high level signal to the node SO. At this time, the bit line selection signals BSLe and BSLo are applied at a low level. The NMOS transistor N114 is turned on according to the read signal READ_R, and the NMOS transistor N113 is turned on according to the potential of the node SO to lower the potential of the node QBb to a low level. Accordingly, the node QB is at a high level, and according to this potential, the PMOS transistor P103 is turned off and the verification signal nWDO_R is in a floating state. When the verification signal nWDO_R of the cache register 103 remains in the floating state, it is determined that the program is successful. On the other hand, if the state of the read cell is not the program state, the node QAb maintains the high level, and since the node QB has no influence on the potential of the node QBb, the node QB maintains the low level. Therefore, the PMOS transistor P103 is driven by the potential of the low level node QB to output the high level verify signal nWDO_R, which is determined to be a program failure.

As described above, according to the present invention, after program data is stored in the cache latch and the main latch during programming, the program and the program verification are performed using only the main latch, and the program verification data is compared with the program data stored in the cache latch. By causing the final verification signal to be output in accordance with the potential of the output terminal, the reliability of the program verification caused by the potential change of the output terminal of the main latch can be prevented.

Claims (3)

A program verification method of a flash memory device having a page buffer of a dual register structure having a main register and a cache register, Storing program data in a main register and a cache register, respectively; Programming a selected cell using program data stored in the main register and then performing program verification using the main register; Resetting the main register and reading state data of the program cell when it is determined that the program is successful as a result of the program verification of the main register; And Comparing the data of the programmed cell with program data stored in the cache register and outputting a verification signal according to the result. A first switch for connecting an even bit line and an odd bit line, respectively, connected to the memory cell array and a sensing node according to a bit line selection signal; A second switch for supplying a predetermined voltage to the sensing node according to a precharge signal so that the sensing node maintains a predetermined potential; A main register for storing program data according to a control signal activated during programming and storing output data from selected cells of the memory cell array according to a potential of the sensing node and a first read signal; A cache register for storing the program data according to a control signal activated during the programming, and comparing the program data with data stored in the main register and data from the main register according to a second read signal; Providing a page buffer including a third switch for outputting a verify signal according to the output signal of the cache register; Initializing the main register and the cache register; Storing the program data in the main register and the cache register, respectively, according to the control signal; Programming a selected cell using program data stored in the main register and then performing program verification using the main register; Resetting the main register and reading state data of the program cell when it is determined that the program is successful as a result of the program verification of the main register; And The potential of the output terminal of the cache register is changed according to the state data of the program cell read out by the main register and the second read signal, and the third switch is driven according to the potential of the output terminal of the cache register. A program verification method for a flash memory device comprising the step of outputting a verify signal. The method of claim 1 or 2, wherein the verification signal maintains a floating state when the program succeeds, and maintains a potential of a power supply voltage level when the verify signal fails.

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