KR20070114522A - Page buffer of flash memory device - Google Patents

Abstract

A page buffer for a flash memory device is provided to prevent an incorrect operation caused by a leakage current in a circuit by discharging power voltage when operating a precharging unit precharging a sensing node of the page buffer excluding a precharging operation. A bit line selector(210) connects a bit line and a sensing line by connecting to the bit line of a memory cell array(100) having a plurality of memory cells and responding to a bit line selection signal. The precharger(220) is connected between the sensing node and the power voltage, precharges the power voltage from the sensing node during the precharging operation, and performs discharging by separating the sensing node and the power voltage and connecting the power voltage to ground voltage during the operation excluding the precharging operation. A register(230) is connected between the sensing node and an I/O(Input/Output) terminal, and temporarily stores program data received through the I/O terminal and transfers the program data to the bit line through the sensing node during a programming operation.

Description

Page buffer of flash memory device

1 is a page buffer block diagram of a flash memory device according to the prior art.

2 is a graph showing off current according to channel length of a PMOS transistor.

3 is a detailed circuit diagram of a page buffer of a semiconductor memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10, 100: cell array 20, 200: page buffer

21, 210: bit line selector 22, 220: precharge unit

23, 230: register

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a page buffer of a semiconductor memory device, and more particularly to a page buffer of a flash memory device for reducing malfunction due to leakage current.

Recently, the demand for semiconductor memory devices that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of erasing data written to the memory cell.

NAND type flash memory device (NAND) in which a plurality of memory cells are connected in series (that is, a structure in which adjacent cells share drain or source with each other) to form a string for high integration of the memory device. -type flash memory device) has been developed. Unlike a NOR-type flash memory device, a NAND type flash memory device is a memory device that reads information sequentially. Programming and erasing of such a NAND type flash memory device is performed by controlling the threshold voltage of the memory cell while injecting or emitting electrons into a floating gate using an F-N tunneling method.

A NAND type flash memory device uses a page buffer to store a large amount of information in a short time.

Referring to FIG. 1, a flash memory device includes a cell array 10 having a plurality of memory cells and a page buffer 20.

The page buffer 20 may include a bit line selector 210 connected between the bit lines BLe and BLo of the cell array 10 and the sensing node SO, and a precharge unit 22 connected to the sensing node SO. And a register 23 connected between the sensing node SO and the input / output terminal YA. The register includes a latch 231 for temporarily storing data.

The page buffer 20 transmits program data to the bit line BLe or BLo through the sensing node SO precharged by the precharge unit 22 during a program operation, and the memory cell array 10 during a read operation. The data transmitted from the data is stored in the latch 231 of the register 23 through the sensing node SO precharged by the precharge unit 22. The sensing node SO is precharged by the precharge unit 22 during various operations of the flash memory device such as a copyback operation and a verify operation.

In general, the precharge unit 22 is configured using a PMOS transistor.

2 is a graph showing off current according to channel length of a PMOS transistor.

Referring to FIG. 2, as the degree of integration increases, the size of the transistor decreases, and as a result, leakage current rapidly increases, which may cause a malfunction in operation of the device.

An object of the present invention is to prevent the circuit malfunction due to leakage current by discharging the power supply voltage when the precharge unit precharges the sensing node of the page buffer other than the precharge.

A page bit line selector, a precharge unit, and a register of a flash memory device according to the present invention are included.

The bit line selector is connected to a bit line of a memory cell array having a plurality of memory cells, and connects the bit line and the sense node in response to a bit line select signal. The precharge unit is connected between the sensing node and the power supply voltage, and precharges by connecting the power supply voltage to the sensing node during the precharge operation, and separates the power supply voltage and the sensing node during operation other than the precharge operation, and connects the power supply voltage to the ground voltage. To discharge. The register is connected between the sensing node and the input / output terminal, and includes a register for temporarily storing program data input through the input / output terminal during a program operation and then transmitting the bit to the bit line through the sensing node.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a detailed circuit diagram of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 3, the flash memory device includes a cell array 100 and a page buffer 200.

The page buffer 200 includes a bit line selection circuit 210, a precharge unit 220, and a register 230.

The bit line selector 210 includes a plurality of NMOS transistors N201 to N204. The NMOS transistors N201 and N202 are connected in series between the even bit line BLe and the odd bit line BLO, and are driven in accordance with the discharge signals DISCHe and DISCHo so that the bias signal VIRPWR is applied to the bit line BLe. And BLo). The NMOS transistors N203 and N204 are connected between the bit lines BLe and BLo and the sensing node SO, and driven according to the bit line selection signals BSLe and BSLo, so that the NMOS transistors N203 and N204 are connected to the bit lines BLe and BLo and the sensing node ( SO) is connected.

The precharge unit 220 includes a PMOS transistor P201 connected between the voltage terminal VCC and the sensing node SO, and an NMOS transistor N205 connected between the voltage terminal VCC and the ground terminal VSS. The PMOS transistor P201 is turned on or off according to the precharge signal PRECHb to apply or block the power supply voltage VCC to the sensing node SO. The NMOS transistor N205 is turned on or off according to the precharge signal PRECHb to connect the power supply voltage VCC to the ground voltage VSS for discharge or to separate the power supply voltage VCC and the ground voltage VSS. .

The register 230 is connected between the sensing node SO and the input / output terminal YA and includes a latch 231 for temporarily storing data. A detailed configuration thereof will be described below.

The NMOS transistor N210 is connected between the node Q and the ground terminal VSS and is turned on according to the reset signal RESET so that the ground voltage VSS is applied to the node Q. Thus, node Q of latch 231 is initialized to a low level. The NMOS transistor N208 is connected between the node Qb and the input / output terminal YA, and is turned on according to the data input signal DI to connect the node Qb and the input / output terminal YA. The NMOS transistor N209 is connected between the node Q and the input / output terminal YA, and is turned on according to the inversion data input signal nDI to connect the input / output terminal YA and the node Q. The NMOS transistor N22 is connected between the node Q and the sensing node SO, and is turned on according to the program signal PGM to connect the node Q and the sensing node SO. NMOS transistor N206 and NMOS transistor N207 are connected in series between node Qb and ground terminal VSS. The NMOS transistor N206 is turned on according to the sensing node SO potential, and the NMOS transistor N207 is turned on according to the read signal READ so that the ground voltage VSS is applied to the node Qb. Thus, the potential of the node Qb is changed. The NMOS transistor N211 is connected between the node Q of the latch 231 and the input / output terminal YA and turned on according to the data output signal DO to output data stored in the latch 231 during a read operation. To pass). The PMOS transistor P202 is connected between the power supply voltage VCC and the detection signal terminal nWDO, and is turned on or off according to the potential of the node Q of the latch 231 to be connected to the detection signal terminal nWDO during the verify operation. Connect or disconnect the supply voltage VCC.

Referring to FIG. 3, the operation of the page buffer according to the present invention will be described with reference to a program operation of a flash memory device.

1) Initialization section of latch

 The reset signal RESET is applied to the NMOS transistor N210 of the register 231 so that the node Q of the latch 231 is connected to the ground VSS. Thus, node Q is initialized to the low level. For example, when programming '1' data, the data input signal DI is applied to the NMOS transistor N208 of the register 231 to connect the input / output terminal YA and the node Qb of the latch 231. . During the program operation, the node Qb becomes low level and the node Q becomes high level by the input / output terminal YA connected to the ground voltage. On the other hand, when inputting '0' data, the inverted data input signal nDI is applied to the NMOS transistor N209 to connect the input / output terminal YA and the node Q of the latch 231. Therefore, node Qb maintains a high level, and node Qb also maintains a low level.

2) Precharge section

The NMOS transistor N205 is turned off in response to the low level precharge signal PRECHb that has been added for a predetermined time. Therefore, the ground voltage VSS connected to the power supply voltage VCC is separated. In addition, the PMOS transistor P201 is turned on in response to the low level precharge signal PRECHb. Accordingly, the power supply voltage VCC is applied to the sensing node SO, and the sensing node SO is precharged to the power supply voltage VCC level. After a certain time, the precharge signal PRECHb transitions to a high level. The NMOS transistor N205 is turned on in response to the high level precharge signal PRECHb to connect the power supply voltage VCC and the ground voltage VSS. In addition, the PMOS transistor P201 is turned off in response to the high level precharge signal PRECHb. At this time, since the power supply voltage VCC is discharged by the NMOS transistor N205, the amount of leakage current by the PMOS transistor P201 is reduced.

3) Program section

In response to the low-level discharge signal DSICHe, the NMOS transistor N201 is turned off to block the bias voltage VIRPWR applied to the bit line BLe. The bit line BLe and the sensing node SO are turned on in response to the high level bit line selection signal BSLe.

The NMOS transistor N212 of the register 230 is turned on in response to the high level program signal PGM. Accordingly, the node Q and the sensing node SO are connected to transmit data stored in the latch 231 to the sensing node SO. That is, when the data stored in the latch 231 is "1", the sensing node SO maintains a high level, and when the stored data is "0", the sensing node SO transitions to a low level. The data transmitted to the sensing node SO is transferred to the memory cells of the cell array 100 through the connected bit line BLe, and the data is programmed according to a program voltage applied to the word lines of the memory cells.

In an embodiment of the present invention, the precharge portion of the page buffer has been described as an example, but it is obvious to those skilled in the art that the PMOS transistor is applicable to various circuit structures for precharging nodes.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, by discharging the power supply voltage when the precharge unit precharges the sensing node of the page buffer other than the precharge, malfunction of the circuit due to leakage current can be prevented.

Claims (3)

A bit line selection unit connected to a bit line of a memory cell array having a plurality of memory cells, and connecting the bit line and the sensing node in response to a bit line selection signal; Connected between the sensing node and a power supply voltage, and precharged by connecting the power supply voltage to the sensing node during a precharge operation, separating the power supply voltage from the sensing node and grounding the power supply voltage during an operation other than a precharge operation. A precharge unit connected to a voltage to be discharged; And And a register coupled between the sensing node and an input / output terminal, the register temporarily storing program data input through the input / output terminal during a program operation and transmitting the temporary data to the bit line through the sensing node. The method of claim 1, wherein the precharge unit A PMOS transistor coupled between the power supply voltage and the sensing node and turned on in response to a precharge signal to couple the power supply voltage to the sensing node; And And an NMOS transistor coupled between the power supply voltage and the ground voltage and turned on in response to the precharge signal to connect the power supply voltage to the ground voltage. The method of claim 2, And the precharge signal is enabled at a low level during the precharge operation and disabled at a high level during operation other than the precharge operation.

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