CN112885776A - 一种半导体器件及其制程方法 - Google Patents
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
本发明提出了一种半导体器件及其制程方法。半导体器件包括硅基板(100),多个磊晶(110),邻近两个磊晶(110)之间形成的沟道(120),栅极堆叠件(200),栅极间隔件(300),介电层(500);还包括:贯穿介电层(500)、栅极间隔件(300)并连接至磊晶(110)的第一连通孔(700),贯穿介电层(500)并连接至栅极堆叠件(200)的第二连通孔(710);连通孔孔壁上覆盖有钽基衬套、钴层衬套;钴层衬套所围的空间填充有铜填充部。本发明的半导体器件及其制程方法设计新颖,实用性强。
Description
技术领域
本发明涉及半导体生产技术领域,尤其涉及一种半导体器件及其制程方法。
背景技术
半导体中段制程(MEoL,Middle End of line)接点的电阻值对半导体器件的性能起着非常重要的作用。随着鳍式场效应晶体管(FinFET,Fin Field-Effect Transistor)通过世代缩放,半导体中段制程接点区域显著缩小,从而提高了半导体中段制程接点的电阻值。为了减轻该电阻值所带来的不良影响,需要创造一种技术对该电阻值进行减弱和控制。
发明内容
本发明针对以上技术问题,提供一种半导体器件及其制程方法。
本发明所提出的技术方案如下:
本发明提出了一种半导体器件的制程方法,包括以下步骤:
步骤S1、提供前体,所述前体包括硅基板、栅极堆叠件和栅极间隔件;硅基板上形成有多个磊晶,并在邻近两个磊晶之间形成有沟道;栅极堆叠件位于硅基板上的沟道内;栅极间隔件位于硅基板和磊晶上并环绕栅极堆叠件;
步骤S2、在栅极堆叠件和栅极间隔件上方形成介电层;依次蚀刻介电层和栅极间隔件,形成连接至磊晶的第一连通孔;蚀刻介电层,形成连接至栅极堆叠件的第二连通孔;
步骤S3、在介电层上方化学沉积金属钽,从而形成钽基层;该钽基层包括覆盖在第一连通孔孔壁上,并封闭第一连通孔的底部开口,与磊晶连接的第一钽基衬套,以及覆盖在第二连通孔孔壁上,并封闭第二连通孔的底部开口,与栅极堆叠件连接的第二钽基衬套;
步骤S4、在钽基层上方化学沉积金属钴,从而形成钴层;钴层包括覆盖在第一钽基衬套上的第一钴层衬套,以及覆盖在第二钽基衬套上的第二钴层衬套;
步骤S5、依次蚀刻钽基层和钴层,从而将介电层顶面暴露出来;然后,将金属铜填充在第一连通孔中由第一钴层衬套所围的空间,从而形成第一铜填充部;并将金属铜填充在第二连通孔中由第二钴层衬套所围的空间,从而形成第二铜填充部。
本发明上述的制程方法中,步骤S2还包括:
在栅极堆叠件和栅极间隔件上方形成金属闸极保护层,再在金属闸极保护层上方形成介电层;
依次蚀刻介电层、金属闸极保护层和栅极间隔件,形成连接至磊晶的第一连通孔;依次蚀刻介电层、金属闸极保护层,形成连接至栅极堆叠件的第二连通孔。
本发明上述的制程方法中,在步骤S5之后,还包括:
步骤S6、形成密封覆盖第一连通孔的顶部开口,用于与第一钴层衬套配合包裹第一铜填充部的第一钴帽;并形成密封覆盖第二连通孔的顶部开口,用于与第二钴层衬套配合包裹第二铜填充部的第二钴帽。
本发明还提出了一种半导体器件,包括:
硅基板,形成有多个磊晶,并在邻近两个磊晶之间形成有沟道;
栅极堆叠件,位于硅基板上的沟道内;
栅极间隔件,位于硅基板和磊晶上并环绕栅极堆叠件;
介电层,位于栅极堆叠件和栅极间隔件上方;
第一连通孔,贯穿介电层、栅极间隔件并连接至磊晶;
第二连通孔,贯穿介电层并连接至栅极堆叠件;
第一钽基衬套,覆盖在第一连通孔孔壁上,并封闭第一连通孔的底部开口,与磊晶连接;
第二钽基衬套,覆盖在第二连通孔孔壁上,并封闭第二连通孔的底部开口,与栅极堆叠件连接;
第一钴层衬套,覆盖在第一钽基衬套上;
第二钴层衬套,覆盖在第二钽基衬套上;
第一铜填充部,填充在第一连通孔中由第一钴层衬套所围的空间;
第二铜填充部,填充在第二连通孔中由第二钴层衬套所围的空间。
本发明上述的半导体器件中,还包括:
金属闸极保护层,位于栅极堆叠件和栅极间隔件上方,并处于介电层下方;
第一连通孔和第二连通孔分别贯穿金属闸极保护层。
本发明上述的半导体器件中,还包括:
第一钴帽,密封覆盖第一连通孔的顶部开口,用于与第一钴层衬套配合包裹第一铜填充部;
第二钴帽,密封覆盖第二连通孔的顶部开口,用于与第二钴层衬套配合包裹第二铜填充部。
本发明的半导体器件及其制程方法采用钽基衬套、钴层衬套以及铜填充部改变了以往半导体中段制程接点的接触形状,并在接触特性上避免了鳍式场效应晶体管世代缩放所造成的不利影响。本发明的半导体器件及其制程方法设计新颖,实用性强。
附图说明
图1示出了本发明优选实施例的半导体器件的结构示意图;
图2示出了该半导体器件的制程方法的流程的第一步骤状态示意图;
图3示出了该半导体器件的制程方法的流程的第二步骤状态示意图;
图4示出了该半导体器件的制程方法的流程的第三步骤状态示意图;
图5示出了该半导体器件的制程方法的流程的第四步骤状态示意图;
图6示出了该半导体器件的制程方法的流程的第五步骤状态示意图。
具体实施方式
本发明所要解决的技术问题是:随着鳍式场效应晶体管(FinFET,Fin Field-Effect Transistor)通过世代缩放,半导体中段制程接点区域显著缩小,从而提高了半导体中段制程接点的电阻值。为了减轻该电阻值所带来的不良影响,需要创造一种技术对该电阻值进行减弱和控制。
为了使得本发明的技术方案、技术目的以及技术效果更为清楚,以使得本领域技术人员能够理解和实施本发明,下面将结合附图及具体实施例对本发明做进一步详细的描述。
如图1所示,图1示出了本发明优选实施例的半导体器件的结构示意图。
具体地,该半导体器件包括:
硅基板100,形成有多个磊晶110,并在邻近两个磊晶110之间形成有沟道120;
栅极堆叠件200,位于硅基板100上的沟道120内;
栅极间隔件300,位于硅基板100和磊晶110上并环绕栅极堆叠件200;
介电层500,位于栅极堆叠件200和栅极间隔件300上方;
第一连通孔700,贯穿介电层500、栅极间隔件300并连接至磊晶110;
第二连通孔710,贯穿介电层500并连接至栅极堆叠件200;
第一钽基衬套610,覆盖在第一连通孔700孔壁上,并封闭第一连通孔 700的底部开口,与磊晶110连接;
第二钽基衬套620,覆盖在第二连通孔710孔壁上,并封闭第二连通孔 710的底部开口,与栅极堆叠件200连接;
第一钴层衬套630,覆盖在第一钽基衬套610上;
第二钴层衬套640,覆盖在第二钽基衬套620上;
第一铜填充部650,填充在第一连通孔700中由第一钴层衬套630所围的空间;
第二铜填充部660,填充在第二连通孔710中由第二钴层衬套640所围的空间。
在上述技术方案中,由于在20℃下,铜的电阻率为1.68×10-8Ω·m;退火处理的铜的电阻率为1.72×10-8Ω·m;钨的电阻率为5.6×10-8Ω·m;钴的电阻率为5.6×10-8Ω·m;钽的电阻率为1.3×10-7Ω·m,因此,通过采用钽基衬套和钴层衬套将铜限制在半导体中段制程接点的特性和功能范围内,并利用铜填充部作为内胆,相比于现有技术,减少设置在磊晶处的源极/漏极的电阻值。
半导体器件可以是IC的处理期间制造的中间器件或其部分,可以包括静态随机存取存储器(SRAM)和/或逻辑电路;诸如电阻器、电容器和电感器的无源组件和诸如p-型场效应晶体管(PFET)、n-型FET(NFET)、诸如 FinFET的多栅极FET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极型晶体管、高压晶体管、高频晶体管、其它存储单元和它们的组合的有源组件。
栅极堆叠件200包括界面层和界面层上方的多晶硅层,还可以包括设置在界面层和多晶硅层之间的栅极介电层和金属栅极层。在一些实施例中,栅极堆叠件200包括代替多晶硅层的一个或多个金属层。界面层可以包括诸如氧化硅(SiO2)或氮氧化硅(SiON)的介电材料,并且可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其它合适的方法形成。多晶硅层可以通过诸如低压化学汽相沉积(LPCVD)和等离子体增强 CVD(PECVD)的合适的沉积工艺形成。栅极介电层可以包括诸如氧化铪 (HfO2)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)、其它合适的金属氧化物或它们的组合的高k介电层;并且可以通过ALD和/或其它合适的方法形成。金属栅极层可以包括p-型功函金属层或n-型功函金属层。P-型功函金属层包括但是不限于从氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或它们的组合的组中选择的金属。n-型功函金属层包括但是不限于从钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)或其组合的组中选择的金属。P-型功函金属层或n-型功函金属层可以包括多个层并且可以通过CVD、PVD和/或其它合适的工艺沉积。一个或多个金属层可以包括铝(Al)、钨(W)、钴(Co)、铜(Cu)和/或其它合适的材料,并且可以通过CVD、 PVD、镀和/或其它合适的工艺形成。
介电层500分别包括金属氧化物、金属氮化物或其它合适的介电材料。例如,金属氧化物可以是氧化钛(TiO2)、氧化铝(Al2O3)或其它金属氧化物。例如,金属氮化物可以是氮化钛(TiN)、氮化铝(AlN)、氮氧化铝(AlON)、氮化钽(TaN)或其它金属氮化物。介电层500可以通过一个或多个沉积和蚀刻工艺在栅极堆叠件上方形成。
进一步地,在本发明中,半导体器件还包括:
金属闸极保护层400,位于栅极堆叠件200和栅极间隔件300上方,并处于介电层500下方;
第一连通孔700和第二连通孔710分别贯穿金属闸极保护层400。
金属闸极保护层400用于对栅极堆叠件200进行保护。
进一步地,在本发明中,半导体器件还包括:
第一钴帽800,密封覆盖第一连通孔700的顶部开口,用于与第一钴层衬套630配合包裹第一铜填充部650;
第二钴帽810,密封覆盖第二连通孔710的顶部开口,用于与第二钴层衬套640配合包裹第二铜填充部660。
进一步地,本发明还提出了上述半导体器件的制程方法,如图1-图6所示,图2示出了该半导体器件的制程方法的流程的第一步骤状态示意图;图3 示出了该半导体器件的制程方法的流程的第二步骤状态示意图;图4示出了该半导体器件的制程方法的流程的第三步骤状态示意图;图5示出了该半导体器件的制程方法的流程的第四步骤状态示意图;图6示出了该半导体器件的制程方法的流程的第五步骤状态示意图;图1作为该半导体器件的制程方法的流程的第六步骤状态示意图。该半导体器件的制程方法,包括以下步骤:
步骤S1、提供前体,所述前体包括硅基板100、栅极堆叠件200和栅极间隔件300;硅基板100上形成有多个磊晶110,并在邻近两个磊晶110之间形成有沟道120;栅极堆叠件200位于硅基板100上的沟道120内;栅极间隔件300位于硅基板100和磊晶110上并环绕栅极堆叠件200;
步骤S2、在栅极堆叠件200和栅极间隔件300上方形成介电层500;依次蚀刻介电层500和栅极间隔件300,形成连接至磊晶110的第一连通孔700;蚀刻介电层500,形成连接至栅极堆叠件200的第二连通孔710;
步骤S3、在介电层500上方化学沉积金属钽,从而形成钽基层;该钽基层包括覆盖在第一连通孔700孔壁上,并封闭第一连通孔700的底部开口,与磊晶110连接的第一钽基衬套610,以及覆盖在第二连通孔710孔壁上,并封闭第二连通孔710的底部开口,与栅极堆叠件200连接的第二钽基衬套620;
步骤S4、在钽基层上方化学沉积金属钴,从而形成钴层;钴层包括覆盖在第一钽基衬套610上的第一钴层衬套630,以及覆盖在第二钽基衬套620上的第二钴层衬套640;
步骤S5、依次蚀刻钽基层和钴层,从而将介电层500顶面暴露出来;然后,将金属铜填充在第一连通孔700中由第一钴层衬套630所围的空间,从而形成第一铜填充部650;并将金属铜填充在第二连通孔710中由第二钴层衬套640所围的空间,从而形成第二铜填充部660。
进一步地,步骤S2还包括:
在栅极堆叠件200和栅极间隔件300上方形成金属闸极保护层400,再在金属闸极保护层400上方形成介电层500;
依次蚀刻介电层500、金属闸极保护层400和栅极间隔件300,形成连接至磊晶110的第一连通孔700;依次蚀刻介电层500、金属闸极保护层400,形成连接至栅极堆叠件200的第二连通孔710;
进一步地,半导体器件的制程方法,在步骤S5之后,还包括:
步骤S6、形成密封覆盖第一连通孔700的顶部开口,用于与第一钴层衬套630配合包裹第一铜填充部650的第一钴帽800;并形成密封覆盖第二连通孔710的顶部开口,用于与第二钴层衬套640配合包裹第二铜填充部660的第二钴帽810。
本发明的半导体器件及其制程方法采用钽基衬套、钴层衬套以及铜填充部改变了以往半导体中段制程接点的接触形状,并在接触特性上避免了鳍式场效应晶体管世代缩放所造成的不利影响。本发明的半导体器件及其制程方法设计新颖,实用性强。
上面结合附图对本发明的实施例进行了描述,但是本发明并不局限于上述的具体实施方式,上述的具体实施方式仅仅是示意性的,而不是限制性的,本领域的普通技术人员在本发明的启示下,在不脱离本发明宗旨和权利要求所保护的范围情况下,还可做出很多形式,这些均属于本发明的保护之内。
Claims (6)
1.一种半导体器件的制程方法,其特征在于,包括以下步骤:
步骤S1、提供前体,所述前体包括硅基板(100)、栅极堆叠件(200)和栅极间隔件(300);硅基板(100)上形成有多个磊晶(110),并在邻近两个磊晶(110)之间形成有沟道(120);栅极堆叠件(200)位于硅基板(100)上的沟道(120)内;栅极间隔件(300)位于硅基板(100)和磊晶(110)上并环绕栅极堆叠件(200);
步骤S2、在栅极堆叠件(200)和栅极间隔件(300)上方形成介电层(500);依次蚀刻介电层(500)和栅极间隔件(300),形成连接至磊晶(110)的第一连通孔(700);蚀刻介电层(500),形成连接至栅极堆叠件(200)的第二连通孔(710);
步骤S3、在介电层(500)上方化学沉积金属钽,从而形成钽基层;该钽基层包括覆盖在第一连通孔(700)孔壁上,并封闭第一连通孔(700)的底部开口,与磊晶(110)连接的第一钽基衬套(610),以及覆盖在第二连通孔(710)孔壁上,并封闭第二连通孔(710)的底部开口,与栅极堆叠件(200)连接的第二钽基衬套(620);
步骤S4、在钽基层上方化学沉积金属钴,从而形成钴层;钴层包括覆盖在第一钽基衬套(610)上的第一钴层衬套(630),以及覆盖在第二钽基衬套(620)上的第二钴层衬套(640);
步骤S5、依次蚀刻钽基层和钴层,从而将介电层(500)顶面暴露出来;然后,将金属铜填充在第一连通孔(700)中由第一钴层衬套(630)所围的空间,从而形成第一铜填充部(650);并将金属铜填充在第二连通孔(710)中由第二钴层衬套(640)所围的空间,从而形成第二铜填充部(660)。
2.根据权利要求1所述的制程方法,其特征在于,步骤S2还包括:
在栅极堆叠件(200)和栅极间隔件(300)上方形成金属闸极保护层(400),再在金属闸极保护层(400)上方形成介电层(500);
依次蚀刻介电层(500)、金属闸极保护层(400)和栅极间隔件(300),形成连接至磊晶(110)的第一连通孔(700);依次蚀刻介电层(500)、金属闸极保护层(400),形成连接至栅极堆叠件(200)的第二连通孔(710)。
3.根据权利要求1所述的制程方法,其特征在于,在步骤S5之后,还包括:
步骤S6、形成密封覆盖第一连通孔(700)的顶部开口,用于与第一钴层衬套(630)配合包裹第一铜填充部(650)的第一钴帽(800);并形成密封覆盖第二连通孔(710)的顶部开口,用于与第二钴层衬套(640)配合包裹第二铜填充部(660)的第二钴帽(810)。
4.一种半导体器件,其特征在于,包括:
硅基板(100),形成有多个磊晶(110),并在邻近两个磊晶(110)之间形成有沟道(120);
栅极堆叠件(200),位于硅基板(100)上的沟道(120)内;
栅极间隔件(300),位于硅基板(100)和磊晶(110)上并环绕栅极堆叠件(200);
介电层(500),位于栅极堆叠件(200)和栅极间隔件(300)上方;
第一连通孔(700),贯穿介电层(500)、栅极间隔件(300)并连接至磊晶(110);
第二连通孔(710),贯穿介电层(500)并连接至栅极堆叠件(200);
第一钽基衬套(610),覆盖在第一连通孔(700)孔壁上,并封闭第一连通孔(700)的底部开口,与磊晶(110)连接;
第二钽基衬套(620),覆盖在第二连通孔(710)孔壁上,并封闭第二连通孔(710)的底部开口,与栅极堆叠件(200)连接;
第一钴层衬套(630),覆盖在第一钽基衬套(610)上;
第二钴层衬套(640),覆盖在第二钽基衬套(620)上;
第一铜填充部(650),填充在第一连通孔(700)中由第一钴层衬套(630)所围的空间;
第二铜填充部(660),填充在第二连通孔(710)中由第二钴层衬套(640)所围的空间。
5.根据权利要求4所述的半导体器件,其特征在于,还包括:
金属闸极保护层(400),位于栅极堆叠件(200)和栅极间隔件(300)上方,并处于介电层(500)下方;
第一连通孔(700)和第二连通孔(710)分别贯穿金属闸极保护层(400)。
6.根据权利要求4所述的半导体器件,其特征在于,还包括:
第一钴帽(800),密封覆盖第一连通孔(700)的顶部开口,用于与第一钴层衬套(630)配合包裹第一铜填充部(650);
第二钴帽(810),密封覆盖第二连通孔(710)的顶部开口,用于与第二钴层衬套(640)配合包裹第二铜填充部(660)。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1466190A (zh) * | 2002-06-29 | 2004-01-07 | ����ʿ�뵼������˾ | 形成铜金属线的方法 |
CN1828884A (zh) * | 2005-01-25 | 2006-09-06 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
US20110104890A1 (en) * | 2008-07-18 | 2011-05-05 | Ulvac, Inc | Method for forming cu electrical interconnection film |
US20130043539A1 (en) * | 2011-08-18 | 2013-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interlayer dielectric structure and method making the same |
CN105321810A (zh) * | 2014-07-08 | 2016-02-10 | 联华电子股份有限公司 | 制作半导体元件的方法 |
-
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1466190A (zh) * | 2002-06-29 | 2004-01-07 | ����ʿ�뵼������˾ | 形成铜金属线的方法 |
CN1828884A (zh) * | 2005-01-25 | 2006-09-06 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
US20110104890A1 (en) * | 2008-07-18 | 2011-05-05 | Ulvac, Inc | Method for forming cu electrical interconnection film |
US20130043539A1 (en) * | 2011-08-18 | 2013-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interlayer dielectric structure and method making the same |
CN105321810A (zh) * | 2014-07-08 | 2016-02-10 | 联华电子股份有限公司 | 制作半导体元件的方法 |
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