CN113284892A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN113284892A
CN113284892A CN202110417853.5A CN202110417853A CN113284892A CN 113284892 A CN113284892 A CN 113284892A CN 202110417853 A CN202110417853 A CN 202110417853A CN 113284892 A CN113284892 A CN 113284892A
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metal
metal layer
layer
gate
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CN113284892B (zh
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洪庆文
吴家荣
张宗宏
林静龄
李怡慧
黄志森
陈意维
林俊贤
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法，其中该半导体元件主要包含鳍状结构设于基底上、浅沟隔离环绕该鳍状结构、第一金属栅极设于鳍状结构上、第二金属栅极设于第一金属栅极一侧的鳍状结构边缘以及浅沟隔离上、第三金属栅极设于第一金属栅极另一侧的鳍状结构边缘以及浅沟隔离上、源极/漏极区域设于第一金属栅极两侧的基底中、层间介电层设于基底上并围绕第一金属栅极、第二金属栅极以及第三金属栅极、多个接触插塞电连接源极/漏极区域以及金属硅化物设于该多个接触插塞及源极/漏极区域之间。

Description

半导体元件及其制作方法
本申请是中国发明专利申请(申请号：201410379206.X，申请日：2014年08月04日，发明名称：制作半导体元件的方法)的分案申请。
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于形成接触洞后以两次热处理制作工艺形成金属硅化物的方法。
背景技术
在半导体集成电路的制作工艺中，金属氧化物半导体(metal-oxide-semiconductor,MOS)晶体管是一种极重要的电子元件，而随着半导体元件的尺寸越来越小，MOS晶体管的制作工艺步骤也有许多的改进，以制造出体积小而高品质的MOS晶体管。
现有的MOS晶体管制作工艺是在半导体基底上形成栅极结构之后，再于栅极结构相对两侧的基底中形成轻掺杂漏极结构(lightly doped drain,LDD)。接着于栅极结构侧边形成间隙壁(spacer)，并以此栅极结构及间隙壁作为掩模，再进行离子注入步骤，以于半导体基底中形成源极/漏极区域。而为了要将晶体管的栅极与源极/漏极区域适当电连接于电路中，因此需要形成接触插塞(contact plug)来进行导通。通常接触插塞的材质为钨(W)、铝、铜等金属导体，然其与栅极结构、源极/漏极区域等多晶或单晶硅等材质之间的直接导通并不理想；因此为了改善金属插塞与栅极结构、源极/漏极区之间的欧米接触(Ohmicontact)，通常会在栅极结构与源极/漏极区域的表面再形成一金属硅化物(silicide)。
然而，现阶段的金属硅化物制作工艺仍有许多待改进的缺点，因此如何改良现行制作工艺以提升MOS晶体管的效能即为现今一重要课题。
发明内容
本发明一实施例揭露一种半导体元件，其主要包含鳍状结构设于基底上、浅沟隔离环绕该鳍状结构、第一金属栅极设于鳍状结构上、第二金属栅极设于第一金属栅极一侧的鳍状结构边缘以及浅沟隔离上、第三金属栅极设于第一金属栅极另一侧的鳍状结构边缘以及浅沟隔离上、接触洞蚀刻停止层环绕第一金属栅极、第二金属栅极以及第三金属栅极、源极/漏极区域设于第一金属栅极两侧的基底中、层间介电层设于基底上并围绕第一金属栅极、第二金属栅极以及第三金属栅极、多个接触插塞电连接源极/漏极区域以及金属硅化物设于该多个接触插塞及源极/漏极区域之间。其中该多个接触插塞包含第一金属层与第二金属层，该第一金属层环绕该第二金属层，金属硅化物包含一C54相位的结构，金属硅化物直接接触第二金属层，接触洞蚀刻停止层位于金属硅化物上，且接触插塞的宽度与两接触洞蚀刻停止层的宽度之和等于金属硅化物的宽度。
本发明另一实施例揭露一种半导体元件，其主要包含第一金属栅极与第二金属栅极设于基底上、接触洞蚀刻停止层环绕第一金属栅极与第二金属栅极、源极/漏极区域设于邻近第一金属栅极的基底中、层间介电层设于基底上并环绕第一金属栅极与第二金属栅极、多个第一接触插塞电连接源极/漏极区域、第二接触插塞电连接第二金属栅极以及金属硅化物设于第一接触插塞及源极/漏极区域之间。其中该多个第一接触插塞包含第一金属层与第二金属层，该多个第一接触插塞的第一金属层仅设于第二金属层的两侧壁，第二接触插塞也包含该第一金属层与该第二金属层，第二接触插塞的第一金属层完整接触第二金属层的两侧壁与底表面，且金属硅化物直接接触第一接触插塞的第一金属层与第二金属层。
附图说明
图1至图8为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底
14 鳍状结构
16 绝缘层
18 金属栅极
20 金属栅极
22 金属栅极
24 间隙壁
26 源极/漏极区域
28 外延层
30 接触洞蚀刻停止层
32 层间介电层
34 功函数金属层
36 低阻抗金属层
38 硬掩模
40 介电层
42 接触洞
44 接触洞
46 预清洗制作工艺
48 第一金属层
50 第二金属层
52 金属硅化物
54 第三金属层
56 接触插塞
58 接触插塞
具体实施方式
请参照图1至图8，图1至图8为本发明较佳实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。
基底12上具有至少一鳍状结构14及一绝缘层16，其中鳍状结构14的底部被绝缘层16，例如氧化硅所包覆而形成浅沟隔离，且部分的鳍状结构14上另分别设有一金属栅极18与多个选择性设置的金属栅极20。在后续制得的晶体管元件中，鳍状结构14与金属栅极18间的重叠区域可以作为载流子流通的通道。另外在本实施例中，除了鳍状结构14上所设置的金属栅极18、20，绝缘层16上也可依据制作工艺需求而形成有其他MOS晶体管的金属栅极22穿过。
上述鳍状结构14的形成方式可以包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中。接着，对应三栅极晶体管元件及双栅极鳍状晶体管元件结构特性的不同，而可选择性去除或留下图案化掩模，并利用沉积、化学机械研磨(chemical mechanical polishing,CMP)及回蚀刻制作工艺而形成一环绕鳍状结构14底部的绝缘层16。除此之外，鳍状结构14的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出半导体层，此半导体层即可作为相对应的鳍状结构14。同样的，另可以选择性去除或留下图案化硬掩模层，并透过沉积、CMP及回蚀刻制作工艺形成一绝缘层16以包覆住鳍状结构14的底部。另外，当基底12为硅覆绝缘(SOI)基板时，则可利用图案化掩模来蚀刻基底上的一半导体层，并停止于此半导体层下方的一底氧化层以形成鳍状结构，故可省略前述制作绝缘层16的步骤。
金属栅极18、20、22的制作方式可先于鳍状结构14与绝缘层16上形成一较佳包含高介电常数介电层与多晶硅材料所构成的虚置栅极(图未示)，然后于虚置栅极侧壁形成间隙壁24。接着于间隙壁24两侧的鳍状结构14以及/或基底12中形成一源极/漏极区域26与外延层28、形成一接触洞蚀刻停止层30覆盖虚置栅极，并形成一层间介电层32于接触洞蚀刻停止层30上。
之后可进行一金属栅极置换(replacement metal gate)制作工艺，以平坦化部分的层间介电层32及接触洞蚀刻停止层30，并将虚置栅极转换为一金属栅极。金属栅极置换制作工艺可包括先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除虚置栅极中的多晶硅材料以于层间介电层32中形成一凹槽。之后形成一至少包含U型功函数金属层34与低阻抗金属层36的导电层于该凹槽内，并再搭配进行一平坦化制作工艺以形成金属栅极18、20、22。
在本实施例中，功函数金属层34较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层34可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层34可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层34与低阻抗金属层36之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层44则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极乃此领域者所熟知技术，在此不另加赘述。
形成金属栅极18、20、22后可选择性先去除部分功函数金属层34与低阻抗金属层36，然后填入一硬掩模38于功函数金属层34与低阻抗金属层36上。其中硬掩模38可为单一材料层或复合材料层，例如一包含氧化硅与氮化硅的复合层。接着平坦化后再沉积一介电层40，例如一前金属介电层(pre-metal dielectric,PMD)于层间介电层32上并覆盖金属栅极18、20、22。
然后如图2所示，进行一光刻暨蚀刻制作工艺，例如先形成一图案化光致抗蚀剂层(图未示)于介电层40上，接着进行一蚀刻制作工艺，去除部分介电层40与金属栅极18两侧的层间介电层32，以形成多个接触洞42并暴露出源极/漏极区域26上的外延层28。在本实施例中，为了制作后续与源极/漏极区域26电连接的插塞而进行的前述光刻暨蚀刻制作工艺较佳称为第零金属接触图案转移(M0CT patterning)。
接着如图3所示，进行另一光刻暨蚀刻制作工艺，例如可再形成一图案化光致抗蚀剂层(图未示)于介电层40上，然后进行一蚀刻制作工艺，去除部分介电层40与金属栅极22上方的部分介电层40、部分层间介电层32以及硬掩模38，以形成一接触洞44并暴露出金属栅极22表面。在本实施例中，为了制作后续与金属栅极22电连接的插塞而进行的前述光刻暨蚀刻制作工艺较佳称为第零金属栅极接触图案转移(M0PY patterning)。
在完成前述双重成像暨双重蚀刻(double-patterning and double-etching,2P2E)制成以形成接触洞42、44之后。随后如图4所示，进行一预清洗制作工艺46，以去除接触洞42、44内经由前述光刻暨蚀刻制作工艺后所剩余的残留物。
接着如图5所示，依序沉积一第一金属层48及第二金属层50于接触洞42、44中，其中第一金属层48与第二金属层50较佳共形地(conformally)形成于介电层40与外延层28的表面及各接触洞42、44的内侧侧壁。在本实施例中，第一金属层48较佳选自钛、钴、镍及铂等所构成的群组，且最佳为钛，而第二金属层50则较佳包含氮化钛、氮化钽等金属化合物。
在连续沉积第一金属层48与第二金属层50之后，然后如图6所示，依序进行一第一热处理制作工艺与一第二热处理制作工艺以形成一金属硅化物52于外延层28上。在本实施例中，第一热处理制作工艺包含一常温退火(soak anneal)制作工艺，其温度较佳介于500℃至600℃，且最佳为550℃，而其处理时间则较佳介于10秒至60秒，且最佳为30秒。第二热处理制作工艺包含一峰值退火(spike anneal)制作工艺，其温度较佳介于600℃至950℃，且最佳为600℃，而其处理较佳时间则较佳介于100毫秒至5秒，且最佳为5秒。
待进行两次热处理制作工艺后，如图7所示，形成一第三金属层54并填满接触洞42、44。在本实施例中，第三金属层54较佳包含钨，但不局限于此。
最后如图8所示，进行一平坦化制作工艺，例如以化学机械研磨(chemicalmechanical polishing,CMP)制作工艺部分去除第三金属层54、部分第二金属层50及部分第一金属层48，甚至可视制作工艺需求接着去除部分介电层40，以形成多个接触插塞56分别电连接源极/漏极区域26以及接触插塞58电连接金属栅极22。至此即完成本发明较佳实施例制作一鳍状场效晶体管的流程。
依据本发明的优选实施例，图6所进行的两次热处理制作工艺较佳将第一金属层48转化为一金属硅化物52。更具体而言，第一次热处理制作工艺较佳将第一金属层48接触外延层28的部分完全转换为具有C49相位的二硅化钛(TiSi2)金属硅化物。而在经过第二次热处理后，C49相位的金属硅化物会进而转换为阻值较低且具有C54相位的金属硅化物。需注意的是，由于仅有与外延层28接触的第一金属层48会转化为金属硅化物52，亦即位于接触洞42底部的第一金属层48会完全转化为金属硅化物52，因此未与外延层28接触的第一金属层48在经过两次热处理制作工艺后将不会被转化为金属硅化物52，且仍以原始金属层型态设于接触洞42、44侧壁。同样地，在接触洞44内，与金属栅极22接触的第一金属层48，在经过两次热处理制作工艺后亦仍为原始金属层型态，而不会被转化为金属硅化物52。
其次，由于第二金属层50较佳用来避免第三金属层54的金属原子扩散至周围的材料层中并同时增加第三金属层54与介电层40之间的附着力，因此从头到尾均未反应为金属硅化物52。以结构来看，经过两次热处理制作工艺后的第二金属层50较佳同时覆盖于金属硅化物52上以及未反应并设于接触洞42、44侧壁的第一金属层48上。
请再参照图8，本发明另揭露一种半导体元件结构，其包含一基底12、至少一金属栅极18设于基底12上、一鳍状结构14设于基底12与金属栅极18之间、一源极/漏极区域26设于邻近金属栅极18的基底12中、一层间介电层32设于基底12上并围绕金属栅极18、多个接触插塞56电连接源极/漏极区域26以及一金属硅化物52设于接触插塞56与源极/漏极区域26之间。依据本发明的较佳实施例，金属硅化物52包含一C54相位的结构。而与金属栅极22相接触的接触插塞58中仍具有二层完整的第一金属层48与第二金属层50。
此外，半导体元件另包含一外延层28设于金属硅化物52与源极/漏极区域26之间，接触插塞56包含一第一金属层48环绕一第二金属层50及一第三金属层54，且第二金属层50较佳直接接触金属硅化物52。在本实施例中，第一金属层48是选自由钛、钴、镍及铂所构成的群组，第二金属层50包含氮化钛，第三金属层54包含钨，但不局限于此。
综上所述，本发明主要揭露一种鳍状场效晶体管(FinFET)制作工艺，其较佳于形成金属栅极与接触洞后(post contact)依序以两道热处理制作工艺将接触洞中的金属层形成金属硅化物并由此晶体管的整体效能。更具体而言，本发明较佳于形成接触洞后先依序沉积一第一金属层与第二金属层于接触洞内，然后利用第一道热处理制作工艺将接触外延层或源极/漏极区域等含硅区域的第一金属层转换为C49相位的金属硅化物，接着再利用第二道热处理制作工艺将已形成的金属硅化物再次转换为阻值较低且具有C54相位的金属硅化物。之后在不去除任何未反应第一金属层的情况下直接将一第三金属层填入接触洞内，并搭配化学机械研磨制作工艺去除部分第三金属层、第二金属层及第一金属层以形成多个接触插塞电连接源极/漏极区域及金属栅极。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (9)

1.一种半导体元件，其特征在于，包含：
鳍状结构，设于基底上；
浅沟隔离，环绕该鳍状结构；
第一金属栅极，设于该鳍状结构上；
第二金属栅极，设于该第一金属栅极一侧的该鳍状结构边缘以及该浅沟隔离上；
第三金属栅极，设于该第一金属栅极另一侧的该鳍状结构边缘以及该浅沟隔离上；
接触洞蚀刻停止层，环绕该第一金属栅极、该第二金属栅极以及该第三金属极；
源极/漏极区域，设于该第一金属栅极两侧的该基底中；
层间介电层，设于该基底上并围绕该第一金属栅极、该第二金属栅极以及该第三金属栅极；
多个接触插塞，电连接该源极/漏极区域，该多个接触插塞包含第一金属层与第二金属层，且该第一金属层环绕该第二金属层；以及
金属硅化物，设于该多个接触插塞及该源极/漏极区域之间，其中该金属硅化物包含C54相位的结构，该金属硅化物直接接触该第二金属层，该接触洞蚀刻停止层位于该金属硅化物上，且该接触插塞的宽度与两接触洞蚀刻停止层的宽度之和等于金属硅化物的宽度。
2.如权利要求1所述的半导体元件，另包含外延层设于该金属硅化物与该源极/漏极区域之间。
3.如权利要求1所述的半导体元件，其中该等接触插塞包含第三金属层，且该第一金属层环绕该第三金属层。
4.如权利要求3所述的半导体元件，其中该第一金属层选自由钛、钴、镍及铂所构成的群组，该第二金属层包含氮化钛，该第三金属层包含钨。
5.一种半导体元件，其特征在于，包含：
第一金属栅极与第二金属栅极，设于基底上；
接触洞蚀刻停止层，环绕该第一金属栅极与该第二金属栅极；
源极/漏极区域，设于邻近该第一金属栅极的该基底中；
层间介电层，设于该基底上并环绕该第一金属栅极与该第二金属栅极；
多个第一接触插塞，电连接该源极/漏极区域，该多个第一接触插塞包含第一金属层与第二金属层，且该第一金属层仅设于该第二金属层的两侧壁；
第二接触插塞，电连接该第二金属栅极，该第二接触插塞包含该第一金属层与该第二金属层，且该第一金属层接触该第二金属层的两侧壁与底表面；以及
金属硅化物，设于该第一接触插塞及该源极/漏极区域之间，其中该金属硅化物直接接触该第一接触插塞的该第一金属层。
6.如权利要求5所述的半导体元件，另包含：
鳍状结构，设于该基底上；以及
浅沟隔离，环绕该鳍状结构，其中该第一金属栅极设于该鳍状结构上且该第二金属栅极设于该浅沟隔离上。
7.如权利要求5所述的半导体元件，其中各该第一接触插塞与该第二接触插塞包含第三金属层，且该第一金属层环绕该第三金属层。
8.如权利要求7所述的半导体元件，其中该第一金属层选自由钛、钴、镍及铂所构成的群组，该第二金属层包含氮化钛，该第三金属层包含钨。
9.如权利要求5所述的半导体元件，其中该金属硅化物直接接触该第一接触插塞的该第二金属层。
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