TW201913747A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

Info

Publication number
TW201913747A
TW201913747A TW106128223A TW106128223A TW201913747A TW 201913747 A TW201913747 A TW 201913747A TW 106128223 A TW106128223 A TW 106128223A TW 106128223 A TW106128223 A TW 106128223A TW 201913747 A TW201913747 A TW 201913747A
Authority
TW
Taiwan
Prior art keywords
layer
contact hole
etch stop
stop layer
hole etch
Prior art date
Application number
TW106128223A
Other languages
English (en)
Other versions
TWI728174B (zh
Inventor
許得彰
陳俊嘉
王堯展
黃俊仁
Original Assignee
聯華電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW106128223A priority Critical patent/TWI728174B/zh
Priority to US15/710,820 priority patent/US10777657B2/en
Publication of TW201913747A publication Critical patent/TW201913747A/zh
Priority to US16/985,242 priority patent/US11742412B2/en
Application granted granted Critical
Publication of TWI728174B publication Critical patent/TWI728174B/zh
Priority to US18/218,599 priority patent/US20230352565A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明揭露一種製作半導體元件的方法，其主要先形成一閘極結構於一基底上，然後形成側壁子於閘極結構周圍，形成第一接觸洞蝕刻停止層於側壁子周圍，形成一遮罩層於第一接觸洞蝕刻停止層上，去除部分該遮罩層，去除部分第一接觸洞蝕刻停止層，形成第二接觸洞蝕刻停止層於遮罩層以及閘極結構上，最後再去除部分第二接觸洞蝕刻停止層。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種於側壁子旁形成兩層接觸洞蝕刻停止層的方法。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
一般而言，傳統平面型金屬閘極電晶體通常採用離子佈植的方式來同時調整電晶體的臨界電壓。然而隨著場效電晶體(field effect transistors, FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。然而現今鰭狀場效電晶體的製程中，當施加於介電材料上的電場強度超過臨界值時，若流過該介電材料電流突然增大容易使介電材料完全失效而產生所謂的時間相依介電崩潰(time-dependent dielectric breakdown, TDDB)問題。因此如何在鰭狀電晶體的架構下改良此缺點即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法，其主要先形成一閘極結構於一基底上，然後形成側壁子於閘極結構周圍，形成第一接觸洞蝕刻停止層於側壁子周圍，形成一遮罩層於第一接觸洞蝕刻停止層上，去除部分該遮罩層，去除部分第一接觸洞蝕刻停止層，形成第二接觸洞蝕刻停止層於遮罩層以及閘極結構上，最後再去除部分第二接觸洞蝕刻停止層。
本發明另一實施例揭露一種半導體元件，其主要包含：一閘極結構設於基底上、側壁子環繞閘極結構、第一接觸洞蝕刻停止層環繞側壁子以及第二接觸洞蝕刻停止層環繞側壁子並設於第一接觸洞蝕刻停止層上。
請參照第1圖至第8圖，第1圖至第8圖為本發明一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離。需注意的是，本實施例雖以製作非平面型場效電晶體(non-planar)例如鰭狀結構場效電晶體為例，但不侷限於此，本發明又可應用至一般平面型(planar)場效電晶體，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構14較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構14之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著可於基底12上形成至少一閘極結構或虛置閘極，例如閘極結構16以及閘極結構18。在本實施例中，閘極結構16、18之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一由多晶矽所構成之閘極材料層、一第一硬遮罩以及一第二硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分第二硬遮罩、部分第一硬遮罩、部分閘極材料層以及部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層20、圖案化之閘極材料層22、圖案化之第一硬遮罩24以及圖案化之第二硬遮罩26所構成的閘極結構16、18。
在本實施例中，第一硬遮罩24與第二硬遮罩26較佳包含不同材料，例如第一硬遮罩24較佳包含氮化矽而第二硬遮罩26較佳包含氧化矽，但均不限於此。另外需注意的是，本實施例雖於鰭狀結構14上形成兩個閘極結構16、18為例，但閘極結構的數量並不侷限於此，而可視產品需求任意調整。
然後在閘極結構16、18側壁分別形成至少一側壁子28，接著於側壁子28兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域34及/或磊晶層，並選擇性於源極/汲極區域34及/或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，側壁子28可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子30以及一主側壁子32。其中偏位側壁子30與主側壁子28可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域34可依據所置備電晶體的導電型式而包含不同摻質與磊晶材料，例如NMOS區域的源極/汲極區域34可包含碳化矽(SiC)或磷化矽(SiP)而PMOS區域的源極/汲極區域34可包含鍺化矽(SiGe)，但均不限於此。
接著形成一第一接觸洞蝕刻停止層36於鰭狀結構14表面與閘極結構16上。在本實施例中，第一接觸洞蝕刻停止層36較佳由低介電常數材料所構成，其較佳包含氮碳氧化矽(SiOCN)，但不侷限於此。
如第2圖所示，然後形成一遮罩層38於第一接觸洞蝕刻停止層36上。在本實施例中，遮罩層38較佳由氧化矽所構成，但不侷限於此。
如第3圖所示，接著進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分遮罩層38並使遮罩層38上表面切齊閘極結構16、18或第一接觸洞蝕刻停止層36上表面。
隨後如第4圖所示，進行一蝕刻製程再次去除部分遮罩層38並使遮罩層38上表面低於閘極結構16、18上表面，或更具體而言利用蝕刻去除部分遮罩層38並使遮罩層38上表面低於各閘極結構16、18中的閘極材料層22或閘極電極上表面。在本實施例中，可在不形成其他圖案化遮罩的情況下直接利用遮罩層38與第一接觸洞蝕刻停止層36之間的選擇比來去除部分遮罩層38，其中蝕刻製程可利用稀釋氫氟酸(diluted hydrofluoric acid, dHF)或SiCoNi製程來達成。補充說明的是：SiCoNi製程主要是利用含氟氣體和氧化矽反應生成氟矽酸銨((NH4 )2 SiF6 )，來選擇性移除原生氧化矽，其中前述含氟氣體可包含氟化氫(HF)或三氟化氮(NF3 )。
如第5圖所示，然後進行一蝕刻製程去除部分第一接觸洞蝕刻停止層36，使剩餘的第一接觸洞蝕刻停止層36形成約略側壁子的半月形，其中剩餘的第一接觸洞蝕刻停止層36頂部較佳略低於各閘極結構16、18中的閘極材料層22上表面並可同時略高於遮罩層38上表面或切齊遮罩層38上表面(圖未示)。在本實施例中，用來去除部分第一接觸洞蝕刻停止層36的蝕刻製程可包含例如四氟化碳(CF4 )等蝕刻氣體成分，但不侷限於此。
如第6圖所示，接著形成一第二接觸洞蝕刻停止層40於遮罩層38以及閘極結構16、18上。在本實施例中，第一接觸洞蝕刻停止層36與第二接觸洞蝕刻停止層40較佳包含不同介電常數之材料，或更具體而言第一接觸洞蝕刻停止層36之介電常數較佳低於第二接觸洞蝕刻停止層40之介電常數。在本實施例中，第一接觸洞蝕刻停止層36較佳由例如氮碳氧化矽所構成而第二接觸洞蝕刻停止層40則較佳利用較高射頻功率(RF power)形成具有較少氫鍵的氮化矽所構成，其中第一接觸洞蝕刻停止層36的介電常數較佳介於4-5，第二接觸洞蝕刻停止層40的介電常數則介於7-8。
然後如第7圖所示，進行一蝕刻製程去除部分第二接觸洞蝕刻停止層40，使剩餘的第二接觸洞蝕刻停止層40形成約略側壁子的半月形於閘極結構16、18側壁。在本實施例中，用來去除部分第二接觸洞蝕刻停止層40的蝕刻製程可包含溴化氫(HBr)、CF4 、或其組合，但不侷限於此。
如第8圖所示，隨後進行一金屬閘極置換製程將閘極結構16、18轉換為金屬閘極。舉例來說，可先形成一介電層42於遮罩層38上並覆蓋閘極結構16、18。然後進行一平坦化製程，例如利用化學機械研磨去除部分介電層42、第二硬遮罩26以及第一硬遮罩24並暴露出各閘極結構16、18中的閘極材料層22，使閘極材料層22上表面與介電層42上表面齊平。在本實施例中，介電層42與遮罩層38可一同構成一層間介電層44，其中介電層42與遮罩層38可包含相同或不同材料，例如兩者均可由氧化矽所構成，但不侷限於此。
之後進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極材料層22甚至選擇性去除閘極介電層20，以於層間介電層44中形成凹槽(圖未示)。之後依序形成另一閘極介電層或介質層46、一高介電常數介電層48、一功函數金屬層50以及一低阻抗金屬層52於凹槽內，然後進行一平坦化製程，例如利用CMP去除部分低阻抗金屬層52、部分功函數金屬層50與部分高介電常數介電層48以形成金屬閘極54、56。
隨後可去除部分低阻抗金屬層52、部分功函數金屬層50以及部分高介電常數介電層48以形成凹槽(圖未示)，再填入一由例如氮化矽所構成的硬遮罩58於凹槽內並使硬遮罩58上表面切齊層間介電層44上表面。以本實施例利用後高介電常數介電層製程所製作的閘極結構為例，所形成的金屬閘極56、58各包含一介質層46或閘極介電層、一U型高介電常數介電層48、一U型功函數金屬層50以及一低阻抗金屬層52。
在本實施例中，高介電常數介電層48包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶（strontium titanate oxide, SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。
功函數金屬層50較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層50可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層50可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層50與低阻抗金屬層52之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層52則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
之後可進行一圖案轉移製程，例如可利用一圖案化遮罩去除金屬閘極54、56旁的部分的層間介電層44以及部分第一接觸洞蝕刻停止層36以形成複數個接觸洞(圖未示)並暴露出下面的源極/汲極區域34。然後再於各接觸洞中填入所需的金屬材料，例如包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等的阻障層材料以及選自鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合的低阻抗金屬層。之後進行一平坦化製程，例如以化學機械研磨去除部分金屬材料以分別形成接觸插塞60於各接觸洞內電連接源極/汲極區域34。至此即完成本發明較佳實施例之半導體元件的製作。
請再參照第8圖，第8圖為本發明一實施例之一半導體元件之結構示意圖。如第8圖所示，半導體元件主要包含至少一閘極結構如金屬閘極54設於鰭狀結構14上、一硬遮罩58設於金屬閘極54上、一側壁子28環繞金屬閘極54、一第一接觸洞蝕刻停止層36環繞並接觸側壁子28、一第二接觸洞蝕刻停止層40環繞並接觸側壁子28且設於第一接觸洞蝕刻停止層36上以及一層間介電層44環繞金屬閘極54且層間介電層44上表面切齊硬遮罩58以及第二接觸洞蝕刻停止層40上表面。
從細部來看，第一接觸洞蝕刻停止層36上表面較佳低於金屬閘極54上表面，第一接觸洞蝕刻停止層36與第二接觸洞蝕刻停止層40較佳包含不同材料或具有不同介電常數之材料，或更具體而言第一接觸洞蝕刻停止層36之介電常數較佳低於第二接觸洞蝕刻停止層40之介電常數。在本實施例中，第一接觸洞蝕刻停止層36較佳由例如氮碳氧化矽所構成而第二接觸洞蝕刻停止層40則較佳利用較高射頻功率(RF power)形成具有較少氫鍵的氮化矽所構成，其中第一接觸洞蝕刻停止層36的介電常數較佳介於4-5，第二接觸洞蝕刻停止層40的介電常數則介於7-8。
一般而言，現今鰭狀場效電晶體的製程中若於閘極結構側壁設置由低介電常數材料所構成的接觸洞蝕刻停止層可改善電阻電容延遲效應(RC delay)的問題，但同時也會使所謂時間相依介電崩潰(time-dependent dielectric breakdown, TDDB)現象亦趨嚴重。為了改善此問題，本發明特別於閘極結構或側壁子側壁設置由兩種不同材料所構成的接觸洞蝕刻停止層，其中設置於下層的第一接觸洞蝕刻停止層較佳由較低介電常數的材料例如氮碳氧化矽所構成，而設於上層的第二接觸洞蝕刻停止層則較佳由較高介電常數的材料例如氮化矽所構成。藉由將兩種不同介電常數的材料分別設置於相對應側壁子的下半部側壁與上半部側壁，本發明可同時改善上述RC delay以及TDDB等問題並提升元件的整體效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧閘極結構
18‧‧‧閘極結構
20‧‧‧閘極介電層
22‧‧‧閘極材料層
24‧‧‧第一硬遮罩
26‧‧‧第二硬遮罩
28‧‧‧側壁子
30‧‧‧偏位側壁子
32‧‧‧主側壁子
34‧‧‧源極/汲極區域
36‧‧‧第一接觸洞蝕刻停止層
38‧‧‧遮罩層
40‧‧‧第二接觸洞蝕刻停止層
42‧‧‧介電層
44‧‧‧層間介電層
46‧‧‧介質層
48‧‧‧高介電常數介電層
50‧‧‧功函數金屬層
52‧‧‧低阻抗金屬層
54‧‧‧金屬閘極
56‧‧‧金屬閘極
58‧‧‧硬遮罩
60‧‧‧接觸插塞
第1圖至第8圖為本發明一實施例製作一半導體元件之方法示意圖。

Claims (18)

  1. 一種製作半導體元件的方法，包含： 形成一閘極結構於一基底上； 形成一側壁子於該閘極結構周圍； 形成一第一接觸洞蝕刻停止層於該側壁子周圍；以及 形成一第二接觸洞蝕刻停止層於該側壁子旁並設於該第一接觸洞蝕刻停止層上。
  2. 如申請專利範圍第1項所述之方法，包含： 形成該第一接觸洞蝕刻停止層於該閘極結構上； 形成一遮罩層於該第一接觸洞蝕刻停止層上； 去除部分該遮罩層； 去除部分該第一接觸洞蝕刻停止層； 形成該第二接觸洞蝕刻停止層於該遮罩層以及該閘極結構上；以及 去除部分該第二接觸洞蝕刻停止層。
  3. 如申請專利範圍第2項所述之方法，其中去除部分該遮罩層之步驟包含： 進行一平坦化製程去除部分該遮罩層並使該遮罩層上表面切齊該閘極結構上表面；以及 進行一蝕刻製程去除部分該遮罩層並使該遮罩層上表面低於該閘極結構上表面。
  4. 如申請專利範圍第2項所述之方法，其中該第一接觸洞蝕刻停止層高於該遮罩層上表面。
  5. 如申請專利範圍第2項所述之方法，其中該閘極結構包含一閘極材料層、一第一硬遮罩設於該閘極材料層上以及一第二硬遮罩設於該第一硬遮罩上，該方法包含： 去除部分該遮罩層並使該遮罩層上表面低於該閘極材料層上表面。
  6. 如申請專利範圍第5項所述之方法，其中該第二接觸洞蝕刻停止層下表面低於該閘極材料層上表面。
  7. 如申請專利範圍第1項所述之方法，另包含於形成該第二接觸洞蝕刻停止層之後進行一金屬閘極置換製程將該閘極結構轉換為金屬閘極。
  8. 如申請專利範圍第1項所述之方法，另包含於形成該第一接觸洞蝕刻停止層之前形成一源極/汲極區域於該側壁子兩側之該基底內。
  9. 如申請專利範圍第1項所述之方法，其中該第一接觸洞蝕刻停止層以及該第二接觸洞蝕刻停止層包含不同介電常數。
  10. 如申請專利範圍第1項所述之方法，其中該第一接觸洞蝕刻停止層之介電常數低於該第二接觸洞蝕刻停止層之介電常數。
  11. 一種半導體元件，包含： 一閘極結構設於一基底上； 一側壁子環繞該閘極結構； 一第一接觸洞蝕刻停止層環繞該側壁子；以及 一第二接觸洞蝕刻停止層環繞該側壁子並設於該第一接觸洞蝕刻停止層上。
  12. 如申請專利範圍第11項所述之半導體元件，其中該閘極結構包含一金屬閘極以及一硬遮罩設於該金屬閘極上。
  13. 如申請專利範圍第12項所述之半導體元件，另包含一層間介電層環繞該閘極結構，其中該層間介電層上表面切齊該硬遮罩上表面。
  14. 如申請專利範圍第12項所述之半導體元件，其中該層間介電層上表面切齊該第二接觸洞蝕刻停止層上表面。
  15. 如申請專利範圍第12項所述之半導體元件，其中該第一接觸洞蝕刻停止層上表面低於該金屬閘極上表面。
  16. 如申請專利範圍第11項所述之半導體元件，另包含一源極/汲極區域設於該側壁子兩側之該基底內。
  17. 如申請專利範圍第11項所述之半導體元件，其中該第一接觸洞蝕刻停止層以及該第二接觸洞蝕刻停止層包含不同介電常數。
  18. 如申請專利範圍第11項所述之半導體元件，其中該第一接觸洞蝕刻停止層之介電常數低於該第二接觸洞蝕刻停止層之介電常數。
TW106128223A 2017-08-21 2017-08-21 半導體元件及其製作方法 TWI728174B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW106128223A TWI728174B (zh) 2017-08-21 2017-08-21 半導體元件及其製作方法
US15/710,820 US10777657B2 (en) 2017-08-21 2017-09-20 Metal gate transistor with a stacked double sidewall spacer structure
US16/985,242 US11742412B2 (en) 2017-08-21 2020-08-05 Method for fabricating a metal gate transistor with a stacked double sidewall spacer structure
US18/218,599 US20230352565A1 (en) 2017-08-21 2023-07-06 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106128223A TWI728174B (zh) 2017-08-21 2017-08-21 半導體元件及其製作方法

Publications (2)

Publication Number Publication Date
TW201913747A true TW201913747A (zh) 2019-04-01
TWI728174B TWI728174B (zh) 2021-05-21

Family

ID=65361388

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106128223A TWI728174B (zh) 2017-08-21 2017-08-21 半導體元件及其製作方法

Country Status (2)

Country Link
US (3) US10777657B2 (zh)
TW (1) TWI728174B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216468B (zh) * 2017-06-29 2021-08-13 中芯国际集成电路制造(上海)有限公司 电阻器件及其制造方法
CN114446883A (zh) * 2017-09-22 2022-05-06 蓝枪半导体有限责任公司 半导体元件及其制作方法
US10510555B2 (en) * 2017-09-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanism for manufacturing semiconductor device
US10381459B2 (en) * 2018-01-09 2019-08-13 Globalfoundries Inc. Transistors with H-shaped or U-shaped channels and method for forming the same
US10629739B2 (en) * 2018-07-18 2020-04-21 Globalfoundries Inc. Methods of forming spacers adjacent gate structures of a transistor device
CN115565878A (zh) * 2021-07-02 2023-01-03 联华电子股份有限公司 半导体元件及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194302B1 (en) 1999-09-30 2001-02-27 Taiwan Semiconductor Manufacturing Company Integrated process flow to improve the electrical isolation within self aligned contact structure
US6420250B1 (en) * 2000-03-03 2002-07-16 Micron Technology, Inc. Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates
DE102004026149B4 (de) * 2004-05-28 2008-06-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen eines Halbleiterbauelements mit Transistorelementen mit spannungsinduzierenden Ätzstoppschichten
US7488659B2 (en) * 2007-03-28 2009-02-10 International Business Machines Corporation Structure and methods for stress concentrating spacer
US8664102B2 (en) * 2010-03-31 2014-03-04 Tokyo Electron Limited Dual sidewall spacer for seam protection of a patterned structure
US8637941B2 (en) * 2010-11-11 2014-01-28 International Business Machines Corporation Self-aligned contact employing a dielectric metal oxide spacer
US8617973B2 (en) * 2011-09-28 2013-12-31 GlobalFoundries, Inc. Semiconductor device fabrication methods with enhanced control in recessing processes
US9034701B2 (en) 2012-01-20 2015-05-19 International Business Machines Corporation Semiconductor device with a low-k spacer and method of forming the same
US8975673B2 (en) * 2012-04-16 2015-03-10 United Microelectronics Corp. Method of trimming spacers and semiconductor structure thereof
CN105225937B (zh) * 2014-06-30 2018-03-30 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US9601593B2 (en) * 2014-08-08 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
TWI633669B (zh) * 2014-12-26 2018-08-21 聯華電子股份有限公司 半導體元件及其製程
CN106920771B (zh) * 2015-12-28 2020-03-10 中芯国际集成电路制造(北京)有限公司 金属栅晶体管源漏区接触塞的制作方法

Also Published As

Publication number Publication date
US20190058050A1 (en) 2019-02-21
US20200365710A1 (en) 2020-11-19
US10777657B2 (en) 2020-09-15
TWI728174B (zh) 2021-05-21
US20230352565A1 (en) 2023-11-02
US11742412B2 (en) 2023-08-29

Similar Documents

Publication Publication Date Title
CN106803484B (zh) 半导体元件及其制作方法
TWI722073B (zh) 半導體元件及其製作方法
CN106684041B (zh) 半导体元件及其制作方法
TWI728174B (zh) 半導體元件及其製作方法
TWI716601B (zh) 半導體元件及其製作方法
TWI804632B (zh) 半導體元件及其製作方法
TWI729181B (zh) 半導體元件及其製作方法
US11901239B2 (en) Semiconductor device and method for fabricating the same
US11239082B2 (en) Method for fabricating semiconductor device
TW202002017A (zh) 半導體元件及其製作方法
CN112436004A (zh) 半导体元件及其制作方法
CN110828377B (zh) 一种具有不对称功函数金属层的半导体元件
US11552181B2 (en) Semiconductor device and method for fabricating the same
TWI821535B (zh) 一種製作半導體元件的方法
US20230411489A1 (en) Semiconductor device and method for fabricating the same
CN109545747B (zh) 半导体元件及其制作方法
TW202401662A (zh) 半導體元件及其製作方法
CN115910786A (zh) 半导体元件及其制作方法
TW202015112A (zh) 半導體元件及其製作方法
CN118039468A (zh) 半导体元件及其制作方法