US20230352565A1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- US20230352565A1 US20230352565A1 US18/218,599 US202318218599A US2023352565A1 US 20230352565 A1 US20230352565 A1 US 20230352565A1 US 202318218599 A US202318218599 A US 202318218599A US 2023352565 A1 US2023352565 A1 US 2023352565A1
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 description 1
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- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Definitions
- the invention relates to a method for fabricating semiconductor device, and more particularly, to a method for forming dual contact etch stop layers (CESLs) adjacent to the spacer.
- CTLs dual contact etch stop layers
- polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors.
- MOS metal-oxide-semiconductor
- the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices.
- work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers.
- threshold voltage in conventional planar metal gate transistors is adjusted by the means of ion implantation.
- MOS metal oxide semiconductor transistors
- three-dimensional or non-planar transistor technology such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors.
- FinFET fin field effect transistor technology
- TDDB time-dependent dielectric breakdown
- a method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
- CESL contact etch stop layer
- a semiconductor device includes: a gate structure on a substrate; a spacer around the gate structure; a first contact etch stop layer (CESL) around the spacer; and a second CESL around the spacer and on the first CESL.
- CESL contact etch stop layer
- FIGS. 1 - 8 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention.
- FIGS. 1 - 8 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention.
- a substrate 12 such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, and at least a transistor region such as a NMOS region or a PMOS region are defined on the substrate 12 .
- a fin-shaped structure 14 is formed on the substrate 12 , in which the bottom of the fin-shaped structure 14 is surrounded by an insulating layer or shallow trench isolation (STI) made of material including but not limited to for example silicon oxide.
- STI shallow trench isolation
- the fin-shaped structure 14 could be obtained by a sidewall image transfer (SIT) process.
- a layout pattern is first input into a computer system and is modified through suitable calculation.
- the modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process.
- a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers.
- sacrificial layers can be removed completely by performing an etching process.
- the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.
- the fin-shaped structure 14 could also be obtained by first forming a patterned mask (not shown) on the substrate, 12 , and through an etching process, the pattern of the patterned mask is transferred to the substrate 12 to form the fin-shaped structure.
- the formation of the fin-shaped structure could also be accomplished by first forming a patterned hard mask (not shown) on the substrate 12 , and a semiconductor layer composed of silicon germanium is grown from the substrate 12 through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structure.
- gate structures 16 and 18 are formed on the fin-shaped structure 14 .
- the formation of the gate structures 16 and 18 could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process.
- a gate dielectric layer or interfacial layer, a gate material layer made of polysilicon, a first hard mask, and a second hard mask could be formed sequentially on the substrate 12 , and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the second hard mask, part of the first hard mask, part of the gate material layer, and part of the gate dielectric layer through single or multiple etching processes.
- gate structures 16 and 18 each composed of a patterned gate dielectric layer 20 , a patterned material layer 22 , a patterned first hard mask 24 , and a patterned second hard mask 26 are formed on the fin-shaped structure 14 .
- the first hard mask 24 and the second hard mask 26 are preferably made of different material, in which the first hard mask 24 preferably includes silicon nitride while the second hard mask 26 preferably includes silicon oxide, but not limited thereto. It should also be noted that even though two gate structures 16 and 18 are formed on the fin-shaped structure 14 in this embodiment, the quantity of the gate structures could also be adjusted depending on the demand of the product.
- a spacer 28 is formed on the sidewalls of the each of the gate structure 16 and 18 , a source/drain region 34 and/or epitaxial layer (not shown) is formed in the fin-shaped structure 14 adjacent to two sides of the spacer 28 , and selective silicide layers (not shown) could be formed on the surface of the source/drain regions 34 .
- the spacer 28 could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer 30 and a main spacer 32 .
- the offset spacer 30 and the main spacer 32 could include same material or different material while both the offset spacer 30 and the main spacer 32 could be made of material including but not limited to for example SiO 2 , SiN, SiON, SiCN, or combination thereof.
- the source/drain region 34 could include dopants and epitaxial material of different conductive type depending on the type of device being fabricated.
- the source/drain region 34 on NMOS region could include SiC or SiP while the source/drain region 34 on PMOS region could include SiGe, but not limited thereto.
- a first contact etch stop layer (CESL) 36 is formed on the surface of the fin-shaped structure 14 and the gate structure 16 .
- the first CESL is preferably made of low-k material including but not limited to for example SiOCN.
- a mask layer 38 is formed on the first CESL 36 .
- the mask layer 38 is made of dielectric material including but not limited to for example silicon oxide.
- a planarizing process such as a chemical mechanical polishing (CMP) process is conducted to remove part of the mask layer 38 so that the top surface of the mask layer 38 is even with the top surface of the gate structures 16 , 18 or the top surface of the first CESL 36 .
- CMP chemical mechanical polishing
- an etching process is conducted to remove part of the mask layer 38 so that the top surface of the mask layer 38 is lower than the top surface of the gate structures 16 and 18 , or more specifically the top surface of the mask layer 38 is removed to be lower than the top surface of the gate material layer 22 or gate electrode in the gate structures 16 , 18 .
- the SiCoNi process is commonly conducted by reacting fluorine-containing gas with silicon oxide to form ((NH 4 ) 2 SiF 6 ) thereby removing native oxide, in which the fluorine-containing gas could include HF or NF 3 .
- an etching process is conducted to remove part of the first CESL 36 so that the remaining portion of the first CESL 36 directly contacting the main spacer 32 becomes slightly spacer shaped and a top surface of the remaining first CESL 36 is slightly lower than the top surface of the gate material layer 22 of each of the gate structures 16 , 18 and slightly higher than the top surface of the mask layer 38 as shown in FIG. 5 or even coplanar with the top surface of the mask layer 38 .
- the etching process used to remove part of the first CESL 36 could include gas such as but not limited to for example CF 4 .
- a second CESL 40 is formed on the mask layer 38 and the gate structures 16 , 18 .
- the first CESL 36 and the second CESL 40 preferably include different material and/or different dielectric constant, and the dielectric constant of the first CESL 36 is specifically lower than the dielectric constant of the second CESL 40 .
- the first CESL 36 is preferably made of low-k SiOCN and the second CESL 40 is made of silicon nitride fabricated through higher radio-frequency (RF) power thereby having less hydrogen bond.
- RF radio-frequency
- the dielectric constant of the first CESL 36 is between 4-5 and the dielectric constant of the second CESL 40 is between 7-8.
- an etching process is conducted to remove part of the second CESL 40 so that the remaining second CESL 40 becomes slightly spacer shaped on the sidewall of the main spacer 32 while sitting on top of the first CESL 36 .
- the etching process used to remove part of the second CESL 40 could include gas such as but not limited to for example HBr, CF 4 , or combination thereof.
- a replacement metal gate (RMG) process is conducted to transform the gate structures 16 , 18 into metal gates.
- a dielectric layer 42 could be formed on the mask layer 38 to cover the gate structures 16 , 18 , and a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the dielectric layer 42 , the second hard mask 26 , and the first hard mask 24 to expose the gate material layer 22 of each of the gate structures 16 , 18 so that the top surfaces of the gate material layer 22 and the dielectric layer 42 are coplanar.
- CMP chemical mechanical polishing
- the dielectric layer 42 and the mask layer 38 could constitute an interlayer dielectric (ILD) layer 44 altogether, in which the dielectric layer 42 and the mask layer 38 could be made of same material such as silicon oxide or different material, which are all within the scope of the present invention.
- ILD interlayer dielectric
- etchants including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 22 and even gate dielectric layer 20 for forming a recess (not shown) in the ILD layer 44 .
- etchants including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 22 and even gate dielectric layer 20 for forming a recess (not shown) in the ILD layer 44 .
- a gate dielectric layer or interfacial layer 46 , a high-k dielectric layer 48 , a work function metal layer 50 , and a low resistance metal layer 52 are formed in the recess, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer 52 , part of work function metal layer 50 , and part of high-k dielectric layer 48 to form metal gates 54 , 56 .
- each of the gate structure or metal gates 56 , 58 fabricated through high-k last process of a gate last process preferably includes an interfacial layer 46 or gate dielectric layer, a U-shaped high-k dielectric layer 48 , a U-shaped work function metal layer 50 , and a low resistance metal layer 52 .
- the high-k dielectric layer 48 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4.
- the high-k dielectric layer 48 may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), barium strontium titanate (
- the work function metal layer 50 is formed for tuning the work function of the metal gate in accordance with the conductivity of the device.
- the work function metal layer 50 having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto.
- the work function metal layer 50 having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto.
- An optional barrier layer (not shown) could be formed between the work function metal layer 50 and the low resistance metal layer 52 , in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN).
- the material of the low-resistance metal layer 52 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.
- a photo-etching process is conducted by using a patterned mask (not shown) as mask to remove part of the ILD layer 44 adjacent to the metal gates 54 , 56 for forming contact holes (not shown) exposing the source/drain region 34 underneath.
- metals including a barrier layer selected from the group consisting of Ti, TiN, Ta, and TaN and a low resistance metal layer selected from the group consisting of W, Cu, Al, TiAl, and CoWP are deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of aforementioned barrier layer and low resistance metal layer for forming contact plugs 60 electrically connecting the source/drain region 34 .
- FIG. 8 further illustrates a structural view of a semiconductor device according to an embodiment of the present invention.
- the semiconductor device includes a gate structure such as metal gate 54 on the fin-shaped structure 14 , a hard mask 58 on the metal gate 54 , a spacer 28 around the metal gate 54 , a first CESL 36 around and contacting the spacer 28 , a second CESL 40 around and contacting the spacer 28 and sitting on top of the first CESL 36 , and a ILD layer 48 around the metal gate 54 , in which the top surface of the ILD layer 44 is even with the top surfaces of the hard mask 58 and the second CESL 40 .
- the top surface of the first CESL 36 is slightly lower than the top surface of the metal gate 54
- the first CESL 36 and the second CESL 40 are preferably made of different material and/or having different dielectric constant
- the dielectric constant of the first CESL 36 is preferably lower than the dielectric constant of the second CESL 40
- the first CESL 36 is preferably made of SiOCN while the second CESL 40 is made of silicon nitride fabricated through higher RF power thereby having less hydrogen bond.
- the dielectric constant of the first CESL 36 is between 4-5 and the dielectric constant of the second CESL 40 is between 7-8.
- the present invention specifically forms CESL made of two different material on the sidewalls of the gate structure or spacer, in which the first CESL on the lower level is preferably made of low-k material such as SiOCN while the second CESL on the higher level is made of material having higher dielectric constant such as SiN.
Abstract
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
Description
- This application is a continuation application of U.S. application Ser. No. 16/985,242, filed on Aug. 5, 2020, which is a division of U.S. application Ser. No. 15/710,820, filed on Sep. 20, 2017. The contents of these applications are incorporated herein by reference.
- The invention relates to a method for fabricating semiconductor device, and more particularly, to a method for forming dual contact etch stop layers (CESLs) adjacent to the spacer.
- In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers.
- Typically, threshold voltage in conventional planar metal gate transistors is adjusted by the means of ion implantation. With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Nevertheless, when electrical field applied onto a dielectric material exceeds a threshold value, a sudden increase in the electrical current passing through the dielectric material would easily induce a time-dependent dielectric breakdown (TDDB) issue. Hence, how to resolve this issue in today's FinFET architecture has become an important task in this field.
- According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
- According to another aspect of the present invention, a semiconductor device includes: a gate structure on a substrate; a spacer around the gate structure; a first contact etch stop layer (CESL) around the spacer; and a second CESL around the spacer and on the first CESL.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-8 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. - Referring to
FIGS. 1-8 ,FIGS. 1-8 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown inFIG. 1 , asubstrate 12, such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, and at least a transistor region such as a NMOS region or a PMOS region are defined on thesubstrate 12. Next, at least a fin-shaped structure 14 is formed on thesubstrate 12, in which the bottom of the fin-shaped structure 14 is surrounded by an insulating layer or shallow trench isolation (STI) made of material including but not limited to for example silicon oxide. It should be noted that even though this embodiment pertains to the fabrication of a non-planar FET device such as FinFET device, it would also be desirable to apply the following processes to a planar FET device, which is also within the scope of the present invention. - According to an embodiment of the present invention, the fin-
shaped structure 14 could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained. - Alternatively, the fin-
shaped structure 14 could also be obtained by first forming a patterned mask (not shown) on the substrate, 12, and through an etching process, the pattern of the patterned mask is transferred to thesubstrate 12 to form the fin-shaped structure. Moreover, the formation of the fin-shaped structure could also be accomplished by first forming a patterned hard mask (not shown) on thesubstrate 12, and a semiconductor layer composed of silicon germanium is grown from thesubstrate 12 through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structure. These approaches for forming fin-shaped structure are all within the scope of the present invention. - Next, at least a gate structures or dummy gate such as
gate structures shaped structure 14. In this embodiment, the formation of thegate structures substrate 12, and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the second hard mask, part of the first hard mask, part of the gate material layer, and part of the gate dielectric layer through single or multiple etching processes. After stripping the patterned resist,gate structures dielectric layer 20, a patternedmaterial layer 22, a patterned firsthard mask 24, and a patterned secondhard mask 26 are formed on the fin-shaped structure 14. - In this embodiment, the first
hard mask 24 and the secondhard mask 26 are preferably made of different material, in which the firsthard mask 24 preferably includes silicon nitride while the secondhard mask 26 preferably includes silicon oxide, but not limited thereto. It should also be noted that even though twogate structures shaped structure 14 in this embodiment, the quantity of the gate structures could also be adjusted depending on the demand of the product. - Next, at least a
spacer 28 is formed on the sidewalls of the each of thegate structure drain region 34 and/or epitaxial layer (not shown) is formed in the fin-shaped structure 14 adjacent to two sides of thespacer 28, and selective silicide layers (not shown) could be formed on the surface of the source/drain regions 34. In this embodiment, thespacer 28 could be a single spacer or a composite spacer, such as a spacer including but not limited to for example anoffset spacer 30 and amain spacer 32. Preferably, theoffset spacer 30 and themain spacer 32 could include same material or different material while both theoffset spacer 30 and themain spacer 32 could be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof. The source/drain region 34 could include dopants and epitaxial material of different conductive type depending on the type of device being fabricated. For example, the source/drain region 34 on NMOS region could include SiC or SiP while the source/drain region 34 on PMOS region could include SiGe, but not limited thereto. - Next, a first contact etch stop layer (CESL) 36 is formed on the surface of the fin-
shaped structure 14 and thegate structure 16. In this embodiment, the first CESL is preferably made of low-k material including but not limited to for example SiOCN. - Next, as shown
FIG. 2 , amask layer 38 is formed on the first CESL 36. Preferably, themask layer 38 is made of dielectric material including but not limited to for example silicon oxide. - Next, as shown in
FIG. 3 , a planarizing process such as a chemical mechanical polishing (CMP) process is conducted to remove part of themask layer 38 so that the top surface of themask layer 38 is even with the top surface of thegate structures first CESL 36. - Next, as shown in
FIG. 4 , an etching process is conducted to remove part of themask layer 38 so that the top surface of themask layer 38 is lower than the top surface of thegate structures mask layer 38 is removed to be lower than the top surface of thegate material layer 22 or gate electrode in thegate structures mask layer 38 and the first CESL 36 to remove part of themask layer 38 without forming any patterned mask, in which the etching process could be accomplished by the involvement of diluted hydrofluoric acid (dHF) or SiCoNi process. It is to be noted that the SiCoNi process is commonly conducted by reacting fluorine-containing gas with silicon oxide to form ((NH4)2SiF6) thereby removing native oxide, in which the fluorine-containing gas could include HF or NF3. - Next, as shown in
FIG. 5 , an etching process is conducted to remove part of thefirst CESL 36 so that the remaining portion of thefirst CESL 36 directly contacting themain spacer 32 becomes slightly spacer shaped and a top surface of the remainingfirst CESL 36 is slightly lower than the top surface of thegate material layer 22 of each of thegate structures mask layer 38 as shown inFIG. 5 or even coplanar with the top surface of themask layer 38. In this embodiment, the etching process used to remove part of the first CESL 36 could include gas such as but not limited to for example CF4. - Next, as shown in
FIG. 6 , a second CESL 40 is formed on themask layer 38 and thegate structures first CESL 36 and thesecond CESL 40 preferably include different material and/or different dielectric constant, and the dielectric constant of thefirst CESL 36 is specifically lower than the dielectric constant of thesecond CESL 40. In this embodiment, the first CESL 36 is preferably made of low-k SiOCN and the second CESL 40 is made of silicon nitride fabricated through higher radio-frequency (RF) power thereby having less hydrogen bond. Preferably, the dielectric constant of thefirst CESL 36 is between 4-5 and the dielectric constant of thesecond CESL 40 is between 7-8. - Next, as shown in
FIG. 7 , an etching process is conducted to remove part of thesecond CESL 40 so that the remainingsecond CESL 40 becomes slightly spacer shaped on the sidewall of themain spacer 32 while sitting on top of thefirst CESL 36. In this embodiment, the etching process used to remove part of thesecond CESL 40 could include gas such as but not limited to for example HBr, CF4, or combination thereof. - Next, as shown in
FIG. 8 , a replacement metal gate (RMG) process is conducted to transform thegate structures dielectric layer 42 could be formed on themask layer 38 to cover thegate structures dielectric layer 42, the secondhard mask 26, and the firsthard mask 24 to expose thegate material layer 22 of each of thegate structures gate material layer 22 and thedielectric layer 42 are coplanar. In this embodiment, thedielectric layer 42 and themask layer 38 could constitute an interlayer dielectric (ILD)layer 44 altogether, in which thedielectric layer 42 and themask layer 38 could be made of same material such as silicon oxide or different material, which are all within the scope of the present invention. - Next, a selective dry etching or wet etching process is conducted by using etchants including but not limited to for example ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the
gate material layer 22 and evengate dielectric layer 20 for forming a recess (not shown) in theILD layer 44. Next, a gate dielectric layer orinterfacial layer 46, a high-k dielectric layer 48, a workfunction metal layer 50, and a lowresistance metal layer 52 are formed in the recess, and a planarizing process such as CMP is conducted to remove part of lowresistance metal layer 52, part of workfunction metal layer 50, and part of high-k dielectric layer 48 to formmetal gates - Next, part of the low
resistance metal layer 52, part of the workfunction metal layer 50, and part of the high-k dielectric layer 48 are removed to form another recess (not shown), and ahard mask 58 made of dielectric material including but not limited to for example silicon nitride is deposited into each recess so that the top surfaces of thehard mask 58 andILD layer 44 are coplanar. In this embodiment, each of the gate structure ormetal gates interfacial layer 46 or gate dielectric layer, a U-shaped high-k dielectric layer 48, a U-shaped workfunction metal layer 50, and a lowresistance metal layer 52. - In this embodiment, the high-
k dielectric layer 48 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer 48 may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof. - In this embodiment, the work
function metal layer 50 is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the workfunction metal layer 50 having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the workfunction metal layer 50 having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the workfunction metal layer 50 and the lowresistance metal layer 52, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer 52 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof. - Next, a photo-etching process is conducted by using a patterned mask (not shown) as mask to remove part of the
ILD layer 44 adjacent to themetal gates drain region 34 underneath. Next, metals including a barrier layer selected from the group consisting of Ti, TiN, Ta, and TaN and a low resistance metal layer selected from the group consisting of W, Cu, Al, TiAl, and CoWP are deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of aforementioned barrier layer and low resistance metal layer for forming contact plugs 60 electrically connecting the source/drain region 34. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention. - Referring again to
FIG. 8 ,FIG. 8 further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG. 8 , the semiconductor device includes a gate structure such asmetal gate 54 on the fin-shapedstructure 14, ahard mask 58 on themetal gate 54, aspacer 28 around themetal gate 54, afirst CESL 36 around and contacting thespacer 28, asecond CESL 40 around and contacting thespacer 28 and sitting on top of thefirst CESL 36, and aILD layer 48 around themetal gate 54, in which the top surface of theILD layer 44 is even with the top surfaces of thehard mask 58 and thesecond CESL 40. - Viewing from a more detailed perspective, the top surface of the
first CESL 36 is slightly lower than the top surface of themetal gate 54, thefirst CESL 36 and thesecond CESL 40 are preferably made of different material and/or having different dielectric constant, and the dielectric constant of thefirst CESL 36 is preferably lower than the dielectric constant of thesecond CESL 40. In this embodiment, thefirst CESL 36 is preferably made of SiOCN while thesecond CESL 40 is made of silicon nitride fabricated through higher RF power thereby having less hydrogen bond. Preferably, the dielectric constant of thefirst CESL 36 is between 4-5 and the dielectric constant of thesecond CESL 40 is between 7-8. - It has been commonly observed that if a CESL made of low-k dielectric material were formed on the sidewalls of the gate structure during FinFET process problem such as RC delay could be improved. This however brings out another drawback such as the time-dependent dielectric breakdown (TDDB) issue. In order to resolve these two issues at the same time, the present invention specifically forms CESL made of two different material on the sidewalls of the gate structure or spacer, in which the first CESL on the lower level is preferably made of low-k material such as SiOCN while the second CESL on the higher level is made of material having higher dielectric constant such as SiN. By forming CESL made of materials having different dielectric constant on the corresponding lower sidewalls and upper sidewalls of the spacer, both issues including RC delay and TDDB could be resolved simultaneously.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (11)
1. A method for fabricating semiconductor device, comprising:
forming a gate structure on a substrate;
forming a spacer around the gate structure, wherein the spacer comprises:
an offset spacer adjacent to the gate structure; and
a main spacer adjacent to the offset spacer;
forming a first contact etch stop layer (CESL) around the spacer and on and directly contacting the substrate; and
forming a second CESL around the spacer and on and directly contacting the offset spacer, the main spacer, and the first CESL.
2. The method of claim 1 , further comprising:
forming the first CESL on the gate structure;
forming a mask layer on the first CESL;
removing part of the mask layer;
removing part of the first CESL;
forming the second CESL on the mask layer and the gate structure; and
removing part of the second CESL.
3. The method of claim 2 , wherein the step of remove part of the mask layer comprises:
performing a planarizing process to remove part of the mask layer so that the top surfaces of the mask layer and the first CESL are coplanar; and
performing an etching process to remove part of the mask layer so that the top surface of the mask layer is lower than a top surface of the gate structure.
4. The method of claim 2 , wherein a top surface of the first CESL is higher than a top surface of the mask layer.
5. The method of claim 2 , wherein the gate structure comprises a gate material layer, a first hard mask on the gate material layer, and a second hard mask on the first hard mask, the method further comprising:
removing part of the mask layer so that the top surface of the mask layer is lower than a top surface of the gate material layer.
6. The method of claim 5 , wherein a bottom surface of the second CESL is lower than a top surface of the gate material layer.
7. The method of claim 1 , further comprising performing a replacement metal gate (RMG) process to transform the gate structure into metal gate after forming the second CESL.
8. The method of claim 1 , further comprising forming a source/drain region adjacent to two sides of the spacer in the substrate before forming the first CESL.
9. The method of claim 1 , wherein the first CESL and the second CESL comprise different material.
10. The method of claim 1 , wherein the first CESL and the second CESL comprise different dielectric constant.
11. The method of claim 1 , wherein a dielectric constant of the first CESL is lower than a dielectric constant of the second CESL.
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US15/710,820 US10777657B2 (en) | 2017-08-21 | 2017-09-20 | Metal gate transistor with a stacked double sidewall spacer structure |
US16/985,242 US11742412B2 (en) | 2017-08-21 | 2020-08-05 | Method for fabricating a metal gate transistor with a stacked double sidewall spacer structure |
US18/218,599 US20230352565A1 (en) | 2017-08-21 | 2023-07-06 | Semiconductor device and method for fabricating the same |
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CN109545784A (en) | 2017-09-22 | 2019-03-29 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
US10510555B2 (en) * | 2017-09-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanism for manufacturing semiconductor device |
US10381459B2 (en) * | 2018-01-09 | 2019-08-13 | Globalfoundries Inc. | Transistors with H-shaped or U-shaped channels and method for forming the same |
US10629739B2 (en) | 2018-07-18 | 2020-04-21 | Globalfoundries Inc. | Methods of forming spacers adjacent gate structures of a transistor device |
CN115565878A (en) * | 2021-07-02 | 2023-01-03 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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US6194302B1 (en) | 1999-09-30 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Integrated process flow to improve the electrical isolation within self aligned contact structure |
US6420250B1 (en) * | 2000-03-03 | 2002-07-16 | Micron Technology, Inc. | Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates |
DE102004026149B4 (en) * | 2004-05-28 | 2008-06-26 | Advanced Micro Devices, Inc., Sunnyvale | A method of producing a semiconductor device having transistor elements with voltage-inducing etch stop layers |
US7488659B2 (en) * | 2007-03-28 | 2009-02-10 | International Business Machines Corporation | Structure and methods for stress concentrating spacer |
US8664102B2 (en) * | 2010-03-31 | 2014-03-04 | Tokyo Electron Limited | Dual sidewall spacer for seam protection of a patterned structure |
US8637941B2 (en) * | 2010-11-11 | 2014-01-28 | International Business Machines Corporation | Self-aligned contact employing a dielectric metal oxide spacer |
US8617973B2 (en) * | 2011-09-28 | 2013-12-31 | GlobalFoundries, Inc. | Semiconductor device fabrication methods with enhanced control in recessing processes |
US9034701B2 (en) | 2012-01-20 | 2015-05-19 | International Business Machines Corporation | Semiconductor device with a low-k spacer and method of forming the same |
US8975673B2 (en) * | 2012-04-16 | 2015-03-10 | United Microelectronics Corp. | Method of trimming spacers and semiconductor structure thereof |
CN105225937B (en) * | 2014-06-30 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
US9601593B2 (en) * | 2014-08-08 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
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