CN114446883A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN114446883A
CN114446883A CN202210020249.3A CN202210020249A CN114446883A CN 114446883 A CN114446883 A CN 114446883A CN 202210020249 A CN202210020249 A CN 202210020249A CN 114446883 A CN114446883 A CN 114446883A
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contact hole
layer
stop layer
etch stop
hole etch
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CN202210020249.3A
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许得彰
陈俊嘉
王尧展
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Blue Gun Semiconductor Co ltd
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Blue Gun Semiconductor Co ltd
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Priority to CN202210020249.3A priority Critical patent/CN114446883A/zh
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法为，首先形成一栅极结构于一基底上，然后形成一接触洞蚀刻停止层于栅极结构上，形成一层间介电层于接触洞蚀刻停止层上，之后进行一固化制作工艺使接触洞蚀刻停止层的氧浓度不同于层间介电层的氧浓度，并再进行一金属栅极置换制作工艺将该栅极结构转换为金属栅极。

Description

半导体元件及其制作方法
本申请是申请日为2017年9月22日、申请号为201710865297.1、发明名称为“半导体元件及其制作方法”的发明专利申请的分案申请。
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种形成层间介电层之后利用固化制作工艺来降低栅极结构与源极/漏极区域间的重叠电容值(capacitanceoverlap,Cov)的方法。
背景技术
在现有半导体产业中，多晶硅系广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boron penetration)效应导致元件效能降低，及其难以避免的空乏效应(depletion effect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(work function)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
然而，在现今金属栅极晶体管制作过程中，由于间隙壁与接触洞蚀刻停止层等元件通常均由具有较高介电常数的材料所构成，使栅极结构与源极/漏极区域之间的重叠电容值(capacitance overlap,Cov)无法控制在一较佳的范围内，进而影响元件效能。因此如何改良现今制作工艺以解决上述问题即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法。首先形成一栅极结构于一基底上，然后形成一接触洞蚀刻停止层于栅极结构上，形成一层间介电层于接触洞蚀刻停止层上，之后进行一固化制作工艺使接触洞蚀刻停止层的氧浓度不同于层间介电层的氧浓度，并再进行一金属栅极置换制作工艺将该栅极结构转换为金属栅极。
本发明又一实施例公开一种半导体元件，其主要包含一栅极结构设于基底上，一间隙壁环绕栅极结构，一接触洞蚀刻停止层设于间隙壁旁以及一层间介电层环绕该接触洞蚀刻停止层，其中该接触洞蚀刻停止层的氧浓度不同于该层间介电层的氧浓度。
附图说明
图1至图5为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 栅极结构 18 栅极介电层
20 栅极材料层 22 第一硬掩模
24 第二硬掩模 26 间隙壁
28 偏位间隙壁 30 主间隙壁
32 源极/漏极区域 34 外延层
36 接触洞蚀刻停止层 38 层间介电层
40 栅极介电层 42 高介电常数介电层
44 功函数金属层 46 低阻抗金属层
48 金属栅极 50 硬掩模
52 接触插塞
具体实施方式
请参照图1至图5，图1至图5为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上可定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。基底12上具有至少一鳍状结构14及一绝缘层(图未示)，其中鳍状结构14的底部被绝缘层，例如氧化硅所包覆而形成浅沟隔离。需注意的是，本实施例虽以制作非平面型场效晶体管(non-planar)例如鳍状结构场效晶体管为例，但不局限于此，本发明又可应用至一般平面型(planar)场效晶体管，此实施例也属本发明所涵盖的范围。
依据本发明一实施例，鳍状结构14较佳通过侧壁图案转移(sidewall imagetransfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构。另外，鳍状结构的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构。这些形成鳍状结构的实施例均属本发明所涵盖的范围。
接着可于基底12上形成至少一栅极结构16或虚置栅极。在本实施例中，栅极结构16的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先依序形成一栅极介电层18或介质层、一由多晶硅所构成的栅极材料层20、一第一硬掩模22以及第二硬掩模24于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分第二硬掩模24、部分第一硬掩模22、部分栅极材料层20以及部分栅极介电层18，然后剥除图案化光致抗蚀剂，以于基底12上形成由图案化的栅极介电层18、图案化的栅极材料层20、图案化的第一硬掩模22以及图案化的第二硬掩模24所构成的栅极结构16。
然后在栅极结构16侧壁形成至少一间隙壁26，于间隙壁26两侧的鳍状结构14以及/或基底12中形成一源极/漏极区域32及/或外延层34，选择性于源极/漏极区域32及/或外延层34的表面形成一金属硅化物(图未示)，并形成一接触洞蚀刻停止层36于基底12表面以及栅极结构16上。在本实施例中，间隙壁26可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁28以及一主间隙壁30。其中偏位间隙壁28与主间隙壁30可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅(SiON)以及氮碳化硅(SiCN)所构成的群组。源极/漏极区域32可依据所置备晶体管的导电型式而包含不同掺质，例如可包含P型掺质或N型掺质。接触洞蚀刻停止层36则较佳包含氮化硅或氮碳化硅，但均不局限于此。
然后如图2所示，先形成一由二氧化硅或氧碳化硅(silicon oxycarbide,SiOC)所构成的层间介电层38于接触洞蚀刻停止层36上，再进行一固化制作工艺来提升主间隙壁30的强度。从细部来看，本实施例所进行的固化制作工艺较佳为一极紫外光(extremeultraviolet,EUV)固化制作工艺，其中固化制作工艺较佳在进行紫外光照射的同时通入臭氧(O3)并搭配进行一热处理制作工艺，由此改变间隙壁26以及接触洞蚀刻停止层36的介电常数并同时降低栅极结构16与源极/漏极区域32之间所产生的重叠电容值(capacitanceoverlap,Cov)。
值得注意的是，本实施例的主间隙壁30以及接触洞蚀刻停止层36在进行固化制作工艺之前较佳由介电常数较高的材料所构成，例如主间隙壁30以及接触洞蚀刻停止层36均较佳由氮碳化硅(SiCN)所构成。由于本实施例在进行上述固化制作工艺时主要通过热处理将臭氧中的氧原子驱入主间隙壁30、接触洞蚀刻停止层36以及层间介电层38内，因此主间隙壁30、接触洞蚀刻停止层36以及层间介电层38等在进行极紫外光固化制作工艺后较佳转换为较低介电常数的材料。更具体而言，原本由氮碳化硅所构成的主间隙壁30以及接触洞蚀刻停止层36在驱入氧原子后较佳转换为介电常数更低的氮碳氧化硅(SiOCN)而由氧碳化硅(silicon oxycarbide,SiOC)所构成的层间介电层38则维持原本材料。
此外，主间隙壁30、接触洞蚀刻停止层36以及层间介电层38等三者的介电常数也会在固化制作工艺的过程中略为调整。举例来说，原本介电常数约5.0且由氮碳化硅所构成的主间隙壁30较佳转换为介电常数约4.6的氮碳氧化硅，原本介电常数约5.0或略高于5.0且由氮碳化硅所构成的接触洞蚀刻停止层36较佳转换为介电常数约4.6的氮碳氧化硅，而原本介电常数约4.6且由氧碳化硅所构成的层间介电层则维持相同材料与介电常数。换句话说，原本分别具有不同介电常数的主间隙壁30、接触洞蚀刻停止层36以及层间介电层38等三者在经过前述固化制作工艺后较佳转换为具有相同介电常数但可能不同材质的材料。原本例如由氮碳化硅所构成的偏位间隙壁28由于所在位置较靠近栅极结构16且在固化过程中较不会被驱入氧原子而降低介电常数，因此其介电常数值在固化制作工艺后仍较佳略高于主间隙壁30的介电常数，例如约5.0。
另外前述实施例虽以主间隙壁30以及接触洞蚀刻停止层36由氮碳化硅所构成为例，但不局限于此，依据本发明一实施例，主间隙壁30以及接触洞蚀刻停止层36的其中一者或两者在进行固化制作工艺之前又可选择由介电常数约6.5的氮化硅所构成，而在此情况下，主间隙壁30与接触洞蚀刻停止层36在进行固化制作工艺驱入氧原子后较佳分别由氮化硅转换为氮氧化硅(SiON)，且两者的介电常数在经由固化制作工艺降低后可约略等于层间介电层38的介电常数值，此实施例也属本发明所涵盖的范围。
此外，从另一角度来看，由于本实施例在进行上述固化制作工艺时较佳利用热处理制作工艺将臭氧中的氧原子驱入主间隙壁30、接触洞蚀刻停止层36以及层间介电层38内，因此进行固化制作工艺后接触洞蚀刻停止层36的氧浓度较佳不同于层间介电层38的氧浓度，例如层间介电层38的氧浓度在固化制作工艺后较佳高于接触洞蚀刻停止层36的氧浓度，或从更细部来看，位于接触洞蚀刻停止层36表面的氧浓度又较佳高于接触洞蚀刻停止层36内部的氧浓度。
在本实施例中，紫外光固化制作工艺中热处理的温度较佳介于摄氏500度至摄氏800度，固化制作工艺的压力较佳介于1托(Torr)至760托，而固化制作工艺的时间则介于50分钟至70分钟或最佳约60分钟。
如图3所示，然后进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)去除部分层间介电层32以及部分接触洞蚀刻停止层30并暴露出第二硬掩模24，使各第二硬掩模24上表面与层间介电层32上表面齐平。值得注意的是，本实施例虽较佳于平坦化制作工艺前进行前述固化制作工艺，但不局限于此顺序，依据本发明一实施例又可选择在平坦化制作工艺之后，例如使第二硬掩模24上表面切齐层间介电层38上表面之后才进行前述的固化制作工艺，此实施例也属本发明所涵盖的范围。
如图4所示，随后进行一金属栅极置换制作工艺将各栅极结构16转换为金属栅极。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构16中的第二硬掩模24、第一硬掩模22、栅极材料层20甚至栅极介电层18，以于层间介电层38中形成凹槽(图未示)。之后依序形成一选择性介质层或栅极介电层40、一高介电常数介电层42、一功函数金属层44以及一低阻抗金属层46于凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层46、部分功函数金属层44与部分高介电常数介电层42以形成由金属栅极48所构成的栅极结构。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，各金属栅极48较佳包含一介质层或栅极介电层40、一U型高介电常数介电层42、一U型功函数金属层44以及一低阻抗金属层46。
在本实施例中，高介电常数介电层42包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层44较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层44可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层44可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层44与低阻抗金属层46之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层46则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
随后如图5所示，可去除部分低阻抗金属层46、部分功函数金属层44以及部分高介电常数介电层42以形成凹槽(图未示)，再填入一由例如氮化硅所构成的硬掩模50于凹槽内并使硬掩模50上表面切齐层间介电层38上表面。
之后可进行一图案转移制作工艺，例如可利用一图案化掩模去除金属栅极48旁的部分的层间介电层38以及部分接触洞蚀刻停止层36以形成多个接触洞(图未示)并暴露出下面的源极/漏极区域32。然后再于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。之后进行一平坦化制作工艺，例如以化学机械研磨去除部分金属材料以分别形成接触插塞52于各接触洞内电连接源极/漏极区域32。至此即完成本发明优选实施例的半导体元件的制作。
请继续参照图5，图5另公开本发明一半导体元件的结构示意图。如图5所示，半导体元件主要包含一栅极结构或金属栅极48设于基底12或鳍状结构14上、间隙壁26环绕栅极结构、接触洞蚀刻停止层36设于间隙壁26旁以及层间介电层38环绕接触洞蚀刻停止层36，其中间隙壁26又细部包含一偏位间隙壁28以及一主间隙壁30。
在本实施例中，由于依据前述在固化制作工艺的过程中利用热处理将氧原子驱入主间隙壁30、接触洞蚀刻停止层36以及层间介电层38内，因此接触洞蚀刻停止层36的氧浓度较佳不同于层间介电层38的氧浓度，或更具体而言层间介电层38的氧浓度较佳高于接触洞蚀刻停止层36的氧浓度，且接触洞蚀刻停止层36表面的氧浓度又高于接触洞蚀刻停止层36内部的氧浓度。
此外，若从介电常数值的观点来看，接触洞蚀刻停止层36以及层间介电层38在固化制作工艺后均较佳具有相同介电常数，或依据本发明一实施例主侧壁30、接触洞蚀刻停止层36以及层间介电层38在固化制作工艺后均转换成相同介电常数。偏位间隙壁28的介电常数在固化制作工艺后则较佳大于主侧壁30、接触洞蚀刻停止层36以及层间介电层38。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种制作半导体元件的方法，包含：
形成一栅极结构于一基底上；
形成一层间介电层于该栅极结构周围；
进行一固化制作工艺；以及
进行一金属栅极置换制作工艺将该栅极结构转换为金属栅极。
2.如权利要求1所述的方法，还包含：
形成一接触洞蚀刻停止层于该栅极结构上；
形成该层间介电层于该接触洞蚀刻停止层上；
进行该固化制作工艺并使该接触洞蚀刻停止层的氧浓度不同于该层间介电层的氧浓度。
3.如权利要求2所述的方法，其中该层间介电层的氧浓度高于该接触洞蚀刻停止层的氧浓度。
4.如权利要求2所述的方法，其中该接触洞蚀刻停止层表面的氧浓度高于该接触洞蚀刻停止层内的氧浓度。
5.如权利要求1所述的方法，还包含进行该固化制作工艺，并使该接触洞蚀刻停止层以及该层间介电层具有相同介电常数。
6.如权利要求1所述的方法，另包含形成一间隙壁于该栅极结构周围，其中该间隙壁包含一偏位间隙壁以及一主间隙壁。
7.如权利要求6所述的方法，还包含进行该固化制作工艺使该主侧壁、该接触洞蚀刻停止层以及该层间介电层具有相同介电常数。
8.如权利要求1所述的方法，还包含：
进行一平坦化制作工艺去除部分该层间介电层；以及
进行该金属栅极置换制作工艺。
9.如权利要求1所述的方法，其中该固化制作工艺的温度介于摄氏500度至摄氏800度。
10.如权利要求1所述的方法，其中该固化制作工艺的时间介于50分钟至70分钟。
11.一种半导体元件，包含：
栅极结构，设于一基底上；
间隙壁，环绕该栅极结构；
接触洞蚀刻停止层，设于该间隙壁旁；以及
层间介电层，环绕该接触洞蚀刻停止层，其中该接触洞蚀刻停止层的氧浓度不同于该层间介电层的氧浓度。
12.如权利要求11所述的半导体元件，其中该层间介电层的氧浓度高于该接触洞蚀刻停止层的氧浓度。
13.如权利要求11所述的半导体元件，其中该接触洞蚀刻停止层表面的氧浓度高于该接触洞蚀刻停止层内的氧浓度。
14.如权利要求11所述的半导体元件，其中该接触洞蚀刻停止层以及该层间介电层具有相同介电常数。
15.如权利要求11所述的半导体元件，其中该间隙壁包含一偏位间隙壁以及一主间隙壁。
16.如权利要求15所述的半导体元件，其中该主侧壁、该接触洞蚀刻停止层以及该层间介电层具有相同介电常数。
17.如权利要求15所述的半导体元件，其中该主间隙壁以及该接触洞蚀刻停止层包含相同材料。
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