WO2022061738A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022061738A1
WO2022061738A1 PCT/CN2020/117831 CN2020117831W WO2022061738A1 WO 2022061738 A1 WO2022061738 A1 WO 2022061738A1 CN 2020117831 W CN2020117831 W CN 2020117831W WO 2022061738 A1 WO2022061738 A1 WO 2022061738A1
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WIPO (PCT)
Prior art keywords
layer
source
drain
gate
sidewall
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PCT/CN2020/117831
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English (en)
French (fr)
Inventor
苏博
吴汉洙
Original Assignee
中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Application filed by 中芯国际集成电路制造(上海)有限公司, 中芯国际集成电路制造(北京)有限公司 filed Critical 中芯国际集成电路制造(上海)有限公司
Priority to PCT/CN2020/117831 priority Critical patent/WO2022061738A1/zh
Priority to CN202080103574.5A priority patent/CN115989577A/zh
Priority to TW110128225A priority patent/TWI786757B/zh
Publication of WO2022061738A1 publication Critical patent/WO2022061738A1/zh
Priority to US18/124,768 priority patent/US20230238449A1/en

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    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
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    • H01L21/764—Air gaps
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Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
  • the interconnect structure includes interconnect lines and contact plugs formed in the contact openings.
  • the contact plug is connected with the semiconductor device, and the interconnection wire realizes the connection between the contact plugs, thereby forming a circuit.
  • Contact plugs within the transistor structure include gate contact plugs on the gate structure for connecting the gate structure with external circuits, and source-drain contact plugs on the source-drain doped regions for Realize the connection between source and drain doped regions and external circuits.
  • an active gate contact plug Contact Over Active Gate, COAG
  • COAG Contact Over Active Gate
  • the problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a gate structure on the substrate, and source and drain doped regions in the substrate on both sides of the gate structure , and a bottom dielectric layer located on the substrate on the side of the gate structure and covering the source and drain doped regions; forming a bottom dielectric layer penetrating the top of the source and drain doped regions and in contact with the source and drain doped regions forming a top dielectric layer on the bottom dielectric layer, covering the gate structure and the source-drain interconnect layer; forming a top dielectric layer through the top of the gate structure and exposing the gate structure a gate contact hole at the top, and a source-drain contact hole that penetrates the top dielectric layer on top of the source-drain interconnection layer and exposes the top of the source-drain interconnection layer; the gate contact hole and the source-drain contact hole forming a sacrificial sidewall layer on the sidewall of the the the
  • an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a gate structure, located on the substrate; a source-drain doped region, located in the substrate on both sides of the gate structure; a source-drain interconnection a layer on top of and in contact with the source and drain doped regions; a gate plug on top of and in contact with the gate structure; a source a drain plug located on top of the source-drain interconnection layer and in contact with the source-drain plug; a dielectric layer covering the sidewalls of the gate plug and the source-drain plug and filling the between the gate plug and the source-drain plug; the first gap is located between the sidewall of the gate plug and the dielectric layer, and between the sidewall of the source-drain plug and the dielectric layer a sealing layer on the dielectric layer and sealing the first gap, at least one of the first gap located on the sidewall of the source-drain plug and the first gap located on the sidewall of the gate plug , forming a first air
  • a sacrificial sidewall layer is also formed on the sidewalls of the gate contact hole and the source-drain contact hole and then forming gate plugs filled in the gate contact holes and source-drain plugs filled in the source-drain contact holes on the sacrificial sidewall layer, and removing the sacrificial sidewall layer to form exposing the gate plug sidewalls and the first gap between the source and drain plug sidewalls, and then forming a sealing layer on the gate plug and the source/drain plug to seal the first gap, so that the At least one of the first gap on the sidewall of the source-drain plug and the first gap on the sidewall of the gate plug and the sealing layer form a first air gap; For the sacrificial sidewall layer occupied by the first gap, after the gate plug and the source-drain plug are formed, the sacrificial sidewall layer is removed, so
  • the air gap has a lower dielectric constant than dielectric materials commonly used in semiconductor processes (eg: low-k dielectric materials or ultra-low-k dielectric materials), thereby helping to reduce the gate plug and the source-drain plug Parasitic capacitance between plugs (Parasitic Capacitance), reducing the RC (resistor capacitance) delay, thereby improving the performance of the semiconductor structure.
  • the substrate includes an active region; the forming method further includes: after providing the substrate, before forming the source-drain interconnection layer, removing a part of the thickness of the gate structure, and in the remaining all forming a gate capping layer on top of the gate structure; the gate contact hole penetrates the gate capping layer and the top dielectric layer on top of the gate structure of the active region; correspondingly, forming the gate
  • the gate plug is located above the gate structure of the active region, and the gate plug is an active gate contact hole plug (Contact plug).
  • the distance between the gate plug and the source-drain plug in the embodiment of the present invention is closer, through the sidewall of the gate plug and the The sidewalls of the source-drain plug form a first gap, and the first gap is sealed.
  • the parasitic capacitance between the source and drain plugs reduces the RC delay, thereby significantly improving the performance of the semiconductor structure.
  • 1 to 16 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
  • the COAG process is beneficial to save the chip area.
  • the gate contact plug formed by the COAG process is located in the active region (Active Area, AA), the distance between the gate contact plug and the source-drain contact plug is closer than that of the traditional gate contact plug located above the gate structure of the isolation area, which is easy to cause the gate
  • the parasitic capacitance between the pole contact plug and the source-drain contact plug is too large, resulting in poor device performance.
  • the sacrificial sidewall layer for occupying the first gap is formed first, and after the gate plug and the source-drain plug are formed , removing the sacrificial sidewall layer to form a first gap on the sidewall of the gate plug and the sidewall of the source-drain plug, and then sealing the top of the first gap so that the source At least one of the first gap on the sidewall of the drain plug and the first gap located on the sidewall of the gate plug and the sealing layer form a first air gap, and the air gap has a dielectric material that is higher than that commonly used in semiconductor processes (eg: low-k dielectric material or ultra-low-k dielectric material) lower dielectric constant, which is beneficial to reduce the parasitic capacitance between the gate plug and the source-drain plug, reduce the RC delay, and improve the performance of the semiconductor structure.
  • a dielectric material that is higher than that commonly used in semiconductor processes (eg: low-k dielectric material or ultra-low-k dielectric material) lower dielectric constant, which is beneficial to
  • 1 to 16 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
  • a substrate 100 , a gate structure 110 on the substrate 100 , source and drain doped regions 130 in the substrate 100 on both sides of the gate structure 110 , and a substrate on the side of the gate structure 110 are provided 100 and cover the bottom dielectric layer 135 of the source and drain doped regions 130 .
  • the substrate 100 is used to provide a process platform for subsequent processes.
  • the base 100 is a planar substrate.
  • the base can also be a three-dimensional base, for example, the base includes a substrate and fins protruding from the substrate.
  • the base 100 is a silicon substrate.
  • the substrate may also be a substrate of other material types.
  • the substrate 100 includes an active region (Active Area, AA) 100a.
  • the gate structure 110 serves as the gate of the device, and is used to control the on or off of the conductive channel when the device operates.
  • the gate structure 110 is a metal gate structure, and the gate structure 110 is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high k last metal gate last).
  • the source and drain doped regions 130 are used to provide a carrier source when the device operates.
  • Bottom dielectric layer 135 is used to isolate adjacent devices.
  • the material of the bottom dielectric layer 135 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
  • the material of the bottom dielectric layer 135 is silicon oxide.
  • dummy spacers 120 in contact with the sidewalls of the gate structure 110 and a contact etch stop layer located on the sidewalls of the dummy spacers 120 (Contact Etch Stop Layer (CESL) 140 , the contact etch stop layer 140 is also located between the source and drain doped regions 130 and the bottom dielectric layer 135 .
  • CESL Contact Etch Stop Layer
  • Subsequent steps further include: removing the dummy spacer 120 to form a second gap exposing the sidewall of the gate structure 110, the second gap is located between the contact etch stop layer 140 and the sidewall of the gate structure 110, therefore, the dummy The spacer 120 is used to occupy space for forming the second gap, so as to subsequently form a cover dielectric layer sealing the second gap, and the dielectric constant of the material of the cover dielectric layer is lower than the dielectric constant of the material of the dummy spacer 120, correspondingly making the gate electrode
  • the material on the sidewall of the structure 110 has a lower dielectric constant, which is beneficial to reduce the parasitic capacitance of the semiconductor structure, for example, reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer formed subsequently, and furthermore It is beneficial to improve the performance of the semiconductor structure.
  • materials with lower dielectric constants are selected for the subsequent covering dielectric layers, such as low-k dielectric materials or ultra-low-k dielectric materials.
  • the material is usually a material with a relatively loose structure and low density.
  • the process of forming the source and drain doped regions 130 includes a pre-cleaning step, and the forming of the gate structure 110 includes removing the dummy gate structure to form a gate opening exposing the dummy sidewall spacers 120 .
  • the density and etching resistance of the dummy sidewall spacers 120 are high, which is beneficial to reduce the probability that the dummy sidewall spacers 120 are wrongly etched in these two steps.
  • the material of the dummy spacer 120 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride.
  • the material of the dummy spacer 120 is an oxygen-containing material.
  • the material of the dummy spacer 120 is silicon oxide. Silicon oxide is an insulating material that is readily available and commonly used in semiconductor processes, which is beneficial to improve the compatibility of the dummy sidewall spacers 120 with existing processes, reduce process risks, and save costs.
  • the thickness of the dummy sidewall spacers 120 should not be too small, otherwise the width of the second gap formed later along the direction perpendicular to the sidewall of the gate structure 110 is also small, and the material of the subsequent top dielectric layer is difficult to fill in the second gap, so The effect of reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer is not obvious; the thickness of the dummy spacer 120 should not be too large, otherwise the channel length will be caused along the direction perpendicular to the sidewall of the gate structure 110 . Too large, it is difficult to meet the needs of device miniaturization. To this end, in a direction parallel to the surface of the substrate 100 and perpendicular to the sidewall of the gate structure 110 , the thickness of the dummy spacer 120 is 2 nm to 12 nm.
  • a source-drain interconnection layer in contact with the source-drain doped region 130 is formed in the bottom dielectric layer 135 on top of the source-drain doped region 130 , and the process of forming the source-drain interconnection layer includes etching the bottom dielectric layer 135 to form interconnections
  • the contact etch stop layer 140 is used to temporarily define the position of the etch stop during the process of forming the interconnect via hole, so as to improve the etching consistency and help prevent the source and drain doped regions 130 from being damaged.
  • the material of the contact etch stop layer 140 is a low-k dielectric material or an ultra-low-k dielectric material, so that the contact etch stop layer 140 between the dummy sidewall spacers 120 and the bottom dielectric layer 135 can be further reduced in size Effective capacitance between the gate structure 110 and the source-drain interconnect layer.
  • the material of the contact etch stop layer may also be silicon nitride.
  • an anti-diffusion layer 125 is further formed between the dummy sidewall spacer 120 and the contact etch stop layer 140 to prevent easily diffusible ions in the dummy sidewall spacer 120 from diffusing into the contact etch stop layer 140 , thereby preventing
  • the contact etch stop layer 140 material is adversely affected by ion diffusion.
  • the material of the dummy sidewall spacers 120 is an oxygen-containing material (eg, silicon oxide). When oxygen ions diffuse into the contact etching stop layer 140, the dielectric constant of the contact etching stop layer 140 material will increase. The formation of the anti-diffusion layer 125 can reduce the probability that the dielectric constant of the material of the contact etch stop layer 140 increases.
  • the density of the anti-diffusion layer 125 is relatively high, and the anti-diffusion layer 125 is subsequently retained, and the material of the anti-diffusion layer 125 is an insulating material.
  • the material of the anti-diffusion layer 125 includes one of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride variety.
  • the material of the anti-diffusion layer 125 is silicon nitride.
  • the anti-diffusion layer 125 is also located between the source-drain interconnection layer and the gate structure 110, and the anti-diffusion layer 125 also affects the source-drain interconnection layer and the gate structure 110. effective capacitance between. Therefore, while ensuring the anti-diffusion effect of the anti-diffusion layer 125 on ions, in order to prevent the effective capacitance between the source-drain interconnection layer and the gate structure 110 from being too large, and to prevent the source-drain interconnection layer and the gate structure 110 from being too large The distance between them is too large to occupy too much chip area, and the thickness of the anti-diffusion layer 125 is less than or equal to 30 ⁇ .
  • the thickness of the anti-diffusion layer 125 is less than or equal to 15 ⁇ . Wherein, when the thickness of the anti-diffusion layer 125 is too small, the effect of preventing ion diffusion of the anti-diffusion layer 125 is likely to deteriorate. Therefore, in this embodiment, the thickness of the anti-diffusion layer 125 is 5 ⁇ to 15 ⁇ .
  • a substrate 100 is formed; a dummy gate structure 115 is formed on the substrate 100 .
  • the dummy gate structure 115 is used to occupy space for forming the gate structure.
  • the dummy gate structure 115 is a single-layer or stacked-layer structure.
  • the dummy gate structure 115 is a single-layer structure, and the material of the dummy gate structure 115 is polysilicon.
  • dummy spacers 120 are formed on the sidewalls of the dummy gate structures 115 .
  • the dummy spacers 120 are also formed on the top of the dummy gate structure 115 and on the substrate 100 .
  • the process of forming the dummy spacer 120 includes an atomic layer deposition process.
  • the atomic layer deposition process has a higher step coverage capability, and is also beneficial to improve the thickness uniformity of the dummy sidewall spacers 120 .
  • the forming method before forming the dummy spacer 120 , the forming method further includes: forming an offset spacer 105 on the sidewall of the dummy gate structure 115 .
  • the offset spacers 105 are used to increase the channel length of the formed transistor to improve the short channel effect and the hot carrier effect caused by the short channel effect.
  • the offset spacers 105 are also formed on the top of the dummy gate structure 115 and the substrate 100 . Accordingly, dummy spacers 120 are formed on the offset spacers 105 .
  • the material of the offset spacers 105 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxynitride, or silicon oxynitride. In this embodiment, the material of the offset spacers 105 is silicon nitride.
  • source and drain doped regions 130 are formed in the substrate 100 on both sides of the dummy gate structure 115 .
  • the forming method further includes: removing the dummy spacers 120 and the offset spacers 105 on the substrate 100 on both sides of the dummy gate structure 115 to expose the substrates on both sides of the dummy gate structure 115 100 , so as to prepare for the formation of the source and drain doped regions 130 .
  • a contact etch stop layer 140 is formed conformally covering the dummy spacers 120 and the source and drain doped regions 130 .
  • the anti-diffusion layer 125 conformally covering the dummy spacers 120 and the source-drain doped regions 130 is formed before the contact etch stop layer 140 is formed. Accordingly, the contact etch stop layer 140 is formed on the diffusion prevention layer 125 .
  • the process of forming the anti-diffusion layer 125 includes an atomic layer deposition process, a chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process.
  • the atomic layer deposition process is used to form the anti-diffusion layer 125, so that the anti-diffusion layer 125 with a small thickness is easily formed, and the thickness uniformity and density of the anti-diffusion layer 125 are good. 125 has good step coverage.
  • a bottom dielectric layer 135 exposing the top of the dummy gate structure 115 is formed on the contact etch stop layer 140 on both sides of the dummy gate structure 115 .
  • the steps of forming the bottom dielectric layer 135 include: forming an initial dielectric layer (not shown) covering the top of the dummy gate structure 115 on the substrate 100 ; removing the initial dielectric layer higher than the top of the dummy gate structure 115 to form a bottom Dielectric layer 135 .
  • the offset spacers 105 , the dummy spacers 120 , the anti-diffusion layer 125 and the etch stop layer on the top of the dummy gate structure 115 are also removed 140 , thereby exposing the top of the dummy gate structure 115 so as to facilitate subsequent removal of the dummy gate structure 115 .
  • the dummy gate structure 115 is removed to form a gate opening (not shown); the gate structure 110 is formed in the gate opening.
  • the forming method further includes: after providing the substrate 100 , removing a partial thickness of the gate structure 110 , and forming a gate capping layer 145 on top of the remaining gate structure 110 .
  • the top surface of the gate capping layer 145 is flush with the top surface of the bottom dielectric layer 135 .
  • the gate capping layer 145 is used to protect the top of the gate structure 110 during the subsequent formation of the source-drain interconnection layer and the formation of the source-drain plug, thereby reducing damage to the gate structure 110 and reducing the gate structure Probability of a shorting problem between 110 and the source-drain interconnect layer or source-drain plug.
  • the gate capping layer 145 is selected from the source-drain capping layer and the bottom dielectric.
  • the layer 135 and the subsequently formed dielectric layer have materials with etch selectivity, so as to ensure the protection effect of the gate capping layer 145 on the gate structure 110 .
  • the material of the gate capping layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride.
  • the material of the gate capping layer 145 is silicon nitride.
  • a source-drain interconnection layer 150 is formed through the bottom dielectric layer 135 on top of the source-drain doped region 130 and in contact with the source-drain doped region 130 .
  • the source-drain interconnection layer 150 is in contact with the source-drain doped region 130, and is used to realize electrical connection between the source-drain doped region 130 and external circuits or other interconnect structures.
  • the material of the source-drain interconnection layer 150 is copper.
  • the lower resistivity of copper is beneficial to improving the signal delay of the RC in the later stage, improving the processing speed of the chip, and at the same time, it is also beneficial to reduce the resistance of the source-drain interconnection layer 150 and correspondingly reduce the power consumption.
  • the material of the source-drain interconnection layer may also be a conductive material such as tungsten or cobalt.
  • the source-drain interconnection layer 150 also penetrates the contact etch stop layer 140 and the anti-diffusion layer 125 on the source-drain doped region 130 .
  • the forming method further includes: after forming the source-drain interconnection layer 150 , removing a partial thickness of the source-drain interconnection layer 150 , and forming a source-drain capping layer 155 on top of the remaining source-drain interconnection layer 150 .
  • the top surface of the source-drain cap layer 155 is flush with the top surface of the bottom dielectric layer 135 .
  • a gate plug is subsequently formed in contact with the gate structure 110, and the source-drain capping layer 155 is located on the top surface of the source-drain interconnection layer 150.
  • the source-drain capping layer 155 is able to The interconnection layer 150 plays a protective role, which is beneficial to reduce damage to the source-drain interconnection layer 150 and reduce the probability of short circuit between the gate plug and the source-drain interconnection layer 150 .
  • the source-drain capping layer 155 is selected from materials with higher etch selectivity than the gate capping layer 145 , the dummy sidewall spacers 120 , the bottom dielectric layer 135 and the subsequent dielectric layers, so as to ensure that the source-drain capping layer 155 is not connected to the source-drain interconnection layer 150 protective effect.
  • the material of the source-drain cap layer 155 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride.
  • the materials of the source-drain capping layer 155 and the gate capping layer 145 are different, and the materials of the source-drain capping layer 155 and the dummy sidewall spacers 120 are different.
  • the material of the source-drain capping layer 155 is silicon carbide.
  • a top dielectric layer 160 is formed on the bottom dielectric layer 135 to cover the gate structure 110 and the source-drain interconnection layer 150 .
  • source-drain plugs in contact with the source-drain interconnection layer 150 and gate plugs in contact with the gate structure 110 are formed in the top dielectric layer 160, and the top dielectric layer 160 is used to realize the source-drain plugs and the gate Electrical isolation between pole plugs.
  • the top dielectric layer 160 and the dummy spacers 120 are subsequently removed, and a second gap is formed between the bottom dielectric layer 135 and the sidewalls of the gate structure 110 ; A dielectric layer covering the top of the two gaps.
  • the top dielectric layer 160 is also used to occupy a space for forming a capping dielectric layer.
  • the top dielectric layer 160 covers the gate capping layer 145 and the source-drain capping layer 155 .
  • the material of the top dielectric layer 160 is an insulating material. Moreover, in this embodiment, the top dielectric layer 160 will be etched later, therefore, the top dielectric layer 160 is made of materials that are easy to be etched.
  • the material of the top dielectric layer 160 includes one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. In this embodiment, the material of the top dielectric layer 160 is silicon oxide.
  • the top dielectric layer 160 penetrating the top of the gate structure 110 and exposing the gate contact hole 10 on the top of the gate structure 110 is formed, and the top dielectric layer 160 penetrating the top of the source-drain interconnection layer 150 and exposing the source and drain are formed The source-drain contact hole 20 on the top of the interconnect layer 150 .
  • the gate contact holes 10 are used to provide spatial locations for forming gate plugs.
  • the source-drain contact hole 20 is used to provide a space for forming the source-drain plug.
  • the gate contact hole 10 and the source-drain contact hole 20 are also used to reserve space for the subsequent formation of the sacrificial sidewall layer, and the sidewalls of the gate contact hole 10 and the source-drain contact hole 20 are used to form the sacrificial sidewall
  • the wall layer provides support.
  • the sacrificial sidewall layer formed subsequently has a thickness. Therefore, in order to reserve enough space for the formation of the sacrificial sidewall layer and the gate plug in the gate contact hole 10 , the gate can be appropriately increased in this embodiment according to actual process requirements.
  • the size of the opening of the contact hole 10 in order to reserve enough space for the source-drain contact hole 20 for forming the sacrificial sidewall layer and the source-drain plug, in this embodiment, the size of the opening of the source-drain contact hole 20 may be appropriately increased according to actual process requirements.
  • the gate contact hole 10 penetrates through the gate capping layer 145 and the top dielectric layer 160 on the top of the gate structure 110 of the active region 100a. Specifically, in this embodiment, in order to increase the size of the gate contact hole 10 , the gate contact hole 10 also penetrates part of the offset spacer 105 located on the sidewall of the gate capping layer 145 . Therefore, the gate contact hole 10 also exposes part of the dummy spacer 120 .
  • the source-drain contact hole 20 penetrates the source-drain cap layer 155 and the top dielectric layer 160 on the top of the source-drain interconnection layer 150 .
  • the source-drain contact hole 20 and the gate contact hole 10 are formed in different steps, respectively.
  • a sacrificial sidewall layer 170 is formed on sidewalls of the gate contact hole 10 and the source-drain contact hole 20 .
  • the remaining space in the gate contact hole 10 is used for forming a gate plug
  • the remaining space in the source-drain contact hole 20 is used for forming a source-drain plug.
  • the sacrificial sidewall layer 170 is used to occupy space for forming the first gap, that is, the sacrificial sidewall layer 170 is subsequently removed to form a first gap exposing the sidewalls of the gate plug and the sidewalls of the source and drain plugs, and the A sealing layer for sealing the first gap is formed on the gate plug and the source-drain plug, so that the first gap and the sealing layer form a first air gap. or ultra-low-k dielectric material) and lower dielectric constant, which is beneficial to reduce the parasitic capacitance between the gate plug and the source-drain plug, reduce the RC delay, and thus improve the performance of the semiconductor structure.
  • the sacrificial sidewall layer 170 needs to be removed later. Therefore, the sacrificial sidewall layer 170 is made of materials that can be easily removed, thereby reducing the difficulty of removing the sacrificial sidewall layer 170; and the material of the sacrificial sidewall layer 170 is selected as: The capping layer 145 , the source-drain capping layer 155 , the bottom dielectric layer 135 , the top dielectric layer 160 , and materials with etch selectivity between the source-drain plugs and the gate plugs, so that the sacrificial sidewall layer 170 is subsequently removed In the step of , both the sacrificial sidewall layer 170 and these film layer structures have an etching selectivity ratio, which is beneficial to reduce the damage to other film layers caused by the removal of the sacrificial sidewall layer 170, thereby improving process compatibility.
  • the material of the sacrificial sidewall layer 170 includes one or more of amorphous silicon, silicon oxycarbide, silicon oxide, silicon nitride, silicon carbide, boron nitride, aluminum oxide, aluminum nitride, and silicon oxynitride. several.
  • the material of the sacrificial sidewall layer 170 is amorphous silicon.
  • the thickness of the sacrificial sidewall layer 170 should not be too small or too large. If the thickness of the sacrificial sidewall layer 170 is too small, the width of the first gap formed by the subsequent removal of the sacrificial sidewall layer 170 is also too small, and the width of the first air gap is correspondingly too small, which is likely to cause the first air gap to be used to reduce The effect of the parasitic capacitance between the source-drain plug and the gate plug is not obvious; if the thickness of the sacrificial sidewall layer 170 is too large, the width of the subsequent first gap is also too large, and the material of the subsequent sealing layer is easily filled to the first Therefore, it is difficult to form the first air gap, and if the width of the sacrificial sidewall layer 170 is too large, it is easy to increase the difficulty of subsequent removal of the sa
  • a sidewall material layer 165 is formed on the sidewall and bottom of the gate contact hole 10 , the sidewall and bottom of the source-drain contact hole 20 , and the top surface of the top dielectric layer 160 .
  • the process of forming the sidewall material layer 165 includes one or both of atomic layer deposition and chemical vapor deposition.
  • the sidewall material layer 165 is formed using an atomic layer deposition process.
  • the atomic layer deposition process is a self-limiting reaction process based on the atomic layer deposition process.
  • the deposited film can reach the thickness of a single layer of atoms, which is conducive to the formation of a thinner sidewall material layer 165, which is correspondingly conducive to making the thickness of the sacrificial sidewall layer meet the requirements.
  • the atomic layer deposition process also has a higher step coverage capability, thereby improving the coverage capability of the sidewall material layer 165 on the sidewalls of the gate contact hole 10 and the source-drain contact hole 20, and correspondingly improving the sidewall material layer 165. Thickness uniformity and film formation quality of layer 165.
  • a chemical vapor deposition process may also be used to form the sidewall material layer.
  • the chemical vapor deposition process may be a conventional chemical vapor deposition process, or may be a chemical vapor deposition process incorporating a plasma treatment function.
  • the chemical vapor deposition process that introduces the plasma treatment function includes multiple deposition cycles. In each deposition cycle, after the film is deposited, it also includes plasma treatment (Plasma Treatment) to improve the density and coverage of the film.
  • the gas used in the plasma treatment includes one or more gases selected from hydrogen, helium, argon, oxygen and nitrogen.
  • the plasma treatment can utilize plasma with energy to reduce or remove the suspension on the surface of the deposited film. bond, thereby increasing the density of the deposited film and preparing it for the next deposition cycle.
  • the bottom of the gate contact hole 10 and the source-drain contact hole 20 and the sidewall material layer 165 on the top surface of the top dielectric layer 160 are removed, and the remaining gate contact hole 10 and the source-drain contact hole 20 are
  • the sidewall material layer 165 on the sidewall is used as the sacrificial sidewall layer 170 .
  • this embodiment can pass The anisotropic etching process removes the sidewall material layer 165 located at the bottom of the gate contact hole 10 and the source-drain contact hole 20 and on the top surface of the top dielectric layer 160 .
  • the anisotropic etching process has the characteristics of anisotropic etching, and the etching rate of the etching process in the direction perpendicular to the surface of the substrate 100 (ie, the longitudinal direction) is greater than that in the direction parallel to the substrate 100 (ie, the lateral direction).
  • the etching rate is high, so that the sidewall material layer 165 located at the bottom of the gate contact hole 10 and the source-drain contact hole 20 and the top surface of the top dielectric layer 160 can be etched and removed, and the sidewall material layer 165 located at the gate contact hole 10 and the source-drain contact hole at the same time.
  • the sidewall material layer 165 on the sidewall 20 can be reserved for use as a sacrificial sidewall layer.
  • the anisotropic etching process includes an anisotropic dry etching process.
  • the dry etching process has high process controllability, etching precision and etching efficiency.
  • gate plugs 11 filled in the gate contact holes 10 and source-drain plugs 21 filled in the source-drain contact holes 20 are formed.
  • the gate plugs 11 are used to make electrical connections between the gate structures 110 and external circuits or other interconnect structures.
  • the gate plug 11 is formed above the gate structure 110 of the active region 100a, and the gate plug 11 is an active gate contact hole plug (COAG), which is beneficial to save the area of the chip, Thus, further reduction in chip size is achieved.
  • COAG active gate contact hole plug
  • the source-drain plugs 21 are in contact with the source-drain interconnection layer 150 , so that the source-drain doped region 130 and the external circuit or other interconnection structures are electrically connected through the source-drain interconnection layer 150 .
  • the source-drain plug 21 and the gate plug 11 are formed in the same step.
  • the method for forming the semiconductor structure further includes the following steps.
  • the top dielectric layer 160 between the top of the dummy spacer 120 and the sacrificial sidewall layer 170 is etched to expose the top surface of the dummy spacer 120 and the sidewall of the sacrificial sidewall layer 170 ; the dummy spacer 120 is removed , a second gap 40 is formed between the contact etch stop layer 140 and the sidewall of the gate structure 110 .
  • the second gap 40 is used to provide a formation space for the subsequent covering dielectric layer. Specifically, in this embodiment, the second gap 40 is formed between the anti-diffusion layer 125 and the offset sidewall spacer 105 and between the anti-diffusion layer 125 and the sacrificial sidewall layer 170 .
  • an isotropic etching process is used to remove the top dielectric layer 160 and the dummy sidewall spacers 120 .
  • the isotropic etching process is a remote plasma (Remote Plasma) etching process.
  • the remote plasma etching process has isotropic etching characteristics, and the remote plasma etching process also has good etching selectivity, thereby reducing the loss of other film layers during the etching process.
  • the principle of the remote plasma etching process is to form plasma outside the etching chamber (for example: plasma generated by a remote plasma generator), and then introduce it into the etching chamber and use the plasma and the layer to be etched.
  • the chemical reaction is used for etching, so an isotropic etching effect can be achieved, and because there is no ion bombardment, other film layers will not be damaged.
  • the isotropic etching process may also be a wet etching process.
  • the materials of the top dielectric layer 160 and the dummy spacers 120 are the same, so the top dielectric layer 160 and the dummy spacers 120 can be removed in the same etching step, which simplifies the process steps.
  • a cover dielectric layer 180 covering the sidewalls of the sacrificial sidewall layer 170 is formed on the bottom dielectric layer 135 , the cover dielectric layer 180 seals the second gap 40 , and the dielectric constant of the material of the cover dielectric layer 180 is lower than that of the dummy sidewall spacers 120 The dielectric constant of the material.
  • the covering dielectric layer 180 seals the second gap 40, thereby reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150, This in turn improves the performance of the semiconductor structure.
  • the covering dielectric layer 180 is also used to achieve electrical isolation between the source-drain plug 21 and the gate plug 11 , and the sacrificial sidewall layer 170 is subsequently removed to cover the dielectric layer 180 and the gate plug 11 .
  • a first gap is formed between the sidewalls of the plug 11 or the sidewalls of the source-drain plug 21; the cover dielectric layer 180 also provides support for the subsequent formation of a sealing layer that seals the first gap.
  • the cover dielectric layer 180 is filled in the second gap 40 as an example, so as to realize the sealing of the second gap 40 .
  • the cover dielectric layer can also seal the top of the second gap, so that the second gap and the cover dielectric layer form a second air gap.
  • the dielectric constant of air is relatively small, which is correspondingly beneficial to further reduce the effective capacitance between the gate structure and the source-drain interconnection layer.
  • the material covering the dielectric layer 180 includes a low-k dielectric material or an ultra-low-k dielectric material, which is beneficial to reduce the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150 , as well as the difference between the source-drain plug 21 and the source-drain interconnection layer 150 .
  • the parasitic capacitance between the gate plugs 11 reduces the RC delay of the interconnect structure in the integrated circuit.
  • the process of forming the cover dielectric layer 180 includes one or more of a flow chemical vapor deposition process, an atomic layer deposition process, a spin coating process and a chemical vapor deposition process.
  • the process of forming the cover dielectric layer 180 includes a spin coating process.
  • the process temperature of the spin coating process is lower, so as to avoid the channel degradation problem caused by high temperature, which is beneficial to improve the performance of the semiconductor structure, and the gap filling capability of the spin coating process is higher, which is beneficial to improve the coverage of the dielectric layer 180 in the second The gap 40 and the filling quality between the source-drain plug 21 and the gate plug 11 .
  • the step of forming the covering dielectric layer 180 includes: forming a dielectric material layer (not shown) covering the sidewalls of the sacrificial sidewall layer 170 on the bottom dielectric layer 135 , and the dielectric material layer also covers the gate plugs 11 and 170 .
  • the dielectric material layer seals the second gap 40 ; the dielectric material layer above the tops of the gate plugs 11 and the source-drain plugs 21 is removed.
  • a spin coating process is used to form the dielectric material layer.
  • the sacrificial sidewall layer 170 is removed to form a first gap 30 exposing the sidewalls of the gate plug 11 and the sidewalls of the source and drain plugs 21 .
  • the first gap 30 is used to enclose a first air gap with the subsequently formed sealing layer.
  • the first gap 30 is formed between the cover dielectric layer 180 and the sidewall of the gate plug 11 and between the cover dielectric layer 180 and the sidewall of the source-drain plug 21 .
  • the sacrificial sidewall layer 170 is removed by an isotropic etching process.
  • An isotropic etching process is adopted, so that the sacrificial sidewall layer 170 can be removed cleanly, and the etching rate is relatively fast.
  • the isotropic etching process is a remote plasma etching process.
  • the remote plasma etching process has isotropic etching characteristics, and the remote plasma etching process also has good etching selectivity, thereby reducing the loss of other film layers during the etching process.
  • the principle of the remote plasma etching process is to form plasma outside the etching chamber (for example: plasma generated by a remote plasma generator), and then introduce it into the etching chamber and use the plasma and the layer to be etched.
  • the chemical reaction is used for etching, so an isotropic etching effect can be achieved, and because there is no ion bombardment, other film layers will not be damaged.
  • the isotropic etching process may also be a wet etching process.
  • a sealing layer 190 for sealing the first gap 30 is formed, so that at least one of the first gap 30 located on the sidewall of the source-drain plug 21 and the first gap 30 located on the sidewall of the gate plug 11 is sealed with the Layer 190 encloses first air gap 50 .
  • the air gap has a lower dielectric constant than dielectric materials commonly used in semiconductor processes (eg, low-k dielectric materials or ultra-low-k dielectric materials), thereby helping to reduce the gap between the gate plug 11 and the source-drain plug 21 This reduces the parasitic capacitance between and reduces the RC delay, thereby improving the performance of the semiconductor structure.
  • the gate plug 11 is an active gate contact hole plug (COAG).
  • COAG active gate contact hole plug
  • the gate plug 11 and the source-drain plug 12 in this embodiment are The distance between them is closer, by forming a first gap 30 on the sidewall of the gate plug 11 and the sidewall of the source-drain plug 21, and sealing the first gap 30, between the source-drain plug 21 and the gate plug
  • the first air gap 50 is formed on the sidewall of at least one of the 11 , which is beneficial to significantly reduce the parasitic capacitance between the gate plug 11 and the source-drain plug 12 and reduce the RC delay problem, thereby significantly improving the performance of the semiconductor structure.
  • the sealing layer 190 covers the source-drain plug 21 , the gate plug 11 and the top of the covering dielectric layer 180 .
  • the subsequent process also includes: forming metal interconnection lines on top of the source-drain plug 21 and the gate plug 11 for realizing the electrical connection between the source-drain plug 21 and the external circuit, and between the gate plug 11 and the external circuit
  • metal interconnection lines are formed in the inter-metal dielectric (Inter Metal Dielectric, IMD) layer.
  • IMD Inter Metal Dielectric
  • a metal interlayer dielectric layer thereby simplifying the process steps of the back end (BEOL) process and making the sealing layer 190 compatible with the back end process.
  • the material of the sealing layer 190 is a dielectric material.
  • the material of the sealing layer 190 is a dielectric material.
  • the sealing layer 190 contacts at the top corners of the first gaps 30 located on the sidewalls of the source-drain plugs 21 , so as to seal the top of the first gaps 30 , so that the top corners of the first gaps 30 located on the sidewalls of the source-drain plugs 21 are sealed.
  • the first air gap 50 is surrounded by the first gap 30 and the sealing layer 190 .
  • the sealing layer 190 is filled in the first gap 30 located on the sidewall of the gate plug 11 .
  • the cross-section of the source-drain plug 21 is an inverted trapezoid with a large top and a small bottom, and the sidewall of the first gap 30 located on the sidewall of the source-drain plug 21 also has a certain inclination angle accordingly.
  • the verticality of the sidewall of the plug 11 is greater than the verticality of the sidewall of the source-drain plug 21. Therefore, the filling difficulty of the sealing layer 190 in the first gap 30 located on the sidewall of the source-drain plug 21 is greater than that of the gate plug.
  • the sealing layer can also be located at the The top corner of the first gap on the side wall of the gate plug is in contact, so that the top of the first gap is sealed, so that the first gap located on the side wall of the gate plug and the sealing layer also enclose a first air gap .
  • only the first gap located on the sidewall of the gate plug and the sealing layer may be formed to form a first air gap.
  • the sealing layer 190 is formed by a deposition process with a weak filling ability, so that the sealing layer 190 is not easily filled into the first gap 30 , and thus the sealing layer 190 is easy to contact at the top corner of the first gap 30
  • the first air gap 50 is formed.
  • the process of forming the sealing layer 190 includes one or both of a chemical vapor deposition process and a plasma enhanced chemical vapor deposition process.
  • the COAG process is used as an example for description.
  • the method for forming the semiconductor structure provided in this embodiment can still reduce the parasitic between the source-drain plug and the gate structure. the effect of capacitance.
  • the present invention also provides a semiconductor structure.
  • FIG. 16 a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.
  • the semiconductor structure includes: a substrate 100; a gate structure 110 located on the substrate 100; a source-drain doped region 130 located in the substrate 100 on both sides of the gate structure 110; a source-drain interconnection layer 150 located on the source-drain doped region on top of region 130 and in contact with source-drain doped region 130; gate plug 11 on top of and in contact with gate structure 110; source-drain plug 21 on the source-drain interconnect
  • the top of the layer 150 is in contact with the source-drain plugs 21 ; the dielectric layer 180 covers the sidewalls of the gate plugs 11 and the source-drain plugs 21 and fills the gaps between the gate plugs 11 and the source-drain plugs 21
  • the first gap 30 (as shown in FIG.
  • the sealing layer 190 is located between the sidewall of the gate plug 11 and the dielectric layer 180, and between the sidewall of the source-drain plug 21 and the dielectric layer 180; the sealing layer 190, The first gap 30 located on the dielectric layer 180 and sealed, at least one of the first gap 30 located on the sidewall of the source-drain plug 21 and the first gap 30 located on the sidewall of the gate plug 11 , surrounded by the sealing layer 190 The first air gap 50 .
  • the first gap 30 By disposing the first gap 30 exposing the sidewall of the gate plug 11 and the sidewall of the source-drain plug 12, and disposing the sealing layer 190, the first gap 30 located on the sidewall of the source-drain plug 21 and the gate plug 11. At least one of the first gaps 30 on the sidewalls and the sealing layer 190 form a first air gap 50, and the air gap has a higher density than dielectric materials commonly used in semiconductor processes (eg, low-k dielectric materials or ultra-low-k dielectric materials).
  • the low dielectric constant is beneficial to reduce the parasitic capacitance between the gate plug 11 and the source-drain plug 21 and reduce the RC delay, thereby improving the performance of the semiconductor structure.
  • the substrate 100 is used to provide a platform for the process.
  • the substrate 100 is a planar substrate.
  • the base 100 is a silicon substrate.
  • the substrate 100 includes an active region 100a.
  • the gate structure 110 serves as the gate of the device, and is used to control the on or off of the conductive channel when the device operates.
  • the gate structure 110 is a metal gate structure, and the gate structure 110 is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer.
  • the source and drain doped regions 130 are used to provide a carrier source when the device operates.
  • the semiconductor structure further includes: a bottom dielectric layer 135 (as shown in FIG. 6 ) located on the substrate 100 exposed by the gate structure 110 .
  • Bottom dielectric layer 135 is used to isolate adjacent devices.
  • the material of the bottom dielectric layer 135 is silicon oxide.
  • the source-drain interconnection layer 150 is in contact with the source-drain doped region 130, and is used to realize electrical connection between the source-drain doped region 130 and external circuits or other interconnect structures.
  • the material of the source-drain interconnection layer 150 is copper.
  • the material of the source-drain interconnection layer may also be a conductive material such as tungsten or cobalt.
  • the source-drain interconnection layer 150 penetrates through the bottom dielectric layer 135 on the source-drain doped region 130 .
  • the semiconductor structure further includes: a gate capping layer 145 (as shown in FIG. 8 ), located between the top of the gate structure 110 and the dielectric layer 180 ; a source-drain capping layer 155 , located in the source-drain interconnection between the top of the layer 150 and the dielectric layer 180 .
  • the top surface of the source-drain cap layer 155 is flush with the top surface of the bottom dielectric layer 135 .
  • the source-drain capping layer 155 is located on the top surface of the source-drain interconnection layer 150, and is used to protect the source-drain interconnection layer 150 during the formation of the gate plug 11, which is beneficial to reduce the source-drain interconnection layer. 150 is damaged, and the probability of short circuit between the gate plug 11 and the source-drain interconnection layer 150 is reduced.
  • the gate capping layer 145 is used to protect the top of the gate structure 110 during the process of forming the source-drain interconnection layer 150 and forming the source-drain plug 21 , thereby reducing damage to the gate structure 110 and reducing the gate The probability of a short circuit between the pole structure 110 and the source-drain interconnection layer 150 or the source-drain plug 11 occurs.
  • the semiconductor structure further includes: a contact etch stop layer 140 located on the substrate 100 between the sidewall of the source-drain interconnection layer 150 and the gate structure 110 and disposed opposite to the sidewall of the gate structure 110 , there is a second gap 40 between the contact etch stop layer 140 and the sidewall of the gate structure 110 (as shown in FIG. 13 ).
  • the contact etch stop layer 140 is also located on the top surface of the source-drain doped region 130 , and the contact etch stop layer 140 is used to temporarily define the position where the etching stops during the formation of the source-drain interconnection layer 150 , thereby improving the uniformity of etching and it is beneficial to prevent the source and drain doped regions 130 from being damaged.
  • the material of the contact etch stop layer 140 is a low-k dielectric material or an ultra-low-k dielectric material, so that the contact etch stop layer 140 can further reduce the gap between the gate structure 110 and the source-drain interconnection layer 150 effective capacitance between.
  • the material of the contact etch stop layer may also be silicon nitride.
  • the dielectric layer 180 covers the dielectric layer 180 .
  • the cover dielectric layer 180 seals the second gap 40 .
  • the second gap 40 is used to provide a formation space for the cover dielectric layer 180 .
  • the cover dielectric layer 180 seals the second gap 40, thereby reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150, thereby improving the performance of the semiconductor structure.
  • the material covering the dielectric layer 180 includes a low-k dielectric material or an ultra-low-k dielectric material.
  • the cover dielectric layer 180 is filled in the second gap 40 .
  • the cover dielectric layer seals the top of the second gap, and the second gap and the cover dielectric layer enclose a second air gap.
  • the dielectric constant of air is relatively small, which is correspondingly beneficial to further reduce the effective capacitance between the gate structure and the source-drain interconnection layer.
  • the width of the second gap 40 is 2 nm to 12 nm.
  • the semiconductor structure further includes: an anti-diffusion layer 125 located on the sidewall of the contact etch stop layer 140 exposed by the second gap 40 .
  • the second gap 40 is formed by removing the dummy spacer, and the anti-diffusion layer 125 is used to prevent easily diffusible ions in the dummy spacer from diffusing into the contact etch stop layer 140 , thereby preventing the contact from being etched due to ion diffusion.
  • the stop layer 140 has adverse effects.
  • the density of the anti-diffusion layer 125 is high, and the material of the anti-diffusion layer 125 is an insulating material.
  • the material of the anti-diffusion layer 125 includes one of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride variety.
  • the material of the anti-diffusion layer 125 is silicon nitride.
  • the anti-diffusion layer 125 is also located between the source-drain interconnect layer 150 and the gate structure 110 , and the anti-diffusion layer 125 also affects the effective capacitance between the source-drain interconnect layer 150 and the gate structure 110 . Therefore, while ensuring the anti-diffusion effect of the anti-diffusion layer 125 on ions, in order to prevent the effective capacitance between the source-drain interconnection layer 150 and the gate structure 110 from being too large and to prevent an excessively large chip area, the anti-diffusion layer 125 The thickness is less than or equal to 30 ⁇ . In this embodiment, the thickness of the anti-diffusion layer 125 is less than or equal to 15 ⁇ .
  • the thickness of the anti-diffusion layer 125 is 5 ⁇ to 15 ⁇ .
  • the semiconductor structure further includes: offset sidewall spacers 105 located on the sidewalls of the gate structure 110 exposed by the second gap 40 .
  • the offset spacers 105 are used to improve the short channel effect and the hot carrier effect caused by the short channel effect.
  • the offset sidewall 105 is also located on the substrate 100 exposed from the second gap 40 .
  • the material of the offset spacers 105 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxynitride, or silicon oxynitride.
  • the gate plugs 11 are used to make electrical connections between the gate structures 110 and external circuits or other interconnect structures.
  • the gate plug 11 is located above the gate structure 110 of the active region 100a, the gate plug 11 is the active gate contact hole plug, and the gate plug and the gate structure located in the isolation region Compared with the contact solution, the present embodiment omits the part of the gate structure 110 located in the isolation region, which is beneficial to save the area of the chip, thereby further reducing the size of the chip.
  • the source-drain plugs 21 are in contact with the source-drain interconnection layer 150 , so that the source-drain doped region 130 and the external circuit or other interconnection structures are electrically connected through the source-drain interconnection layer 150 .
  • the cover dielectric layer 180 seals the second gap 40, thereby reducing the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150, thereby improving the performance of the semiconductor structure.
  • the cover dielectric layer 180 is also used to achieve electrical isolation between the source-drain plug 21 and the gate plug 11 , and the cover dielectric layer 180 is also used to form a sealing layer 190 for sealing the first gap 30 Provide support.
  • the material covering the dielectric layer 180 includes a low-k dielectric material or an ultra-low-k dielectric material, so that the effective capacitance between the gate structure 110 and the source-drain interconnection layer 150 can be reduced, and the source-drain interconnection layer 150 can also be reduced.
  • the parasitic capacitance between the plug 21 and the gate plug 11 reduces the RC delay.
  • the first gap 30 is used to form the first air gap 50 , so as to reduce the parasitic capacitance between the source-drain plug 21 and the gate plug 11 .
  • the width of the first gap 30 should not be too small nor too large. If the width of the first gap 30 is too small, the width of the first air gap 50 is correspondingly too small, which may easily lead to the effect of the first air gap 50 being used to reduce the parasitic capacitance between the source-drain plug 21 and the gate plug 11 . It is not obvious; if the width of the first gap 30 is too large, the material of the sealing layer 190 will be easily filled into the first gap 30 , thereby making it difficult to form the first air gap 50 .
  • the width of the first gap 30 is 10 ⁇ to 40 ⁇ , for example, the width of the first gap 30 20 ⁇ , 30 ⁇ .
  • the sealing layer 190 is used to seal the first gap 30 to form the first air gap 50 .
  • the air gap has a lower dielectric constant than dielectric materials commonly used in semiconductor processes (eg, low-k dielectric materials or ultra-low-k dielectric materials), thereby helping to reduce parasitics between the gate plug 11 and the source-drain plug 21 Capacitance, reducing RC delay, thereby improving the performance of the semiconductor structure.
  • the gate plug 11 is an active gate contact hole plug (COAG).
  • COAG active gate contact hole plug
  • the gap between the gate plug 11 and the source-drain plug 12 is When the distance is closer, by arranging the first air gap 50 , it is beneficial to significantly reduce the parasitic capacitance between the gate plug 11 and the source-drain plug 12 and reduce the RC delay problem, thereby significantly improving the performance of the semiconductor structure.
  • the sealing layer 190 covers the source-drain plug 21 , the gate plug 11 and the top of the covering dielectric layer 180 .
  • the subsequent process also includes: forming metal interconnection lines on the top of the source-drain plug 21 and the gate plug 11 to realize the electrical connection between the source-drain plug 21 or the gate plug 11 and the external circuit.
  • the wiring is formed in the inter-metal dielectric (IMD) layer.
  • IMD inter-metal dielectric
  • the material of the sealing layer 190 is a dielectric material.
  • the material of the sealing layer 190 is a dielectric material.
  • the sealing layer 190 contacts at the top corners of the first gaps 30 located on the sidewalls of the source-drain plugs 21 , so as to seal the top of the first gaps 30 , so that the top corners of the first gaps 30 located on the sidewalls of the source-drain plugs 21 are sealed.
  • the first air gap 50 is surrounded by the first gap 30 and the sealing layer 190 .
  • the sealing layer 190 is filled in the first gap 30 located on the sidewall of the gate plug 11 .
  • the cross-section of the source-drain plug 21 is an inverted trapezoid with a large top and a small bottom, and the sidewall of the first gap 30 located on the sidewall of the source-drain plug 21 also has a certain inclination angle accordingly.
  • the verticality of the sidewall of the plug 11 is greater than the verticality of the sidewall of the source-drain plug 21. Therefore, the filling difficulty of the sealing layer 190 in the first gap 30 located on the sidewall of the source-drain plug 21 is greater than that of the gate plug. It is difficult to fill the first gap 30 on the sidewall of 11.
  • the sealing layer 190 and the first gap 30 on the sidewall of the source-drain plug 21 are easy to enclose the first air gap 50.
  • the sealing layer 190 is filled in the gate plug. in the first gap 30 of the side wall of the plug 11 .
  • the sealing layer can also Contact at the top corner of the first gap located on the sidewall of the gate plug, so as to seal the top of the first gap, so that the first gap located on the sidewall of the gate plug and the sealing layer also enclose the first gap air gap.
  • only the first gap located on the sidewall of the gate plug and the sealing layer may be formed to form a first air gap.
  • the gate plug 11 is COAG as an example for description.
  • the semiconductor structure provided in this embodiment can still achieve the effect of reducing the parasitic capacitance between the source-drain plug and the gate structure .
  • the semiconductor structure may be formed by the formation method described in the foregoing embodiments, or may be formed by other formation methods.
  • the specific description of the semiconductor structure in this embodiment reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

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Abstract

一种半导体结构及其形成方法，形成方法包括：提供基底、栅极结构、位于栅极结构两侧基底中的源漏掺杂区以及位于栅极结构侧部基底上的底部介质层；形成贯穿源漏掺杂区顶部的底部介质层的源漏互连层；在底部介质层上形成顶部介质层；形成贯穿栅极结构顶部的顶部介质层的栅极接触孔和贯穿源漏互连层顶部的顶部介质层的源漏接触孔；在栅极接触孔和源漏接触孔的侧壁形成牺牲侧壁层；形成填充栅极接触孔的栅极插塞以及填充源漏接触孔的源漏插塞；去除牺牲侧壁层形成第一间隙；形成密封第一间隙的密封层，使位于源漏插塞侧壁和位于栅极插塞侧壁的第一间隙中的至少一个与密封层围成第一空气隙。本发明实施例有利于降低栅极插塞与源漏插塞之间的寄生电容。

Description

半导体结构及其形成方法 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种半导体结构及其形成方法。
 背景技术
随着集成电路制造技术的不断发展，人们对集成电路的集成度和性能的要求变得越来越高。为了提高集成度，降低成本，元器件的关键尺寸不断变小，集成电路内部的电路密度越来越大，这种发展使得晶圆表面无法提供足够的面积来制作所需要的互连线。
为了满足关键尺寸缩小过后的互连线所需，目前不同金属层或者金属层与基底的导通是通过互连结构实现的。互连结构包括互连线和形成于接触开口内的接触插塞。接触插塞与半导体器件相连接，互连线实现接触插塞之间的连接，从而构成电路。晶体管结构内的接触插塞包括位于栅极结构上的栅极接触插塞，用于实现栅极结构与外部电路的连接，还包括位于源漏掺杂区上的源漏接触插塞，用于实现源漏掺杂区与外部电路的连接。
目前，为实现晶体管面积的进一步缩小，引入了有源栅极接触插塞（Contact Over Active Gate，COAG）工艺。与传统的栅极接触插塞位于隔离区域的栅极结构上方相比，COAG工艺能够把栅极接触插塞做到有源区（Active Area，AA）的栅极结构上方，从而进一步节省芯片的面积。
 技术问题
本发明实施例解决的问题是提供一种半导体结构及其形成方法，提升了半导体结构的性能。
 技术解决方案
为解决上述问题，本发明实施例提供一种半导体结构的形成方法，包括：提供基底、位于所述基底上的栅极结构、位于所述栅极结构两侧的基底中的源漏掺杂区、以及位于所述栅极结构侧部的基底上且覆盖源漏掺杂区的底部介质层；形成贯穿所述源漏掺杂区顶部的底部介质层、与所述源漏掺杂区相接触的源漏互连层；在所述底部介质层上形成顶部介质层，覆盖所述栅极结构和源漏互连层；形成贯穿所述栅极结构顶部的顶部介质层且暴露出栅极结构顶部的栅极接触孔、以及贯穿所述源漏互连层顶部的顶部介质层且暴露出所述源漏互连层顶部的源漏接触孔；在所述栅极接触孔和源漏接触孔的侧壁上形成牺牲侧壁层；在所述牺牲侧壁层上，形成填充于所述栅极接触孔的栅极插塞、以及填充于所述源漏接触孔的源漏插塞；去除所述牺牲侧壁层，形成暴露出所述栅极插塞侧壁和源漏插塞侧壁的第一间隙；形成密封所述第一间隙的密封层，使位于所述源漏插塞侧壁的第一间隙和位于所述栅极插塞侧壁的第一间隙中的至少一个，与所述密封层围成第一空气隙。
相应的，本发明实施例还提供一种半导体结构，包括：基底；栅极结构，位于所述基底上；源漏掺杂区，位于所述栅极结构两侧的基底中；源漏互连层，位于所述源漏掺杂区的顶部上且与所述源漏掺杂区相接触；栅极插塞，位于所述栅极结构的顶部上且与所述栅极结构相接触；源漏插塞，位于所述源漏互连层的顶部上且与所述源漏插塞相接触；介质层，覆盖所述栅极插塞和源漏插塞的侧壁，并填充于所述栅极插塞与源漏插塞之间；第一间隙，位于所述栅极插塞的侧壁与所述介质层之间、以及所述源漏插塞的侧壁与所述介质层之间；密封层，位于所述介质层上且密封所述第一间隙，位于所述源漏插塞侧壁的第一间隙和位于所述栅极插塞侧壁的第一间隙中的至少一个，与所述密封层围成第一空气隙。
 有益效果
本发明实施例提供的半导体结构的形成方法中，在形成所述栅极接触孔和源漏接触孔后，还在所述栅极接触孔和源漏接触孔的侧壁上形成牺牲侧壁层，随后在所述牺牲侧壁层上形成填充于所述栅极接触孔的栅极插塞、以及填充于所述源漏接触孔的源漏插塞，并去除所述牺牲侧壁层，形成暴露出所述栅极插塞侧壁和源漏插塞侧壁的第一间隙，之后在所述栅极插塞和源漏插塞上形成密封所述第一间隙的密封层，使位于所述源漏插塞侧壁的第一间隙和位于所述栅极插塞侧壁的第一间隙中的至少一个，与所述密封层围成第一空气隙；本发明实施例先形成用于为第一间隙占位的所述牺牲侧壁层，在形成栅极插塞和源漏插塞后，去除所述牺牲侧壁层，从而在所述栅极插塞的侧壁、以及源漏插塞的侧壁形成第一间隙，之后对所述第一间隙的顶部密封，使位于所述源漏插塞侧壁的第一间隙和位于所述栅极插塞侧壁的第一间隙中的至少一个，与所述密封层围成第一空气隙（Air Gap），空气隙具有比半导体工艺中常用介质材料（例如：低k介质材料或超低k介质材料）更低的介电常数，从而有利于降低所述栅极插塞与所述源漏插塞之间的寄生电容（Parasitic Capacitance）、减少RC（电阻电容）延迟，进而提升了半导体结构的性能。
可选方案中，所述基底包括有源区；所述形成方法还包括：在提供基底后，在形成所述源漏互连层之前，去除部分厚度的所述栅极结构，在剩余的所述栅极结构的顶部上形成栅极盖帽层；所述栅极接触孔贯穿所述有源区的栅极结构顶部的所述栅极盖帽层和顶部介质层；相应地，在形成所述栅极插塞的步骤中，所述栅极插塞位于所述有源区的栅极结构上方，所述栅极插塞为有源栅极接触孔插塞（Contact Over Active Gate，COAG），和传统位于隔离区的栅极插塞相比，本发明实施例栅极插塞与源漏插塞之间的距离更近，通过在栅极插塞的侧壁以及源漏插塞的侧壁形成第一间隙，并对第一间隙进行密封在源漏插塞和栅极插塞中的至少一个侧壁形成第一空气隙，有利于显著降低栅极插塞与源漏插塞之间的寄生电容、减少RC延迟，进而显著提升半导体结构的性能。
 附图说明
图1至图16是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
由背景技术可知，COAG工艺有利于节省芯片面积。但是，目前所形成的器件仍有性能不佳的问题。具体地，在COAG工艺中，COAG工艺形成的栅极接触插塞位于有源区（Active Area，AA）的栅极结构上方，与传统的栅极接触插塞位于隔离区域的栅极结构上方相比，栅极接触插塞和源漏接触插塞之间的距离更近，容易导致栅极接触插塞和源漏接触插塞之间的寄生电容过大，导致器件的性能不佳。
为了解决所述技术问题，本发明实施例提供的半导体结构的形成方法中，先形成用于为第一间隙占位的所述牺牲侧壁层，在形成栅极插塞和源漏插塞后，去除所述牺牲侧壁层，从而在所述栅极插塞的侧壁、以及源漏插塞的侧壁形成第一间隙，之后对所述第一间隙的顶部密封，使位于所述源漏插塞侧壁的第一间隙和位于所述栅极插塞侧壁的第一间隙中的至少一个，与所述密封层围成第一空气隙，空气隙具有比半导体工艺中常用介质材料（例如：低k介质材料或超低k介质材料）更低的介电常数，从而有利于降低所述栅极插塞与所述源漏插塞之间的寄生电容、减少RC延迟，进而提升了半导体结构的性能。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图16是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
参考图1至图5，提供基底100、位于基底100上的栅极结构110、位于栅极结构110两侧的基底100中的源漏掺杂区130、以及位于栅极结构110侧部的基底100上且覆盖源漏掺杂区130的底部介质层135。
基底100用于为后续制程提供工艺平台。本实施例中，基底100为平面型衬底。在其他实施例中，基底还能够为立体型基底，例如：基底包括衬底以及凸出于衬底的鳍部。本实施例中，基底100为硅衬底。在其他实施例中，基底还可以为其他材料类型的衬底。基底100包括有源区（Active Area，AA）100a。
栅极结构110作为器件栅极，在器件工作时，用于控制导电沟道的开启或关断。本实施例中，栅极结构110为金属栅极结构，栅极结构110通过后形成高k栅介质层后形成栅电极层（high k last metal gate last）工艺形成。
源漏掺杂区130用于在器件工作时提供载流子源。
底部介质层135用于隔离相邻器件。底部介质层135的材料为绝缘材料，包括：氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅和碳氮氧化硅中的一种或多种。本实施例中，底部介质层135的材料为氧化硅。
本实施例中，栅极结构110的侧壁与底部介质层135之间还形成有与栅极结构110侧壁接触的伪侧墙120、以及位于伪侧墙120侧壁的接触刻蚀停止层（Contact Etch Stop Layer，CESL）140，接触刻蚀停止层140还位于源漏掺杂区130与底部介质层135之间。
后续步骤还包括：去除伪侧墙120，形成暴露出栅极结构110的侧壁的第二间隙，第二间隙位于接触刻蚀停止层140与栅极结构110的侧壁之间，因此，伪侧墙120用于为形成第二间隙占据空间，从而后续形成密封第二间隙的覆盖介质层，且覆盖介质层材料的介电常数低于伪侧墙120材料的介电常数，相应使得栅极结构110的侧壁上的材料具有更低的介电常数，有利于减小半导体结构的寄生电容，例如：减少栅极结构110与后续形成的源漏互连层之间的有效电容，进而有利于提升半导体结构的性能。
而且，后续的覆盖介质层选用具有较低介电常数的材料，例如：低k介质材料或超低k介质材料等，为了使覆盖介质层的材料能够具有较低的介电常数，覆盖介质层的材料通常为结构较为疏松、致密度较低的材料，通过先形成用于为第二间隙占位的伪侧墙120，这能够灵活选择伪侧墙120的材料，使得伪侧墙120的材料与后续工艺制程相兼容（例如：对伪侧墙120材料的介电常数要求较低），相应能够选用具有较高致密度和抗刻蚀度的材料作为伪侧墙120的材料，从而有利于降低伪侧墙120在半导体结构的形成过程中被误刻蚀而受损或被去除的概率，有利于保证伪侧墙120的完整性，相应保证第二间隙的尺寸和位置满足设计要求，进而有利于保证栅极结构110与其他导电结构（例如：源漏互连层）之间的绝缘效果，相应提升了半导体结构的性能。
具体地，本实施例中，形成源漏掺杂区130的过程包括进行预清洗（Pre-clean）的步骤，形成栅极结构110包括去除伪栅结构形成暴露出伪侧墙120的栅极开口的步骤，伪侧墙120的致密度和抗刻蚀度高，有利于降低伪侧墙120在这两个步骤中被误刻蚀的几率。
本实施例中，伪侧墙120的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。作为一种示例，伪侧墙120的材料为含氧材料。具体地，伪侧墙120的材料为氧化硅。氧化硅为易于获得且为半导体工艺中常用的绝缘材料，有利于提高伪侧墙120与现有工艺的兼容性、降低工艺风险，还有利于节省成本。
伪侧墙120的厚度不宜过小，否则沿垂直于栅极结构110侧壁的方向，后续形成的第二间隙的宽度也较小，后续顶部介质层的材料难以填充于第二间隙中，从而导致降低栅极结构110与源漏互连层之间的有效电容的效果不明显；伪侧墙120的厚度也不宜过大，否则沿垂直于栅极结构110侧壁的方向，导致沟道长度过大，难以满足器件小型化的需求。为此，在平行于基底100表面且垂直于栅极结构110侧壁的方向上，伪侧墙120的厚度为2nm至12nm。
后续在源漏掺杂区130顶部的底部介质层135中形成与源漏掺杂区130相接触的源漏互连层，形成源漏互连层的过程包括刻蚀底部介质层135形成互连通孔的步骤，接触刻蚀停止层140用于在形成互连通孔的过程中暂时定义刻蚀停止的位置，从而提高刻蚀一致性且有利于防止源漏掺杂区130受损。
本实施例中，接触刻蚀停止层140的材料为低k介质材料或超低k介质材料，从而使得位于伪侧墙120与底部介质层135之间的接触刻蚀停止层140能够进一步减小栅极结构110与源漏互连层之间的有效电容。在其他实施例中，接触刻蚀停止层的材料还可以为氮化硅。
本实施例中，伪侧墙120与接触刻蚀停止层140之间还形成有防扩散层125，用于防止伪侧墙120中的易扩散离子扩散至接触刻蚀停止层140中，从而防止因离子扩散而对接触刻蚀停止层140材料造成不良影响。例如：伪侧墙120的材料为含氧材料（例如，氧化硅），当氧离子扩散至接触刻蚀停止层140中时，会导致接触刻蚀停止层140的材料介电常数变大，通过形成防扩散层125，能够降低接触刻蚀停止层140材料介电常数变大的概率。
因此，防扩散层125的致密度较高，且后续保留防扩散层125，防扩散层125的材料为绝缘材料。具体地，防扩散层125的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼、碳氮化硼、氧化铝和氮化铝中的一种多种。作为一种示例，防扩散层125的材料为氮化硅。
需要说明的是，后续形成源漏互连层后，防扩散层125也位于源漏互连层和栅极结构110之间，防扩散层125也会影响源漏互连层和栅极结构110之间的有效电容。因此，在保证防扩散层125对离子的防扩散作用的同时，为了防止源漏互连层和栅极结构110之间的有效电容过大，以及为防止源漏互连层与栅极结构110之间的距离过大而占用过多的芯片面积，防扩散层125的厚度小于或等于30Å。本实施例中，防扩散层125的厚度小于或等于15Å。其中，当防扩散层125的厚度过小时，易导致防扩散层125的防止离子扩散的作用变差，因此，本实施例中，防扩散层125的厚度为5Å至15Å。
以下结合附图对本发明提供基底100的步骤进行详细说明。
如图1所示，形成基底100；在基底100上形成伪栅结构115。
伪栅结构115用于为形成栅极结构占据空间。伪栅结构115为单层或叠层结构。本实施例中，伪栅结构115为单层结构，伪栅结构115的材料为多晶硅。
如图1所示，在伪栅结构115的侧壁上形成伪侧墙120。本实施例中，伪侧墙120还形成在伪栅结构115的顶部以及基底100上。
本实施例中，形成伪侧墙120的工艺包括原子层沉积工艺。原子层沉积工艺具有较高的阶梯覆盖能力，还有利于提高伪侧墙120的厚度均一性。
本实施例中，在形成伪侧墙120之前，形成方法还包括：在伪栅结构115的侧壁形成偏移侧墙（Offset Spacer）105。偏移侧墙105用于增大所形成晶体管的沟道长度，以改善短沟道效应以及由短沟道效应引起的热载流子效应。
本实施例中，偏移侧墙105还形成在伪栅结构115的顶部以及基底100上。相应地，伪侧墙120形成在偏移侧墙105上。
偏移侧墙105的材料为氧化硅、氮化硅、氮氧化硅、氮碳氧化硅、氮硼氧化硅或氮碳硼氧硅。本实施例中，偏移侧墙105的材料为氮化硅。
如图2所示，在伪栅结构115两侧的基底100中形成源漏掺杂区130。
本实施例中，在源漏掺杂区130之前，形成方法还包括：去除伪栅结构115两侧基底100上的伪侧墙120和偏移侧墙105，暴露出伪栅结构115两侧基底100的表面，从而为形成源漏掺杂区130做准备。
如图3所示，形成保形覆盖伪侧墙120和源漏掺杂区130的接触刻蚀停止层140。本实施例中，在形成接触刻蚀停止层140之前，形成保形覆盖伪侧墙120和源漏掺杂区130的防扩散层125。相应地，接触刻蚀停止层140形成在防扩散层125上。
形成防扩散层125的工艺包括原子层沉积工艺、化学气相沉积工艺或等离子体增强化学气相沉积工艺。本实施例中，采用原子层沉积工艺形成防扩散层125，从而易于形成厚度较小的防扩散层125，且使得防扩散层125的厚度均匀性和致密度好，此外，还使得防扩散层125具有良好的台阶覆盖能力。
如图4所示，在伪栅结构115两侧的接触刻蚀停止层140上形成露出伪栅结构115顶部的底部介质层135。
本实施例中，形成底部介质层135的步骤包括：在基底100上形成覆盖伪栅结构115顶部的初始介质层（图未示）；去除高于伪栅结构115顶部的初始介质层，形成底部介质层135。本实施例中，去除高于伪栅结构115顶部的初始介质层的步骤中，还去除位于伪栅结构115顶部的偏移侧墙105、伪侧墙120、防扩散层125以及刻蚀停止层140，从而暴露出伪栅结构115的顶部，以便于后续去除伪栅结构115。
如图5所示，去除伪栅结构115，形成栅极开口（图未示）；在栅极开口中形成栅极结构110。
结合参考图6，本实施例中，形成方法还包括：在提供基底100后，去除部分厚度的栅极结构110，在剩余的栅极结构110的顶部上形成栅极盖帽层145。本实施例中，栅极盖帽层145的顶面与底部介质层135的顶面相齐平。
栅极盖帽层145用于在后续形成源漏互连层以及形成源漏插塞的过程中，对栅极结构110的顶部起到保护的作用，从而降低栅极结构110受损以及栅极结构110与源漏互连层或源漏插塞之间发生短接问题的概率。
后续还在源漏互连层的顶面上形成源漏盖帽层，用于对源漏互连层的顶部起到保护的作用，因此，栅极盖帽层145选用与源漏盖帽层、底部介质层135以及后续形成的介质层具有刻蚀选择性的材料，从而保证栅极盖帽层145对栅极结构110的保护作用。本实施例中，栅极盖帽层145的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。作为一种示例，栅极盖帽层145的材料为氮化硅。
参考图7，形成贯穿源漏掺杂区130顶部的底部介质层135、且与源漏掺杂区130相接触的源漏互连层150。源漏互连层150与源漏掺杂区130相接触，用于使源漏掺杂区130与外部电路或其他互连结构之间实现电连接。
本实施例中，源漏互连层150的材料为铜。铜的电阻率较低，有利于改善后段RC的信号延迟，提高芯片的处理速度，同时还有利于降低源漏互连层150的电阻，相应降低了功耗。在其他实施例中，源漏互连层的材料还可以为钨或钴等导电材料。
本实施例中，源漏互连层150还贯穿位于源漏掺杂区130上的接触刻蚀停止层140以及防扩散层125。
本实施例中，形成方法还包括：在形成源漏互连层150之后，去除部分厚度的源漏互连层150，在剩余的源漏互连层150顶部上形成源漏盖帽层155。
本实施例中，源漏盖帽层155的顶面与底部介质层135的顶面相齐平。
后续形成与栅极结构110相接触的栅极插塞，源漏盖帽层155位于源漏互连层150的顶面，在形成栅极插塞的过程中，源漏盖帽层155能够对源漏互连层150起到保护的作用，有利于降低源漏互连层150受损以及降低栅极插塞与源漏互连层150发生短接的概率。
源漏盖帽层155选用与栅极盖帽层145、伪侧墙120、底部介质层135以及后续介质层具有较高刻蚀选择性的材料，从而保证源漏盖帽层155对源漏互连层150的保护作用。本实施例中，源漏盖帽层155的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种。具体地，源漏盖帽层155和栅极盖帽层145的材料不同，源漏盖帽层155和伪侧墙120的材料不同。作为一种示例，源漏盖帽层155的材料为碳化硅。
参考图8，在底部介质层135上形成顶部介质层160，覆盖栅极结构110和源漏互连层150。
后续在顶部介质层160中形成与源漏互连层150相接触的源漏插塞、以及与栅极结构110相接触的栅极插塞，顶部介质层160用于实现源漏插塞和栅极插塞之间的电隔离。此外，本实施例中，后续还会去除顶部介质层160和伪侧墙120，在底部介质层135与栅极结构110的侧壁之间形成第二间隙；在底部介质层135上形成密封第二间隙的顶部的覆盖介质层。顶部介质层160还用于为形成覆盖介质层占据空间位置。
本实施例中，顶部介质层160覆盖栅极盖帽层145和源漏盖帽层155。
顶部介质层160的材料为绝缘材料。而且，本实施例中，后续还会刻蚀顶部介质层160，因此，顶部介质层160选用易于被刻蚀的材料。顶部介质层160的材料包括氧化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼、碳氮化硼、氧化铝和氮化铝中的一种或多种。本实施例中，顶部介质层160的材料为氧化硅。
参考图9，形成贯穿栅极结构110顶部的顶部介质层160且暴露出栅极结构110顶部的栅极接触孔10、以及贯穿源漏互连层150顶部的顶部介质层160且暴露出源漏互连层150顶部的源漏接触孔20。
栅极接触孔10用于为形成栅极插塞提供空间位置。源漏接触孔20用于为形成源漏插塞提供空间位置。本实施例中，栅极接触孔10和源漏接触孔20还用于为后续形成牺牲侧壁层预留空间，栅极接触孔10和源漏接触孔20的侧壁用于为形成牺牲侧壁层提供支撑的作用。
后续形成的牺牲侧壁层具有厚度，因此，为了使栅极接触孔10能够为形成牺牲侧壁层和栅极插塞预留足够的空间，本实施例可根据实际工艺需求适当增大栅极接触孔10的开口尺寸。同样的，为了使源漏接触孔20能够为形成牺牲侧壁层和源漏插塞预留足够的空间，本实施例可根据实际工艺需求适当增大源漏接触孔20的开口尺寸。
本实施例中，栅极接触孔10贯穿有源区100a的栅极结构110顶部的栅极盖帽层145和顶部介质层160。具体地，本实施例中，为增大栅极接触孔10的尺寸，栅极接触孔10还贯穿位于栅极盖帽层145侧壁的部分偏移侧墙105。因此，栅极接触孔10还暴露出部分的伪侧墙120。
本实施例中，源漏接触孔20贯穿源漏互连层150顶部的源漏盖帽层155和顶部介质层160。
本实施例中，分别在不同步骤中形成源漏接触孔20和栅极接触孔10。
参考图10至图11，在栅极接触孔10和源漏接触孔20的侧壁上形成牺牲侧壁层170。
形成牺牲侧壁层170后，栅极接触孔10中的剩余空间用于形成栅极插塞，源漏接触孔20中的剩余空间用于形成源漏插塞。
牺牲侧壁层170用于为形成第一间隙占据空间，也就是说，后续去除牺牲侧壁层170，形成暴露出栅极插塞侧壁和源漏插塞侧壁的第一间隙，并在栅极插塞和源漏插塞上形成密封第一间隙的密封层，使第一间隙与密封层围成第一空气隙，空气隙具有比半导体工艺中常用介质材料（例如：低k介质材料或超低k介质材料）更低的介电常数，从而有利于降低栅极插塞与源漏插塞之间的寄生电容、减少RC延迟，进而提升了半导体结构的性能。
后续还需去除牺牲侧壁层170，因此，牺牲侧壁层170选用易于被去除的材料，从而降低去除牺牲侧壁层170的难度；而且，牺牲侧壁层170的材料选取为：与栅极盖帽层145、源漏盖帽层155、底部介质层135、顶部介质层160、以及源漏插塞和栅极插塞之间均具有刻蚀选择性的材料，从而在后续去除牺牲侧壁层170的步骤中，牺牲侧壁层170与这些膜层结构均具有刻蚀选择比，有利于降低去除牺牲侧壁层170对其他膜层的损伤，进而提高工艺兼容性。
本实施例中，牺牲侧壁层170的材料包括无定形硅、碳氧化硅、氧化硅、氮化硅、碳化硅、氮化硼、氧化铝、氮化铝和氮氧化硅中的一种或几种。作为一种示例，牺牲侧壁层170的材料为无定形硅。
需要说明的是，沿垂直于栅极接触孔10侧壁或垂直于源漏接触孔20侧壁的方向，牺牲侧壁层170的厚度不宜过小，也不宜过大。如果牺牲侧壁层170的厚度过小，后续去除牺牲侧壁层170形成的第一间隙的宽度也过小，第一空气隙的宽度相应也过小，容易导致第一空气隙用于减小源漏插塞与栅极插塞之间寄生电容的效果不明显；如果牺牲侧壁层170的厚度过大，则后续第一间隙的宽度也过大，后续密封层的材料容易填充至第一间隙内，进而导致难以形成第一空气隙，而且牺牲侧壁层170的宽度过大还容易增加后续去除牺牲侧壁层170的难度，相应易增加工艺风险。为此，本实施例中，牺牲侧壁层170的厚度为10Å至40Å，例如：牺牲侧壁层170的厚度为20Å、30Å。
以下结合附图对本实施例中形成牺牲侧壁层170的步骤进行详细说明。
如图10所示，在栅极接触孔10的侧壁和底部、源漏接触孔20的侧壁和底部以及顶部介质层160的顶面上形成侧壁材料层165。
形成侧壁材料层165的工艺包括原子层沉积和化学气相沉积中的一种或两种工艺。作为一种示例，采用原子层沉积工艺形成侧壁材料层165。原子层沉积工艺是基于原子层沉积过程的自限制反应过程，沉积所得薄膜可以达到单层原子的厚度，有利于形成较薄的侧壁材料层165，相应有利于使牺牲侧壁层的厚度满足工艺要求；而且，原子层沉积工艺还具有较高的阶梯覆盖能力，从而提高侧壁材料层165在栅极接触孔10和源漏接触孔20的侧壁上的覆盖能力，相应提高侧壁材料层165的厚度均匀性和成膜质量。
在其他实施例中，还可以选用化学气相沉积工艺形成侧壁材料层。化学气相沉积工艺可以为传统的化学气相沉积工艺，也可以为引入等离子体处理功能的化学气相沉积工艺。其中，引入等离子体处理功能的化学气相沉积工艺包括多次的沉积循环，在每一次沉积循环中，在沉积成膜后，还包括对沉积薄膜进行等离子体处理（Plasma Treatment），以提高薄膜的致密度和覆盖能力。具体地，等离子体处理采用的气体包括氢气、氦气、氩气、氧气和氮气中的一种或多种气体，等离子体处理能够利用带有能量的等离子体，减少或去除沉积薄膜表面的悬挂键，从而提高沉积薄膜的致密度，并为下一次的沉积循环做准备。
如图11所示，去除位于栅极接触孔10和源漏接触孔20的底部、以及顶部介质层160顶面上的侧壁材料层165，剩余位于栅极接触孔10和源漏接触孔20侧壁上的侧壁材料层165用于作为牺牲侧壁层170。
由于侧壁材料层165保形覆盖于栅极接触孔10和源漏接触孔20的底部与侧壁、以及顶部介质层160顶面，因此，本实施例能够在无掩膜的环境下，通过各向异性的刻蚀工艺，去除位于栅极接触孔10和源漏接触孔20的底部、以及顶部介质层160顶面上的侧壁材料层165。各向异性的刻蚀工艺具有各向异性刻蚀的特性，该刻蚀工艺在沿垂直于基底100表面方向（即纵向）的刻蚀速率大于在沿平行于基底100方向（即横向）的刻蚀速率，从而能够将位于栅极接触孔10和源漏接触孔20的底部、以及顶部介质层160顶面的侧壁材料层165刻蚀去除，同时位于栅极接触孔10和源漏接触孔20侧壁上的侧壁材料层165能够被保留用于作为牺牲侧壁层。具体地，各向异性的刻蚀工艺包括各向异性的干法刻蚀工艺。干法刻蚀工艺的工艺可控性、刻蚀精度和刻蚀效率高。
参考图12，在牺牲侧壁层170上，形成填充于栅极接触孔10的栅极插塞11、以及填充于源漏接触孔20的源漏插塞21。
栅极插塞11用于实现栅极结构110与外部电路或其他互连结构之间的电连接。
本实施例中，栅极插塞11形成于所述有源区100a的栅极结构110上方，栅极插塞11为有源栅极接触孔插塞（COAG），有利于节省芯片的面积，从而实现芯片尺寸的进一步缩小。
源漏插塞21与源漏互连层150相接触，从而通过源漏互连层150使源漏掺杂区130与外部电路或其他互连结构之间实现电连接。
对栅极插塞11和源漏插塞21的材料的具体描述，可结合参考前述对源漏互连层150的描述，在此不再赘述。
本实施例中，在形成源漏接触孔20和栅极接触孔10后，在同一步骤中，形成源漏插塞21和栅极插塞11。
需要说明的是，本实施例中，在形成栅极插塞11和源漏插塞21之后，所述半导体结构的形成方法还包括以下步骤。
参考图13，刻蚀位于伪侧墙120顶部以及牺牲侧壁层170之间的顶部介质层160，暴露出伪侧墙120的顶面和牺牲侧壁层170的侧壁；去除伪侧墙120，在接触刻蚀停止层140与栅极结构110的侧壁之间形成第二间隙40。
第二间隙40用于为后续覆盖介质层提供形成空间。具体地，本实施例中，在防扩散层125与偏移侧墙105之间、以及防扩散层125与牺牲侧壁层170之间，形成第二间隙40。
本实施例中，采用各向同性的刻蚀工艺，去除顶部介质层160和伪侧墙120。通过采用各向同性的刻蚀工艺，以便于能够将顶部介质层160和伪侧墙120去除干净，而且，刻蚀速率较快。本实施例中，各向同性的刻蚀工艺为远程等离子体（Remote Plasma）刻蚀工艺。远程等离子体蚀刻工艺具有各向同性的刻蚀特性，而且，远程等离子体刻蚀工艺也具有较好的刻蚀选择性，从而在刻蚀的过程中，减小对其他膜层的损耗。其中，远程等离子体蚀刻工艺的原理是在刻蚀腔室外部形成等离子体（例如：通过远程等离子体发生器产生等离子体），然后引入刻蚀腔室中并利用等离子体与被刻蚀层的化学反应进行蚀刻，因而可以实现各向同性的刻蚀效果，且因为没有离子轰击，因而不会损伤其他膜层。
在其他实施例中，各向同性的刻蚀工艺也可以为湿法刻蚀工艺。
本实施例中，顶部介质层160和伪侧墙120的材料相同，因此，能够在同一刻蚀步骤中去除顶部介质层160和伪侧墙120，简化了工艺步骤。
参考图14，在底部介质层135上形成覆盖牺牲侧壁层170侧壁的覆盖介质层180，覆盖介质层180密封第二间隙40，覆盖介质层180材料的介电常数低于伪侧墙120材料的介电常数。
通过去除伪侧墙120，并形成材料介电常数更低的覆盖介质层180，覆盖介质层180密封第二间隙40，从而降低栅极结构110和源漏互连层150之间的有效电容，进而提高半导体结构的性能。此外，本实施例中，覆盖介质层180还用于实现源漏插塞21与栅极插塞11之间的电隔离，而且，后续去除牺牲侧壁层170，覆盖介质层180与栅极插塞11的侧壁或源漏插塞21的侧壁之间具有第一间隙；覆盖介质层180还为后续形成密封第一间隙的密封层提供支撑作用。
本实施例中，以覆盖介质层180填充于第二间隙40内作为示例，从而实现对第二间隙40的密封。在其他实施例中，当第二间隙的深宽比（Aspect Ratio，AR）较大时，覆盖介质层还能够密封第二间隙的顶部，使第二间隙与覆盖介质层围成第二空气隙。空气的介电常数较小，相应有利于进一步降低栅极结构和源漏互连层之间的有效电容。
本实施例中，覆盖介质层180的材料包括低k介质材料或超低k介质材料，有利于降低栅极结构110和源漏互连层150之间的有效电容、以及源漏插塞21与栅极插塞11之间的寄生电容，减少集成电路中互连结构的RC延迟。
形成覆盖介质层180的工艺包括流动式化学气相沉积工艺、原子层沉积工艺、旋涂工艺和化学气相沉积工艺中的一种或几种。本实施例中，形成覆盖介质层180的工艺包括旋涂工艺。旋涂工艺的工艺温度较低，从而避免高温所引起的沟道退化问题，有利于提高半导体结构的性能，而且，旋涂工艺的间隙填充能力较高，有利于提高覆盖介质层180在第二间隙40以及源漏插塞21和栅极插塞11之间的填充质量。
本实施例中，形成覆盖介质层180的步骤包括：在底部介质层135上形成覆盖牺牲侧壁层170侧壁的介质材料层（图未示），介质材料层还覆盖栅极插塞11和源漏插塞21的顶部，介质材料层密封第二间隙40；去除高于栅极插塞11和源漏插塞21顶部的介质材料层。
本实施例中，采用旋涂工艺形成介质材料层。
参考图15，去除牺牲侧壁层170，形成暴露出栅极插塞11侧壁和源漏插塞21侧壁的第一间隙30。第一间隙30用于与后续形成的密封层围成第一空气隙。
本实施例中，在覆盖介质层180与栅极插塞11的侧壁之间、以及覆盖介质层180与源漏插塞21的侧壁之间形成第一间隙30。
本实施例中，采用各向同性的刻蚀工艺去除牺牲侧壁层170。采用各向同性的刻蚀工艺，以便于能够将牺牲侧壁层170去除干净，而且刻蚀速率较快。
本实施例中，各向同性的刻蚀工艺为远程等离子体刻蚀工艺。远程等离子体蚀刻工艺具有各向同性的刻蚀特性，而且，远程等离子体刻蚀工艺也具有较好的刻蚀选择性，从而在刻蚀的过程中，减小对其他膜层的损耗。其中，远程等离子体蚀刻工艺的原理是在刻蚀腔室外部形成等离子体（例如：通过远程等离子体发生器产生等离子体），然后引入刻蚀腔室中并利用等离子体与被刻蚀层的化学反应进行蚀刻，因而可以实现各向同性的刻蚀效果，且因为没有离子轰击，因而不会损伤其他膜层。
在其他实施例中，各向同性的刻蚀工艺也可以为湿法刻蚀工艺。
参考图16，形成密封第一间隙30的密封层190，使位于源漏插塞21侧壁的第一间隙30和位于栅极插塞11侧壁的第一间隙30中的至少一个，与密封层190围成第一空气隙50。
本实施例通过使位于源漏插塞21侧壁的第一间隙30和位于栅极插塞11侧壁的第一间隙30中的至少一个，与密封层190围成第一空气隙（Air Gap）50，空气隙具有比半导体工艺中常用介质材料（例如：低k介质材料或超低k介质材料）更低的介电常数，从而有利于降低栅极插塞11与源漏插塞21之间的寄生电容、减少RC延迟，进而提升了半导体结构的性能。
本实施例中，栅极插塞11为有源栅极接触孔插塞（COAG），和传统位于隔离区的栅极插塞相比，本实施例栅极插塞11与源漏插塞12之间的距离更近，通过在栅极插塞11的侧壁以及源漏插塞21的侧壁形成第一间隙30，并密封第一间隙30，在源漏插塞21和栅极插塞11中的至少一个的侧壁形成第一空气隙50，有利于显著降低栅极插塞11与源漏插塞12之间的寄生电容、减少RC延迟问题，进而显著提升半导体结构的性能。
本实施例中，密封层190覆盖源漏插塞21、栅极插塞11以及覆盖介质层180的顶部。后续制程还包括：在源漏插塞21和栅极插塞11的顶部形成金属互连线，用于实现源漏插塞21与外部电路、以及栅极插塞11与外部电路之间的电连接，金属互连线形成于金属层间介质（Inter Metal Dielectric，IMD）层中，通过使密封层190覆盖源漏插塞180的顶部，使得高于源漏插塞180顶部的密封层190作为金属层间介质层，从而简化后段（BEOL）制程的工艺步骤、并使密封层190与后段工艺相兼容。
密封层190的材料为介质材料。对密封层190的材料的具体描述，可结合参考前述对覆盖介质层180的描述，在此不再赘述。
作为一种示例，密封层190在位于源漏插塞21侧壁的第一间隙30的顶部拐角处相接触，从而将第一间隙30的顶部密封，进而使位于源漏插塞21侧壁的第一间隙30与密封层190围成第一空气隙50。
作为一种示例，密封层190填充于位于栅极插塞11侧壁的第一间隙30中。
具体地，本实施例中，源漏插塞21的剖面为上大下小的倒梯形，位于源漏插塞21侧壁的第一间隙30侧壁相应也具有一定的倾斜角度，栅极插塞11的侧壁垂直度大于源漏插塞21侧壁的垂直度，因此，密封层190在位于源漏插塞21侧壁的第一间隙30中的填充难度，大于在位于栅极插塞11侧壁的第一间隙30中的填充难度，相应地，密封层190易于与源漏插塞21侧壁的第一间隙30围成第一空气隙50，密封层190填充位于栅极插塞11侧壁的第一间隙30中。
在其他实施例中，根据位于栅极插塞的第一间隙的深宽比、以及栅极插塞的剖面形貌、第一间隙的侧壁倾斜度等实际工艺条件，密封层还能够在位于栅极插塞侧壁的第一间隙的顶部拐角处相接触，从而将该第一间隙的顶部密封，进而使位于栅极插塞侧壁的第一间隙与密封层也围成第一空气隙。在另一些实施例中，还可以仅使位于栅极插塞侧壁的第一间隙与密封层围成第一空气隙。
本实施例中，采用填充能力较弱的沉积工艺，形成密封层190，从而使密封层190不易填充至第一间隙30中，进而使密封层190易于在第一间隙30的顶部拐角处相接触形成第一空气隙50。本实施例中，形成密封层190的工艺包括化学气相沉积工艺和等离子体增强化学气相沉积工艺中的一种或两种。
需要说明的是，本实施例中，以COAG工艺为例进行说明。在其他实施例中，当栅极插塞位于隔离区的栅极结构顶部时，通过本实施例提供的半导体结构的形成方法，仍能够起到降低源漏插塞和栅极结构之间的寄生电容的效果。
相应的，本发明还提供一种半导体结构。参考图16，示出了本发明半导体结构一实施例的结构示意图。
所述半导体结构包括：基底100；栅极结构110，位于基底100上；源漏掺杂区130，位于栅极结构110两侧的基底100中；源漏互连层150，位于源漏掺杂区130的顶部上且与源漏掺杂区130相接触；栅极插塞11，位于栅极结构110的顶部上且与栅极结构110相接触；源漏插塞21，位于源漏互连层150的顶部上且与源漏插塞21相接触；介质层180，覆盖栅极插塞11和源漏插塞21的侧壁，并填充于栅极插塞11与源漏插塞21之间；第一间隙30（如图15所示），位于栅极插塞11的侧壁与介质层180之间、以及源漏插塞21的侧壁与介质层180之间；密封层190，位于介质层180上且密封第一间隙30，位于源漏插塞21侧壁的第一间隙30和位于栅极插塞11侧壁的第一间隙30中的至少一个，与密封层190围成第一空气隙50。
通过设置暴露出栅极插塞11侧壁和源漏插塞12侧壁的第一间隙30，以及设置密封层190，位于源漏插塞21侧壁的第一间隙30和位于栅极插塞11侧壁的第一间隙30中的至少一个，与密封层190围成第一空气隙50，空气隙具有比半导体工艺中常用介质材料（例如：低k介质材料或超低k介质材料）更低的介电常数，从而有利于降低栅极插塞11与源漏插塞21之间的寄生电容、减少RC延迟，进而提升了半导体结构的性能。
基底100用于为工艺制程提供平台。本实施例中，基底100为平面型衬底。本实施例中，基底100为硅衬底。基底100包括有源区100a。
栅极结构110作为器件栅极，在器件工作时，用于控制导电沟道的开启或关断。
本实施例中，栅极结构110为金属栅极结构，栅极结构110通过后形成高k栅介质层后形成栅电极层工艺形成。
源漏掺杂区130用于在器件工作时提供载流子源。
本实施例中，半导体结构还包括：底部介质层135（如图6所示），位于栅极结构110露出的基底100上。底部介质层135用于隔离相邻器件。本实施例中，底部介质层135的材料为氧化硅。
源漏互连层150与源漏掺杂区130相接触，用于使源漏掺杂区130与外部电路或其他互连结构之间实现电连接。本实施例中，源漏互连层150的材料为铜。在其他实施例中，源漏互连层的材料还可以为钨或钴等导电材料。
本实施例中，源漏互连层150贯穿位于源漏掺杂区130上的底部介质层135。
本实施例中，半导体结构还包括：栅极盖帽层145（如图8所示），位于所述栅极结构110的顶部与介质层180之间；源漏盖帽层155，位于源漏互连层150的顶部与所述介质层180之间。
本实施例中，源漏盖帽层155的顶面与底部介质层135的顶面相齐平。
源漏盖帽层155位于源漏互连层150的顶面，用于在栅极插塞11的形成过程中，对源漏互连层150起到保护的作用，有利于降低源漏互连层150受损、以及降低栅极插塞11与源漏互连层150发生短接的概率。
栅极盖帽层145用于在形成源漏互连层150以及形成源漏插塞21的过程中，对栅极结构110的顶部起到保护的作用，从而降低栅极结构110受损以及降低栅极结构110与源漏互连层150或源漏插塞11之间发生短接问题的概率。
关于栅极盖帽层145和源漏盖帽层155的材料的具体描述，可参考前述实施例中的相应描述，在此不再赘述。
本实施例中，半导体结构还包括：接触刻蚀停止层140，位于源漏互连层150的侧壁和栅极结构110之间的基底100上，且与栅极结构110的侧壁相对设置，接触刻蚀停止层140和栅极结构110的侧壁之间具有第二间隙40（如图13所示）。
接触刻蚀停止层140还位于源漏掺杂区130的顶面，接触刻蚀停止层140用于在源漏互连层150的形成过程中暂时定义刻蚀停止的位置，从而提高刻蚀一致性且有利于防止源漏掺杂区130受损。本实施例中，接触刻蚀停止层140的材料为低k介质材料或超低k介质材料，从而使得接触刻蚀停止层140，能够进一步减小栅极结构110与源漏互连层150之间的有效电容。在其他实施例中，接触刻蚀停止层的材料还可以为氮化硅。
本实施例中，介质层180为覆盖介质层180。覆盖介质层180密封第二间隙40。第二间隙40用于为覆盖介质层180提供形成空间。
覆盖介质层180密封第二间隙40，从而降低栅极结构110和源漏互连层150之间的有效电容，进而提高半导体结构的性能。
本实施例中，覆盖介质层180的材料包括低k介质材料或超低k介质材料。本实施例中，所述覆盖介质层180填充于第二间隙40。其他实施例中，当第二间隙的深宽比（Aspect Ratio，AR）较大时，覆盖介质层密封第二间隙的顶部，第二间隙与覆盖介质层围成第二空气隙。空气的介电常数较小，相应有利于进一步降低栅极结构和源漏互连层之间的有效电容。
本实施例中，在平行于基底100表面且垂直于栅极结构110侧壁的方向上，第二间隙40的宽度为2nm至12nm。
本实施例中，半导体结构还包括：防扩散层125，位于第二间隙40露出的接触刻蚀停止层140的侧壁。所述第二间隙40通过去除伪侧墙形成，所述防扩散层125用于防止伪侧墙中的易扩散离子扩散至接触刻蚀停止层140中，从而防止因离子扩散而对接触刻蚀停止层140造成不良影响。
因此，防扩散层125的致密度较高，且防扩散层125的材料为绝缘材料。具体地，防扩散层125的材料包括氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼、碳氮化硼、氧化铝和氮化铝中的一种多种。作为一种示例，防扩散层125的材料为氮化硅。
需要说明的是，防扩散层125也位于源漏互连层150和栅极结构110之间，防扩散层125也会影响源漏互连层150和栅极结构110之间的有效电容。因此，在保证防扩散层125对离子的防扩散作用的同时，为了防止源漏互连层150和栅极结构110之间的有效电容过大以及防止占用过大的芯片面积，防扩散层125的厚度小于或等于30Å。本实施例中，防扩散层125的厚度小于或等于15Å。其中，当防扩散层125的厚度过小时，容易导致防扩散层125的防止离子扩散的作用变差。本实施例中，防扩散层125的厚度为5Å至15Å。
本实施例中，半导体结构还包括：偏移侧墙105，位于第二间隙40露出的栅极结构110的侧壁。偏移侧墙105用于改善短沟道效应以及由短沟道效应引起的热载流子效应。
本实施例中，偏移侧墙105还位于第二间隙40露出的基底100上。偏移侧墙105的材料为氧化硅、氮化硅、氮氧化硅、氮碳氧化硅、氮硼氧化硅或氮碳硼氧硅。
栅极插塞11用于实现栅极结构110与外部电路或其他互连结构之间的电连接。
本实施例中，栅极插塞11位于有源区100a的栅极结构110上方，栅极插塞11为有源栅极接触孔插塞，与栅极插塞与位于隔离区的栅极结构相接触的方案相比，本实施例省去了栅极结构110位于隔离区的部分，有利于节省芯片的面积，从而实现芯片尺寸的进一步缩小。
源漏插塞21与源漏互连层150相接触，从而通过源漏互连层150使源漏掺杂区130与外部电路或其他互连结构之间实现电连接。
对栅极插塞11和源漏插塞21的具体描述，可结合参考前述对源漏互连层150的描述，在此不再赘述。
本实施例中，覆盖介质层180密封第二间隙40，从而降低栅极结构110和源漏互连层150之间的有效电容，进而提高半导体结构的性能。此外，本实施例中，覆盖介质层180还用于实现源漏插塞21与栅极插塞11之间的电隔离，而且，覆盖介质层180还为形成密封第一间隙30的密封层190提供支撑作用。
本实施例中，覆盖介质层180的材料包括低k介质材料或超低k介质材料，从而能够降低栅极结构110和源漏互连层150之间的有效电容，而且还有利于降低源漏插塞21与栅极插塞11之间的寄生电容，减少RC延迟。
第一间隙30用于形成第一空气隙50，从而有利于降低源漏插塞21与栅极插塞11之间的寄生电容。
沿垂直于栅极插塞11侧壁或垂直于源漏插塞21侧壁的方向，第一间隙30的宽度不宜过小，也不宜过大。如果第一间隙30的宽度过小，第一空气隙50的宽度相应也过小，容易导致第一空气隙50用于减小源漏插塞21与栅极插塞11之间寄生电容的效果不明显；如果第一间隙30的宽度过大，则密封层190的材料容易填充至第一间隙30内，进而导致难以形成第一空气隙50。为此，本实施例中，沿垂直于栅极插塞11侧壁或垂直于源漏插塞21侧壁的方向，第一间隙30的宽度为10Å至40Å，例如：第一间隙30的宽度为20Å、30Å。
密封层190用于密封第一间隙30，从而形成第一空气隙50。空气隙具有比半导体工艺中常用介质材料（例如：低k介质材料或超低k介质材料）更低的介电常数，从而有利于降低栅极插塞11与源漏插塞21之间的寄生电容、减少RC延迟，进而提升了半导体结构的性能。
本实施例中，栅极插塞11为有源栅极接触孔插塞（COAG），和传统位于隔离区的栅极插塞相比，栅极插塞11与源漏插塞12之间的距离更近，通过设置第一空气隙50，有利于显著降低栅极插塞11与源漏插塞12之间的寄生电容、减少RC延迟问题，进而显著提升半导体结构的性能。
本实施例中，密封层190覆盖源漏插塞21、栅极插塞11以及覆盖介质层180的顶部。后续制程还包括：在源漏插塞21和栅极插塞11的顶部形成金属互连线，用于实现源漏插塞21或栅极插塞11与外部电路之间的电连接，金属互连线形成于金属层间介质（IMD）层中，通过使密封层190覆盖源漏插塞180的顶部，使得密封层190高于源漏插塞180顶部的部分作为金属层间介质层，从而简化后段（BEOL）制程的工艺步骤、并使密封层190与后段工艺相兼容。
密封层190的材料为介质材料。对密封层190的材料的具体描述，可结合参考前述对覆盖介质层180的描述，在此不再赘述。
作为一种示例，密封层190在位于源漏插塞21侧壁的第一间隙30的顶部拐角处相接触，从而将第一间隙30的顶部密封，进而使位于源漏插塞21侧壁的第一间隙30与密封层190围成第一空气隙50。
作为一种示例，密封层190填充于位于栅极插塞11侧壁的第一间隙30中。
具体地，本实施例中，源漏插塞21的剖面为上大下小的倒梯形，位于源漏插塞21侧壁的第一间隙30侧壁相应也具有一定的倾斜角度，栅极插塞11的侧壁垂直度大于源漏插塞21侧壁的垂直度，因此，密封层190在位于源漏插塞21侧壁的第一间隙30中的填充难度，大于在位于栅极插塞11侧壁的第一间隙30中的填充难度，相应地，密封层190易于与源漏插塞21侧壁的第一间隙30围成第一空气隙50，密封层190填充于位于栅极插塞11侧壁的第一间隙30中。
在其他实施例中，根据位于栅极插塞侧壁的第一间隙的深宽比、以及栅极插塞的剖面形貌、第一间隙的侧壁倾斜度等实际工艺条件，密封层还能够在位于栅极插塞侧壁的第一间隙的顶部拐角处相接触，从而将该第一间隙的顶部密封，进而使位于栅极插塞侧壁的第一间隙与密封层也围成第一空气隙。在另一些实施例中，还可以仅使位于栅极插塞侧壁的第一间隙与密封层围成第一空气隙。
需要说明的是，本实施例中，以栅极插塞11为COAG为例进行说明。在其他实施例中，当栅极插塞位于隔离区的栅极结构顶部时，通过本实施例提供的半导体结构，仍能够起到降低源漏插塞和栅极结构之间的寄生电容的效果。
所述半导体结构可以采用前述实施例所述的形成方法所形成，也可以采用其他形成方法所形成。对本实施例所述半导体结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种半导体结构，其特征在于，包括：
    基底；
    栅极结构，位于所述基底上；
    源漏掺杂区，位于所述栅极结构两侧的基底中；
    源漏互连层，位于所述源漏掺杂区的顶部上且与所述源漏掺杂区相接触；
    栅极插塞，位于所述栅极结构的顶部上且与所述栅极结构相接触；
    源漏插塞，位于所述源漏互连层的顶部上且与所述源漏插塞相接触；
    介质层，覆盖所述栅极插塞和源漏插塞的侧壁，并填充于所述栅极插塞与源漏插塞之间；
    第一间隙，位于所述栅极插塞的侧壁与所述介质层之间、以及所述源漏插塞的侧壁与所述介质层之间；
    密封层，位于所述介质层上且密封所述第一间隙，位于所述源漏插塞侧壁的第一间隙和位于所述栅极插塞侧壁的第一间隙中的至少一个，与所述密封层围成第一空气隙。
  2. 如权利要求1所述的半导体结构，其特征在于，所述基底包括有源区；所述半导体结构还包括：栅极盖帽层，位于所述栅极结构的顶部与所述介质层之间；源漏盖帽层，位于所述源漏互连层的顶部与所述介质层之间；所述栅极插塞位于所述有源区的栅极结构上方。
  3. 如权利要求1所述的半导体结构，其特征在于，沿垂直于所述栅极插塞或所述源漏插塞侧壁的方向，所述第一间隙的宽度为10Å至40Å。
  4. 如权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：接触刻蚀停止层，位于所述源漏互连层的侧壁和栅极结构之间的基底上且与所述栅极结构的侧壁相对设置，所述接触刻蚀停止层和栅极结构的侧壁之间具有第二间隙；
    所述介质层填充于所述第二间隙，或者，所述介质层密封所述第二间隙的顶部，所述第二间隙与所述介质层围成第二空气隙。
  5. 如权利要求1或4所述的半导体结构，其特征在于，所述介质层的材料包括低k介质材料或超低k介质材料。
  6. 一种半导体结构的形成方法，其特征在于，包括：
    提供基底、位于所述基底上的栅极结构、位于所述栅极结构两侧的基底中的源漏掺杂区、以及位于所述栅极结构侧部的基底上且覆盖源漏掺杂区的底部介质层；
    形成贯穿所述源漏掺杂区顶部的底部介质层、且与所述源漏掺杂区相接触的源漏互连层；
    在所述底部介质层上形成顶部介质层，覆盖所述栅极结构和源漏互连层；
    形成贯穿所述栅极结构顶部的顶部介质层且暴露出栅极结构顶部的栅极接触孔、以及贯穿所述源漏互连层顶部的顶部介质层且暴露出所述源漏互连层顶部的源漏接触孔；
    在所述栅极接触孔和源漏接触孔的侧壁上形成牺牲侧壁层；
    在所述牺牲侧壁层上，形成填充于所述栅极接触孔的栅极插塞、以及填充于所述源漏接触孔的源漏插塞；
    去除所述牺牲侧壁层，形成暴露出所述栅极插塞侧壁和源漏插塞侧壁的第一间隙；
    形成密封所述第一间隙的密封层，使位于所述源漏插塞侧壁的第一间隙和位于所述栅极插塞侧壁的第一间隙中的至少一个，与所述密封层围成第一空气隙。
  7. 如权利要求6所述的半导体结构的形成方法，其特征在于，提供基底的步骤中，所述基底包括有源区；
    所述半导体结构的形成方法还包括：在提供基底后，形成所述顶部介质层之前，去除部分厚度的所述栅极结构，在剩余的所述栅极结构的顶部上形成栅极盖帽层；
    在形成所述源漏互连层之后，形成所述顶部介质层之前，去除部分厚度的所述源漏互连层，在剩余的所述源漏互连层顶部上形成源漏盖帽层；
    所述顶部介质层覆盖所述栅极盖帽层和所述源漏盖帽层；所述栅极接触孔贯穿所述有源区的栅极结构顶部的所述栅极盖帽层和顶部介质层；所述源漏接触孔贯穿所述源漏互连层顶部的源漏盖帽层和顶部介质层。
  8. 如权利要求6所述的半导体结构的形成方法，其特征在于，提供基底的步骤中，所述栅极结构的侧壁和底部介质层之间还形成有与栅极结构侧壁接触的伪侧墙以及位于所述伪侧墙侧壁的接触刻蚀停止层，所述接触刻蚀停止层还位于所述源漏掺杂区与底部介质层之间；
    所述半导体结构的形成方法还包括：在形成所述栅极插塞和源漏插塞之后，去除所述牺牲侧壁层之前，刻蚀位于所述伪侧墙顶部以及牺牲侧壁层之间的所述顶部介质层，暴露出所述伪侧墙的顶面和牺牲侧壁层的侧壁；去除所述伪侧墙，在所述接触刻蚀停止层与所述栅极结构的侧壁之间形成第二间隙；在所述底部介质层上形成覆盖所述牺牲侧壁层侧壁的覆盖介质层，所述覆盖介质层填充于所述第二间隙内，所述覆盖介质层材料的介电常数低于所述伪侧墙材料的介电常数，或者，所述覆盖介质层密封所述第二间隙的顶部，使所述第二间隙与所述覆盖介质层围成第二空气隙；
    去除所述牺牲侧壁层的步骤中，在所述覆盖介质层与所述栅极插塞的侧壁之间、以及所述覆盖介质层与所述源漏插塞的侧壁之间形成所述第一间隙。
  9. 如权利要求6所述的半导体结构的形成方法，其特征在于，形成所述牺牲侧壁层的步骤包括：在所述栅极接触孔的侧壁和底部、源漏接触孔的侧壁和底部、以及所述顶部介质层的顶面上形成侧壁材料层；
    去除位于所述栅极接触孔和源漏接触孔的底部、以及所述顶部介质层顶面上的侧壁材料层，剩余位于所述栅极接触孔和源漏接触孔侧壁上的侧壁材料层用于作为所述牺牲侧壁层。
  10. 如权利要求9所述的半导体结构的形成方法，其特征在于，形成所述侧壁材料层的工艺包括原子层沉积和化学气相沉积中的一种或两种工艺。
  11. 如权利要求9所述的半导体结构的形成方法，其特征在于，去除位于所述栅极接触孔和源漏接触孔的底部、以及所述顶部介质层顶面上的侧壁材料层的工艺包括各向异性的干法刻蚀工艺。
  12. 如权利要求6所述的半导体结构的形成方法，其特征在于，所述牺牲侧壁层的材料包括无定形硅、碳氧化硅、氧化硅、氮化硅、碳化硅、氮化硼、氧化铝、氮化铝和氮氧化硅中的一种或几种。
  13. 如权利要求6所述的半导体结构的形成方法，其特征在于，形成所述牺牲侧壁层的步骤中，沿垂直于所述栅极接触孔侧壁或垂直于所述源漏接触孔侧壁的方向，所述牺牲侧壁层的厚度为10Å至40Å。
  14. 如权利要求6所述的半导体结构的形成方法，其特征在于，去除所述牺牲侧壁层的工艺包括远程等离子体刻蚀工艺或湿法刻蚀工艺。
  15. 如权利要求6所述的半导体结构的形成方法，其特征在于，形成所述密封层的工艺包括化学气相沉积工艺和等离子体增强化学气相沉积工艺中的一种或两种。
  16. 如权利要求8所述的半导体结构的形成方法，其特征在于，去除所述顶部介质层和伪侧墙的工艺包括远程等离子体刻蚀工艺或湿法刻蚀工艺。
  17. 如权利要求8所述的半导体结构的形成方法，其特征在于，形成所述覆盖介质层的工艺包括流动式化学气相沉积工艺、原子层沉积工艺、旋涂工艺和化学气相沉积工艺中的一种或几种。
  18. 如权利要求8所述的半导体结构的形成方法，其特征在于，所述伪侧墙的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。
  19. 如权利要求8所述的半导体结构的形成方法，其特征在于，所述覆盖介质层的材料包括低k介质材料或超低k介质材料。
  20. 如权利要求6或8所述的半导体结构的形成方法，其特征在于，所述顶部介质层的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅、氮化硼、氧化铝和氮化铝中的一种或多种。
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