WO2022088788A1 - 半导体结构的形成方法以及半导体结构 - Google Patents

半导体结构的形成方法以及半导体结构 Download PDF

Info

Publication number
WO2022088788A1
WO2022088788A1 PCT/CN2021/108403 CN2021108403W WO2022088788A1 WO 2022088788 A1 WO2022088788 A1 WO 2022088788A1 CN 2021108403 W CN2021108403 W CN 2021108403W WO 2022088788 A1 WO2022088788 A1 WO 2022088788A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
bit line
line structure
dielectric layer
forming
Prior art date
Application number
PCT/CN2021/108403
Other languages
English (en)
French (fr)
Inventor
陈龙阳
武宏发
吴公一
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/455,986 priority Critical patent/US11956944B2/en
Publication of WO2022088788A1 publication Critical patent/WO2022088788A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • This application relates to the field of semiconductors.
  • DRAM dynamic random access memory
  • the dummy capacitor contact structure and the dummy bit line structure are the most common dummy structures.
  • multiple wet cleaning processes are required in the manufacturing process of the capacitor contact structure. , resulting in the destruction of part of the structure of the virtual capacitor contact structure, thereby forming deep voids.
  • the conductors of the capacitor contact pads are more and more densely arranged, and the voids are easily formed when the conductors of the capacitor contact pad are formed.
  • the metal material is filled in, thereby shorting the wires of the resulting capacitive contact pads.
  • the embodiments of the present application can/at least avoid the short-circuiting problem of the wires of the capacitive contact pads as the critical dimension shrinks.
  • a first aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate includes contact regions and dummy regions arranged adjacently, and first bit line structures arranged discretely are formed on the substrate and the first dielectric layer, and the extension direction of the first dielectric layer intersects with the extension direction of the first bit line structure, and the first bit line structure and the first dielectric layer enclose a discrete capacitor contact opening; a sacrificial layer; in the dummy area, the first bit line structure with a partial height, the first dielectric layer with a partial height and the first sacrificial layer with a partial height are removed to form the second bit line structure, the second dielectric layer and the second The first opening at the top of the sacrificial layer, wherein the remaining first bit line structure is used as the second bit line structure, the remaining first dielectric layer is used as the second dielectric layer, and the remaining first sacrificial layer is used as the second sacrificial layer;
  • the embodiments of the present disclosure may/at least have the following advantages: before the process flow of forming the capacitor contact structure, by etching the dummy capacitor contact structure with a partial height and the dummy bit line structure with a partial height, the first opening is formed, and the first opening is formed and the first opening is formed.
  • An open insulating layer prevents part of the dummy capacitor contact structure from being damaged in the process of forming the capacitor contact structure, thereby forming a deep cavity, which leads to the subsequent short circuit problem of the formed capacitor contact pads.
  • a second aspect of the present application provides a semiconductor structure, comprising: a substrate including contact regions and dummy regions arranged adjacently; a bit line structure and a dielectric layer, the extension direction of the dielectric layer and the extension of the bit line structure The directions intersect, and the bit line structure and the dielectric layer enclose discrete capacitor contact openings; wherein, the bit line structure includes a first bit line structure and a second bit line structure, the dielectric layer includes a first dielectric layer and a second dielectric layer, and the second The bit line structure and the second dielectric layer are located in the dummy region, the first bit line structure and the first dielectric layer are located in the contact region, and the height of the second bit line structure is lower than that of the first bit line structure, and the second dielectric layer The height is lower than the height of the first dielectric layer; the second sacrificial layer fills the capacitor contact opening in the dummy area; the insulating layer is located on the top surface of the second bit line structure, the second dielectric
  • the embodiments of the present disclosure may/at least have the following advantages: through the insulating layer on top of the second bit line structure and the second dielectric layer, that is, the insulating layer on the top of the dummy capacitor contact structure surrounded by the dummy bit line structure and the dielectric layer, preventing the During the process of forming the capacitive contact structure, part of the structure of the dummy capacitive contact structure is destroyed, thereby forming deep voids, resulting in the subsequent short circuit of the wires of the formed capacitive contact pads.
  • FIG. 1 is a schematic top view of a semiconductor structure provided by a first embodiment of the present application
  • Fig. 2, Fig. 5, Fig. 7, Fig. 10, Fig. 13, Fig. 16, Fig. 18, Fig. 21 and Fig. 24 are schematic cross-sectional views corresponding to each step along the A1 direction in the method for forming a semiconductor structure according to the first embodiment of the present application;
  • FIG. 8 FIG. 11, FIG. 14, FIG. 19 and FIG. 22 are schematic cross-sectional views corresponding to each step along the A2 direction in the method for forming a semiconductor structure according to the first embodiment of the present application;
  • 4 , 6 , 9 , 12 , 15 , 17 , 20 , 23 and 25 are schematic cross-sectional views corresponding to each step along the A3 direction in the method for forming a semiconductor structure according to the first embodiment of the present application.
  • the wet cleaning process has an etching load effect, and the etching rate of the densely etched area will be correspondingly reduced. , resulting in over-etching of other structures, such as over-etching of the dummy capacitive contact structure, in the process of forming the capacitor contact opening, resulting in deep voids in the dummy capacitive contact structure.
  • some metal materials are filled into the cavities.
  • the wires of the capacitor contact pads are arranged more and more densely, and the conductive part of the metal materials of the adjacent capacitor contact pads may be filled. into the same cavity, thereby shorting the wires of the resulting capacitive contact pads.
  • a first embodiment of the present application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes contact regions and dummy regions arranged adjacently, and discretely arranged first bit line structures and a first dielectric are formed on the substrate layer, and the extension direction of the first dielectric layer intersects with the extension direction of the first bit line structure, the first bit line structure and the first dielectric layer enclose discrete capacitor contact openings; a first sacrificial layer filling the capacitor contact openings is formed; In the dummy area, a part of the first bit line structure, a part of the first dielectric layer and a part of the height of the first sacrificial layer are removed to form a top of the second bit line structure, the second dielectric layer and the second sacrificial layer.
  • the first opening wherein the remaining first bit line structure is used as the second bit line structure, the remaining first dielectric layer is used as the second dielectric layer, and the remaining first sacrificial layer is used as the second sacrificial layer;
  • the insulating layer is in the contact area, and the first sacrificial layer is removed to form a second opening; a capacitor contact structure located in the second opening is formed.
  • FIG. 1 is a schematic top view of the semiconductor structure provided by the first embodiment of the application
  • FIG. 2 , FIG. 5 , FIG. 7 , FIG. 10 , FIG. 13 , FIG. 16 , FIG. 18 , FIG. 21 and FIG. 24 are the first embodiment of the application.
  • Cross-sectional schematic diagrams corresponding to each step along the A1 direction in the method for forming a semiconductor structure FIGS. 3 , 8 , 11 , 14 , 19 and 22 are along the A2 direction in the method for forming a semiconductor structure according to the first embodiment of the application.
  • 4, 6, 9, 12, 15, 17, 20, 23 and 25 are the schematic diagrams along the A3 direction in the method for forming the semiconductor structure according to the first embodiment of the present application. Schematic diagram of the cross-section corresponding to the above steps.
  • a substrate 100 is provided, the substrate 100 includes contact regions 110 and dummy regions 120 that are adjacently arranged.
  • the substrate 100 includes an array area and a peripheral area 130 , wherein the array area is divided into a contact area 110 and a dummy area 120 .
  • the contact area 110 is used to form a capacitive contact structure
  • the capacitive contact structure is used to realize the electrical connection between the storage capacitor and the transistor
  • the dummy area 120 is used to form a dummy capacitive contact structure
  • the dummy capacitive contact structure is used to ensure the manufacture of DRAMs with critical dimensions less than 20 nm. process, the integrity and effectiveness of the circuit structure in the DRAM array area.
  • the A3 direction is the extension direction of the bit line structure
  • the A1 direction and the A2 direction are the extension directions of the dielectric layer.
  • the bit line structure and the dielectric layer extending perpendicular to each other are taken as an example for specific introduction.
  • the extension direction of the bit line structure and the dielectric layer only needs to intersect, so as to enclose the capacitor contact opening.
  • the capacitor contact openings surrounded by the dielectric layer and the bit line structure are shown as the larger squares in FIG. 1 .
  • the capacitor contact openings in the contact area 110 and the capacitor contact openings in the dummy area 120 are filled differently only to reflect the different fillings.
  • the capacitor contact opening in the region does not limit the material and structure of the capacitor contact opening.
  • the small boxes on both sides of the capacitor contact opening in FIG. 1 are the isolation layers on the sidewalls of the bit line structure.
  • the sidewall of the bit line structure adopts the structure of multi-layer isolation layers, so as to reduce the parasitic capacitance between the bit line structure and the capacitor contact formed by filling the capacitor contact opening. It should be noted that this embodiment takes the example of the existence of multiple isolation layers on the sidewall of the bit line structure for specific introduction.
  • the isolation layer on the sidewall of the bit line structure may be a single-layer structure.
  • a substrate 100 is provided.
  • the substrate 100 includes contact regions 110 and dummy regions 120 arranged adjacently.
  • the first bit line structure 102 and the first dielectric layer 103 are separately arranged on the substrate 100 .
  • the first The extension direction of the dielectric layer 103 intersects with the extension direction of the first bit line structure 102.
  • the first bit line structure 102 and the first dielectric layer 103 enclose a discrete capacitor contact opening (not shown), and form a filling capacitor contact opening (not shown) of the first sacrificial layer 104 .
  • the substrate 100 includes a shallow trench isolation structure 140 and a word line structure 150 .
  • the shallow trench isolation structure 140 is used for isolating adjacent active regions (not shown), and the word line structure 150 is a buried structure and is formed inside the substrate 100 to serve as the gate of the transistor for connecting to the first bit line structure 102.
  • the substrate 100 also includes other semiconductor structures other than the shallow trench isolation structure 140 and the word line structure 150. Since the other semiconductor structures do not involve the core technology of the present application, they will not be repeated here; Those skilled in the art can understand that the substrate 100 also includes other semiconductor structures other than the shallow trench isolation structure 140 and the word line structure 150 for normal operation of the semiconductor structure.
  • the material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.
  • the substrate 100 is made of silicon material, and those skilled in the art will know that this embodiment uses silicon material as the substrate 100 is for the convenience of those skilled in the art to understand the subsequent formation method, and does not constitute a limitation. In the actual application process, a suitable substrate material can be selected according to requirements.
  • the first bit line structure 102 includes a bit line contact layer 112 , a conductive contact layer 122 , a metal layer 132 and a top dielectric layer 142 which are stacked in sequence.
  • the material of the bit line contact layer 112 includes silicon germanium or polysilicon, which is used to electrically connect the word line structure 150; the material of the conductive contact layer 122 includes titanium nitride, which is used for the bit line contact layer 112 formed by the semiconductor conductive material and the metal conductive material.
  • the electrical connection between the metal layers 132 is formed to reduce the resistance of the electrical connection path between the first bit line structure 102 and the word line structure 150;
  • the metal layer 132 can be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon , titanium, titanium nitride, tungsten and tungsten complexes, etc., are used for signal transmission of the first bit line structure 102;
  • the material of the top dielectric layer 142 includes silicon nitride, silicon dioxide or silicon oxynitride, in this embodiment Among them, the material of the top dielectric layer 142 is silicon nitride, which is used to protect the metal layer 132 in the first bit line structure 102 from short-circuiting with other conductive structures in the DRAM.
  • the top dielectric layer 142 also covers the sidewalls of the bit line contact layer 112 , the conductive contact layer 122 and the metal layer 132 , and serves as the first isolation layer of the first bit line structure 102 .
  • a second isolation layer 152 is further formed on the sidewall of the first isolation layer, and a third isolation layer 162 is further formed on the sidewall of the second isolation layer 152 .
  • a multi-layer isolation layer structure is formed on the sidewall of the first bit line structure 102 to reduce the parasitic capacitance between the first bit line structure 102 and the capacitor contact structure formed by filling the capacitor contact opening.
  • the material of the second isolation layer 152 includes silicon nitride, silicon dioxide or silicon oxynitride.
  • the material of the second isolation layer 152 is silicon dioxide;
  • the material of the third isolation layer 162 includes nitrogen Silicon oxide, silicon dioxide or silicon oxynitride, in this embodiment, the material of the third isolation layer 162 is silicon nitride.
  • the second isolation layer may also be an air isolation layer, and the air isolation can further reduce the parasitic capacitance between the first bit line structure 102 and the capacitive contact formed by filling the capacitive contact opening.
  • the first dielectric layer 103 is formed of an insulating material. Specifically, the first dielectric layer 103 includes silicon nitride, silicon dioxide or silicon oxynitride. In this embodiment, the material of the first dielectric layer 103 is the same as that of the top dielectric layer 142 . Materials are the same.
  • the first sacrificial layer 104 is silicon oxide formed by spin-on deposition (SOD).
  • SOD spin-on deposition
  • the first sacrificial layer 104 formed by SOD has better adhesion and clearance.
  • the filling capability ensures that the formed first sacrificial layer 104 can completely fill the capacitor contact opening surrounded by the first dielectric layer 103 and the first bit line structure 102 .
  • forming the first sacrificial layer 104 filling the capacitor contact opening includes the following steps: forming a first sacrificial film (not shown) filling the capacitor contact opening and covering the first bit line structure 102 and the first dielectric layer 103, removing the A first sacrificial layer 104 is formed over a first sacrificial film (not shown) above the top surface of the first bit line structure 102 .
  • a part of the first bit line structure 102 , a part of the first dielectric layer 103 and a part of the height of the first sacrificial layer 104 are removed to form the second bit line structure 202 , the first opening 401 at the top of the second dielectric layer 203 and the second sacrificial layer 204, wherein the remaining first bit line structure 102 is used as the second bit line structure 202, and the remaining first dielectric layer 103 is used as the second dielectric layer 203, The remaining first sacrificial layer 104 serves as the second sacrificial layer 204 .
  • forming the first opening 401 includes the following steps:
  • a mask layer 201 on the top surfaces of the first bit line structure 102 , the first dielectric layer 103 and the first sacrificial layer 104 is formed.
  • forming the mask layer 210 includes the following steps: in the contact region 110 , the dummy region 120 and the peripheral region 130 , forming a surface on the top surface of the first bit line structure 102 , the first dielectric layer 103 and the first sacrificial layer 104 A mask (not shown), a photoresist is formed on the top surface of the mask (not shown) of the contact region 110 , and a mask layer 201 is formed by patterning the mask (not shown) based on the photoresist.
  • the first bit line structure 102 , the first dielectric layer 103 and the first sacrificial layer 104 in the dummy region 120 are partially removed by etching to form the second bit line structure 202 ,
  • the second dielectric layer 203, the second sacrificial layer 204 and the first opening 401, and the mask layer 201 is removed.
  • the distance between the metal layer 132 in the second bit line structure 202 and the bottom surface of the first opening 401 formed is 20 nm ⁇ 90 nm. If the distance between the metal layer 132 in the second bit line structure 202 and the bottom surface of the first opening 401 is less than 20 nm, it means that the thickness of the top dielectric layer 142 in the etched first bit line structure 102 is relatively thick, and the remaining top dielectric layer The thickness of the layer 142 is thinner, so that the distance between the metal layer 132 of the second bit line structure 202 and other conductive structures in the DRAM is reduced, resulting in an increase in the parasitic capacitance between the metal layer 132 and other conductive structures in the DRAM; if the second bit line structure The distance between the metal layer 132 in 202 and the bottom surface of the first opening 401 formed is greater than 90 nm, indicating that the thickness of the top dielectric layer 142 in the etched first bit line structure 102 is relatively
  • an insulating layer 301 filling the first opening 401 is formed.
  • forming the insulating layer 301 includes the following steps:
  • an insulating film 311 filling the first opening 401 and covering the contact region 110 is formed.
  • the insulating film 311 is formed by the atomic layer deposition process or the chemical vapor deposition method.
  • the insulating film 311 is formed by the atomic layer deposition process.
  • the insulating film 311 formed by the atomic layer deposition process has good Coverability; in other embodiments, for example, the insulating film 311 may be formed by chemical vapor deposition at 500° C. or 600° C.. It should be noted that the above description of the specific temperature parameters using chemical vapor deposition is only to facilitate the understanding of those skilled in the art, and does not constitute a limitation to this solution. In practical applications, as long as the parameters within the above range are within within the scope of protection of this application.
  • the material of the insulating film 311 includes silicon nitride, silicon dioxide or silicon oxynitride. In this embodiment, the material of the insulating film 311 is silicon nitride.
  • the insulating film 311 is etched until the top surface of the first bit line structure 102 and the first dielectric layer 103 are exposed in the contact region 110 to form the insulating layer 301 .
  • the top of the insulating film 311 is polished by chemical mechanical polishing to form the insulating layer 301 with a relatively flat top surface.
  • chemical mechanical polishing has a higher removal rate, which is beneficial to shorten the process cycle.
  • the first sacrificial layer 104 is removed to form a second opening 402 .
  • the first sacrificial layer 104 in the contact region 110 is removed by wet cleaning.
  • a suitable etching material can be selected so that the wet cleaning has a certain etching selectivity ratio for the first sacrificial layer 104 and the first dielectric layer 103, so that in the process of etching the first sacrificial layer 104 In the process, the etching of the first dielectric layer 103 is prevented, thereby damaging the formed semiconductor structure.
  • the material of the first sacrificial layer is a carbon-containing material
  • the sacrificial layer may be removed by ashing; ashing gas and carbon-containing material The material reacts to generate carbon dioxide gas, thereby converting the first sacrificial layer into gaseous carbon dioxide, thereby removing the first sacrificial layer; and avoiding the formation of a large impact on the first dielectric layer of the sidewall in the process of forming the second opening, thereby collapse occurred.
  • a capacitive contact structure 400 located in the second opening 402 is formed.
  • forming the capacitive contact structure 400 includes the following steps:
  • a bottom conductive layer 302 is formed in the second opening 402 , and the height of the top surface of the bottom conductive layer 302 is lower than that of the top surface of the first bit line structure 102 .
  • forming the bottom conductive layer 302 includes the following steps:
  • a first conductive film 312 filling the second opening 402 and covering the dummy region 120 is formed.
  • the first conductive film 312 is polysilicon formed by spin-on deposition (SOD), and the first conductive film 312 formed by SOD has better adhesion and gap filling It is ensured that the formed first conductive film 312 can completely fill the second opening 402 .
  • SOD spin-on deposition
  • the first conductive film 312 above the top surface of the first bit line structure 102 is removed to form a second conductive film (not shown) for filling the second opening 402 .
  • the top of the first conductive film 312 is polished by chemical mechanical polishing until the top surface of the first bit line structure 102 is exposed, and a second conductive film (not shown) filling the second opening 402 is formed.
  • mechanical grinding has a higher removal rate, which is beneficial to shorten the process cycle.
  • the second conductive film (not shown) with a partial thickness is removed, and the remaining second conductive film (not shown) forms a bottom conductive layer 302 .
  • a top conductive layer 303 filling the second opening is formed.
  • the top conductive layer 303 is a conductive material formed by spin-on deposition (SOD), and the top conductive layer 303 formed by SOD has better adhesion and gap filling capability , to ensure that the formed top conductive layer 303 can completely fill the second opening 402 .
  • SOD spin-on deposition
  • the top conductive layer 303 can be made of one conductive material or composed of multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and a compound of tungsten, etc.
  • the material of the top conductive layer 302 is Tungsten and tungsten compounds.
  • a contact layer may also be formed on the top surface of the bottom conductive layer, and the material of the contact layer includes titanium nitride, and the bottom conductive layer used for the formation of the semiconductor conductive material is The metallic conductive material forms an electrical connection between the top conductive layers to reduce the resistance of the capacitive contact structure and the electrical connection paths of the transistors in the substrate.
  • a first opening is formed by etching a dummy capacitor contact structure with a partial height and a dummy bit line structure with a partial height before the process flow of forming the capacitor contact structure, and an insulation filling the first opening is formed. layer to prevent part of the structure of the dummy capacitor contact structure from being damaged in the process of forming the capacitor contact structure, thereby forming deep voids, resulting in the subsequent short circuit of the wires of the formed capacitor contact pads.
  • the second embodiment of the present application relates to a semiconductor structure.
  • the semiconductor structure includes: a substrate 100, including contact regions 110 and dummy regions 120 arranged adjacently; a bit line structure and a dielectric layer, the extension direction of the dielectric layer intersects with the extension direction of the bit line structure, and the bit line structure and the dielectric layer are enclosed Discrete capacitor contact openings; wherein, the bit line structure includes a first bit line structure 102 and a second bit line structure 202, the dielectric layer includes a first dielectric layer 103 and a second dielectric layer 203, and the second bit line structure 202 and the second The dielectric layer 203 is located in the dummy region 120, the first bit line structure 102 and the first dielectric layer 103 are located in the contact region 110, and the height of the second bit line structure 202 is lower than the height of the first bit line structure 102, the second dielectric layer The height of the layer 203 is lower than the height of the first dielectric layer 103 ; the second sacrificial layer 204 fills the capacitor contact opening in the dummy region 120 ; the
  • the substrate 100 includes a shallow trench isolation structure 140 and a word line structure 150 .
  • the shallow trench isolation structure 140 is used for isolating adjacent active regions (not shown), and the word line structure 150 is a buried structure and is formed inside the substrate 100 to serve as the gate of the transistor for connecting to the first bit line structure 102.
  • the substrate 100 also includes other semiconductor structures other than the shallow trench isolation structure 140 and the word line structure 150. Since the other semiconductor structures do not involve the core technology of the present application, they will not be repeated here; Those skilled in the art can understand that the substrate 100 also includes other semiconductor structures other than the shallow trench isolation structure 140 and the word line structure 150 for normal operation of the semiconductor structure.
  • the first bit line structure 102 includes a bit line contact layer 112 , a conductive contact layer 122 , a metal layer 132 and a top dielectric layer 142 which are stacked in sequence.
  • the top dielectric layer 142 also covers the sidewalls of the bit line contact layer 112 , the conductive contact layer 122 and the metal layer 132 , and serves as the first isolation layer of the first bit line structure 102 .
  • a second isolation layer 152 is further formed on the sidewall of the first isolation layer, and a third isolation layer 162 is further formed on the sidewall of the second isolation layer 152 .
  • a multi-layer isolation layer structure is formed on the sidewall of the first bit line structure 102 to reduce the parasitic capacitance between the first bit line structure 102 and the capacitor contact structure formed by filling the capacitor contact opening.
  • the height difference between the height of the bottom surface of the insulating layer 401 and the height of the metal layer 132 in the second bit line structure 202 is 20 nm ⁇ 90 nm.
  • the capacitive contact structure 400 includes: a bottom conductive layer 302 located in the capacitive contact opening in the contact region 110, the height of the top surface of the bottom conductive layer 302 is lower than the height of the top surface of the first bit line structure 102;
  • the conductive layer 303 located on the top surface of the bottom conductive layer 302 , is used to fill the capacitor contact openings in the contact region 110 .
  • a contact layer may also be formed on the top surface of the bottom conductive layer, and the material of the contact layer includes titanium nitride, and the bottom conductive layer used for the formation of the semiconductor conductive material is The metallic conductive material forms an electrical connection between the top conductive layers to reduce the resistance of the capacitive contact structure and the electrical connection paths of the transistors in the substrate.
  • the insulating layer on the top of the second bit line structure and the second dielectric layer that is, the insulating layer on the top of the virtual capacitive contact structure surrounded by the dummy bit line structure and the dielectric layer, prevents the capacitive contact structure from being formed.
  • part of the structure of the virtual capacitor contact structure is destroyed, thereby forming a deep cavity, which leads to the subsequent short circuit problem of the wires of the formed capacitor contact pad.
  • this embodiment can be implemented in cooperation with the first embodiment.
  • the relevant technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

Abstract

本申请实施例提供一种半导体结构的形成方法以及半导体结构，其中，半导体结构的形成方法，包括：提供基底，基底包括相邻排列的接触区和虚拟区，基底上形成有分立排布的第一位线结构和第一介质层，第一位线结构与第一介质层围成分立的电容接触开口；形成填充电容接触开口的第一牺牲层；在虚拟区中，去除部分高度的第一位线结构、部分高度的第一介质层和部分高度的第一牺牲层，形成位于第二位线结构、第二介质层和第二牺牲层顶部的第一开口；形成填充第一开口的绝缘层在接触区中，去除第一牺牲层，形成第二开口；形成位于第二开口中的电容接触结构，本申请实施例避免了随着关键尺寸的微缩，电容接触垫的导线短路问题。

Description

半导体结构的形成方法以及半导体结构
交叉引用
本申请基于申请号为202011173598.6、申请日为2020年10月28日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)的发展追求高速度、高集成密度和低功耗的性能特点。
随着半导体结构尺寸的微缩，尤其是关键尺寸小于20nm的DRAM制造过程中，DRAM阵列区和外围区的刻蚀负载效应越来越大，为了保证DRAM阵列区电路结构的完整性和有效性，通常需要在阵列区中设计虚拟结构。
在DRAM制造过程中，虚拟电容接触结构和虚拟位线结构是最常见的虚拟结构，然而申请人发现：由于制程的需求，在电容接触结构的制程工艺流程中需要用到多次湿法清洗工艺，导致虚拟电容接触结构的部分结构被破坏，从而形成较深的空洞，随着关键尺寸的微缩，电容接触垫的导线排布越来越密集，空洞在形成电容接触垫的导线时，容易被填入金属材料，从而导致形成的电容接触垫的导线短路。
发明内容
本申请实施例可以/至少避免了随着关键尺寸的微缩，电容接触垫的导线短路问题。
根据一些实施例，本申请第一方面提供了一种半导体结构的形成方法，包括：提供基底，基底包括相邻排列的接触区和虚拟区，基底上形成有分立排布的第一位线结构和第一介质层，且第一介质层的延伸方向与第一位线结构的延伸方向相交，第一位线结构与第一介质层围成分立的电容接触开口；形成填充电容接触开口的第一牺牲层；在虚拟区中，去除部分高度的第一位线结构、部分高度的第一介质层和部分高度的第一牺牲层，形成位于第二位线结构、第二介质层和第二牺牲层顶部的第一开口，其中，剩余的第一位线结构作为第二位线结构，剩余的第一介质层作为第二介质层，剩余的第一牺牲层作为第二牺牲层；形成填充第一开口的绝缘层在接触区中，去除第一牺牲层，形成第二开口；形成位于第二开口中的电容接触结构。
本公开实施例可以/至少具有以下优点，通过在形成电容接触结构的制程工艺流程之前，刻蚀部分高度的虚拟电容接触结构和部分高度的虚拟位线结构，形成第一开口，并形成填充第一开口的绝缘层，防止在形成电容接触结构的过程中，虚拟电容接触结构的部分结构被破坏，从而形成较深的空洞，导致的后续出现形成的电容接触垫的导线短路问题。
根据一些实施例，本申请第二方面提供了一种半导体结构，包括：基底，包括相邻排列的接触区和虚拟区；位线结构和介质层，介质层的延伸方向与位线结构的延伸方向相交，位线结构与介质层围成分立 的电容接触开口；其中，位线结构包括第一位线结构和第二位线结构，介质层包括第一介质层和第二介质层，第二位线结构和第二介质层位于虚拟区中，第一位线结构和第一介质层位于接触区中，且第二位线结构的高度低于第一位线结构的高度，第二介质层的高度低于第一介质层的高度；第二牺牲层，填充虚拟区中的电容接触开口；绝缘层，位于虚拟区中第二位线结构、第二介质层和第二牺牲层顶部表面，绝缘层的顶部表面与第一位线结构顶部表面齐平；电容接触结构，填充接触区中的电容接触开口。
本公开实施例可以/至少具有以下优点，通过位于第二位线结构和第二介质层顶部的绝缘层，即位于虚拟位线结构和介质层围成的虚拟电容接触结构顶部的绝缘层，防止在形成电容接触结构的过程中，虚拟电容接触结构的部分结构被破坏，从而形成较深的空洞，导致的后续出现形成的电容接触垫的导线短路问题。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例提供的半导体结构的俯视示意图；
图2、图5、图7、图10、图13、图16、图18、图21和图24为本申请第一实施例半导体结构的形成方法中沿A1方向上各步骤对 应的剖面示意图；
图3、图8、图11、图14、图19和图22为本申请第一实施例半导体结构的形成方法中沿A2方向上各步骤对应的剖面示意图；
图4、图6、图9、图12、图15、图17、图20、图23和图25为本申请第一实施例半导体结构的形成方法中沿A3方向上各步骤对应的剖面示意图。
具体实施方式
目前，由于制程的需求，在电容接触结构的制程工艺流程中需要用到多次湿法清洗工艺，湿法清洗工艺存在刻蚀负载效应，对刻蚀密集的区域的刻蚀速率会相应减小，导致在形成电容接触开口的过程中，存在对其他结构的过刻蚀，例如对虚拟电容接触结构的过刻蚀，导致虚拟电容接触结构存在较深的空洞。后续在形成电容接触垫的导线时，部分金属材料填入空洞中，随着关键尺寸的微缩，电容接触垫的导线排布越来越密集，相邻电容接触垫的导电的部分金属材料可能填入同一空洞中，从而导致形成的电容接触垫的导线短路。
本申请第一实施例提供了一种半导体结构的形成方法，包括：提供基底，基底包括相邻排列的接触区和虚拟区，基底上形成有分立排布的第一位线结构和第一介质层，且第一介质层的延伸方向与第一位线结构的延伸方向相交，第一位线结构与第一介质层围成分立的电容接触开口；形成填充电容接触开口的第一牺牲层；在虚拟区中，去除部分高度的第一位线结构、部分高度的第一介质层和部分高度的第一 牺牲层，形成位于第二位线结构、第二介质层和第二牺牲层顶部的第一开口，其中，剩余的第一位线结构作为第二位线结构，剩余的第一介质层作为第二介质层，剩余的第一牺牲层作为第二牺牲层；形成填充第一开口的绝缘层在接触区中，去除第一牺牲层，形成第二开口；形成位于第二开口中的电容接触结构。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本申请第一实施例提供的半导体结构的俯视示意图；图2、图5、图7、图10、图13、图16、图18、图21和图24为本申请第一实施例半导体结构的形成方法中沿A1方向上各步骤对应的剖面示意图；图3、图8、图11、图14、图19和图22为本申请第一实施例半导体结构的形成方法中沿A2方向上各步骤对应的剖面示意图；图4、图6、图9、图12、图15、图17、图20、图23和图25为本申请第一实施例半导体结构的形成方法中沿A3方向上各步骤对应的剖面示意图。
参考图1，提供基底100，基底100包括相邻排列的接触区110 和虚拟区120。
具体地，基底100包括阵列区和外围区130，其中阵列区分为接触区110和虚拟区120。接触区110用于形成电容接触结构，电容接触结构用于实现存储电容与晶体管的电连接，虚拟区120用于形成虚拟电容接触结构，虚拟电容接触结构用于保证在关键尺寸小于20nm的DRAM制造过程中，DRAM阵列区电路结构的完整性和有效性。
图1中A3方向为位线结构的延伸方向，A1方向和A2方向为介质层的延伸方向，本实施例以相互垂直的延伸的位线结构和介质层为例进行具体介绍，在其他实施例中，位线结构和介质层的延伸方向相交即可，以围成电容接触开口。介质层与位线结构围成的电容接触开口如图1中较大的方块所示，接触区110中的电容接触开口和虚拟区120中的电容接触开口采用不同的填充仅是为了体现位于不同区域的电容接触开口，并不对电容接触开口的材料和结构进行限定。
图1中位于电容接触开口两侧的小方框即位线结构侧壁的隔离层。位线结构侧壁采用多层隔离层的结构，以减小位线结构与填充电容接触开口形成的电容接触之间的寄生电容。需要说明的是，本实施例以位线结构侧壁存在多层隔离层为例进行具体介绍，位线结构侧壁存储在剁成隔离层只是作为一个较优的实施方式，并不构成对本实施例的限定，在其他实施例方式中，位线结构侧壁的隔离层可以为单层结构。
下面对照分别沿A1、A2和A3方向的剖面结构示意图对本实施例的半导体结构的形成方法进行具体介绍。
参考图2～图4，提供基底100，基底100包括相邻排列的接触区110和虚拟区120，基底100上形成有分立排布的第一位线结构102和第一介质层103，第一介质层103的延伸方向与第一位线结构102的延伸方向相交，第一位线结构102与第一介质层103围成分立的电容接触开口(未图示)，并形成填充电容接触开口(未图示)的第一牺牲层104。
具体地，基底100中包括浅沟槽隔离结构140和字线结构150。浅沟槽隔离结构140用于隔离相邻有源区(未图示)，字线结构150为埋入式结构，形成在基底100内部，作为晶体管的栅极，用于连接第一位线结构102，需要说明的是，基底100中还包括浅沟槽隔离结构140和字线结构150外的其他半导体结构，由于其他半导体结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除浅沟槽隔离结构140和字线结构150外的其他半导体结构，用于半导体结构的正常运行。
基底100的材料可以包括蓝宝石、硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料，本领域技术人员清楚，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
第一位线结构102包括依次堆叠设置的位线接触层112、导电接触层122、金属层132以及顶层介质层142。
位线接触层112的材料包括锗化硅或多晶硅，用于电连接字线结 构150；导电接触层122的材料包括氮化钛，用于半导体导电材料形成的位线接触层112与金属导电材料形成金属层132之间的电连接，以降低第一位线结构102与字线结构150电连接路径的电阻；金属层132可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，用于第一位线结构102的信号传输；顶层介质层142的材料包括氮化硅、二氧化硅或氮氧化硅，在本实施例中，顶层介质层142的材料为氮化硅，用于保护第一位线结构102中的金属层132与DRAM中的其它导电结构发生短路现象。
在本实施例中，顶层介质层142还覆盖位线接触层112、导电接触层122和金属层132的侧壁，作为第一位线结构102的第一隔离层。第一隔离层侧壁还形成有第二隔离层152，第二隔离层152侧壁还形成有第三隔离层162。本实施例通过在第一位线结构102侧壁形成多层隔离层的结构，以减小第一位线结构102与填充电容接触开口形成的电容接触结构之间的寄生电容。
具体地，第二隔离层152的材料包括氮化硅、二氧化硅或氮氧化硅，在本实施例中，第二隔离层152的材料为二氧化硅；第三隔离层162的材料包括氮化硅、二氧化硅或氮氧化硅，在本实施例中，第三隔离层162的材料为氮化硅。在其他实施例中第二隔离层还可以为空气隔离层，通过空气隔离可以进一步减小第一位线结构102与填充电容接触开口形成的电容接触之间的寄生电容。
第一介质层103采用绝缘材料形成，具体地，第一介质层103包括氮化硅、二氧化硅或氮氧化硅，在本实施例中，第一介质层103的 材料与顶层介质层142的材料相同。
在本实施例中，第一牺牲层104为采用旋转涂覆(Spin-On Deposition，SOD)的方式形成的氧化硅，采用SOD的方式形成第一牺牲层104具有较好的粘附性和间隙填充能力，保证形成的第一牺牲层104可以完全填充第一介质层103与第一位线结构102围成的电容接触开口。
具体地，形成填充电容接触开口的第一牺牲层104，包括以下步骤：形成填充电容接触开口且覆盖第一位线结构102和第一介质层103的第一牺牲膜(未图示)，去除高于第一位线结构102顶部表面的第一牺牲膜(未图示)，形成第一牺牲层104。
参考图5～图9，在虚拟区120中，去除部分高度的第一位线结构102、部分高度的第一介质层103和部分高度的第一牺牲层104，形成位于第二位线结构202、第二介质层203和第二牺牲层204顶部的第一开口401，其中，剩余第一位线结构102作为第二位线结构202，剩余的第一介质层103作为第二介质层203，剩余的第一牺牲层104作为第二牺牲层204。
具体地，形成第一开口401，包括以下步骤：
参考图5和图6，在接触区110中，形成位于第一位线结构102、第一介质层103和第一牺牲层104顶部表面的掩膜层201。
具体地，形成掩膜层210，包括以下步骤：在接触区110、虚拟区120和外围区130中，形成位于第一位线结构102、第一介质层103和第一牺牲层104顶部表面的掩膜(未图示)，在所述接触区110的 掩膜(未图示)顶部表面形成光刻胶，基于光刻胶图形化掩膜(未图示)，形成掩膜层201。
参考图7～图9，基于掩膜层201，刻蚀去除虚拟区120中部分高度的第一位线结构102、第一介质层103和第一牺牲层104，形成第二位线结构202、第二介质层203、第二牺牲层204和第一开口401，并去除掩膜层201。
在本实施例中，在垂直于基底100的方向上，第二位线结构202中的金属层132和形成的第一开口401底部表面的距离为20nm～90nm。若第二位线结构202中的金属层132和形成的第一开口401底部表面的距离小于20nm，说明被刻蚀的第一位线结构102中顶层介质层142的厚度较厚，剩余顶层介质层142的厚度较薄，使得第二位线结构202的金属层132与DRAM中其他导电结构的距离减小，导致金属层132与DRAM中其他导电结构寄生电容增大；若第二位线结构202中的金属层132和形成的第一开口401底部表面的距离大于90nm，说明被刻蚀的第一位线结构102中顶层介质层142的厚度较薄，可能无法防止在形成电容接触结构的过程中，虚拟电容接触结构的部分结构被破坏，从而形成较深的空洞，导致的后续出现形成的电容接触垫的导线短路问题。
参考图10～图15，形成填充第一开口401的绝缘层301。
具体地，形成绝缘层301，包括以下步骤：
参考图10～图12，形成填充第一开口401且覆盖接触区110的绝缘膜311。
具体地，采用原子层沉积工艺或化学气相沉积的方法形成绝缘膜311，在本实施例中，采用原子层沉积工艺的方式形成绝缘膜311，采用原子层沉积工艺形成的绝缘膜311具有良好的覆盖性；在其他实施例中，例如，可以采用500℃或600℃下进行化学气相沉积的方法形成绝缘膜311。需要说明是的，上述采用化学气相沉积的具体温度参数的举例说明，仅便于本领域技术人员的理解，并不构成对本方案的限定，在实际应用中只要符合上述范围中的参数都应落入本申请的保护范围中。
绝缘膜311的材料包括氮化硅、二氧化硅或氮氧化硅，在本实施例中，绝缘膜311的材料为氮化硅。
参考图13～图15，刻蚀绝缘膜311，直至接触区110中暴露出第一位线结构102和第一介质层103的顶部表面，形成绝缘层301。
具体地，采用化学机械研磨的方式对绝缘膜311的顶部进行打磨，形成顶部表面较为平坦的绝缘层301，化学机械研磨相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
参考图16和图17，在所述接触区110中，去除第一牺牲层104，形成第二开口402。
具体地，在本实施例中，采用湿法清洗的方式去除接触区110中的第一牺牲层104。采用湿法清洗的方法可以通过选取合适的刻蚀材料，使得湿法清洗对第一牺牲层104和第一介质层103具有一定的刻蚀选择比，从而在刻蚀第一牺牲层104的过程中，防止对第一介质层103的刻蚀，从而损坏形成的半导体结构。
另外，在其他实施例中，第一牺牲层的材料为含碳材料，后续在去除第一牺牲层形成第二开口的过程中，可采用灰化的方式去除牺牲层；灰化气体与含碳材料反应生成二氧化碳气体，从而将第一牺牲层转换成气体二氧化碳，从而除去第一牺牲层；并且避免了在形成第二开口的过程中对侧壁的第一介质层形成较大的冲击，从而发生的坍塌现象。
参考图18～图25，形成位于第二开口402中的电容接触结构400。
具体地，形成电容接触结构400，包括以下步骤：
参考图18～图23，形成位于第二开口402中的底导电层302，底导电层302顶部表面高度低于第一位线结构102顶部表面的高度。
具体地，形成底导电层302，包括以下步骤：
参考图18～图20，形成填充第二开口402且覆盖虚拟区120的第一导电膜312。
在本实施例中，第一导电膜312为采用旋转涂覆(Spin-On Deposition，SOD)的方式形成的多晶硅，采用SOD的方式形成第一导电膜312具有较好的粘附性和间隙填充能力，保证形成的第一导电膜312可以完全填充第二开口402。
去除高于第一位线结构102顶部表面的第一导电膜312，形成用于填充第二开口402的第二导电膜(未图示)。
具体地，采用化学机械研磨的方式对第一导电膜312的顶部进行打磨，直至暴露出第一位线结构102顶部表面，形成填充第二开口402的第二导电膜(未图示)，化学机械研磨相对于刻蚀工艺具有较 高的去除速率，有利于缩短工艺周期。
参考图21～图23，去除部分厚度的第二的导电膜(未图示)，剩余第二导电膜(未图示)形成底导电层302。
参考图24和图25，形成填充第二开口的顶导电层303。形成的底导电层302和顶导电层303共同构成电容接触结构400。
在本实施例中，顶导电层303为采用旋转涂覆(Spin-On Deposition，SOD)的方式形成的导电材料，采用SOD的方式形成顶导电层303具有较好的粘附性和间隙填充能力，保证形成的顶导电层303可以完全填充第二开口402。
顶导电层303可以为一种导电材料或者由多种导电材料构成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等，在本实施例中，顶导电层302的材料为钨以及钨的复合物。
需要说明的是，在其他实施例中，在形成顶导电层之前，还可以在底导电层顶部表面形成接触层，接触层的材料包括氮化钛，用于半导体导电材料形成的底导电层与金属导电材料形成顶导电层之间的电连接，以降低电容接触结构与基底中的晶体管电连接路径的电阻。
相对于相关技术而言，通过在形成电容接触结构的制程工艺流程之前，刻蚀部分高度的虚拟电容接触结构和部分高度的虚拟位线结构，形成第一开口，并形成填充第一开口的绝缘层，防止在形成电容接触结构的过程中，虚拟电容接触结构的部分结构被破坏，从而形成较深的空洞，导致的后续出现形成的电容接触垫的导线短路问题。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个 步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请第二实施例涉及一种半导体结构。
参考图1、图24和图25，以下将结合附图对本实施例提供的半导体结构进行详细说明，与第一实施例相同或相应的部分，以下将不做详细赘述。
半导体结构，包括：基底100，包括相邻排列的接触区110和虚拟区120；位线结构和介质层，介质层的延伸方向与位线结构的延伸方向相交，位线结构与介质层围成分立的电容接触开口；其中，位线结构包括第一位线结构102和第二位线结构202，介质层包括第一介质层103和第二介质层203，第二位线结构202和第二介质层203位于虚拟区120中，第一位线结构102和第一介质层103位于接触区110中，且第二位线结构202的高度低于第一位线结构102的高度，第二介质层203的高度低于第一介质层103的高度；第二牺牲层204，填充虚拟区120中的电容接触开口；绝缘层401，位于虚拟区120中第二位线结构202、第二介质层203和第二牺牲层204顶部表面，绝缘层401的顶部表面与第一位线结构102顶部表面齐平；电容接触结构400，填充接触区110中的电容接触开口。
具体地，基底100中包括浅沟槽隔离结构140和字线结构150。浅沟槽隔离结构140用于隔离相邻有源区(未图示)，字线结构150 为埋入式结构，形成在基底100内部，作为晶体管的栅极，用于连接第一位线结构102，需要说明的是，基底100中还包括浅沟槽隔离结构140和字线结构150外的其他半导体结构，由于其他半导体结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除浅沟槽隔离结构140和字线结构150外的其他半导体结构，用于半导体结构的正常运行。
第一位线结构102包括依次堆叠设置的位线接触层112、导电接触层122、金属层132以及顶层介质层142。在本实施例中，顶层介质层142还覆盖位线接触层112、导电接触层122和金属层132的侧壁，作为第一位线结构102的第一隔离层。第一隔离层侧壁还形成有第二隔离层152，第二隔离层152侧壁还形成有第三隔离层162。本实施例通过在第一位线结构102侧壁形成多层隔离层的结构，以减小第一位线结构102与填充电容接触开口形成的电容接触结构之间的寄生电容。
在本实施例中，绝缘层401底部表面的高度与第二位线结构202中的金属层132的高度差为20nm～90nm。通过保证第二位线结构202中的金属层132与第一开口401底部表面之间的距离，减小位线结构的金属层与其他导电结构之间的寄生电容。
在本实施例中，电容接触结构400包括：底导电层302，位于接触区110中的电容接触开口中，底导电层302顶部表面的高度低于第一位线结构102顶部表面的高度；顶导电层303，位于底导电层302顶部表面，用于填充接触区110中的电容接触开口。
需要说明的是，在其他实施例中，在形成顶导电层之前，还可以在底导电层顶部表面形成接触层，接触层的材料包括氮化钛，用于半导体导电材料形成的底导电层与金属导电材料形成顶导电层之间的电连接，以降低电容接触结构与基底中的晶体管电连接路径的电阻。
与相关技术相比，通过位于第二位线结构和第二介质层顶部的绝缘层，即位于虚拟位线结构和介质层围成的虚拟电容接触结构顶部的绝缘层，防止在形成电容接触结构的过程中，虚拟电容接触结构的部分结构被破坏，从而形成较深的空洞，导致的后续出现形成的电容接触垫的导线短路问题。
由于第一实施例与本实施例相互对应，因此本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (12)

  1. 一种半导体结构的形成方法，包括：
    提供基底，所述基底包括相邻排列的接触区和虚拟区，所述基底上形成有分立排布的第一位线结构和第一介质层，且所述第一介质层的延伸方向与所述第一位线结构的延伸方向相交，所述第一位线结构与所述第一介质层围成分立的电容接触开口；
    形成填充所述电容接触开口的第一牺牲层；
    在所述虚拟区中，去除部分高度的所述第一位线结构、部分高度的所述第一介质层和部分高度的所述第一牺牲层，形成位于第二位线结构、第二介质层和第二牺牲层顶部的第一开口，其中，剩余的第一位线结构作为所述第二位线结构，剩余的第一介质层作为所述第二介质层，剩余的第一牺牲层作为所述第二牺牲层；
    形成填充所述第一开口的绝缘层；
    在所述接触区中，去除所述第一牺牲层，形成第二开口；
    形成位于所述第二开口中的电容接触结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，形成填充所述电容接触开口的第一牺牲层，包括以下步骤：
    形成填充所述电容接触开口且覆盖所述第一位线结构和所述第一介质层的第一牺牲膜；
    去除高于所述第一位线结构顶部表面的所述第一牺牲膜，形成所述第一牺牲层。
  3. 根据权利要求1所述的半导体结构的形成方法，其中，在所述 虚拟区中，去除部分高度的所述第一位线结构、所述第一介质层和所述牺牲层，形成位于第二位线结构、第二介质层和第二牺牲层顶部的第一开口，包括以下步骤：
    在所述接触区中，形成位于所述第一位线结构、所述第一介质层和所述第一牺牲层顶部表面的掩膜层；
    基于所述掩膜层，刻蚀去除所述虚拟区中部分高度的所述第一位线结构、所述第一介质层和所述第一牺牲层，形成所述第二位线结构、所述第二介质层、所述第二牺牲层和所述第一开口。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，在所述接触区中，形成位于所述第一位线结构、所述第一介质层和所述第一牺牲层顶部表面的掩膜层，包括以下步骤：
    形成位于所述第一位线结构、所述第一介质层和所述第一牺牲层顶部表面的掩膜；
    在所述接触区的掩膜顶部表面形成光刻胶；
    基于所述光刻胶图形化所述掩膜，形成所述掩膜层。
  5. 根据权利要求1所述的半导体结构的形成方法，其中，在垂直于所述基底的方向上，位于所述第二位线结构中的金属层和形成的所述第一开口底部表面的距离为20nm～90nm。
  6. 根据权利要求1所述的半导体结构的形成方法，其中，形成填充所述第一开口的绝缘层，包括以下步骤：
    形成填充所述第一开口且覆盖所述接触区的绝缘膜；
    刻蚀所述绝缘膜，直至所述接触区中暴露出所述第一位线结构和 所述第一介质层的顶部表面，形成所述绝缘层。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，采用湿法清洗的方式去除所述接触区中的所述第一牺牲层。
  8. 根据权利要求1所述的半导体结构的形成方法，其中，形成位于所述第二开口中的电容接触结构，包括以下步骤：
    形成位于第二开口中的底导电层，所述底导电层顶部表面高度低于所述第一位线结构顶部表面的高度；
    形成填充所述第二开口的顶导电层。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，形成位于第二开口中的底导电层，包括以下步骤：
    形成填充所述第二开口且覆盖所述虚拟区的第一导电膜；
    去除高于所述第一位线结构顶部表面的所述第一导电膜，形成用于填充所述第二开口的第二导电膜；
    去除部分厚度的所述第二导电膜，剩余所述第二导电膜形成所述底导电层。
  10. 一种半导体结构，包括：
    基底，包括相邻排列的接触区和虚拟区；
    位线结构和介质层，所述介质层的延伸方向与所述位线结构的延伸方向相交，所述位线结构与所述介质层围成分立的电容接触开口；
    其中，位线结构包括第一位线结构和第二位线结构，介质层包括第一介质层和第二介质层，所述第二位线结构和所述第二介质层位于所述虚拟区中，所述第一位线结构和所述第一介质层位于所述接触区 中，且所述第二位线结构的高度低于所述第一位线结构的高度，所述第二介质层的高度低于所述第一介质层的高度；
    第二牺牲层，填充虚拟区中的所述电容接触开口；
    绝缘层，位于所述虚拟区中所述第二位线结构、所述第二介质层和所述第二牺牲层顶部表面，所述绝缘层的顶部表面与所述第一位线结构顶部表面齐平；
    电容接触结构，填充所述接触区中的所述电容接触开口。
  11. 根据权利要求10所述的半导体结构，其中，所述电容接触结构包括：
    底导电层，位于所述接触区中的所述电容接触开口中，所述底导电层顶部表面的高度低于所述第一位线结构顶部表面的高度；
    顶导电层，位于所述底导电层顶部表面，用于填充所述接触区中的所述电容接触开口。
  12. 根据权利要求10所述的半导体结构，其中，所述绝缘层底部表面的高度与所述第二位线结构中的金属层的高度差为20nm～90nm。
PCT/CN2021/108403 2020-10-28 2021-07-26 半导体结构的形成方法以及半导体结构 WO2022088788A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/455,986 US11956944B2 (en) 2020-10-28 2021-11-22 DRAM semiconductor structure formation method and DRAM semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011173598.6A CN114420641A (zh) 2020-10-28 2020-10-28 半导体结构的形成方法以及半导体结构
CN202011173598.6 2020-10-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/455,986 Continuation US11956944B2 (en) 2020-10-28 2021-11-22 DRAM semiconductor structure formation method and DRAM semiconductor structure

Publications (1)

Publication Number Publication Date
WO2022088788A1 true WO2022088788A1 (zh) 2022-05-05

Family

ID=81260573

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/108403 WO2022088788A1 (zh) 2020-10-28 2021-07-26 半导体结构的形成方法以及半导体结构

Country Status (2)

Country Link
CN (1) CN114420641A (zh)
WO (1) WO2022088788A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115132777B (zh) * 2022-08-31 2022-11-25 睿力集成电路有限公司 半导体结构及其形成方法、存储器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1178393A (zh) * 1996-06-03 1998-04-08 世界先进积体电路股份有限公司 在存储单元的电容器阵列上制作位线的方法
US20190198504A1 (en) * 2017-12-25 2019-06-27 Nanya Technology Corporation Semiconductor memory structure and method for preparing the same
CN111834301A (zh) * 2019-04-22 2020-10-27 华邦电子股份有限公司 存储元件的制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1178393A (zh) * 1996-06-03 1998-04-08 世界先进积体电路股份有限公司 在存储单元的电容器阵列上制作位线的方法
US20190198504A1 (en) * 2017-12-25 2019-06-27 Nanya Technology Corporation Semiconductor memory structure and method for preparing the same
CN111834301A (zh) * 2019-04-22 2020-10-27 华邦电子股份有限公司 存储元件的制造方法

Also Published As

Publication number Publication date
CN114420641A (zh) 2022-04-29

Similar Documents

Publication Publication Date Title
WO2022088758A1 (zh) 半导体结构的形成方法以及半导体结构
US9613967B1 (en) Memory device and method of fabricating the same
KR102482369B1 (ko) 반도체 소자 및 그 제조 방법
CN110061001B (zh) 半导体元件及其制作方法
KR20210032595A (ko) 반도체 소자 및 그의 제조 방법
JP2010153509A (ja) 半導体装置およびその製造方法
WO2021233111A1 (zh) 存储器的形成方法及存储器
WO2022088788A1 (zh) 半导体结构的形成方法以及半导体结构
US6991978B2 (en) World line structure with single-sided partially recessed gate structure
US20230238449A1 (en) Semiconductor structure and forming method therefor
TWI769797B (zh) 動態隨機存取記憶體及其製造法方法
TWI741602B (zh) 半導體裝置及其製造方法
US11956944B2 (en) DRAM semiconductor structure formation method and DRAM semiconductor structure
CN113838852B (zh) 半导体存储装置及其形成方法
US20220130836A1 (en) Semiconductor structure formation method and semiconductor structure
WO2022062717A1 (zh) 半导体结构形成方法以及半导体结构
WO2023184571A1 (zh) 半导体结构及其制备方法
TWI841063B (zh) 記憶體裝置和其形成方法
KR100487915B1 (ko) 반도체소자의캐패시터형성방법
WO2022134623A1 (zh) 半导体结构的形成方法及半导体结构
TWI779639B (zh) 半導體結構和其形成方法
US20230247825A1 (en) Semiconductor device
WO2022037273A1 (zh) 半导体结构及其制作方法
US20240049447A1 (en) Semiconductor memory device
WO2022062536A1 (zh) 存储器的制作方法及存储器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21884523

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21884523

Country of ref document: EP

Kind code of ref document: A1