WO2022062536A1 - 存储器的制作方法及存储器 - Google Patents

存储器的制作方法及存储器 Download PDF

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Publication number
WO2022062536A1
WO2022062536A1 PCT/CN2021/103375 CN2021103375W WO2022062536A1 WO 2022062536 A1 WO2022062536 A1 WO 2022062536A1 CN 2021103375 W CN2021103375 W CN 2021103375W WO 2022062536 A1 WO2022062536 A1 WO 2022062536A1
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Prior art keywords
layer
hole
substrate
filling
etching
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PCT/CN2021/103375
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English (en)
French (fr)
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卢经文
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长鑫存储技术有限公司
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Priority to US17/447,433 priority Critical patent/US20220093606A1/en
Publication of WO2022062536A1 publication Critical patent/WO2022062536A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present application relates to the technical field of storage devices, and in particular, to a method for manufacturing a memory and a memory.
  • Dynamic Random Access Memory (DRAM for short) is widely used in various electronic devices because of its high density and fast read and write speed.
  • Dynamic memory generally consists of multiple memory cells, each memory cell usually includes a transistor and a capacitor.
  • the capacitor stores data information, and the transistor controls the reading and writing of data information in the capacitor.
  • the gate of the transistor is electrically connected to the word line (Word Line, WL) of the dynamic random access memory, and the voltage on the word line controls the opening and closing of the transistor. Closed; one of the source and drain of the transistor is electrically connected to the bit line (Bit Line, BL for short), the other of the source and drain is electrically connected to the capacitor, and data information is stored or stored through the bit line. output.
  • a dynamic random access memory includes a substrate, the substrate includes an active region, and the substrate is provided with bit lines arranged at intervals and a support layer covering the outside of the bit lines.
  • the bit line is electrically connected with the active area
  • the support layer is formed with a contact hole
  • the contact hole is filled with a wire
  • the wire is used to electrically connect the capacitor and the active area.
  • a contact groove is usually formed on the surface of the substrate located in the contact hole.
  • An embodiment of the present application provides a method for fabricating a memory, including: providing a substrate, the substrate including an active region; forming a bit line on the substrate, the bit line covering part of the active region; A support layer covering the bit lines and the substrate is formed on the substrate, the support layer is provided with a first intermediate hole penetrating the support layer and extending to the active region, and the second There is a space between a middle hole and the bit line; a first protective layer is formed in the first middle hole, and an etching hole communicated with the substrate is formed in the first protective layer, so that part of the The active region is exposed in the etching hole; the substrate and the active region exposed in the etching hole are etched along the etching hole to form a contact groove; A wire for electrically connecting the active region is formed in the first intermediate hole, the etching hole, and the contact groove.
  • a substrate including an active region is provided, and then a bit line in contact with a part of the active region and a support layer covering the bit line and the substrate are formed on the substrate, and the support layer
  • a first middle hole is provided that penetrates through the support layer and extends to the active region; by forming a first protective layer on the sidewall of the first middle hole, the etching holes in the first protective layer and communicating with the substrate are exposed to the The substrate and active area in the etching hole are etched to form the contact groove, the sidewall of the contact groove is not easy to be etched through.
  • An embodiment of the present application further provides a memory, including a substrate, the substrate including an active region; a bit line, the bit line being located on the substrate and contacting a part of the active region; a support layer, The support layer covers the bit line and the substrate, the support layer is provided with a wire hole passing through the support layer, and the wire hole is provided with extending into the substrate and connected with the active Conductors in contact with the region; a first protective layer, the first protective layer is located on the inner wall of the conductive hole and on the substrate.
  • the substrate is provided with an active region, a bit line in contact with a part of the active region is provided on the substrate, and a support layer is covered on the bit line and the substrate to protect and electrically insulate the bit line
  • the support layer is also provided with a wire hole running through the support layer, the wire is arranged in the wire hole and extends into the substrate, and is in contact with the active area of the substrate; through the outer side of the wire and the inner side of the wire hole
  • the first protective layer is provided to prevent direct conduction between the wire and the bit line, thereby improving the yield of the memory.
  • FIG. 1 is a flowchart of a method for manufacturing a memory in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram after forming a first support pad in an embodiment of the present application
  • Fig. 3 is the front view of Fig. 2;
  • Fig. 4 is the top view of Fig. 2;
  • FIG. 5 is a schematic structural diagram after forming a sacrificial layer in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of the sacrificial layer after planarization processing in an embodiment of the present application.
  • Fig. 7 is the front view of Fig. 6;
  • Fig. 8 is the top view of Fig. 6;
  • FIG. 9 is a schematic structural diagram after forming a mask layer in an embodiment of the present application.
  • Fig. 10 is the top view of Fig. 9;
  • FIG. 11 is a schematic structural diagram after forming a first filling hole in an embodiment of the present application.
  • Fig. 12 is the top view of Fig. 11;
  • FIG. 13 is a schematic structural diagram after forming the second support pad in the embodiment of the application.
  • Fig. 14 is the top view of Fig. 13;
  • FIG. 15 is a schematic structural diagram after forming the first intermediate hole in the embodiment of the application.
  • Fig. 16 is the top view of Fig. 15;
  • FIG. 17 is a schematic structural diagram after forming a first filling layer in an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram after exposing part of the first middle hole in the embodiment of the present application.
  • Fig. 20 is the front view of Fig. 19;
  • Fig. 21 is the top view of Fig. 19;
  • FIG. 22 is a schematic structural diagram after forming a second filling layer in an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram after forming a second intermediate hole in an embodiment of the present application.
  • Fig. 24 is the front view of Fig. 23;
  • Fig. 25 is the top view of Fig. 23;
  • FIG. 26 is a schematic structural diagram after forming a first protective layer in an embodiment of the present application.
  • Fig. 27 is the front view of Fig. 26;
  • Fig. 28 is the top view of Fig. 26;
  • FIG. 29 is a schematic structural diagram after forming a contact groove in an embodiment of the application.
  • Fig. 30 is the front view of Fig. 29;
  • Figure 31 is the top view of Figure 29;
  • 32 is a schematic structural diagram of a memory in an embodiment of the present application.
  • Fig. 33 is the top view of Fig. 32;
  • FIG. 34 is a schematic diagram of the structure after the transformation region is formed in the embodiment of the present application.
  • the present application provides a method for manufacturing a memory.
  • a bit line is formed on a substrate, and a support layer covering the bit line and the substrate is provided.
  • the support layer is provided with a first intermediate hole.
  • a protective layer when the contact groove is etched to the substrate along the etch hole in the first protective layer, the sidewall of the contact groove is less likely to be etched than the substrate is directly etched along the first intermediate hole , after the conductive lines are subsequently formed in the first intermediate hole, the etching hole and the contact groove, the direct conduction between the conductive lines and the bit lines can be avoided, thereby improving the yield of the memory.
  • FIG. 1 is a schematic structural diagram of a flowchart of a method for manufacturing a memory in an embodiment of the present application.
  • FIGS. 2 to 33 are schematic structural diagrams of a memory in various stages and a schematic structural diagram of a memory in an embodiment of the present application. The following is combined with FIG. 1 . The manufacturing method of the memory in the embodiment of the present application will be described in detail to FIG. 33 .
  • the substrate 10 is provided with an active region 11, the active region 11 may include a first contact region 111 and a second contact region 112, and the first contact region 111 may be located in the middle region of the active region 11, using is electrically connected to the bit line 20 .
  • the second contact regions 112 may be located at both ends of the active region 11 for electrical connection with the capacitors in the memory cells, for example, the second contact regions 112 are electrically connected with the capacitors through the wires 70 .
  • the active region 11 can form a transistor in the memory cell.
  • the first contact region 111 is a source region
  • the second contact region 112 is a drain region
  • the source region and the drain region are formed by an ion implantation process.
  • the material of the substrate 10 may be silicon oxide
  • the material of the active region 11 may be a semiconductor material, such as silicon material.
  • a plurality of active regions 11 may be provided to improve the utilization rate of the substrate 10 and the density of memory cells. There may be a certain interval between the plurality of active regions 11, that is, the active regions 11 are not connected to each other. A plurality of active regions 11 may be arranged in parallel, and shallow trench isolation may be provided between the active regions 11 .
  • the bit line 20 on the substrate 10 is electrically connected to a portion of the active region 11 .
  • the bit line 20 is a conductive material, such as one or more of tungsten, titanium, nickel, aluminum, titanium oxide, and titanium nitride, and the bit line is formed by depositing the conductive material on part of the substrate 10 and part of the active region 11 20. Specifically, the bit line 20 covers the first contact region 111 of the active region 11.
  • the bit line 20 includes a first sub-body 21 close to the substrate 10 and a second sub-body 22 in contact with the first sub-body 21 .
  • the first body 21 is in contact with the substrate 10 and the active region 11 , and the material of the first body 21 may be titanium nitride (TiN).
  • the second body 22 is located on the side of the first body 21 away from the substrate 10 , and the material of the second body 22 may be tungsten (W).
  • a plurality of bit lines 20 may be provided on the substrate 10, and the plurality of bit lines 20 may be arranged at intervals. There is a certain angle between the orthographic projection of the bit line 20 on the substrate 10 and the orthographic projection of the active region 11 on the substrate 10 , that is, the two orthographic projections are not parallel.
  • bit lines 20 are arranged vertically, the plurality of bit lines 20 are parallel to each other, the active regions 11 are arranged obliquely, and the plurality of active regions 11 are parallel to each other.
  • One bit line 20 is disposed on each active region 11 , and the same bit line 20 can pass through a plurality of active regions 11 .
  • the support layer is provided with a first middle hole penetrating the support layer and extending to the active region, and there is a space between the first middle hole and the bit line.
  • the cross-sectional shape of the first intermediate hole 36 may be a polygon, and the polygon may be a regular polygon such as a square, a regular pentagon, or the like. This embodiment and the following embodiments are described in detail by taking the cross-sectional shape of the first intermediate hole 36 as a rectangle as an example.
  • the material of the support layer 30 can be an insulating material, such as silicon nitride, to protect and electrically isolate the bit line 20 .
  • the first middle hole 36 is a vertical hole, the first middle hole 36 extends to the substrate 10 and communicates with a part of the active region 11 . Specifically, the first intermediate hole 36 communicates with the second contact region 112 of the active region 11 .
  • the support layer 30 and the first intermediate hole 36 can be formed by the following steps:
  • first support pads 31 are formed on the substrate 10 and respectively cover the outside of the bit lines 20 .
  • a substrate 10 is provided with a plurality of active regions 11 , a plurality of bit lines 20 are provided on the substrate 10 , and one bit line 20 contacts a plurality of active regions in the plurality of active regions 11 11 , and contact the first contact region 111 of each active region 11 .
  • Each bit line 20 is covered with first support pads 31 respectively, and the number of the first support pads 31 is consistent with the number of the bit lines 20 .
  • the first support pads 31 are arranged at intervals. As shown in FIG. 4 , there are gaps 32 between the first support pads 31 .
  • the first support pad 31 is made of insulating material, such as silicon nitride.
  • a sacrificial layer 33 is formed to fill the gap 32 between the first support pads to form the structure shown in FIG. 5 .
  • a sacrificial layer 33 covering the substrate 10 and the first support pad 31 is formed, and the sacrificial layer 33 can be formed by a spin-on-dielectrics (SOD for short) process, for example, the sacrificial layer 33 is formed by a spin-on-dielectrics Silicon oxide is formed.
  • the sacrificial layer 33 is annealed to cure the sacrificial layer 33 and densify the layer to facilitate subsequent processing.
  • the material of the sacrificial layer 33 may be silicon oxide.
  • the silicon oxide material has a high selectivity ratio, is easy to etch, and can reduce the height of the mask.
  • the surface of the sacrificial layer 33 may be planarized. As shown in FIG. 6 to FIG. processing.
  • the upper surface of the sacrificial layer 33 is flat, so that other required layers can be disposed on the sacrificial layer 33 .
  • the surface of the sacrificial layer 33 facing away from the substrate 10 may be subjected to mechanical chemical polishing (Chemical Mechanical Polishing for short CMP).
  • mechanical chemical polishing Chemical Mechanical Polishing for short CMP
  • the sacrificial layer 33 may also be planarized by methods such as ion etching, which is not limited in this embodiment of the present application.
  • first filling holes 34 are formed in the sacrificial layer 33 to form the structure shown in FIG. 11 .
  • the first filling hole 34 is formed by etching. Specifically, a mask layer 40 is formed on the sacrificial layer 33 first, and then the sacrificial layer 33 is etched by using the mask layer 40 to form the first filling hole 34 extending to the substrate 10 ; finally, the mask layer 40 is removed.
  • the mask layer 40 may be formed on the upper surface of the sacrificial layer 33 by deposition.
  • the mask layer 40 has a certain pattern, as shown in FIG. 9 and FIG. 10 , the mask layer 40 has a plurality of grooves parallel to each other, and the orthographic projections of the plurality of grooves and the first support pad 31 on the surface of the substrate 10 are mutually Vertically, these parallel trenches form etching windows along which the sacrificial layer 33 is etched.
  • the material of the mask layer 40 may be photoresist (Photo Resist, PR for short).
  • the first fill hole 34 is shown. The first filling hole 34 penetrates through the sacrificial layer 33 and is in contact with the substrate 10 .
  • a second supporting pad 35 is formed in the first filling hole 34.
  • the second supporting pad 35 and the first supporting pad 34 have the same height to form the supporting layer 30 together, forming FIG. 13 . and the structure shown in Figure 14.
  • the material of the second support pad 35 may be the same as that of the first support pad 31 , and the second support pad 35 is filled in the first filling hole 34 .
  • the orthographic projections of the first support pad 31 and the second support pad 35 on the surface of the substrate 10 may be perpendicular, that is, the first support pad 31 may be arranged in the vertical direction shown in FIG.
  • the two support pads 35 can be arranged along the horizontal direction as shown in FIG. 14 .
  • the second support pad 35 and the first support pad 34 have the same height, and together constitute the support layer 30 .
  • the upper surface of the second support pad 35 may be smoothed by CMP, so that the height of the second support pad 35 and the first support pad 31 are the same.
  • various parts other than the upper surface of the first support pad 31 can be removed, that is, part of the second support pad 35 and part of the sacrificial layer 33 can be removed by grinding until the first support pad 31 is exposed.
  • Part of the surface layer of the first support pad 31 and parts outside the surface layer can also be removed, that is, part of the first support pad 31 , part of the second support pad 35 and part of the sacrificial layer 33 can be removed by grinding.
  • a second support pad 35 is formed in the first filling hole 34 , and the second support pad 35 and the first support pad 34 have the same height to form the support layer 30 , and then the sacrificial layer 33 is removed to form the first middle in the support layer 30
  • the hole 36 forms the structure shown in FIGS. 15 and 16 .
  • the remaining sacrificial layer 33 located between the gaps 32 of the first support pad 31 is removed, and the sacrificial layer 33 is completely removed so far.
  • first middle hole 36 penetrates through the support layer 30 and extends to the substrate 10 and the active region 11 . Specifically, as shown in FIG. 16 , the first middle hole 36 exposes part of the substrate 10 and the active region The second contact area 112 of 11 is used for subsequent filling of the wires 70 .
  • the number of the first intermediate holes 36 is multiple, and the sizes and shapes of the multiple first intermediate holes 36 may be consistent.
  • the first protective layer 80 is disposed on the inner wall of the first middle hole 36 and is in contact with the substrate 10 , and an etching hole 51 is formed in the first protective layer 80 to protect the first middle hole 36 , especially the first middle hole 36 .
  • the middle hole 36 is close to the portion of the substrate 10 .
  • the first protective layer 80 can reduce the etching on the sidewall of the first intermediate hole 36 during etching. eclipse impact.
  • the etching holes 51 are in the first protective layer 80 and take a plane parallel to the surface of the substrate 10 as a cross section, the cross-sectional area of the etching holes 51 is smaller than that of the first intermediate holes 36 .
  • the etching is performed with a certain margin, so as to prevent the sidewalls of the contact groove 12 and/or the first intermediate hole 36 from being etched through, thereby exposing the bit line 20 and/or the contact with the bit line 20 .
  • the first protective layer 80 may be provided along the circumferential direction of the first intermediate hole 36 for an entire circumference, or may be discontinuous along the circumferential direction of the first intermediate hole 36 .
  • the first protective layer 80 includes a plurality of protective blocks, the plurality of protective blocks are arranged at intervals along the circumference of the first intermediate hole 36 , and each protective block is in contact with the substrate 10 .
  • a first filling layer 50 is formed in the first intermediate hole 36 and on the surface of the support layer 30 to form the structure shown in FIG. 17 .
  • the first filling layer 50 covering the first intermediate hole 36 and the supporting layer 30 may be formed by an atomic layer deposition process (Atomic Layer Deposition, ALD for short).
  • the gas can be bis(isopropylamino)silane LTO520/O2 or bis(diethylamino)silane N zero/O2.
  • the height of the first filling layer 50 is higher than the height of the supporting layer 30 , and the material of the first filling layer 50 may be silicon oxide.
  • the process includes:
  • a part of the first filling layer 50 in the first middle hole 36 is removed to expose a part of the sidewall of the first middle hole 36 .
  • the first filling layer 50 on the surface of the supporting layer 30 may be removed by mechanochemical grinding, and grinding until the surface of the supporting layer 30 is exposed, that is, the first filling layer 50 located on the upper surface of the supporting layer 30 is removed. , the structure shown in Figure 18 is formed.
  • a part of the first filling layer 50 located in the first intermediate hole 36 may be removed by etching to form the structure shown in FIGS. 1/5 to 1/4 of the height of the side wall, that is, the height of the exposed side wall of the first middle hole 36 accounts for 1/5 to 1/4 of the height of the entire side wall of the first middle hole 36 .
  • a second filling layer 60 is formed in the first middle hole 36 to cover the exposed The sidewalls of the first middle hole 36 and the top of the remaining first filling layer 50 are removed to form a second middle hole 61 in the second filling layer 60 .
  • a second filling layer 60 is formed on the sidewall of the first intermediate hole 36 , the upper surface of the first filling layer 50 and the upper surface of the supporting layer 30 .
  • the second filling layer 60 can be formed by deposition, and the material of the second filling layer 60 can be the same as that of the first filling layer 50 , for example, both are made of silicon oxide.
  • the second filling layer 60 located in the first intermediate hole 36 forms the second intermediate hole 61 , that is, the cross-sectional area of the second intermediate hole 61 is smaller than the cross-sectional area of the first intermediate hole 36 with the surface parallel to the substrate 10 as the plane.
  • the cross-sectional area of the second intermediate hole 61 is less than or equal to 3/4 of the cross-sectional area of the first intermediate hole 36 .
  • the second filling layer 60 located on the sidewall of the first intermediate hole 36 will also be etched away.
  • the effect of etching on the sidewall of the first middle hole 36 is reduced, and on the other hand, the wire 70 located in the first middle hole 36 can have a larger cross-sectional area, thereby reducing the influence on the conductive performance of the wire 70 .
  • a second filling layer 60 is formed in the first middle hole 36 , covering the exposed sidewalls of the first middle hole 36 and the top of the remaining first filling layer 50 , in the second filling layer 60
  • the second filling layer 60 and part of the first filling layer 50 are removed until the substrate 10 is exposed, and the remaining first filling layer 50 forms the first protective layer 80 .
  • a second filling layer 60 is formed in the first middle hole 36 to cover the exposed sidewall of the first middle hole 36 and the top of the remaining first filling layer 50 , and a second filling layer 60 is formed in the second filling layer 60 .
  • the second filling layer 60 and part of the first filling layer 50 are removed until the substrate 10 is exposed, and before the remaining first filling layer 50 is formed into the first protective layer 80 , it also includes removing the supporting layer
  • the second filling layer 60 on the 30 and the second filling layer 60 at the bottom of the second middle hole 36 form the structure shown in FIGS.
  • the first filling layer 50 is removed.
  • the second filling layer 60 and part of the first filling layer 50 are removed until the substrate 10 is exposed, and the remaining first filling layer 50 to form the first protective layer 80 includes: :
  • the first part of the first filling layer 50 is removed along the second middle hole 61; the second part of the first filling layer 50 is removed until the substrate 10 is exposed.
  • the remaining third portion of the filling layer 50 constitutes the first protective layer 80 to form the structures shown in FIGS. 26 to 28 .
  • the part of the first filling layer 50 that is opposite to the second middle hole 61 is removed along the second middle hole 61 , and this part is the first filling layer 50 .
  • the height of the first part is the same as the height of the removed second filling layer 60 . It can be understood that the first filling layer 50 does not expose the substrate 10 , and after the first part of the first filling layer 50 is removed, the first filling layer 50 is formed with a protruding portion that fits with the first middle hole 36 .
  • the removal of the first filling layer 50 is continued until the substrate 10 is exposed. During this process, the part of the remaining first filling layer 50 facing the second middle hole 61 is removed along the second middle hole 61 , and the part of the protrusion of the first filling layer 50 is removed along the first middle hole 36 , The part and the part of the protrusion in the first filling layer 50 are the second part of the first filling layer 50 .
  • the third part may be a plurality of first protective layer segments, each of which is connected to two adjacent sidewalls in the first middle hole 36 . It can be understood that each first protective layer segment is correspondingly distributed at each corner of the first middle hole 36 , and these first protective layer segments together constitute the first protective layer 80 .
  • the first and second portions of the first filling layer 50 may be removed by dry etching. After the first part and the second part are etched, an etching hole 51 is formed in the first filling layer 50 , and the etching hole 51 communicates with a part of the substrate 10 and the active region 11 .
  • the sidewall of the etched hole 51 includes the inner side of the first filling layer 50 and a part of the inner wall of the first middle hole 36. Since the first filling layer 50 has a larger etching depth, with the increase of the etching time, the first filling layer 50 has a large etching depth.
  • the inner side surface of the filling layer 50 forms an arc surface, that is, the transition between two adjacent side walls in the first middle hole 36 is rounded by the first protective layer 80 to form the structure shown in FIG. 26 .
  • the first middle hole 36 and the etching hole 51 form a stepped structure, and when the wire 70 is subsequently formed in the first middle hole 36 and the etching hole 51 , the cross-sectional area of the wire 70 in the first middle hole 36 is larger and can be reduced Resistance of wire 70.
  • the substrate 10 and the active region 11 are etched along the etching hole 51 to form the contact groove 12 , and part of the side and bottom surfaces of the contact groove 12 are the active region 11 .
  • the second contact area 112 The deeper the depth of the contact groove 12 is, the larger the exposed surface area of the second contact region 112 in the active region 11 is, and the larger the contact area between the conductive line 70 filled in the contact groove 12 and the active region 11 is, the larger the contact area of the conductive line 70 is.
  • the contact resistance with the active region 11 is reduced, so that the conductive performance of the wire 70 is better.
  • the wire 70 may be made of polysilicon, which is formed by depositing in the first intermediate hole 36 , the etching hole 51 and the contact groove 12 .
  • the material of the first protective layer 80 is usually oxide, and the material of the support layer 30 is usually nitride.
  • the method further includes: nitriding the first protective layer 80, so that the material of the first protective layer 80 is the same as that of the supporting layer 30, so that the first protective layer 80 is made of the same material as the supporting layer 30. 80 and the support layer 30 may form a unitary body.
  • plasma nitriding can be performed on the first protective layer 80.
  • NH3 is used as the plasma nitriding gas
  • the plasma intensity is 600-2000 W
  • the nitriding temperature is 600-800 °C
  • the nitriding pressure is 1 ⁇ 10pa.
  • the material of the substrate 10 is silicon oxide and the material of the active region 11 is silicon
  • the first protective layer 80 is nitrided, part of the substrate 10 and the active region 11 will also be converted That is, in the substrate 10 and the active region 11, the portion corresponding to the etched hole 51 is also converted into silicon nitride, and the converted region A shown by the dotted line in FIG. 34 is the converted silicon nitride region. During subsequent etching along the etching hole 51, the conversion region A will be removed.
  • a substrate 10 including an active region 11 is provided, and then a bit line 20 in contact with a part of the active region 11 and a covering bit line 20 and the substrate are formed on the substrate 10
  • the support layer 30 of 10, the support layer 30 is provided with a first middle hole 36 that penetrates through the support layer 30 and extends to the active region 11;
  • the etching hole 51 in 80 and communicating with the substrate 10 etches the substrate 10 and the active region 11 exposed in the etching hole 51, and when the contact groove 12 is formed, the sidewall of the contact groove 12 is not easily damaged.
  • the wire 70 for electrically connecting the active region 11 is formed in the first intermediate hole 36, the etching hole 51 and the contact groove 12, the wire 70 and the bit line 20 can be prevented from being directly connected, thereby improving the memory yield.
  • FIG. 32 is a schematic structural diagram of a memory in an embodiment of the present application.
  • the memory includes a substrate 10 , a bit line 20 , a support layer 30 and a first protective layer 80 .
  • the substrate 10 includes an active region 11, and the active region 11 may include a first contact region 111 electrically connected to the bit line 20 and a second contact region 112 electrically connected to the wire 70, and the first contact region 111 is located in the active region In the middle of the region 11 , the second contact regions 112 are located at both ends of the active region 11 .
  • the bit line 20 is located on the substrate 10 and is in contact with a portion of the active region 11 .
  • the bit line 20 may be a conductive material, making electrical contact with the first contact region 111 in the active region 11 .
  • the bit line 20 includes a first body 21 close to the substrate 10 and a second body 22 in contact with the first body 21 .
  • the material of the first body 21 may be titanium nitride (TiN).
  • the material of the second body 22 may be tungsten (W).
  • each active region 11 contacts at most one bit line 20, exemplarily, a plurality of bit lines 20 are arranged in parallel, and a plurality of active regions 11 are arranged in parallel, and the bit lines 20 are arranged obliquely between the orthographic projection of the upper surface of the substrate 10 and the orthographic projection of the active region 11 on the upper surface of the substrate 10 .
  • the support layer 30 covers the bit line 20 and the substrate 10 .
  • the support layer 30 is usually an insulating material.
  • the support layer 30 is provided with a wire hole penetrating the support layer 30 to accommodate the wire 70 .
  • the wire 70 may extend into the substrate 10 and make contact with a portion of the active region 11 , for example with the second contact region 112 in the active region 11 .
  • There is a space between the wire hole and the bit line 20 so that the wire 70 and the bit line 20 are not directly conductive.
  • the lead hole includes the first intermediate hole 36 , the etching hole 51 and the contact groove 12 connected in sequence from top to bottom.
  • the first intermediate hole 36 and the etching hole 51 are located in the support layer 30 on the substrate 10 and penetrate through the support layer 30 .
  • Contact grooves 12 are formed in substrate 10 . Taking a plane parallel to the surface of the substrate 10 as a cross-section, the cross-sectional area of the etching hole 51 is smaller than that of the first intermediate hole 36 .
  • the first protective layer 80 is located on the inner wall of the wire hole and is in contact with the substrate 10. Referring to FIG. 30, the first protective layer 80 is located on the substrate 10, and is located between the inner side of the wire hole and the outer side of the wire 70. Specifically Yes, the first protective layer 80 is located between the inner side of the etching hole 51 and the outer side of the wire 70 .
  • the first protective layer 80 constitutes at least part of the inner wall of the etched hole 51 .
  • the first protective layer 80 may surround the first middle hole 36 in the circumferential direction of the first middle hole 36 for a whole circumference, and the inner wall of the first protective layer 80 It is the inner wall of the etching hole 51 .
  • the first protective layer 80 may also be arranged at intervals along the circumference of the first middle hole 36 , so that the inner wall of the first protective layer 80 and the inner wall of the first middle hole 36 together constitute the inner wall of the etching hole 51 .
  • the first protective layer 80 includes a plurality of protective blocks, all of which are in contact with the substrate 10 , and each protective block is connected to two parts of the first middle hole 36 .
  • Each of the adjacent sidewalls, each protection block and the sidewalls of the first middle hole 36 form sidewalls of the etching hole 51 .
  • the sidewalls of the protection block and the sidewalls of the first intermediate holes 36 are alternately connected to form sidewalls of the etching holes 51 .
  • each protection block facing away from the two side walls of the first intermediate hole 36 connected to the protection block are arc surfaces, that is, the surface of each protection block facing the centerline of the first intermediate hole 36 is an arc surface.
  • Part of the inner wall of the formed etching hole 51 is an arc surface through the arc transition of the side wall of the first protection block between two adjacent side walls 36 . In this way, while avoiding contact between the wire 70 and the bit line 20 , the cross-sectional area of the etching hole 51 is larger, so that the wire 70 has a larger cross-sectional area and reduces the resistance of the wire 70 .
  • the height of the etching hole 51 may be lower than the height of the first middle hole 36 , that is, the upper surface of the etching hole 51 is lower than the upper surface of the first middle hole 36 , so that the upper part of the wire 70 has The larger cross-sectional area further reduces the resistance of the wire 70 .
  • the substrate 10 is provided with an active region 11 , a bit line 20 in contact with a part of the active region 11 is provided on the substrate 10 , and the bit line 20 and the substrate 10 are covered with a support layer 30 to The bit line 20 is protected and electrically insulated; the support layer 30 is also provided with a wire hole penetrating the support layer 30 , and the wire 70 is arranged in the wire hole and extends into the substrate 10 to be in contact with the active region 11 of the substrate 10 ; By setting the first protective layer 80 on the outer side of the wire 70 and the inner side of the wire hole to prevent the wire 70 from being directly connected to the bit line 20, thereby improving the yield of the memory.

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Abstract

本申请属于存储设备技术领域，涉及一种存储器的制作方法及存储器，用于解决存储器成品率低的问题。该存储器的制作方法包括：提供衬底，衬底包括有源区；在衬底上形成位线，位线覆盖部分有源区；在衬底上形成覆盖位线和衬底的支撑层，支撑层设有贯穿支撑层并延伸至有源区的第一中间孔，第一中间孔与位线之间具有间隔；在第一中间孔内形成第一保护层，在第一保护层内形成有与衬底相通的刻蚀孔；沿刻蚀孔对暴露在刻蚀孔内的衬底及有源区进行刻蚀，形成接触凹槽；在第一中间孔、刻蚀孔以及接触凹槽内形成导线；通过设置第一保护层可以使接触凹槽的侧壁不易被刻穿，避免导线与位线直接导通，进而提高了存储器成品率。

Description

存储器的制作方法及存储器
本申请要求于2020年09月24日提交中国专利局、申请号为202011016007.4、申请名称为“存储器的制作方法及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储设备技术领域，尤其涉及一种存储器的制作方法及存储器。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称DRAM)因具有较高的密度以及较快的读写速度广泛地应用在各种电子设备中。动态存储器一般由多个存储单元组成，每个存储单元通常包括晶体管和电容器。电容器存储数据信息，晶体管控制电容器中的数据信息的读写，其中，晶体管的栅极与动态随机存储器的字线(Word Line，简称WL)电连接，通过字线上的电压控制晶体管的开启和关闭；晶体管的源极和漏极中的一极与位线(Bit Line，简称BL)电连接，源极和漏极中的另一极与电容器电连接，通过位线对数据信息进行存储或者输出。
相关技术中，动态随机存储器包括衬底，衬底中包括有源区，衬底上设置有间隔排布的位线以及包覆于位线外的支撑层。位线与有源区电连接，支撑层形成有接触孔，接触孔中填充有导线，导线用于电连接电容器与有源区。为了增大导线与有源区的接触面积，通常在位于接触孔中的衬底的表面上形成接触凹槽。然而，在制作动态随机存储器的过程中，易出现位线与导线连通导致的晶体管失效，进而导致动态随机存储器成品率较低。
发明内容
本申请实施例提供了一种存储器的制作方法，包括：提供衬底，所述 衬底包括有源区；在所述衬底上形成位线，所述位线覆盖部分所述有源区；在所述衬底上形成覆盖所述位线和所述衬底的支撑层，所述支撑层设有贯穿所述支撑层并延伸至所述有源区的第一中间孔，且所述第一中间孔与所述位线之间具有间隔；在所述第一中间孔内形成第一保护层，在所述第一保护层内形成有与所述衬底相通的刻蚀孔，使部分所述有源区暴露在所述刻蚀孔内；沿所述刻蚀孔对暴露在所述刻蚀孔内的所述衬底及所述有源区进行刻蚀，形成接触凹槽；在所述第一中间孔、所述刻蚀孔，以及所述接触凹槽内形成用于电连接所述有源区的导线。
本申请实施例提供的存储器的制作方法中，提供包括有源区的衬底，然后在衬底上形成与部分有源区相接触的位线和覆盖位线及衬底的支撑层，支撑层设有贯穿支撑层并延伸至有源区的第一中间孔；通过在第一中间孔的侧壁形成第一保护层，使得沿第一保护层内且与衬底相通的刻蚀孔对暴露在刻蚀孔内的衬底及有源区进行刻蚀，形成接触凹槽时，接触凹槽的侧壁不易被刻穿，后续在第一中间孔、刻蚀孔以及接触凹槽内形成用于电连接有源区的导线后，可以避免导线与位线直接导通，进而提高了存储器的成品率。
本申请实施例还提供了一种存储器，包括衬底，所述衬底包括有源区；位线，所述位线位于所述衬底上，且接触部分所述有源区；支撑层，所述支撑层覆盖所述位线和所述衬底，所述支撑层设有贯穿所述支撑层的导线孔，所述导线孔内设有延伸入所述衬底中并与所述有源区接触的导线；第一保护层，所述第一保护层位于所述导线孔的内壁且位于所述衬底上。
本申请实施例提供的存储器中，衬底设置有源区，衬底上设置与部分有源区相接触的位线，位线和衬底上覆盖支撑层，以对位线进行保护和电气绝缘；支撑层中还设置贯穿所述支撑层的导线孔，导线设置在导线孔中并延伸入衬底中，与衬底的有源区相接触；通过在导线的外侧面与导线孔的内侧面设置第一保护层，以防止导线与位线直接导通，进而提高存储器的成品率。
附图说明
图1为本申请实施例中的存储器的制作方法的流程图；
图2为本申请实施例中形成第一支撑垫后的结构示意图；
图3为图2的正视图；
图4为图2的俯视图；
图5为本申请实施例中形成牺牲层后的结构示意图；
图6为本申请实施例中对牺牲层平坦化处理后的结构示意图；
图7为图6的正视图；
图8为图6的俯视图；
图9为本申请实施例中形成掩膜层后的结构示意图；
图10为图9的俯视图；
图11为本申请实施例中形成第一填充孔后的结构示意图；
图12为图11的俯视图；
图13为本申请实施例中形成第二支撑垫后的结构示意图；
图14为图13的俯视图；
图15为本申请实施例中形成第一中间孔后的结构示意图；
图16为图15的俯视图；
图17为本申请实施例中形成第一填充层后的结构示意图；
图18为本申请实施例中去除支撑层上的第一填充层后的结构示意图；
图19为本申请实施例中暴露部分第一中间孔后的结构示意图；
图20为图19的正视图；
图21为图19的俯视图；
图22为本申请实施例中形成第二填充层后的结构示意图；
图23为本申请实施例中形成第二中间孔后的结构示意图；
图24为图23的正视图；
图25为图23的俯视图；
图26为本申请实施例中形成第一保护层后的结构示意图；
图27为图26的正视图；
图28为图26的俯视图；
图29为本申请实施例中形成接触凹槽后的结构示意图；
图30为图29的正视图；
图31为图29的俯视图；
图32为本申请实施例中的存储器的结构示意图；
图33为图32的俯视图；
图34为本申请实施例中形成转化区域后的结构示意图。
具体实施方式
本申请提供一种存储器的制作方法，在衬底上形成有位线，以及包覆位线和衬底的支撑层，支撑层内设置有第一中间孔，通过在第一中间孔中设置第一保护层，沿第一保护层中的刻蚀孔对衬底刻蚀接触凹槽时，相较于沿第一中间孔直接对衬底进行刻蚀，接触凹槽的侧壁不易被刻穿，后续在第一中间孔、刻蚀孔以及接触凹槽内形成导线后，可以避免导线与位线直接导通，进而提高了存储器的成品率。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
实施例一
图1为本申请实施例中的存储器的制作方法的流程图的结构示意图，图2至图33为本申请实施例中的存储器在各阶段中的结构示意图以及存储器的结构示意图，以下结合图1至图33详述本申请实施例中的存储器的制作方法。
本申请实施例中的存储器的制作方法包括以下步骤：
S101、提供衬底，衬底包括有源区。
参照图2至图4，衬底10设置有源区11，有源区11可以包括第一接触区111和第二接触区112，第一接触区111可以位于有源区11的中间区域，用于与位线20电连接。第二接触区112可以位于有源区11的两端部，用于与存储单元中的电容器电连接，例如，第二接触区112通过导线70与电容器电连接。
有源区11可以形成存储单元中的晶体管，示例性的，第一接触区111为源区，第二接触区112为漏区，源区和漏区通过离子注入工艺形成。衬底10 的材质可以为氧化硅，有源区11的材质可以为半导体材质，例如硅材质。
有源区11可以设置有多个，以提高衬底10的利用率以及存储单元的密度。多个有源区11之间可以具有一定间隔，即有源区11之间互不连通。多个有源区11可以平行排布，有源区11之间可以设置浅槽隔离。
S102、在衬底上形成位线，位线覆盖部分有源区。
继续参照图2至图4，衬底10上的位线20与部分有源区11电连接。位线20为导电材料，例如钨、钛、镍、铝、氧化钛、氮化钛中的一种或者多种，通过将导电材料沉积在部分衬底10和部分有源区11上形成位线20，具体的，位线20覆盖有源区11的第一接触区111。
本申请实施例中，位线20包括与靠近衬底10的第一分体21和与第一分体21相接触的第二分体22。第一分体21与衬底10和有源区11接触，第一分体21的材质可以为氮化钛(TiN)。第二分体22位于第一分体21远离衬底10的一侧，第二分体22的材质可以为钨(W)。
当衬底10包括多个有源区11时，衬底10上可以设置多条位线20，多条位线20间隔设置。位线20在衬底10上的正投影与有源区11在衬底10上的正投影之间具有一定角度，即这两个正投影不平行。
示例性的，以图4中所示方位，位线20竖直设置，多条位线20之间相互平行，有源区11倾斜设置，多个有源区11之间相互平行。每个有源区11上设置一条位线20，同一条位线20可以穿过多个有源区11。
S103、在衬底上形成覆盖位线和衬底的支撑层，支撑层设有贯穿支撑层并延伸至有源区的第一中间孔，且第一中间孔与位线之间具有间隔。
以平行于衬底10的平面为截面，第一中间孔36的截面形状可以为多边形，多边形可以为正方形、正五边形等正多边形。本实施例及以下各实施例以第一中间孔36的截面形状为矩形为例进行详述。
支撑层30的材质可以为绝缘材质，例如氮化硅，以对位线20进行保护以及电气隔离。以图2所示方位为例，第一中间孔36为竖直孔，第一中间孔36延伸至衬底10，且连通部分有源区11。具体的，第一中间孔36连通有源区11的第二接触区112。
当位线20设置有多条时，支撑层30和第一中间孔36可以通过以下步骤 形成：
首先，在衬底10上形成分别包覆于位线20外的第一支撑垫31。
参照图2至图4，衬底10中设置有多个有源区11，衬底10上设置有多条位线20，一条位线20接触多个有源区11中的数个有源区11，且接触每个有源区11的第一接触区111。
每条位线20外分别包覆有第一支撑垫31，第一支撑垫31的数量与位线20的数量相一致。第一支撑垫31间隔设置，如图4所示，第一支撑垫31之间具有间隙32。第一支撑垫31为绝缘材质，例如氮化硅。
在衬底10上形成分别包覆于位线20外的第一支撑垫31之后，形成牺牲层33填充第一支撑垫之间的间隙32，形成图5所示结构。
也就是说，形成覆盖于衬底10和第一支撑垫31的牺牲层33，牺牲层33可以通过旋涂绝缘介质(Spin on Dielectrics，简称SOD)工艺形成，例如牺牲层33通过旋涂绝缘介质氧化硅形成。通过旋涂绝缘介质形成牺牲层33后，对牺牲层33进行退火(Anneal)处理，对牺牲层33进行固化，同时使得该层致密化，以便于后续加工。
示例性的，牺牲层33的材质可以为氧化硅，氧化硅材质具有较高的选择比，容易刻蚀，可以降低掩膜高度。
需要说明的是，形成牺牲层33后，进行下步处理前，可以对牺牲层33的表面进行平坦化处理，如图6至图8所示，对牺牲层33背离衬底10的表面进行平坦化处理。
平坦化处理后，牺牲层33的上表面平整，便于牺牲层33上设置其他所需层。牺牲层33背离衬底10的表面可以通过机械化学研磨(Chemical Mechanical Polishing简称CMP)。当然，牺牲层33也可以通过离子刻蚀等方法进行平坦化，本申请实施例在此不做限定。
形成牺牲层33填充第一支撑垫之间的间隙32之后，在牺牲层33中形成第一填充孔34，形成图11所示结构。
在一种可能的示例中，第一填充孔34通过刻蚀形成。具体的，先在牺牲层33上形成掩膜层40，然后利用掩膜层40对牺牲层33进行刻蚀，以形成延伸至衬底10的第一填充孔34；最后去除掩膜层40。
示例性的，掩膜层40可以通过沉积形成于牺牲层33的上表面。掩膜层40具有一定图案，如图9和图10所示，掩膜层40具有相互平行的多个沟槽，多个沟槽与第一支撑垫31在衬底10的表面的正投影相互垂直，这些平行的沟槽形成刻蚀窗口，沿刻蚀窗口对牺牲层33进行刻蚀。掩膜层40的材质可以为光刻胶(Photo Resist，简称PR)。
需要说明的是，在刻蚀过程中，去除部分牺牲层33，在利用刻蚀液或者刻蚀气体刻蚀牺牲层33，不会刻蚀第一支撑垫31，形成如图11和图12所示的第一填充孔34。第一填充孔34贯穿牺牲层33，并与衬底10相接触。
在牺牲层33中形成第一填充孔34之后，在第一填充孔34中形成第二支撑垫35，第二支撑垫35与第一支撑垫34高度相同，共同构成支撑层30，形成图13和图14所示的结构。
第二支撑垫35的材质可以与第一支撑垫31的材质相同，第二支撑垫35填充在第一填充孔34中。如图14所示，第一支撑垫31与第二支撑垫35在衬底10的表面上的正投影可以相垂直，即第一支撑垫31可以沿图14所示的竖直方向设置，第二支撑垫35可以沿图14所示的水平方向设置。
第二支撑垫35与第一支撑垫34高度相同，共同构成支撑层30。示例性的，可以通过CMP将第二支撑垫35的上表面磨平，使得第二支撑垫35与第一支撑垫31的高度相一致。
可以理解的是，在进行CMP处理时，可以去除第一支撑垫31的上表面之外的各部分，即研磨去除部分第二支撑垫35和部分牺牲层33，直至露出第一支撑垫31的上表面为止；也可以去除第一支撑垫31的部分表层以及位于该表层之外的各部分，即研磨去除部分第一支撑垫31、部分第二支撑垫35的以及部分牺牲层33。
在第一填充孔34中形成第二支撑垫35，第二支撑垫35与第一支撑垫34高度相同，共同构成支撑层30之后，去除牺牲层33，以形成支撑层30中的第一中间孔36，形成图15和图16所示结构。
具体的，去除位于第一支撑垫31的间隙32之间的剩余的牺牲层33，至此将牺牲层33完全去除。
可以理解的是，第一中间孔36贯穿支撑层30并延伸至衬底10和有源区 11，具体的，如图16所示，第一中间孔36中暴露部分衬底10和有源区11的第二接触区112，用于后续填充导线70。第一中间孔36的数量为多个，多个第一中间孔36的尺寸与形状可以一致。
S104、在第一中间孔内形成第一保护层，在第一保护层内形成有与衬底相通的刻蚀孔，使部分有源区暴露在刻蚀孔内。
具体的，第一保护层80设置在第一中间孔36的内壁且与衬底10相接触，第一保护层80内形成刻蚀孔51，用于保护第一中间孔36，尤其是第一中间孔36靠近衬底10的部分。
通过第一保护层80内的刻蚀孔51在衬底10上刻蚀接触凹槽12时，一方面，刻蚀时，第一保护层80可以减少对第一中间孔36的侧壁的刻蚀影响。另一方面，由于刻蚀孔51在第一保护层80内，以平行于衬底10的表面的平面为截面，刻蚀孔51的截面积小于第一中间孔36的截面积。刻蚀时具有一定的裕量，从而防止将接触凹槽12和/或第一中间孔36的侧壁刻穿，从而使得位线20和/或与位线20接触暴露。
需要说明的是，第一保护层80可以沿第一中间孔36的周向方向设置一整周，也可以沿第一中间孔36的周向不连续。示例性的，第一保护层80包括多个保护块，多个保护块沿第一中间孔36的周向间隔排布，且各个保护块均与衬底10相接触。
以下对在第一中间孔36内形成第一保护层80的过程进行详述。
首先，在第一中间孔36内以及支撑层30表面形成第一填充层50，以形成图17所示结构。具体的，可以通过原子层沉积工艺(Atomic Layer Deposition，简称ALD)形成覆盖第一中间孔36和支撑层30的第一填充层50。原子层沉积过程中，气体可以为二(异丙氨基)硅烷LTO520/O2或者双(二乙氨基)硅烷N zero/O2。第一填充层50的高度高于支撑层30的高度，第一填充层50的材质可以为氧化硅。
然后，去除支撑层30表面上以及第一中间孔36内的部分第一填充层50，形成第一保护层80。具体的，该过程包括：
参照图18至图21，去除第一中间孔36中的部分第一填充层50，以暴露出部分第一中间孔36的侧壁。
示例性的，可以通过机械化学研磨去除支撑层30的表面上的第一填充层50，研磨至露出支撑层30的表面为止，即将位于支撑层30的上表面之上的第一填充层50去除，形成图18所示结构。
示例性的，可以通过刻蚀去除位于第一中间孔36中的部分第一填充层50，形成图19至图21所示结构，去除的第一填充层50的高度为第一中间孔36整个侧壁高度的1/5至1/4，即暴露出的第一中间孔36的侧壁高度占第一中间孔36整个侧壁高度的1/5至1/4。
参照图22，在去除第一中间孔36中的部分第一填充层50，以暴露出部分第一中间孔36的侧壁之后，在第一中间孔36中形成第二填充层60，覆盖暴露出的第一中间孔36的侧壁和剩余第一填充层50的顶部，在第二填充层60中形成第二中间孔61。
具体的，参照图22，在第一中间孔36的侧壁、第一填充层50的上表面以及支撑层30的上表面形成第二填充层60。第二填充层60可以通过沉积形成，第二填充层60的材质可以与第一填充层50的材质相同，例如均为氧化硅材质。
位于第一中间孔36的第二填充层60形成第二中间孔61，即以平行于衬底10的表面为平面，第二中间孔61的截面积小于第一中间孔36的截面积。
示例性的，第二中间孔61的截面积小于或者等于第一中间孔36的截面积的3/4。如此设置，在后续去除第一填充层50时，由于第二填充层60的厚度较小，位于第一中间孔36的侧壁上的第二填充层60也会被刻蚀掉，一方面可以减小第一中间孔36的侧壁的刻蚀影响，另一方面可以使得位于第一中间孔36中的导线70具有较大的截面积，减小对导线70导电性能的影响。
参照图23至图28，在第一中间孔36中形成第二填充层60，覆盖暴露出的第一中间孔36的侧壁和剩余第一填充层50的顶部，在第二填充层60中形成第二中间孔61之后，去除第二填充层60和部分第一填充层50，直至暴露出衬底10，留下的第一填充层50形成第一保护层80。
需要说明的是，在第一中间孔36中形成第二填充层60，覆盖暴露出的第一中间孔36的侧壁和剩余第一填充层50的顶部，在第二填充层60中形成第二中间孔61之后，在去除第二填充层60和部分第一填充层50，直至暴露出 衬底10，留下的第一填充层50形成第一保护层80之前，还包括去除位于支撑层30上的第二填充层60和位于第二中间孔36孔底的第二填充层60，形成图23至图25所示的结构，以暴露第一填充层50，便于沿第二中间孔61去除第一填充层50。
以第一中间孔36的截面形状为矩形为例，去除第二填充层60和部分第一填充层50，直至暴露出衬底10，留下的第一填充层50形成第一保护层80包括：
沿第一中间孔36去除第二填充层60的同时，沿第二中间孔61去除第一填充层50的第一部分；去除第一填充层50的第二部分，直至暴露出衬底10，第一填充层50中剩余的第三部分构成第一保护层80，形成图26至图28所示的结构。
示例性的，沿第一中间孔36去除第二填充层60时，沿第二中间孔61去除第一填充层50中与第二中间孔61正对的部分，该部分为第一填充层50的第一部分，第一部分的高度与去除的第二填充层60的高度相一致。可以理解的是，第一填充层50未暴露衬底10，第一填充层50的第一部分去除后，第一填充层50形成有与第一中间孔36相贴合的凸出部。
继续去除第一填充层50，直至暴露出衬底10。在此过程中，沿第二中间孔61去除剩余的第一填充层50中与第二中间孔61正对的部分，并沿第一中间孔36去除第一填充层50的部分凸出部，第一填充层50中的该部分与该部分凸出部为第一填充层50的第二部分。
第一填充层50去除第二部分后，第一填充层50中的位于第一中间孔36中每相邻的两个侧壁之间的部分保留，该部分为第一填充层50的第三部分。第三部分可以为多个第一保护层分块，每个第一保护层分块连接第一中间孔36中相邻的两个侧壁。可以理解的是，各第一保护层分块对应分布在第一中间孔36的各拐角处，这些第一保护层分块共同构成第一保护层80。
第一填充层50的第一部分和第二部分可以通过干法刻蚀去除。第一部分和第二部分刻蚀后，第一填充层50中形成刻蚀孔51，刻蚀孔51连通部分衬底10及有源区11。刻蚀孔51的侧壁包括第一填充层50的内侧面以及部分第一中间孔36的内壁，由于第一填充层50具有较大的刻蚀深度，随着刻蚀时 间的增加，第一填充层50的内侧面形成弧面，即第一中间孔36中两个相邻的侧壁之间通过第一保护层80圆角过渡，形成如图26所示的结构。
第一中间孔36和刻蚀孔51形成阶梯结构，后续在第一中间孔36和刻蚀孔51中形成导线70时，位于第一中间孔36中的导线70截面积较大，可以减小导线70的电阻。
S105、沿刻蚀孔51对暴露在刻蚀孔51内的衬底10及有源区11进行刻蚀，形成接触凹槽12。
参照图29至图31，沿刻蚀孔51对衬底10及有源区11进行刻蚀，形成接触凹槽12，接触凹槽12的部分侧面和底面为有源区11，具体的，为第二接触区112。接触凹槽12的深度越深，有源区11中的第二接触区112露出的表面积越大，填充于接触凹槽12中的导线70与有源区11的接触面积也越大，导线70与有源区11的接触电阻减小，使得导线70的导电性能较好。
可以理解的是，由于第一保护层80的存在，使得有源区11如图30所示横向击穿的可能性降低。
S106、在第一中间孔36、刻蚀孔51，以及接触凹槽12内形成用于电连接有源区11的导线70。
参照图32和图33，导线70的材质可以为多晶硅，通过在第一中间孔36、刻蚀孔51和接触凹槽12中沉积形成。
需要说明的是，第一保护层80的材质通常为氧化物，支撑层30的材质通常为氮化物，在步骤S105沿刻蚀孔51对暴露在刻蚀孔51内的衬底10及有源区11进行刻蚀，形成接触凹槽12之前，还包括：对第一保护层80进行氮化处理，以使第一保护层80的材质与支撑层30的材质相同，从而使得第一保护层80和支撑层30可以形成一个整体。
具体的，对第一保护层80可以进行等离子氮化处理，例如，以NH3作为等离子氮化气体，等离子强度为600～2000W，氮化处理的温度为600～800℃，氮化处理的压力为1～10pa。
需要说明的是，当衬底10的材质为氧化硅，有源区11的材质为硅时，对第一保护层80进行氮化处理时，部分衬底10及有源区11也会发生转换，即衬底10和有源区11中，与刻蚀孔51相对应的部分也转换为氮化硅，如图 34中虚线所示的转化区域A为转化后的氮化硅区域。后续沿刻蚀孔51刻蚀时，转化区域A会被去除。
本申请实施例提供的存储器的制作方法中，提供包括有源区11的衬底10，然后在衬底10上形成与部分有源区11相接触的位线20和覆盖位线20及衬底10的支撑层30，支撑层30设有贯穿支撑层30并延伸至有源区11的第一中间孔36；通过在第一中间孔36内形成第一保护层80，使得沿第一保护层80内且与衬底10相通的刻蚀孔51对暴露在刻蚀孔51内的衬底10及有源区11进行刻蚀，形成接触凹槽12时，接触凹槽12的侧壁不易被刻穿，后续在第一中间孔36、刻蚀孔51以及接触凹槽12内形成用于电连接有源区11的导线70后，可以避免导线70与位线20直接导通，进而提高了存储器的成品率。
实施例二
参照图29至图33，本申请实施例提供一种存储器。图32为本申请实施例中的存储器的结构示意图。
存储器包括衬底10、位线20、支撑层30以及第一保护层80。其中，衬底10包括有源区11，有源区11可以包括与位线20电连接的第一接触区111和与导线70电连接的第二接触区112，第一接触区111位于有源区11的中间部位，第二接触区112位于有源区11的两端部。
位线20位于衬底10上，且与部分有源区11接触。例如，位线20可以为导电材料，与有源区11中的第一接触区111电接触。具体的，位线20包括与靠近衬底10的第一分体21和与第一分体21相接触的第二分体22，第一分体21的材质可以为氮化钛(TiN)。第二分体22的材质可以为钨(W)。
为了提高存储器的存储密度和存储效率，有源区11的数量可以有多个，位线20的数量可以有多条。一条位线20穿过数个有源区11中的第一接触区111，每个有源区11至多接触一条位线20，示例性的，多条位线20平行设置，多个有源区11平行设置，位线20在衬底10的上表面的正投影与有源区11在衬底10的上表面的正投影之间倾斜设置。
支撑层30覆盖在位线20与衬底10上，支撑层30通常为绝缘材质，支撑层30设有贯穿支撑层30的导线孔，以容纳导线70。导线70可以延伸至衬 底10中，并与部分有源区11接触，例如与有源区11中的第二接触区112相接触。导线孔与位线20之间具有间隔，从而使得导线70与位线20之间不直接导通。
具体的，沿垂直于衬底10的方向，导线孔由上至下包括依次连通的第一中间孔36、刻蚀孔51和接触凹槽12。第一中间孔36和刻蚀孔51位于衬底10上的支撑层30中，且贯穿支撑层30。接触凹槽12形成于衬底10中。以平行于衬底10的表面的平面为截面，刻蚀孔51的截面积小于第一中间孔36的截面积。
第一保护层80位于导线孔的内壁且与衬底10相接触，参照图30，第一保护层80位于衬底10上，且位于导线孔的内侧面和导线70的外侧面之间，具体的，第一保护层80位于刻蚀孔51的内侧面和导线70的外侧面之间。
第一保护层80构成刻蚀孔51的至少部分内壁，示例性的，第一保护层80可以第一中间孔36的周向环绕第一中间孔36一整周，第一保护层80的内壁为刻蚀孔51的内壁。第一保护层80也可以沿第一中间孔36的周向环绕间隔设置，使得第一保护层80的内壁与第一中间孔36的内壁共同构成刻蚀孔51的内壁。
具体的，当第一中间孔36的截面形状为多边形时，第一保护层80包括多个保护块，多个保护块均与衬底10接触，每个保护块连接第一中间孔36的两个相邻的侧壁，各保护块以及第一中间孔36的侧壁形成刻蚀孔51的侧壁。保护块的侧壁与第一中间孔36的侧壁交替连接形成刻蚀孔51的侧壁。
各保护块背离与该保护块相连接的第一中间孔36的两个侧壁的表面为弧面，即各保护块朝向第一中间孔36的中心线的表面为弧面，第一中间孔36相邻的两个侧壁之间通过第一保护块的侧壁圆弧过渡，形成的刻蚀孔51的部分内壁为弧面。如此设置，在避免导线70与位线20相接触的同时，刻蚀孔51的截面积较大，以使得导线70具有较大的截面积，减小导线70的电阻。
需要说明的是，刻蚀孔51的高度可以低于第一中间孔36的高度，即刻蚀孔51的上表面低于第一中间孔36的上表面，如此设置，可以使得导线70的上部具有较大的截面积，进一步减小导线70的电阻。
本申请实施例提供的存储器中，衬底10设置有源区11，衬底10上设置 与部分有源区11相接触的位线20，位线20和衬底10上覆盖支撑层30，以对位线20进行保护和电气绝缘；支撑层30中还设置贯穿支撑层30的导线孔，导线70设置在导线孔中并延伸入衬底10中，与衬底10的有源区11相接触；通过在导线70的外侧面与导线孔的内侧面设置第一保护层80，以防止导线70与位线20直接导通，进而提高存储器的成品率。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (13)

  1. 一种存储器的制作方法，其中，包括：
    提供衬底，所述衬底包括有源区；
    在所述衬底上形成位线，所述位线覆盖部分所述有源区；
    在所述衬底上形成覆盖所述位线和所述衬底的支撑层，所述支撑层设有贯穿所述支撑层并延伸至所述有源区的第一中间孔，且所述第一中间孔与所述位线之间具有间隔；
    在所述第一中间孔内形成第一保护层，在所述第一保护层内形成有与所述衬底相通的刻蚀孔，使部分所述有源区暴露在所述刻蚀孔内；
    沿所述刻蚀孔对暴露在所述刻蚀孔内的所述衬底及所述有源区进行刻蚀，形成接触凹槽；
    在所述第一中间孔、所述刻蚀孔，以及所述接触凹槽内形成用于电连接所述有源区的导线。
  2. 根据权利要求1所述的存储器的制作方法，其中，以平行于所述衬底的平面为截面，所述第一中间孔的形状为多边形；
    在所述第一中间孔内形成第一保护层的步骤包括：
    在所述第一中间孔内以及所述支撑层的表面形成第一填充层；
    去除所述支撑层的表面上以及所述第一中间孔内的部分所述第一填充层，形成所述第一保护层。
  3. 根据权利要求2所述的存储器的制作方法，其中，去除所述支撑层的表面上以及所述第一中间孔内的部分所述第一填充层，形成所述第一保护层的步骤包括：
    去除所述第一中间孔中的部分所述第一填充层，以暴露出部分所述第一中间孔的侧壁；
    在所述第一中间孔内形成第二填充层，覆盖暴露出的所述第一中间孔的侧壁和剩余所述第一填充层的顶部，在所述第二填充层内形成第二中间孔；
    去除所述第二填充层和部分所述第一填充层，直至暴露出所述衬底，留下的所述第一填充层形成所述第一保护层。
  4. 根据权利要求3所述的存储器的制作方法，其中，去除所述第一中间孔中的部分所述第一填充层，以暴露出部分所述第一中间孔的侧壁的步骤包括：暴露出的所述第一中间孔的侧壁高度占所述第一中间孔整个侧壁高度的1/5至1/4。
  5. 根据权利要求3所述的存储器的制作方法，其中，去除所述第二填充层和部分所述第一填充层，直至暴露出所述衬底，留下的所述第一填充层形成所述第一保护层的步骤包括：
    沿所述第一中间孔去除所述第二填充层的同时，沿所述第二中间孔去除所述第一填充层的第一部分；
    去除所述第一填充层的第二部分，直至暴露出所述衬底，所述第一填充层中剩余的第三部分构成所述第一保护层。
  6. 根据权利要求5所述的存储器的制作方法，其中，去除所述第一填充层的第二部分，直至暴露出所述衬底，所述第一填充层中剩余的第三部分构成所述第一保护层包括：
    去除所述第一填充层的第二部分，直至暴露出所述衬底，保留位于所述第一中间孔中每相邻的两个侧壁之间的所述第一填充层的第三部分作为第一保护层分块，各所述第一保护层分块共同构成所述第一保护层。
  7. 根据权利要求1项所述的存储器的制作方法，其中，
    当所述第一保护层的材质包括氧化硅，所述支撑层的材质包括氮化硅时，沿所述刻蚀孔对暴露在所述刻蚀孔内的所述衬底及所述有源区进行刻蚀，形成接触凹槽之前，所述存储器的制作方法还包括：
    对所述第一保护层进行氮化处理，以使所述第一保护层的材质与所述支撑层的材质相同。
  8. 根据权利要求1所述的存储器的制作方法，其中，所述衬底上设置有多条位线；
    在所述衬底上形成覆盖所述位线和所述衬底的支撑层，所述支撑层设有贯穿所述支撑层并延伸至所述有源区的第一中间孔，且所述第一中间孔与所述位线之间具有间隔的步骤包括：
    在所述衬底上形成分别包覆于所述位线外的第一支撑垫；
    形成牺牲层填充所述第一支撑垫之间的间隙；
    在所述牺牲层中形成第一填充孔；
    在所述第一填充孔中形成第二支撑垫，所述第二支撑垫与所述第一支撑垫高度相同，共同构成所述支撑层；
    去除所述牺牲层，以形成所述支撑层中的所述第一中间孔。
  9. 根据权利要求8所述的存储器的制作方法，其中，在所述牺牲层中形成第一填充孔的步骤包括：
    在所述牺牲层上形成掩膜层；
    利用所述掩膜层对所述牺牲层进行刻蚀，以形成延伸至所述衬底的第一填充孔；
    去除所述掩膜层。
  10. 一种存储器，其中，所述存储器包括：
    衬底，所述衬底包括有源区；
    位线，所述位线位于所述衬底上，且接触部分所述有源区；
    支撑层，所述支撑层覆盖所述位线和所述衬底，所述支撑层设有贯穿所述支撑层的导线孔，所述导线孔内设有延伸入所述衬底中并与所述有源区接触的导线；
    第一保护层，所述第一保护层位于所述导线孔的内壁且位于所述衬底上。
  11. 根据权利要求10所述的存储器，其中，沿垂直于所述衬底的方向，所述导线孔包括依次连通的第一中间孔、刻蚀孔和接触凹槽；
    所述第一中间孔和所述刻蚀孔位于所述衬底上的所述支撑层中，所述接触凹槽位于所述衬底中。
  12. 根据权利要求11所述的存储器，其中，以平行于所述衬底的平面为截面，所述第一中间孔的截面形状为多边形；
    所述第一保护层构成所述刻蚀孔的至少部分内壁。
  13. 根据权利要求12所述的存储器，其中，所述刻蚀孔的至少部分内壁为弧面。
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