WO2022028109A1 - 半导体结构的制备方法 - Google Patents

半导体结构的制备方法 Download PDF

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Publication number
WO2022028109A1
WO2022028109A1 PCT/CN2021/099716 CN2021099716W WO2022028109A1 WO 2022028109 A1 WO2022028109 A1 WO 2022028109A1 CN 2021099716 W CN2021099716 W CN 2021099716W WO 2022028109 A1 WO2022028109 A1 WO 2022028109A1
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WIPO (PCT)
Prior art keywords
layer
bit line
conductive
conductive layer
semiconductor structure
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PCT/CN2021/099716
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English (en)
French (fr)
Inventor
卢经文
洪海涵
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长鑫存储技术有限公司
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Priority to US17/400,442 priority Critical patent/US11856757B2/en
Publication of WO2022028109A1 publication Critical patent/WO2022028109A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to a method for preparing a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line structure, one of the drain or source is connected to the bit line structure, and one of the drain or source is connected to the capacitor.
  • the voltage signal can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line structure, or write the data information into the capacitor through the bit line structure for storage.
  • the conductive connection method between the capacitor and the drain or source of the transistor of the DRAM is to connect through a polysilicon-metal plug.
  • the size of the polysilicon-metal plug also shrinks.
  • the electrical conductivity of the plug and its contact resistance with the drain or source become important factors affecting the electrical properties of the semiconductor structure.
  • the embodiments of the present application provide a method for fabricating a semiconductor structure, which can improve the electrical performance of the semiconductor structure.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate, the substrate including a substrate layer and a plurality of bit line structures arranged on the substrate layer along a first direction; the substrate layer includes a shallow a trench isolation structure, an active region defined by the shallow trench isolation structure, and a plurality of word line structures arranged along the second direction, the word line structures passing through the shallow trench isolation structure and the active region , the area defined by two adjacent bit line structures and two adjacent word line structures is a conductive contact area, and the conductive contact area exposes part of the active area; between the bit line structures A conductive layer is formed between the two layers, the conductive layer covers the substrate layer, and the conductive layer extends along the first direction; part of the conductive layer is removed, and the conductive layer corresponding to the conductive contact area is retained to form a first capacitor conducting wires; forming an isolation layer, and the isolation layer fills the gaps between the first capacitive conducting wires.
  • the method further includes: etching back the first capacitor wire to a predetermined depth to form a contact hole; and forming a second capacitor wire in the contact hole.
  • the method before forming a conductive layer between the bit line structures, the method further includes: forming a protective layer, the protective layer covering the surface of the bit line structure and the surface of the substrate layer; Part of the protective layer is removed, and the protective layer on the sidewall of the bit line structure remains.
  • the method before forming a conductive layer between the bit line structures, the method further includes: etching the substrate layer not covered by the bit line structures to remove part of the shallow trench isolation structure, so that the area of the active region exposed by the conductive contact region is increased.
  • removing part of the conductive layer and retaining the conductive layer corresponding to the conductive contact area to form a first capacitance wire includes: on a plane formed by the conductive layer and the bit line structure forming a patterned photoresist layer, the photoresist layer has a plurality of photoresist strips, each of the photoresist strips extending along the second direction, and the photoresist strips pass over the conductive contact areas; to The photoresist strip is a mask, and the exposed conductive layer is removed; the photoresist strip is removed to form the first capacitor wire.
  • the forming an isolation layer, and the isolation layer fills the gaps between the first capacitor wires includes: filling an isolation layer material, and the isolation layer material fills the first capacitor wires and covering the surface of the first capacitor wire and the bit line structure; removing the isolation layer material on the surface of the first capacitor wire and the bit line structure to form the isolation layer.
  • the method for forming a plurality of bit line structures arranged along a first direction on the substrate layer includes: forming a bottom plate on the substrate layer; patterning the bottom plate to form a plurality of opening a window, which exposes at least part of the active region; filling conductive material in the opening to form a bit line contact island; forming a plurality of extending along the first direction and covering part of the bottom plate and all the The bit line contacts the bit line of the island; the exposed bottom plate and a part of the substrate layer below it are removed until the active region is exposed, and the bit line structure is formed.
  • the patterning of the base plate to form a plurality of openings includes: forming a mask layer on the base plate, the mask layer has a plurality of openings, and the center of the opening is The position corresponds to the center position where the openings need to be formed; using the mask layer as a mask, the pattern of the mask layer is transferred to the base plate to form the plurality of openings.
  • the line connecting the center points of the window is coincident with the center line of the bit line.
  • the method before the conductive material is filled in the opening, the method further includes: performing over-etching on the active region exposed by the opening to form a groove; and the conductive material is filled in the opening to form the bit line contact island.
  • the forming a plurality of bit lines extending along the first direction and covering part of the bottom plate and the bit line contact islands includes: forming a plurality of bit lines on the bottom plate and the bit line contact islands The bottom conductive layer, the top conductive layer and the blocking layer are sequentially covered; the blocking layer, the top conductive layer and the bottom conductive layer are sequentially patterned to form a plurality of the bit lines extending along the first direction.
  • the advantage of the embodiments of the present application is that a conductive layer is first formed between the bit line structures, and then the conductive layer is divided to form a first capacitor wire.
  • the area of the capacitor contact hole is large, so that the contact between the deposited conductive layer and the substrate layer is more sufficient, so as to avoid the inconsistency between the first capacitor wire and the substrate layer caused by directly depositing the first capacitor wire in the capacitor contact hole in the related art.
  • a sufficient condition occurs, which in turn reduces the contact resistance and improves the electrical performance of the semiconductor structure.
  • the space of the first capacitor wire is also filled with the isolation layer, which further improves the electrical performance of the first capacitor wire.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for fabricating a semiconductor structure provided by an embodiment of the present application
  • FIGS. 2 to 19 are process flow diagrams of an embodiment of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • a method of forming a polysilicon-metal plug in the related art is to form a capacitor contact hole first, and then deposit polysilicon and a metal conductive material in the capacitor contact hole to form a polysilicon-metal plug.
  • the size of the polysilicon-metal plug is also shrinking, and the semiconductor structure using the polysilicon-metal plug has poor electrical conductivity.
  • the reason for this situation is that, on the one hand, the polysilicon will form voids during the deposition, and the voids will cause the electrical conductivity of the polysilicon-metal plug to decrease.
  • the size of the capacitor contact hole will also shrink.
  • the reduction in the size of the capacitor contact hole will make the deposited polysilicon and the active area not fully contacted, resulting in poor contact and contact resistance. increase, thereby affecting the electrical properties of the semiconductor structure.
  • the embodiments of the present application provide a method for preparing a semiconductor structure, which can avoid the formation of voids in polysilicon, and can increase the contact area between polysilicon and the active region, and improve the electrical performance of the semiconductor structure.
  • FIG. 1 is a schematic diagram of steps of an embodiment of a method for fabricating a semiconductor structure provided by an embodiment of the present application. Please refer to FIG. 1.
  • the method for fabricating a semiconductor structure provided by an embodiment of the present application includes the following steps: Step S10, providing a substrate, and the The base includes a substrate layer and a plurality of bit line structures arranged on the substrate layer along a first direction; the substrate layer includes a shallow trench isolation structure, an active region defined by the shallow trench isolation structure, and a plurality of edge word line structures arranged in the second direction, the word line structures pass through the shallow trench isolation structure and the active region, two adjacent bit line structures and two adjacent word lines
  • the area defined by the structure is a conductive contact area, and the conductive contact area exposes part of the active area; step S11, a conductive layer is formed between the bit line structures, the conductive layer covers the substrate layer, and the The conductive layer extends along the first direction; in step S12, part of the conductive layer is removed, and the conductive
  • FIGS. 2 to 19 are process flow diagrams of an embodiment of a method for fabricating a semiconductor structure provided by an embodiment of the present application.
  • FIG. 3 is a top view of the structure shown in FIG. 2 , providing a substrate 100 , the substrate 100 includes a substrate layer 110 and is located on the substrate layer 110 along a first direction (X A plurality of bit line structures 120 arranged in the direction).
  • the substrate layer 110 includes a shallow trench isolation structure 111 , an active region 112 defined by the shallow trench isolation structure 111 , and a plurality of word line structures 113 arranged along the second direction (Y direction).
  • the word line structure 113 passes through the shallow trench isolation structure 111 and the active region 112 , and the area defined by two adjacent bit line structures 120 and two adjacent word line structures 113 For the conductive contact area A, the conductive contact area A exposes a portion of the active area 112 .
  • the bit line structure 120 includes a bit line 120A and a plurality of bit line contact islands 120B, the bit line contact islands 120B are insulated from each other, and the bit line 120A is connected to the active region through the bit line contact islands 120B 112 is electrically connected. It can be understood that the number of the bit line structures 120 is not limited to this, and can be set by those skilled in the art according to actual requirements.
  • the method for forming the active region 112 is to form a trench in a silicon substrate, and form a shallow trench isolation structure 111 in the trench, and the shallow trench isolation structure 111 isolates the silicon lining The bottom serves as the active region 112 .
  • the shallow trench isolation structure 111 may be formed by deposition of materials such as silicon oxide, nitride, and the like.
  • the word line structure 113 includes a word line 113A and a passivation layer 113B covering the word line 113A, the passivation layer 113B is exposed on the surface of the substrate layer 110 , and part of the passivation layer 113B is covered by The word line structures 120 cover. It can be understood that the number of the word line structures 113 is not limited to this, and can be set by those skilled in the art according to actual needs.
  • the bit line structure 120 extends in the first direction (X direction), the word line structure 113 extends in the second direction (Y direction), and passes through the shallow trench isolation structure 111 and the active District 112.
  • the first direction is perpendicular to the second direction. It can be understood that the present application is not limited to this. In other embodiments, the first direction may be perpendicular to the second direction. Set at a non-90 degree angle.
  • the portion of the word line structure 113 passing through the active region serves as the gate of a metal oxide semiconductor (MOS) transistor, and the active region 112 corresponding to the bit line structure 120 As the source or drain of the MOS transistor, the active region 112 corresponding to the conductive contact region A acts as the drain or source of the MOS transistor.
  • MOS metal oxide semiconductor
  • the preparation method further includes the following steps:
  • a protective layer material 400 is formed, and the protective layer material 400 covers the surface of the bit line structure 120 and the surface of the substrate layer 110 .
  • the protective layer material 400 can be formed by an atomic layer deposition process (Atomic Layer Deposition, ALD).
  • ALD atomic Layer Deposition
  • the protective layer material 400 formed by the atomic layer deposition process has a dense structure and can play a good isolation role.
  • the protective layer material 400 can be a silicon nitride layer, and in other embodiments, the protective layer material 400 can be a silicon nitride-silicon oxide-silicon nitride composite layer.
  • part of the protective layer material 400 is removed, and the protective layer 401 on the sidewall of the bit line structure 120 remains.
  • the protection layer 401 can isolate the bit line 120A from the outside, and protect the bit line 120A from being oxidized.
  • the substrate layer 110 not covered by the bit line structure 120 may be etched to remove part of the shallow trench isolation structure 111, so that all the conductive contact region A is exposed.
  • the area of the active region 112 increases, thereby increasing the contact area between the first capacitor wire and the active region 112 to be subsequently formed, thereby reducing the contact resistance.
  • part of the protective layer material 400 is removed by etching until the surface of the substrate layer 110 is exposed, and then, referring to FIG. 6 , the shallow trench isolation structure 111 is over-etched to make the word line structure 113 and the active region 112 are highlighted, so that the area of the active region 112 exposed by the conductive contact region A is increased.
  • an etching solution whose etching rate for the shallow trench isolation structure 111 is higher than the etching rate for the word line structure 113 and the active region 112 can be selected, so that this step mainly removes the shallow trench isolation structure 111, the word line structure 113 and the active region 112 are reserved.
  • the substrate layer not covered by the bit line structure may be directly etched on the structure formed in step S10 to remove part of the shallow trench isolation structure 111 .
  • a conductive layer 130 is formed between the bit line structures 120 , the conductive layer 130 covers the substrate layer 110 , and the conductive layer 130 is along the first direction (X direction) extend. Since the bit line structures 120 extend along the first direction (X direction), the space between the bit line structures 120 also extends along the first direction (X direction), so that the formed conductive layer 130 also extends along the first direction (X direction) extension.
  • the conductive layer 130 may be formed by depositing a conductive material through a low-pressure chemical vapor deposition (Low-pressure Chemical Vapor Deposition, LPCVD) process.
  • the conductive layer 130 includes, but is not limited to, a polysilicon layer.
  • the conductive material in order to make the conductive layer 130 fill the area between the bit line structures 120, when the conductive layer is formed, the conductive material is not only filled between the bit line structures 120, but also covers the bit line structures. 120 top surface. After the conductive material is filled, a part of the conductive material is removed by etching and other methods until the top surface of the bit line structure 120 is exposed, so that the top surface of the conductive layer 130 is flat with the top surface of the bit line structure 120 together.
  • step S12 part of the conductive layer 130 is removed, and the conductive layer corresponding to the conductive contact area A is retained to form the first capacitor wire 140 .
  • the method for removing part of the conductive layer 130 is:
  • a patterned photoresist layer 800 is formed on the plane formed by the conductive layer 130 and the bit line structure 120.
  • the photoresist layer 800 has a plurality of photoresist strips 801, each of which The resist strips 801 extend along the second direction (Y direction), and the photoresist strips 801 pass over the conductive contact area A. As shown in FIG. It should be noted that only a limited number of photoresist strips 801 are shown in FIG. 8 . It can be understood that the number of photoresist strips 801 is not limited to this, and those skilled in the art can set them according to actual needs. In this step, the photoresist strip 801 blocks the area of the conductive layer 130 that needs to be retained later, and the area of the conductive layer 130 that needs to be removed later is exposed.
  • the exposed conductive layer 130 is removed. After the conductive layer 130 is removed, the substrate layer 110 is exposed. In this step, the conductive layer 130 shielded by the photoresist strip 801 is reserved as the first capacitor wire 140 . It can be understood that when the conductive layer 130 is removed, the top layer of the bit line 120A will also be partially removed due to the effect of the etching solution (not shown in the drawings). The top layer may be a silicon nitride layer. After the exposed conductive layer 130 is removed, the photoresist strip 801 is also removed to form the first capacitor wire 140 .
  • FIG. 10 is a schematic side view of C of the structure shown in FIG. 9 .
  • the gap will affect the electrical properties of the conductive layer 130 .
  • the gap is also generated when the conductive layer is deposited.
  • the conductive layer is directly used as a capacitor wire in the subsequent process, it will not be deeply treated, so that the gap always exists.
  • part of the conductive layer 130 will be removed (as shown in FIG. 9 ), and the void B will be exposed, which can be processed to eliminate the void B.
  • an isolation layer 150 is formed, and the isolation layer 150 fills the gaps between the first capacitor wires 140 .
  • the method for forming the isolation layer 150 includes the following steps:
  • FIG. 12 is a schematic side view of C of the structure shown in FIG. 11 .
  • the isolation layer material 900 is filled, and the isolation layer material 900 fills the gaps between the first capacitor wires 140 and covers Surfaces of the first capacitor wire 140 and the bit line structure 120 .
  • the isolation layer material 900 will be filled in the gap B, so as to eliminate the gap B, and when the first capacitor wire 140 is subsequently etched back, there will be no problem.
  • the gap B will increase, thereby improving the electrical performance of the first capacitor wire 140 .
  • the isolation layer material 900 can be deposited by using the atomic layer deposition technology, and the formed isolation layer material 900 has a dense structure and good isolation performance.
  • the isolation layer material 900 may be an insulating material such as silicon nitride.
  • the isolation layer material on the surface of the first capacitor wire 140 and the bit line structure 120 is removed to form the isolation layer 150 , and the isolation layer 150 serves as an isolation structure between the first capacitor wires 140 .
  • the first capacitor wire 140 and the bit line structure 120 are exposed.
  • the preparation method of the semiconductor structure further includes the following steps:
  • the first capacitor wire 140 is etched back to a predetermined depth to form a contact hole. In this step, since the space B of the first capacitor wire 140 is filled with the isolation layer 150, the space B will not be enlarged due to etching.
  • a second capacitor wire is formed in the contact hole.
  • the second capacitor wire has a conventional structure and may include multiple metal conductive layers, which will not be repeated here.
  • a conductive layer is first formed between the bit line structures, and then the conductive layer is divided to form a first capacitor wire. Since the area of the space between the bit line structures is relatively small The area of the capacitor contact hole in the related art is large, so that the contact between the deposited conductive layer and the substrate layer is more sufficient, so that the first capacitor wire and the lining caused by directly depositing the first capacitor wire in the capacitor contact hole in the related art can be avoided. Insufficient contact of the bottom layer occurs, thereby reducing the contact resistance and improving the electrical performance of the semiconductor structure. In addition, the space of the first capacitor wire is also filled with the isolation layer, which improves the electrical performance of the first capacitor wire.
  • a plurality of bit line structures 120 are arranged along the first direction (X direction) on the substrate layer 110 of the semiconductor structure of the present application.
  • the fabrication method of the semiconductor structure of the present application also provides an embodiment of forming the bit line structure 120 .
  • the specific description is as follows.
  • a substrate layer 110 is provided, and a bottom plate 200 is formed on the substrate layer 110 .
  • the base plate 200 may be a nitride layer or an oxide layer.
  • the base plate 200 may be formed by chemical vapor deposition, and the base plate 200 covers the substrate layer 110 .
  • FIGS. 15 and 16 wherein FIG. 15 is a schematic side view C of the structure after the three-dimensional view shown in FIG. 14 is patterned, and FIG. 16 is a top view of the structure after the three-dimensional view shown in FIG. 14 is patterned.
  • the bottom plate 200 is formed with a plurality of openings 201 , and the openings 201 expose at least part of the active region 112 .
  • the opening 201 also exposes part of the top surface of the bit line structure 112 and part of the top surface of the shallow trench isolation structure 111 .
  • a patterned photoresist layer can be used as a mask to form the opening 201 .
  • a mask layer is formed on the bottom plate 200, the mask layer has a plurality of openings, and the center positions of the openings correspond to the center positions of the openings 201 to be formed; The pattern of the mask layer is transferred to the base plate 200 to form the opening 201 .
  • the active region 112 exposed by the opening 201 is over-etched, so that the height of the top surface of the active region 112 is smaller than that of the shallow trench isolation structure
  • the height of the top surface of 111 forms the groove 202 .
  • the formation of the grooves 202 can enable the subsequently formed bit line contact islands 120B to have better contact performance with the active regions 112 .
  • conductive material is filled in the openings 201 to form bit line contact islands 120B.
  • the conductive material is polysilicon.
  • the method of filling the conductive material may be LPCVD, and the reactive gas may be 2-propyl nitrogen silane (H 3 SiN(C 3 H 7 ) 2 )/disilane (Si 2 H 6 )/3-dimethylaminosilicon hydride (SiH[N(CH 3 ) 2 ] 3 ), the reaction temperature may be 380° C. ⁇ 500° C., and the reaction gas pressure may be 1 (Torr, Torr) ⁇ 3 Torr.
  • a conductive material is also deposited in the groove 202 , and the groove 202 can limit the conductive material, so that the formed bit line contact island 120B is in closer contact with the active region 112 .
  • bit lines extending along the first direction and covering part of the bottom plate and the bit line contact island are formed.
  • the bottom conductive layer 300 , the top conductive layer 310 and the barrier layer 320 are sequentially covered on the bottom plate 200 and the bit line contact islands 120B.
  • the bottom conductive layer 300 can be metal titanium nitride
  • the top conductive layer 310 can be metal tungsten
  • the barrier layer 320 can be silicon nitride.
  • the barrier layer 320 , the top conductive layer 310 and the bottom conductive layer 300 are sequentially patterned to form a plurality of bit lines 120A extending along the first direction (X direction).
  • the bit lines 120A are arranged at equal intervals. Wherein, in the first direction (X direction), the connection between the center points of the window 201 and the center line of the bit line 120A overlap, so that the bit line 120A and the bit line can contact the island 120B.
  • the contact area is maximized and the electrical conductivity of the bit line structure 120 is improved.
  • the exposed bottom plate 200 and a portion of the substrate layer 110 thereunder are removed by an etching process until the active region 112 is exposed, so as to form the bit line structures 120 (eg, shown in Figure 2).

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Abstract

本申请实施例提供一种半导体结构的制备方法，包括：提供基底，所述基底包括衬底层及位于所述衬底层上、沿第一方向排列的多条位线结构；所述衬底层包括浅沟槽隔离结构、所述浅沟槽隔离结构限定的有源区及多条沿第二方向排列的字线结构，所述字线结构穿过所述浅沟槽隔离结构及所述有源区，相邻的两条所述位线结构与相邻的两条所述字线结构限定的区域为导电接触区，所述导电接触区暴露部分所述有源区；在所述位线结构之间形成导电层，所述导电层覆盖所述衬底层，且所述导电层沿所述第一方向延伸；去除部分所述导电层，保留所述导电接触区对应的导电层，形成第一电容导线；形成隔离层，所述隔离层填充所述第一电容导线之间的空隙。

Description

半导体结构的制备方法
相关申请的交叉引用
本申请基于申请号为202010771964.1、申请日为2020年8月4日、发明名称为“半导体结构的制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体制造领域，尤其涉及一种半导体结构的制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线结构相连、漏极或源极其中之一与位线结构相连、漏极或源极其中之一与电容器相连，字线结构上的电压信号能够控制晶体管的打开或关闭，进而通过位线结构读取存储在电容器中的数据信息，或者通过位线结构将数据信息写入到电容器中进行存储。
电容器与DRAM的晶体管的漏极或源极之间的导电连接方法为通过多晶硅-金属插栓连接，当半导体存储器件制程微缩时，多晶硅-金属插栓的尺寸也随之微缩，多晶硅-金属插栓的导电性能及其与漏极或源极的接触电阻成为影响半导体结构的电学性能的重要因素。
发明内容
本申请实施例提供一种半导体结构的制备方法，能够提高半导体结构的电学性能。
本申请实施例提供了一种半导体结构的制备方法，包括：提供基底，所述基底包括衬底层及位于所述衬底层上沿第一方向排列的多条位线结构；所述衬底层包括浅沟槽隔离结构、所述浅沟槽隔离结构限定的有源区及多条沿第二方向排列的字线结构，所述字线结构穿过所述浅沟槽隔离结构及所述有源区，相邻的两条所述位线结构与相邻的两条所述字线结构限定的区域为导电接触区，所述导电接触区暴露部分所述有源区；在所述位线结构之间形成导电层，所述导电层覆盖所述衬底层，且所述导电层沿所述第一方向延伸；去除部分所述导电层，保留所述导电接触区对应的导电层，形成第一电容导线；形成隔离层，所述隔离层填充所述第一电容导线之间的空隙。
在本申请的一些实施例中，在形成隔离层之后，所述方法还包括：回刻所述第一电容导线至预设深度，形成接触孔；在所述接触孔内形成第二电容导线。
在本申请的一些实施例中，在所述位线结构之间形成导电层之前，所述方法还包括：形成保护层，所述保护层覆盖所述位线结构表面及所述衬底层表面；去除部分所述保护层，保留位于所述位线结构侧壁的保护层。
在本申请的一些实施例中，在所述位线结构之间形成导电层之前，所述方法还包括：对未被所述位线结构覆盖的衬底层进行刻蚀，去除部分浅沟槽隔离结构，以使所述导电接触区暴露的所述有源区的面积增大。
在本申请的一些实施例中，所述去除部分导电层，保留所述导电接触区对应的导电层，形成第一电容导线，包括：在所述导电层及所述位线结构构成的平面上形成图形化的光阻层，所述光阻层具有多个光阻条，每一所述光阻条沿所述第二方向延伸，且所述光阻条经过所述导电接触区上方；以所述光阻条为掩膜，去除暴露的所述导电层；去除所述光阻条，形成所述第一电容导线。
在本申请的一些实施例中，所述形成隔离层，所述隔离层填充所述第 一电容导线之间的空隙，包括：填充隔离层材料，所述隔离层材料填充所述第一电容导线之间的空隙，并覆盖所述第一电容导线及所述位线结构的表面；去除所述第一电容导线及所述位线结构表面的隔离层材料，形成所述隔离层。
在本申请的一些实施例中，在所述衬底层上形成沿第一方向排列的多条位线结构的方法，包括：在所述衬底层上形成底板；图形化所述底板，形成多个开窗，所述开窗至少暴露出部分所述有源区；在所述开窗中填充导电材料，形成位线接触岛；形成多个沿第一方向延伸，且覆盖部分所述底板及所述位线接触岛的位线；去除暴露的底板及其下方部分衬底层，至暴露出有源区停止，形成所述位线结构。
在本申请的一些实施例中，所述图形化所述底板，形成多个开窗，包括：在所述底板上形成掩膜层，所述掩膜层具有多个开口，所述开口的中心位置与需要形成开窗的中心位置对应；以所述掩膜层为掩膜，将所述掩膜层的图形转移到所述底板上，以形成所述多个开窗。
在本申请的一些实施例中，在第一方向上，所述开窗的中心点连线与所述位线的中心线重合。
在本申请的一些实施例中，在所述开窗中填充导电材料之前，所述方法还包括：对所述开窗暴露的有源区进行过刻蚀，形成凹槽；在所述凹槽及所述开窗内填充所述导电材料，形成所述位线接触岛。
在本申请的一些实施例中，所述形成多个沿第一方向延伸，且覆盖部分所述底板及所述位线接触岛的位线，包括：在所述底板及所述位线接触岛上依次覆盖底层导电层、顶层导电层及阻挡层；依次图形化所述阻挡层、所述顶层导电层及所述底层导电层，形成多个沿所述第一方向延伸的所述位线。
本申请实施例的优点在于，先在所述位线结构之间形成导电层，再对导电层进行分割形成第一电容导线，由于所述位线结构之间间隔的区域的 面积较相关技术中的电容接触孔的面积大，使得沉积的导电层与衬底层的接触更充分，从而能够避免相关技术中直接在电容接触孔中沉积第一电容导线而造成的第一电容导线与衬底层接触不充分的情况发生，进而减小了接触电阻，提高了半导体结构的电学性能。另外，所述第一电容导线的空隙也会被隔离层填充，进一步提高了第一电容导线的电学性能。
附图说明
图1是本申请实施例提供的半导体结构的制备方法的一实施例的步骤示意图；
图2～图19是本申请实施例提供的半导体结构的制备方法的一实施例的工艺流程图。
具体实施方式
下面结合附图对本申请实施例提供的半导体结构的制备方法的实施例做详细说明。
相关技术中形成多晶硅-金属插栓的方法是，先形成电容接触孔，再在所述电容接触孔内沉积多晶硅及金属导电材料，以形成多晶硅-金属插栓。然而，随着半导体存储器件制程的微缩，多晶硅-金属插栓的尺寸也随之微缩，采用多晶硅-金属插栓的半导体结构的导电性能不好。经研究发现，造成该种情况的原因，一方面是，多晶硅在沉积时内部会形成空隙，空隙会导致多晶硅-金属插栓的导电性能下降，且随着多晶硅-金属插栓尺寸的微缩，空隙对导电性能的影响越来越明显；另一方面是，电容接触孔的尺寸也会微缩，电容接触孔尺寸的缩小使得沉积的多晶硅与有源区不会完全接触，造成接触不良，导致接触电阻增加，从而影响半导体结构的电学性能。
基于相关技术中存在的上述问题，本申请实施例提供一种半导体结构 的制备方法，能够避免多晶硅内部形成空隙，且能够提高多晶硅与有源区的接触面积，提高半导体结构的电学性能。
图1是本申请实施例提供的半导体结构的制备方法的一实施例的步骤示意图，请参阅图1，本申请实施例提供的半导体结构的制备方法包括如下步骤：步骤S10，提供基底，所述基底包括衬底层及位于所述衬底层上沿第一方向排列的多条位线结构；所述衬底层包括浅沟槽隔离结构、所述浅沟槽隔离结构限定的有源区及多条沿第二方向排列的字线结构，所述字线结构穿过所述浅沟槽隔离结构及所述有源区，相邻的两条所述位线结构与相邻的两条所述字线结构限定的区域为导电接触区，所述导电接触区暴露部分所述有源区；步骤S11，在所述位线结构之间形成导电层，所述导电层覆盖所述衬底层，且所述导电层沿所述第一方向延伸；步骤S12，去除部分所述导电层，保留所述导电接触区对应的导电层，形成第一电容导线；步骤S13，形成隔离层，所述隔离层填充所述第一电容导线之间的空隙。
图2～图19是本申请实施例提供的半导体结构的制备方法的一实施例的工艺流程图。
请参阅步骤S10、图2及图3，其中，图3为图2所示结构的俯视图，提供基底100，所述基底100包括衬底层110及位于所述衬底层110上沿第一方向(X方向)排列的多条位线结构120。所述衬底层110包括浅沟槽隔离结构111、所述浅沟槽隔离结构111限定的有源区112及多条沿第二方向(Y方向)排列的字线结构113。所述字线结构113穿过所述浅沟槽隔离结构111及所述有源区112，相邻的两条所述位线结构120与相邻的两条所述字线结构113限定的区域为导电接触区A，所述导电接触区A暴露部分所述有源区112。
在图2及图3中示意性绘示三条位线结构120。其中，所述位线结构120包括位线120A及多个位线接触岛120B，所述位线接触岛120B彼此 绝缘，所述位线120A通过所述位线接触岛120B与所述有源区112电连接。可以理解的是，所述位线结构120的数量不限于此，本领域技术人员可根据实际需求设置。
在本申请实施例中，形成有源区112的方法为，在一硅衬底中形成沟槽，在沟槽中形成浅沟槽隔离结构111，所述浅沟槽隔离结构111隔离的硅衬底作为所述有源区112。所述浅沟槽隔离结构111可采用硅氧化物、氮化物等材料沉积而成。
在图2及图3中示意性绘示五条字线结构113。其中，所述字线结构113包括字线113A及覆盖所述字线113A的钝化层113B，所述钝化层113B暴露于所述衬底层110的表面，且部分所述钝化层113B被所述字线结构120覆盖。可以理解的是，所述字线结构113的数量不限于此，本领域技术人员可根据实际需求设置。
其中，所述位线结构120在第一方向(X方向)延伸，所述字线结构113在第二方向(Y方向)延伸，并穿过所述浅沟槽隔离结构111及所述有源区112。在本申请实施例中，所述第一方向与所述第二方向垂直，可以理解的是，本申请并不限于此，在其它实施例中，所述第一方向可与所述第二方向呈一非90度角设置。
在所述基底100中，所述字线结构113穿过有源区的部分作为金属氧化物半导体(Metal Oxide Semiconductor，MOS)管的栅极，与所述位线结构120对应的有源区112作为MOS管的源极或者漏极，与所述导电接触区A对应的有源区112作为MOS管的漏极或源极。
在一些实施例中，在步骤S10后，所述制备方法还包括如下步骤：
请参阅图4，形成保护层材料400，所述保护层材料400覆盖所述位线结构120表面及所述衬底层110表面。可采用原子层沉积工艺(Atomic Layer Deposition，ALD)形成所述保护层材料400，原子层沉积工艺形成的保护层材料400结构致密，能够起到良好的隔离作用。在本申请实施例 中，所述保护层材料400可为氮化硅层，而在其它实施例中，所述保护层材料400可为氮化硅-氧化硅-氮化硅复合层。
请参阅图5，去除部分所述保护层材料400，保留位于所述位线结构120侧壁的保护层401。所述保护层401能够将所述位线120A与外界隔离，保护所述位线120A不被氧化。
在一些实施例中，在步骤S10之后，可对未被所述位线结构120覆盖的衬底层110进行刻蚀，去除部分浅沟槽隔离结构111，以使所述导电接触区A暴露的所述有源区112的面积增大，进而增大后续形成第一电容导线与所述与有源区112的接触面积，从而减小接触电阻。在本申请实施例中，刻蚀去除部分所述保护层材料400至暴露出衬底层110的表面停止，随后，请参阅图6，对浅沟槽隔离结构111进行过刻蚀，使得字线结构113及所述有源区112凸显，进而使所述导电接触区A暴露的所述有源区112的面积增大。在该步骤中，可选择对浅沟槽隔离结构111的刻蚀速率大于对字线结构113及所述有源区112的刻蚀速率的刻蚀溶液，使得该步骤主要去除浅沟槽隔离结构111，所述字线结构113及所述有源区112被保留。在其他实施例中，若不形成所述保护层401，则可直接在步骤S10形成的结构上对未被所述位线结构覆盖的衬底层进行刻蚀，去除部分浅沟槽隔离结构111。
请参阅步骤S11及图7，在所述位线结构120之间形成导电层130，所述导电层130覆盖所述衬底层110，且所述导电层130沿所述第一方向(X方向)延伸。由于所述位线结构120沿第一方向(X方向)延伸，则所述位线结构120之间的间隔也沿第一方向(X方向)延伸，使得形成的导电层130也沿第一方向(X方向)延伸。
在该步骤中，可通过低压力化学气相沉积(Low-pressure Chemical Vapor Deposition，LPCVD)工艺沉积导电材料，形成所述导电层130。所述导电层130包括但不限于多晶硅层。
可以理解的是，为了使所述导电层130能够充满所述位线结构120之间的区域，在形成导电层时，导电材料不仅填充在位线结构120之间，还覆盖所述位线结构120的顶面。在填充导电材料之后，再采用刻蚀等方法去除部分导电材料，直至暴露出所述位线结构120的顶面，使所述导电层130的顶面与所述位线结构120的顶面平齐。
请参阅步骤S12、图8及图9，去除部分导电层130，保留所述导电接触区A对应的导电层，形成第一电容导线140。
在该步骤中，去除部分导电层130的方法为：
请参阅图8，在所述导电层130及所述位线结构120构成的平面上形成图形化的光阻层800，所述光阻层800具有多个光阻条801，每一所述光阻条801沿所述第二方向(Y方向)延伸，且所述光阻条801经过所述导电接触区A上方。需要说明的是，图8中只是绘示了有限个数的光阻条801，可以理解的是，光阻条801的个数不限于此，实际本领域技术人员可根据实际需求设置。在该步骤中，所述光阻条801遮挡后续需要保留的导电层130区域，而后续需要去除的导电层130区域被暴露。
请参阅图9，以所述光阻条801为掩膜，去除暴露的所述导电层130，所述导电层130被去除后，暴露出衬底层110。在该步骤中，被所述光阻条801遮挡的导电层130被保留，作为第一电容导线140。可以理解的是，在去除所述导电层130时，由于刻蚀液的作用，所述位线120A的顶层也会被部分去除(附图中未绘示)，其中，所述位线120A的顶层可为氮化硅层。在去除暴露的所述导电层130后，所述光阻条801也被去除，形成所述第一电容导线140。
在沉积形成所述导电层130时，由于沉积工艺限制，在所述导电层130中会形成空隙。请参阅图10，图10为图9所示结构的C侧面示意图，在导电层130中存在空隙B，该空隙会影响导电层130的电学性能。在相关技术中，沉积导电层时也会产生该空隙，而由于后续工艺直接将导电层 作为电容导线，不会对其进行深度处理，使得该空隙一直存在，而在本申请的制备方法中，形成导电层130后，会去除部分导电层130(如图9所示步骤)，则所述空隙B会暴露，能够对其进行处理，以消除空隙B。
请参阅步骤S13、图11、图12及图13，形成隔离层150，所述隔离层150填充所述第一电容导线140之间的空隙。
在本申请实施例中，形成隔离层150的方法包括如下步骤：
请参阅图11及图12，其中，图12为图11所示结构的C侧面示意图，填充隔离层材料900，所述隔离层材料900填充所述第一电容导线140之间的空隙，并覆盖所述第一电容导线140及所述位线结构120的表面。其中，由于所述空隙B被暴露，则所述隔离层材料900会填充在所述空隙B内，从而消除所述空隙B，则在后续对第一电容导线140进行回刻处理时，也不会使空隙B增大，进而提高第一电容导线140的电学性能。本申请实施例中，可采用原子层沉积技术沉积所述隔离层材料900，形成的隔离层材料900结构致密，隔离性能好。所述隔离层材料900可为氮化硅等绝缘材料。
请参阅图13，去除所述第一电容导线140及所述位线结构120表面的隔离层材料，形成所述隔离层150，所述隔离层150作为第一电容导线140之间的隔离结构。所述第一电容导线140及所述位线结构120被暴露。
在形成隔离层150的步骤之后，所述半导体结构的制备方法还包括如下步骤：
回刻所述第一电容导线140至预设深度，形成接触孔。在该步骤中，由于所述第一电容导线140的空隙B被隔离层150填充，则空隙B不会由于刻蚀而变大。
在所述接触孔内形成第二电容导线。其中，所述第二电容导线为常规结构，可以包括多层金属导电层，在此不再赘述。
本申请实施例提供的半导体结构的制备方法先在所述位线结构之间 形成导电层，再对导电层进行分割形成第一电容导线，由于所述位线结构之间间隔的区域的面积较相关技术中的电容接触孔的面积大，使得沉积的导电层与衬底层的接触更充分，从而能够避免相关技术中直接在电容接触孔中沉积第一电容导线而造成的第一电容导线与衬底层接触不充分的情况发生，进而减小了接触电阻，提高了半导体结构的电学性能。另外，所述第一电容导线的空隙也会被隔离层填充，提高了第一电容导线的电学性能。
在一些实施例中，如图2所示，本申请半导体结构的所述衬底层110上沿第一方向(X方向)排列的多条位线结构120。本申请半导体结构的制备方法还提供了形成位线结构120的一实施例。具体说明如下。
请参阅图14，提供衬底层110，在所述衬底层110上形成底板200。所述底板200可为氮化物层或者氧化物层。在本申请实施例中，可采用化学气相沉积的方法形成所述底板200，所述底板200覆盖所述衬底层110。
请参阅图15及图16，其中，图15为对图14所示立体图进行图形化后的结构的C侧面示意图，图16为对图14所示立体图进行图形化后的结构的俯视图，图形化所述底板200，形成多个开窗201，所述开窗201至少暴露出部分所述有源区112。在该实施例中，所述开窗201还暴露出所述部分位线结构112的顶面及部分浅沟槽隔离结构111的顶面。
在该步骤中，可采用图形化的光阻层作为掩膜，形成所述开窗201。在所述底板200上形成掩膜层，所述掩膜层具有多个开口，所述开口的中心位置与需要形成开窗201的中心位置对应；以所述掩膜层为掩膜，将所述掩膜层的图形转移到所述底板200上，从而形成所述开窗201。
在一些实施例中，在形成所述开窗201后，对所述开窗201暴露的有源区112进行过刻蚀，使得所述有源区112的顶面的高度小于浅沟槽隔离结构111的顶面的高度，形成凹槽202。该凹槽202的形成可使得后续形成的位线接触岛120B与有源区112具有更好的接触性能。
请参阅图17，在所述开窗201中填充导电材料，形成位线接触岛120B。在本实施例，所述导电材料为多晶硅。填充所述导电材料的方法可为LPCVD，反应气体可为2-丙基氮硅烷(H 3SiN(C 3H 7) 2)/乙硅烷(Si 2H 6)/3-二甲氨基氢化硅(SiH[N(CH 3) 2] 3)，反应温度可为380℃～500℃，反应气压可为1(托，Torr)～3Torr。在该步骤中，所述凹槽202中也沉积了导电材料，所述凹槽202能够限位所述导电材料，使得形成的位线接触岛120B与有源区112的接触更紧密。
请参阅图18及图19，形成多个沿第一方向延伸，且覆盖部分所述底板及所述位线接触岛的位线。
请参阅图18，在所述底板200及所述位线接触岛120B上依次覆盖底层导电层300、顶层导电层310及阻挡层320。所述底层导电层300可为金属氮化钛，所述顶层导电层310可为金属钨，所述阻挡层320可为氮化硅。
请参阅图19，依次图形化所述阻挡层320、顶层导电层310及底层导电层300，形成多个沿第一方向(X方向)延伸的位线120A。所述位线120A等间距设置。其中，在第一方向(X方向)上，所述开窗201的中心点连线与所述位线120A的中心线重合，则能够使所述位线120A与所述位线接触岛120B的接触面积最大化，提高位线结构120的导电性能。
采用刻蚀工艺去除暴露的底板200及其下方部分衬底层110，至暴露出有源区112停止，以形成位于所述衬底层110上的沿第一方向排列的所述位线结构120(如图2所示)。
以上所述是本申请的一些实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (11)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底包括衬底层及位于所述衬底层上、沿第一方向排列的多条位线结构；所述衬底层包括浅沟槽隔离结构、所述浅沟槽隔离结构限定的有源区及多条沿第二方向排列的字线结构，所述字线结构穿过所述浅沟槽隔离结构及所述有源区，相邻的两条所述位线结构与相邻的两条所述字线结构限定的区域为导电接触区，所述导电接触区暴露部分所述有源区；
    在所述位线结构之间形成导电层，所述导电层覆盖所述衬底层，且所述导电层沿所述第一方向延伸；
    去除部分所述导电层，保留所述导电接触区对应的导电层，形成第一电容导线；
    形成隔离层，所述隔离层填充所述第一电容导线之间的空隙。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，在形成隔离层之后，所述方法还包括：
    回刻所述第一电容导线至预设深度，形成接触孔；
    在所述接触孔内形成第二电容导线。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，在所述位线结构之间形成导电层之前，所述方法还包括：
    形成保护层，所述保护层覆盖所述位线结构表面及所述衬底层表面；
    去除部分所述保护层，保留位于所述位线结构侧壁的保护层。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，在所述位线结构之间形成导电层之前，所述方法还包括：
    对未被所述位线结构覆盖的衬底层进行刻蚀，去除部分浅沟槽隔离结构，以使所述导电接触区暴露的所述有源区的面积增大。
  5. 根据权利要求1所述的半导体结构的制备方法，其中，所述去除部分导电层，保留所述导电接触区对应的导电层，形成第一电容导线，包括：
    在所述导电层及所述位线结构构成的平面上形成图形化的光阻层，所述光阻层具有多个光阻条，每一所述光阻条沿所述第二方向延伸，且所述光阻条经过所述导电接触区上方；
    以所述光阻条为掩膜，去除暴露的所述导电层；
    去除所述光阻条，形成所述第一电容导线。
  6. 根据权利要求1所述的半导体结构的制备方法，其中，所述形成隔离层，所述隔离层填充所述第一电容导线之间的空隙，包括：
    填充隔离层材料，所述隔离层材料填充所述第一电容导线之间的空隙，并覆盖所述第一电容导线及所述位线结构的表面；
    去除所述第一电容导线及所述位线结构表面的隔离层材料，形成所述隔离层。
  7. 根据权利要求1所述的半导体结构的制备方法，其中，在所述衬底层上形成沿第一方向排列的多条位线结构的方法，包括：
    在所述衬底层上形成底板；
    图形化所述底板，形成多个开窗，所述开窗至少暴露出部分所述有源区；
    在所述开窗中填充导电材料，形成位线接触岛；
    形成多个沿第一方向延伸，且覆盖部分所述底板及所述位线接触岛的位线；
    去除暴露的底板及其下方部分衬底层，至暴露出有源区停止，形成所述位线结构。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，所述图形化所述底板，形成多个开窗，包括：
    在所述底板上形成掩膜层，所述掩膜层具有多个开口，所述开口的中心位置与需要形成开窗的中心位置对应；
    以所述掩膜层为掩膜，将所述掩膜层的图形转移到所述底板上，以形成所述多个开窗。
  9. 根据权利要求7所述的半导体结构的制备方法，其中，在第一方向上，所述开窗的中心点连线与所述位线的中心线重合。
  10. 根据权利要求7所述的半导体结构的制备方法，其中，在所述开窗中填充导电材料之前，所述方法还包括：
    对所述开窗暴露的有源区进行过刻蚀，形成凹槽；
    在所述凹槽及所述开窗内填充所述导电材料，形成所述位线接触岛。
  11. 根据权利要求7所述的半导体结构的制备方法，其中，所述形成多个沿第一方向延伸，且覆盖部分所述底板及所述位线接触岛的位线，包括：
    在所述底板及所述位线接触岛上依次覆盖底层导电层、顶层导电层及阻挡层；
    依次图形化所述阻挡层、所述顶层导电层及所述底层导电层，形成多个沿所述第一方向延伸的所述位线。
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