TWI809359B - 動態隨機存取記憶體的製造方法 - Google Patents

動態隨機存取記憶體的製造方法 Download PDF

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TWI809359B
TWI809359B TW110106821A TW110106821A TWI809359B TW I809359 B TWI809359 B TW I809359B TW 110106821 A TW110106821 A TW 110106821A TW 110106821 A TW110106821 A TW 110106821A TW I809359 B TWI809359 B TW I809359B
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鄭逸生
程建彰
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華邦電子股份有限公司
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Abstract

一種動態隨機存取記憶體的製造方法，包括：於基底上形成硬罩幕層；於所述硬罩幕層與所述基底中形成開口；於所述開口的側壁形成介電層；於所述開口的下部形成埋入式字元線的第一部分；於所述硬罩幕層的頂面上形成障礙層，所述障礙層具有懸突，覆蓋所述硬罩幕層的頂角；藉由所述懸突的阻礙，於所述基底上沉積第一阻障層，所述第一阻障層覆蓋所述障礙層以及上述第一部分的頂面，裸露出所述開口的側壁上的所述介電層；以及於所述開口中形成第一導體層，所述第一導體層的側壁所述介電層接觸。

Description

動態隨機存取記憶體的製造方法
本發明是有關於一種積體電路及其製造方法，且特別是有關於一種動態隨機存取記憶體及其製造方法。
隨著科技日新月異，為了符合消費者對於小型化電子裝置的需求，動態隨機存取記憶體設計的尺寸不斷縮小，並朝高積集度發展。近年來發展出埋入式字元線動態隨機存取記憶體(buried word line DRAM)。在埋入式字元線動態隨機存取記憶體的製程中，由於元件尺寸不斷縮小，製程裕度也隨之變小。在形成埋入式字元線時，若有金屬或是阻障層殘留在埋入式字元線溝渠側壁的介電層上時，將造成元件可靠度的問題。
本發明實施例提供一種動態隨機存取記憶體及其製造方法，可以避免金屬或是阻障層殘留在埋入式字元線溝渠側壁的介電層上，提升元件的可靠度。
本發明實施例提供一種動態隨機存取記憶體的製造方法，包括：於基底上形成硬罩幕層；於所述硬罩幕層與所述基底中形成開口；於所述開口的側壁形成介電層；於所述開口的下部形成埋入式字元線的第一部分；於所述基底上形成障礙層，所述障礙層覆蓋所述硬罩幕層的頂面並且所述障礙層具有懸突，覆蓋所述硬罩幕層的頂角；藉由所述懸突的阻礙，於所述基底上沉積第一阻障層，所述第一阻障層覆蓋所述障礙層以及上述第一部分的頂面，裸露出所述開口的側壁上的所述介電層；以及於所述開口中形成第一導體層，所述第一導體層覆蓋所述第一阻障層的頂面，且所述第一導體層的側壁所述介電層接觸。
本發明實施例提供一種動態隨機存取記憶體，包括：基底，所述基底中具有開口；於所述開口的側壁形成介電層；埋入式字元線的第一部分，位於所述開口的下部；埋入式字元線的第二部分，位於所述第一部分上，包括：第一阻障層，位於所述開口中，覆蓋所述第一部分的頂面；以及第一導體層，位於所述開口中，所述第一導體層覆蓋所述第一阻障層的頂面，且所述第一導體層的側壁所述介電層接觸。
基於上述，本發明實施例在開口端形成的懸突，可以阻礙阻障層的沉積，使得阻障層難以沉積在埋入式字元線溝渠的側壁。藉此，在阻障層沉積之後，可以直接進行摻雜多晶矽的沉積製程。由於無需經由蝕刻製程，因此可以節省製程的步驟，且所形成的元件具有高可靠度
請參照圖1A，提供基底10，例如是矽基底。接著，於基底10上形成具有開口圖案的硬罩幕層12。硬罩幕層12的形成方法例如是先形成硬罩幕層材料層。然後，藉由微影與蝕刻製程將硬罩幕層材料層圖案化。硬罩幕層材料層的材料例如是氧化矽，形成的方法例如是熱氧化法或是化學氣相沉積法。之後，以硬罩幕層12為罩幕，進行蝕刻製程，部分地移除基底10，以形成開口14。開口14例如是溝渠。在本實施例中，以埋入式字元線溝渠14做為開口14的例子來說明之，但本發明不限於此。埋入式字元線溝渠14的深度H1例如是110nm至130nm。埋入式字元線溝渠14的高寬比例如是3至10。
請參照圖1A，在硬罩幕層12上以及埋入式字元線溝渠14之中形成介電層16、阻障層18與導體層20。介電層16共形地形成於埋入式字元線溝渠14的內表面。介電層16可以是氧化層，例如是氧化矽，形成的方法例如是臨場蒸氣產生技術（ISSG）。阻障層18又可稱為黏著層。阻障層18可以是單層或是多層，其材料包括金屬或是金屬合金，例如是鈦、氮化鈦、鉭、氮化鉭或其組合。導體層20的材料包括金屬或是金屬合金，例如是鎢。
請參照圖1B，進行蝕刻製程或是化學機械研磨製程，以移除硬罩幕層12上的阻障層18與導體層20，在埋入式字元線溝渠14中留下阻障層18a與導體層20a。
請參照圖1C，進行回蝕刻製程，以部分地移除阻障層18a與導體層20a，使留下來的阻障層18b與導體層20b位於埋入式字元線溝渠14的下側壁LSW以及底部。留下來的導體層20b的高度H2例如是約為埋入式字元線溝渠14的深度H1的1/4~1/3。在一些實施例中，留下來的導體層20b的高度H2例如是50nm至60nm之間。導體層20b與阻障層18b位於埋入式字元線溝渠14的下部做為埋入式字元線的第一部分P1。
請參照圖1D，在基底10上形成障礙層22。障礙層22的階梯覆蓋性（step coverage）較差且在埋入式字元線溝渠14的頂角處具有懸突（overhang）23。障礙層22覆蓋硬罩幕層12的頂面並且覆蓋硬罩幕層12的側壁、埋入式字元線溝渠14的側壁以及阻障層18b與導體層20b的上表面。障礙層22的材料包括介電材料，例如氧化矽。障礙層22的形成方法例如是增強型化學氣相沉積法。
請參照圖1E，移除覆蓋在埋入式字元線溝渠14的上側壁USW以及阻障層18b與導體層20b上的障礙層22，以裸露出硬罩幕層12的側壁、埋入式字元線溝渠14的上側壁USW以及阻障層18b與導體層20b的頂面。留下來的障礙層22a覆蓋硬罩幕層12的頂面。障礙層22a還具有懸突23覆蓋硬罩幕層12的頂角。懸突23之間的開口24的寬度W2小於埋入式字元線溝渠14的寬度W1。
請參照圖1F，在基底10上形成阻障層26。阻障層26可以是單層或是多層，其材料包括金屬或是金屬合金，例如是鈦、氮化鈦、鉭、氮化鉭或其組合。阻障層26可以利用物理氣相沉積法，例如是濺鍍法來形成。阻障層26包括阻障層26a與阻障層26b。阻障層26a覆蓋障礙層22a的頂面與側壁或進一步覆蓋硬罩幕層12的側壁。阻障層26b填入於埋入式字元線溝渠14中，且覆蓋阻障層18b與導體層20b的上表面。由於障礙層22a的懸突23阻礙（hinder）了阻障層26沉積的方向，使得阻障層26難以形成在埋入式字元線溝渠14的上側壁USW接近阻障層26b之處。在埋入式字元線溝渠14的上側壁USW遠離阻障層26b之處的介電層16的側壁上僅有極少許或沒有阻障層26沉積。在接近阻障層26b之處的介電層16的側壁上沒有阻障層26沉積，因此，阻障層26a與阻障層26b彼此分離。阻障層26b的厚度例如是2nm至3nm。
請參照圖1G，由於阻障層26a與阻障層26b彼此已分離，因此無須再進行蝕刻製程來移除埋入式字元線溝渠14的上側壁USW的阻障層26，而可以直接進行後續的沉積製程。緊接著，在埋入式字元線溝渠14之中形成導體層28。導體層28的材料與導體層20不同。在一些實施例中，導體層20為金屬或金屬合金；導體層28為摻雜的多晶矽。導體層28的底面覆蓋且接觸阻障層26b，導體層28的側壁與介電層16接觸。導體層28可以經由沉積與回蝕刻摻雜多晶矽層來形成之。導體層28例如是10nm至20nm。導體層28與阻障層26a、阻障層18b與導體層20b形成埋入式字元線30。阻障層18b與導體層20b共同做為埋入式字元線30的第一部分P1；導體層28與阻障層26a共同做為埋入式字元線30的第二部分P2。第一部分P1的導體層20b的阻值低於導體層28，且導體層20b藉由阻障層18b與介電層16分離。第二部分P2的導體層28與介電層16接觸，且藉由阻障層26a與導體層20b分離。
請參照圖1G，在埋入式字元線溝渠14之中形成絕緣層32。絕緣層32的材料例如為氮化矽。絕緣層32的形成方法例如是沉積與回蝕刻絕緣材料層。
請參照圖1H，進行平坦化製程，以移除硬障礙層12以上的障礙層22a、阻障層26a以及絕緣層32。
綜上所述，本發明在沉積阻障層之前，先在基底上形成具有懸突的障礙層，利用懸突的障礙，使得阻障層難以沉積在埋入式字元線溝渠的側壁。因此，在阻障層沉積之後，可以直接進行摻雜多晶矽的沉積製程。由於無需經由蝕刻製程，因此可以節省製程的步驟，且所形成的元件具有高可靠度。
10:基底 12:硬罩幕層 14、24:開口 16:介電層 18、18a、18b、26、26a、26b:阻障層 20、20a、20b、28:導體層 22、22a:障礙層 23:懸突 30:埋入式字元線 32:絕緣層 H1:深度 H2:高度 P1:第一部分 P2:第二部分 USW:上側壁 LSW:下側壁 W1、W2:寬度
圖1A至圖1H是依照本發明的實施例的一種動態隨機存取記憶體的製造方法的剖面示意圖。
10:基底
12:硬罩幕層
16:介電層
18b、26、26a、26b:阻障層
20b:導體層
22a:障礙層
23:懸突
24:開口
P1:第一部分
USW:上側壁
LSW:下側壁

Claims (8)

  1. 一種動態隨機存取記憶體的製造方法，包括：於基底上形成硬罩幕層；於所述硬罩幕層與所述基底中形成開口；於所述開口的側壁形成介電層；於所述開口的下部形成埋入式字元線的第一部分；於所述基底上形成障礙層，所述障礙層覆蓋所述硬罩幕層的頂面並且所述障礙層具有懸突，覆蓋所述硬罩幕層的頂角；藉由所述懸突的阻礙，於所述基底上沉積第一阻障層，所述第一阻障層覆蓋所述障礙層以及上述第一部分的頂面，裸露出所述開口的側壁上的所述介電層；以及於所述開口中形成第一導體層，所述第一導體層覆蓋所述第一阻障層的頂面，且所述第一導體層的側壁與所述介電層接觸。
  2. 如請求項1所述的動態隨機存取記憶體的製造方法，其中於所述基底上沉積所述第一阻障層後，緊接著於所述開口中形成所述第一導體層。
  3. 如請求項1所述的動態隨機存取記憶體的製造方法，其中於所述基底上沉積所述第一阻障層與於所述開口中形成所述第一導體層的步驟之間，無需進行蝕刻第一阻障層的步驟。
  4. 如請求項1所述的動態隨機存取記憶體的製造方法，其中於所述基底上沉積所述第一阻障層的方法包括物理氣相沉積法。
  5. 如請求項1所述的動態隨機存取記憶體的製造方法，其中於所述基底上形成障礙層的方法包括電漿增強型化學氣象沉積法。
  6. 如請求項1所述的動態隨機存取記憶體的製造方法，其中於所述開口的下部形成埋入式字元線的所述第一部分包括：於所述開口中形成第二阻障層；以及於所述開口中形成第二導體層，其中所述第二導體層的材料與所述第一導體層的材料不同。
  7. 如請求項1所述的動態隨機存取記憶體的製造方法，更包括於所述開口中填入絕緣層，以覆蓋所述第一導體層。
  8. 如請求項1所述的動態隨機存取記憶體的製造方法，更包括移除所述硬罩幕層及其上方的所述障礙層與所述第一阻障層。
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