WO2021109504A1 - 半导体存储器及其形成方法 - Google Patents

半导体存储器及其形成方法 Download PDF

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Publication number
WO2021109504A1
WO2021109504A1 PCT/CN2020/093420 CN2020093420W WO2021109504A1 WO 2021109504 A1 WO2021109504 A1 WO 2021109504A1 CN 2020093420 W CN2020093420 W CN 2020093420W WO 2021109504 A1 WO2021109504 A1 WO 2021109504A1
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Prior art keywords
layer
bit line
forming
semiconductor memory
trench
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PCT/CN2020/093420
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English (en)
French (fr)
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苏茂华
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长鑫存储技术有限公司
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Priority to US17/431,035 priority Critical patent/US20220139925A1/en
Publication of WO2021109504A1 publication Critical patent/WO2021109504A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor memory and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each memory cell usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the storage can be read through the bit line. Data information in the capacitor, or write data information into the capacitor.
  • the present invention provides a semiconductor memory and a forming method thereof, which are used to solve the problem of large internal resistance of the existing semiconductor memory, so as to improve the yield of the semiconductor memory.
  • the present invention provides a method for forming a semiconductor memory, which includes the following steps:
  • bit line Filling a first conductive material in the trench to form a bit line, the top surface of the bit line is located below the top surface of the dielectric layer;
  • An insulating material is filled in the trench to form a bit line capping layer on the top surface of the bit line.
  • the specific steps of forming a trench penetrating the dielectric layer and exposing the bit line contact area include:
  • the dielectric layer is etched along the etching window to form a trench that penetrates the dielectric layer and the liner layer and exposes the bit line contact area.
  • the specific steps of forming a first mask layer on the surface of the liner layer include:
  • the photoresist layer has an initial opening exposing the liner layer
  • the photoresist layer is removed, and an opening exposing the liner layer is formed in the first mask layer.
  • the material of the liner layer is an oxide material
  • the material of the dielectric layer is silicon nitride
  • the material of the first mask layer is an amorphous silicon material
  • the material of the second mask layer is The material is an organic mask material.
  • bit line is further included before forming the bit line:
  • bit line contact layer on the top surface of the bit line contact area.
  • the trench extends into the substrate, the bit line contact layer extends out of the substrate, and the top surface of the bit line contact layer is located below the top surface of the dielectric layer.
  • the specific steps of forming the bit line include:
  • the first conductive material is a metal material
  • the second conductive material is a polysilicon material
  • bit line capping layer extends beyond the dielectric layer; after forming the bit line capping layer on the top surface of the bit line, the method further includes the following steps:
  • the dielectric layer is etched using the isolation layer as a mask pattern to expose the substrate, and the dielectric layer remaining on the surface of the bit line serves as a sidewall protection layer.
  • the materials of the isolation layer, the bit line capping layer, and the dielectric layer are all the same.
  • the present invention also provides a semiconductor memory which is formed by the method for forming a semiconductor memory as described in any one of the above;
  • the semiconductor memory includes:
  • a dielectric layer located on the surface of the substrate, and the dielectric layer has a trench penetrating the dielectric layer and exposing the bit line contact area;
  • a diffusion barrier layer covering at least part of the sidewall of the trench
  • a bit line is filled in the trench and at least the sidewall of the bit line is surrounded by the diffusion barrier layer, the bit line is electrically connected to the bit line contact area, and the top surface of the bit line is located Below the top surface of the dielectric layer;
  • the bit line capping layer is filled in the trench and located on the top surface of the bit line.
  • the trench extends into the substrate;
  • the semiconductor memory further includes:
  • the diffusion barrier layer is also located between the bit line contact layer and the bit line, and the bit line is electrically connected to the bit line contact area through the bit line contact layer.
  • the material of the bit line is a metal material
  • the material of the bit line contact layer is a polysilicon material
  • bit line capping layer extends out of the dielectric layer;
  • semiconductor memory further includes:
  • the isolation layer covers the sidewall surface of the dielectric layer extending from the bit line cap layer.
  • the material of the isolation layer, the material of the bit line capping layer, and the material of the dielectric layer are all the same.
  • the semiconductor memory and its forming method provided by the present invention form a trench penetrating the dielectric layer as a bit line profile, and then fill the trench with a first conductive material to form the bit line, compared with the prior art through deposition
  • the conductive film layer and the subsequent etching of the conductive film layer to form the bit line on the one hand, because the bit line is formed by trench filling, it will not bend due to the small line width of the bit line; on the other hand, Since there is no need to perform wet cleaning on the bit line metal or polysilicon, problems such as bit line side corrosion and sidewall oxidation are avoided, better electron conduction paths are improved, and the internal resistance of the semiconductor memory is reduced.
  • FIG. 1 is a flowchart of a method for forming a semiconductor memory in a specific embodiment of the present invention
  • 2A-2N are schematic cross-sectional views of main processes in the process of forming a semiconductor memory according to the specific embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for forming a semiconductor memory in a specific embodiment of the present invention.
  • Figs. 2A-2N are a process of forming a semiconductor memory in a specific embodiment of the present invention. Schematic diagram of the main process section.
  • the semiconductor memory described in this specific embodiment may be, but is not limited to, a DRAM memory.
  • the method for forming a semiconductor memory provided by this embodiment includes the following steps:
  • a substrate 20 is provided.
  • the substrate 20 has a bit line contact area 201, and the surface of the substrate 20 is covered with a dielectric layer 21.
  • the substrate 20 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, silicon on insulator), or GOI (Germanium On Insulator, germanium on insulator), etc.
  • the substrate 20 is an Si substrate as an example for description.
  • the substrate 20 has a plurality of active areas (Active Area, AA) arranged in an array, and adjacent active areas are electrically isolated by a shallow trench isolation structure (STI)
  • STI shallow trench isolation structure
  • the bit line contact area 201 is located in the active area.
  • Step S12 forming a trench 27 penetrating the dielectric layer 21 and exposing the bit line contact area 201, as shown in FIG. 2E.
  • the specific steps of forming the trench 27 penetrating the dielectric layer 21 and exposing the bit line contact region 201 include:
  • the first mask layer 24 has an opening 241 exposing the liner layer 22, as shown in FIG. 2B;
  • the first mask layer 24 is etched back, and an etching window 26 exposing the liner layer 22 is formed in the second mask layer 25, as shown in FIG. 2D;
  • the dielectric layer 21 is etched along the etching window 26 to form a trench 27 that penetrates the dielectric layer 21 and the liner layer 22 and exposes the bit line contact area 201, as shown in FIG. 2E.
  • the specific steps of forming the first mask layer 24 on the surface of the liner layer 22 include:
  • the photoresist layer 23 has an initial opening exposing the liner layer 22;
  • the photoresist layer 23 is removed, and an opening 241 exposing the liner layer 22 is formed in the first mask layer 24.
  • the liner layer 22 is deposited on the surface of the dielectric layer 21 by using a chemical vapor deposition process, a physical vapor deposition process or other processes.
  • the photoresist layer 23 with initial openings is formed on the surface of the liner layer 22.
  • the first mask layer 24 is deposited on the surface of the photoresist layer 23 and the exposed liner layer 22 to form a structure as shown in FIG. 2A.
  • the first mask layer 24 is etched back to remove the first mask layer 24 on the surface of the liner layer 22 and the top surface of the photoresist layer 23, leaving only the photoresist layer 23 the first mask layer 24 on the sidewall; afterwards, the photoresist layer 23 is stripped to form a structure as shown in FIG.
  • the opening 241 is backfilled to form the second mask layer 25 covering the top surface of the first mask layer 24 and the inner wall of the opening 241, as shown in FIG. 2C.
  • the second mask layer 25 is etched back to expose the first mask layer 24; after that, the first mask layer 24 is removed by a dry etching or wet etching process.
  • An etching window 26 exposing the liner layer 22 is formed in the second mask layer 25, as shown in FIG. 2D.
  • the liner layer 22, the dielectric layer 21 and part of the substrate 20 are etched down along the etching window 26 to form the trench 27, and the second mask layer 25 is peeled off After that, the structure shown in FIG. 2E is obtained.
  • the width of the trench 27 to be formed subsequently can be controlled.
  • the trench 27 extends to the inside of the substrate 20 to further reduce the contact resistance inside the semiconductor memory and to better isolate adjacent bit lines.
  • those skilled in the art can also make the groove 27 only extend to the surface of the substrate 20 according to actual needs.
  • the material of the liner layer 22 is an oxide material
  • the material of the dielectric layer 21 is silicon nitride
  • the material of the first mask layer 24 is an amorphous silicon material
  • the material of the film layer 25 is an organic mask material.
  • the material of the second mask layer 25 is Spin On Carbon (SOC).
  • Step S13 filling the trench 27 with a first conductive material to form a bit line 30, the top surface of the bit line 30 is located below the top surface of the dielectric layer 21, as shown in FIG. 2I.
  • bit line 30 Before forming the bit line 30, the following steps are further included:
  • a second conductive material is filled in the trench 27 to form a bit line contact layer 28 on the top surface of the bit line contact region 201, as shown in FIG. 2G.
  • the trench 27 extends into the substrate 20
  • the bit line contact layer 28 extends out of the substrate 20
  • the top surface of the bit line contact layer 28 is located on the dielectric layer 21 Below the top surface.
  • bit line 30 the specific steps of forming the bit line 30 include:
  • bit line 30 covering the surface of the diffusion barrier layer 29.
  • the first conductive material is a metal material, such as tungsten; the second conductive material is a polysilicon material, and the material of the diffusion barrier layer 29 may be titanium nitride.
  • a polysilicon material is filled in the trench 27 and covers the top surface of the liner layer 22 to form a bit line contact layer 28 as shown in FIG. 2F. Then, the bit line contact layer 28 is etched back, and the top surface of the bit line contact layer 28 is lowered below the top surface of the dielectric layer 21, as shown in FIG. 2G.
  • the diffusion barrier layer 29 covering the sidewalls of the trench 27, the top surface of the bit line contact layer 28 and the top surface of the dielectric layer 21 is formed, and a metal material is filled in the trench 27 to form
  • the bit line 30 covering the surface of the diffusion barrier layer 29, that is, the bottom surface and sidewalls of the bit line 30 are surrounded and covered by the diffusion barrier layer 29, as shown in FIG. 2H.
  • the diffusion barrier layer 29 covering the sidewall of the bit line 30 can effectively prevent metal from diffusing into the dielectric layer 21; the diffusion barrier layer 29 covering the bottom surface of the bit line 30 can be used as
  • the work function layer connecting the bit line 30 (metal material) and the bit line contact layer 28 (polysilicon material) plays a transitional role.
  • bit line 30 and the diffusion barrier layer 29 are etched back, and the top surface of the bit line 30 and the diffusion barrier layer 29 is lowered to below the top surface of the dielectric layer 21, that is, the The height of the bit line 30 and the diffusion barrier layer 29 is such that the top surface of the bit line 30 is flush with the top surface of the diffusion barrier layer 29, forming a structure as shown in FIG. 2I.
  • the contact resistance between the bit line contact area 201 and the bit line 30 can be reduced.
  • bit line contact layer 28 and the bit line 30 in this specific embodiment are both formed by a trench filling process, on the one hand, the verticality of the bit line contact layer 28 and the bit line 30 is ensured.
  • the topography avoids the phenomenon that the feature size of the bit line contact layer 28 and the bit line 30 is too small and easy to be bent; on the other hand, no photoresist ashing process and wet method of the bit line contact layer material are required
  • the cleaning avoids problems such as undercutting and natural oxidation of the sidewalls of the bit line contact layer 28, thereby reducing the internal resistance of the semiconductor memory and improving the performance of the semiconductor memory.
  • step S14 an insulating material is filled in the trench 27 to form a bit line cap layer 31 on the top surface of the bit line 30, as shown in FIG. 2L.
  • bit line cap layer 31 as shown in FIG. 2J is formed. Then, the bit line cap layer 31 is etched back or chemical mechanical polishing process to remove the bit line cap layer 31 covering the top surface of the liner layer 22 to expose the liner layer 22, such as Shown in Figure 2K. Next, a wet etching process is used to remove the liner layer 22 to form a structure as shown in FIG. 2L.
  • bit line capping layer 31 extends out of the dielectric layer; after forming the bit line capping layer 31 on the top surface of the bit line 30, the method further includes the following steps:
  • the dielectric layer 21 is etched using the isolation layer 32 as a mask pattern to expose the substrate 20, and the dielectric layer 21 remaining on the surface of the bit line 30 serves as a sidewall protection layer 33, as shown in FIG. 2N.
  • the bit line cap layer 31 extends beyond the surface of the dielectric layer 21 to be exposed.
  • the isolation layer 32 and the exposed surface are deposited using an atomic layer deposition process.
  • the surface of the dielectric layer 21 and the exposed bit line cap layer 31 are as shown in FIG. 2M.
  • the isolation layer 32 is etched back to remove the isolation layer 32 covering the top surface of the bit line cap layer 31 and the exposed surface of the dielectric layer 21, leaving only the isolation layer 32 covering the bit line cap layer 31 The isolation layer 32 of the sidewall.
  • the dielectric layer 21 is etched using the isolation layer 32 covering the sidewalls of the bit line cap layer 31 as a mask pattern, leaving only the sidewalls covering the bit line 30 and part of the bit line cap
  • the dielectric layer 21 on the sidewall of the layer 31 forms the sidewall protection layer 33, that is, by separating the dielectric layer 21, a plurality of the sidewall protection layers corresponding to the plurality of bit lines 30 are formed one-to-one 33.
  • part of the isolation layer 32 and part of the bit line capping layer 31 are also etched away simultaneously, so that the height of the isolation layer 32 and the bit line capping layer 31 is Lowering, the height of the bit line cap layer 31 etched away may be equivalent to the thickness of the dielectric layer 21.
  • the material of the isolation layer 32, the material of the bit line cap layer 31 and the dielectric layer 21 are the same.
  • the materials of the isolation layer 32, the bit line capping layer 31 and the dielectric layer 21 may all be nitride materials (for example, silicon nitride).
  • this specific embodiment also provides a semiconductor memory.
  • the structure of the semiconductor memory provided by this specific embodiment can be seen in FIG. 2N, and the semiconductor memory can be formed by the method shown in FIGS. 1 and 2A-2N.
  • the semiconductor memory provided by this embodiment includes:
  • the substrate 20 has a bit line contact area 201 inside the substrate 20;
  • the dielectric layer 21 is located on the surface of the substrate 20, and the dielectric layer 21 has a trench 27 that penetrates the dielectric layer 21 and exposes the bit line contact area 201;
  • the diffusion barrier layer 29 covers at least part of the sidewalls of the trench 27;
  • the bit line 30 is filled in the trench 27 and at least the sidewall of the bit line 30 is surrounded by the diffusion barrier layer 29, the bit line 30 is electrically connected to the bit line contact area 201, and the The top surface of the bit line 30 is located below the top surface of the dielectric layer 21;
  • the bit line capping layer 31 is filled in the trench 27 and located on the top surface of the bit line 30.
  • the trench 27 extends into the substrate 20; the semiconductor memory further includes:
  • the bit line contact layer 28 is filled in the trench 27 and is located on the top surface of the bit line contact area 201;
  • the diffusion barrier layer 29 is also located between the bit line contact layer 28 and the bit line 30, and the bit line 30 is electrically connected to the bit line contact area 201 through the bit line contact layer 28.
  • the material of the bit line 30 is a metal material
  • the material of the bit line contact layer 28 is a polysilicon material.
  • bit line cap layer 31 extends out of the dielectric layer 21; the semiconductor memory further includes:
  • the isolation layer 32 covers the sidewall surface of the dielectric layer 21 extending from the bit line cap layer 31.
  • the material of the isolation layer 32, the material of the bit line cap layer 31, and the material of the dielectric layer 21 are all the same.
  • the semiconductor memory and the method for forming the semiconductor memory provided in this embodiment mode form a bit line by forming a trench penetrating the dielectric layer as a bit line profile, and then filling the trench with a first conductive material to form a bit line, which is compared with the prior art
  • the method of forming a bit line by depositing a conductive film layer and subsequently etching the conductive film layer.
  • bit line is formed by trench filling, there is no bending phenomenon due to the small line width of the bit line;
  • bit line metal or polysilicon since there is no need to perform wet cleaning on the bit line metal or polysilicon, problems such as bit line undercutting and sidewall oxidation are avoided, a better electron conduction path is improved, and the internal resistance of the semiconductor memory is reduced.

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Abstract

本发明涉及半导体制造技术领域，尤其涉及一种半导体存储器及其形成方法。所述半导体存储器的形成方法包括如下步骤：提供一衬底，所述衬底内具有位线接触区，所述衬底表面覆盖有介质层；形成贯穿所述介质层并暴露所述位线接触区的沟槽；填充第一导电材料于所述沟槽内，形成位线，所述位线的顶面位于所述介质层的顶面之下；填充绝缘材料于所述沟槽内，形成位于所述位线顶面的位线盖层。本发明一方面，不会因为位线的线宽较小而发生弯曲现象；另一方面，避免了位线侧蚀以及侧壁氧化等问题，提高了较佳的电子传导路径，从而降低了半导体存储器内部的电阻。

Description

半导体存储器及其形成方法
相关申请引用说明
本申请要求于2019年12月02日递交的中国专利申请号201911213052.6、申请名为“半导体存储器及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体存储器及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着半导体集成电路器件的特征尺寸不断缩小，对DRAM等半导体器件制程工艺的要求也越来越高，其中，对密集阵列区(Array)中位线(Bit-line)的设计十分重要。当前主要是通过藉由SADP(Self-Align Double Patterning，自对准双重图像技术)将图像转移至最终的金属层和/或多晶硅层上，再通过原子层沉积工艺生长一层氮化物材料作为绝缘层。在上述工艺过程中，光阻层的剥离以及湿法清洗工艺的实施，会造成位线底部多晶硅的侧蚀，并且多晶硅表面容易被氧化而形成一层自身氧化层。多晶硅的侧蚀以及自身氧化都会造成导电线路上电阻的增加，尤其是当位线工艺微缩至10nm时，这种电阻增加现象更加明显。
因此，如何避免位线在形成过程中的侧蚀以及自身氧化等问题，降低半导体存储器内部的电阻，从而改善半导体存储器的良率，是目前亟待解决的技术问题。
发明内容
本发明提供一种半导体存储器及其形成方法，用于解决现有的半导体存储器内部电阻较大的问题，以改善半导体存储器的良率。
为了解决上述问题，本发明提供了一种半导体存储器的形成方法，包括如下步骤：
提供一衬底，所述衬底内具有位线接触区，所述衬底表面覆盖有介质层；
形成贯穿所述介质层并暴露所述位线接触区的沟槽；
填充第一导电材料于所述沟槽内，形成位线，所述位线的顶面位于所述介质层的顶面之下；
填充绝缘材料于所述沟槽内，形成位于所述位线顶面的位线盖层。
可选的，形成贯穿所述介质层并暴露所述位线接触区的沟槽的具体步骤包括：
形成衬垫层于所述介质层表面；
形成第一掩膜层于所述衬垫层表面，所述第一掩膜层中具有暴露所述衬垫层的开口；
形成填充满所述开口的第二掩膜层；
回刻蚀所述第一掩膜层，于所述第二掩膜层中形成暴露所述衬垫层的刻蚀窗口；
沿所述刻蚀窗口刻蚀所述介质层，形成贯穿所述介质层与所述衬垫层并暴露所述位线接触区的沟槽。
可选的，形成第一掩膜层于所述衬垫层表面的具体步骤包括：
形成光阻层于所述衬垫层表面，所述光阻层中具有暴露所述衬垫层的初始开口；
形成覆盖所述初始开口侧壁的所述第一掩膜层；
去除所述光阻层，于所述第一掩膜层中形成暴露所述衬垫层的开口。
可选的，所述衬垫层的材料为氧化物材料，所述介质层的材料为氮化硅，所述第一掩膜层的材料为非晶硅材料，所述第二掩膜层的材料为有机掩膜材料。
可选的，形成位线之前还包括如下步骤：
填充第二导电材料于所述沟槽内，形成位于所述位线接触区顶面的位线接触层。
可选的，所述沟槽延伸至所述衬底内，所述位线接触层延伸出所述衬底， 且所述位线接触层的顶面位于所述介质层的顶面之下。
可选的，形成所述位线的具体步骤包括：
形成覆盖所述沟槽侧壁以及所述位线接触层顶面的扩散阻挡层；
填充第一导电材料于所述沟槽内，形成覆盖于所述扩散阻挡层表面的位线。
可选的，所述第一导电材料为金属材料，所述第二导电材料为多晶硅材料。
可选的，所述位线盖层延伸出所述介质层；形成位于所述位线顶面的位线盖层之后，还包括如下步骤：
形成覆盖所述位线盖层侧壁的隔离层；
以所述隔离层为掩膜图形刻蚀所述介质层，暴露所述衬底，残留于所述位线表面的介质层作为侧壁保护层。
可选的，所述隔离层的材料、所述位线盖层及所述介质层的材料均相同。
为了解决上述问题，本发明还提供了一种半导体存储器，所述半导体存储器采用如上述任一项所述的半导体存储器的形成方法形成；所述半导体存储器包括：
衬底，所述衬底内具有位线接触区；
介质层，位于所述衬底表面，所述介质层中具有贯穿所述介质层并暴露所述位线接触区的沟槽；
扩散阻挡层，至少覆盖所述沟槽的部分侧壁；
位线，填充于所述沟槽内且至少所述位线的侧壁被所述扩散阻挡层包围，所述位线与所述位线接触区电连接，且所述位线的顶面位于所述介质层的顶面之下；
位线盖层，填充于所述沟槽内，且位于所述位线顶面。
可选的，所述沟槽延伸至所述衬底内；所述半导体存储器还包括：
位线接触层，填充于所述沟槽内，且位于所述位线接触区顶面；
所述扩散阻挡层还位于所述位线接触层与所述位线之间，所述位线通过所述位线接触层与所述位线接触区电连接。
可选的，所述位线的材料为金属材料，所述位线接触层的材料为多晶硅材料。
可选的，所述位线盖层延伸出所述介质层；所述半导体存储器还包括：
隔离层，覆盖于所述位线盖层延伸出的所述介质层的侧壁表面。
可选的，所述隔离层的材料、所述位线盖层的材料及所述介质层的材料均相同。
本发明提供的半导体存储器及其形成方法，通过形成贯穿介质层的沟槽作为位线轮廓，然后在所述沟槽内填充第一导电材料来形成位线，相较于现有技术中通过沉积导电膜层以及后续对导电膜层刻蚀来形成位线的方法，一方面，由于位线是通过沟槽填充形成，所以不会因为位线的线宽较小而发生弯曲现象；另一方面，由于无需对位线金属或多晶硅进行湿法清洗，避免了位线侧蚀以及侧壁氧化等问题，提高了较佳的电子传导路径，从而降低了半导体存储器内部的电阻。
附图说明
附图1是本发明具体实施方式中半导体存储器的形成方法流程图；
附图2A-2N是本发明具体实施方式在形成半导体存储器的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本发明提供的半导体存储器及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体存储器的形成方法，附图1是本发明具体实施方式中半导体存储器的形成方法流程图，附图2A-2N是本发明具体实施方式在形成半导体存储器的过程中主要的工艺截面示意图。本具体实施方式中所述的半导体存储器可以是但不限于DRAM存储器。如图1、图2A-图2N所示，本具体实施方式提供的半导体存储器的形成方法，包括如下步骤：
步骤S11，提供一衬底20，所述衬底20内具有位线接触区201，所述衬底20表面覆盖有介质层21。
具体来说，所述衬底20可以为Si衬底、Ge衬底、SiGe衬底、SOI(Silicon On Insulator，绝缘体上硅)或者GOI(Germanium On Insulator，绝缘体上锗)等。本具体实施方式中以所述衬底20为Si衬底为例进行说明。所述衬底20内具有呈阵列排布的多个有源区(Active Area，AA)，相邻所述有源区之间通 过浅沟槽隔离结构(Shallow Trench Isolation，STI)进行电性隔离，所述位线接触区201位于所述有源区内。
步骤S12，形成贯穿所述介质层21并暴露所述位线接触区201的沟槽27，如图2E所示。
可选的，形成贯穿所述介质层21并暴露所述位线接触区201的沟槽27的具体步骤包括：
形成衬垫层22于所述介质层21表面；
形成第一掩膜层24于所述衬垫层22表面，所述第一掩膜层24中具有暴露所述衬垫层22的开口241，如图2B所示；
形成填充满所述开口241的第二掩膜层25，如图2C所示；
回刻蚀所述第一掩膜层24，于所述第二掩膜层25中形成暴露所述衬垫层22的刻蚀窗口26，如图2D所示；
沿所述刻蚀窗口26刻蚀所述介质层21，形成贯穿所述介质层21与所述衬垫层22并暴露所述位线接触区201的沟槽27，如图2E所示。
可选的，形成第一掩膜层24于所述衬垫层22表面的具体步骤包括：
形成光阻层23于所述衬垫层22表面，所述光阻层23中具有暴露所述衬垫层22的初始开口；
形成覆盖所述初始开口侧壁的所述第一掩膜层24，如图2A所示；
去除所述光阻层23，于所述第一掩膜层24中形成暴露所述衬垫层22的开口241。
具体来说，首先，采用化学气相沉积工艺、物理气相沉积工艺或者其他工艺沉积所述衬垫层22于所述介质层21表面。接着，形成具有初始开口的所述光阻层23于所述衬垫层22表面。之后，沉积所述第一掩膜层24于所述光阻层23和暴露的所述衬垫层22表面，形成如图2A所示的结构。然后，对所述第一掩膜层24进行回刻蚀，去除所述衬垫层22表面和所述光阻层23顶面的所述第一掩膜层24，仅保留所述光阻层23侧壁的所述第一掩膜层24；之后，剥离所述光阻层23，形成如图2B所示的结构。接着，回填所述开口241，形成覆盖所述第一掩膜层24顶面和所述开口241内壁的所述第二掩膜层25，如图2C所示。然后，对所述第二掩膜层25进行回刻蚀，暴露所述第一掩膜层 24；之后，采用干法刻蚀或者湿法刻蚀工艺去除所述第一掩膜层24，于所述第二掩膜层25中形成暴露所述衬垫层22的刻蚀窗口26，如图2D所示。最后，沿所述刻蚀窗口26向下刻蚀所述衬垫层22、所述介质层21和部分的所述衬底20，形成所述沟槽27，剥离所述第二掩膜层25之后，得到如图2E所示的结构。
本具体实施方式中，通过调整位于所述光阻层23侧壁的所述第一掩膜层24的厚度，可以控制后续形成的所述沟槽27的宽度。
在本具体实施方式中，所述沟槽27延伸至所述衬底20内部，以进一步减小半导体存储器内部的接触电阻，并更好的隔离相邻位线。在其他具体实施方式中，本领域技术人员也可以根据实际需要，使得所述沟槽27仅延伸至所述衬底20表面。
所述第一掩膜层24与所述第二掩膜层25之间应该具有较高的刻蚀选择比，以便于后续选择性的刻蚀掉所述第一掩膜层24。可选的，所述衬垫层22的材料为氧化物材料，所述介质层21的材料为氮化硅，所述第一掩膜层24的材料为非晶硅材料，所述第二掩膜层25的材料为有机掩膜材料。例如，第二掩膜层25的材料为旋涂碳层(Spin On Carbon，SOC)。
步骤S13，填充第一导电材料于所述沟槽27内，形成位线30，所述位线30的顶面位于所述介质层21的顶面之下，如图2I所示。
可选的，形成位线30之前还包括如下步骤：
填充第二导电材料于所述沟槽27内，形成位于所述位线接触区201顶面的位线接触层28，如图2G所示。
可选的，所述沟槽27延伸至所述衬底20内，所述位线接触层28延伸出所述衬底20，且所述位线接触层28的顶面位于所述介质层21的顶面之下。
可选的，形成所述位线30的具体步骤包括：
形成覆盖所述沟槽27侧壁以及所述位线接触层28顶面的扩散阻挡层29；
填充第一导电材料于所述沟槽27内，形成覆盖于所述扩散阻挡层29表面的位线30。
可选的，所述第一导电材料为金属材料，例如可以为钨；所述第二导电材料为多晶硅材料，所述扩散阻挡层29的材料可以为氮化钛。
具体来说，在形成所述沟槽27之后，首先，填充多晶硅材料于所述沟槽27内、并覆盖所述衬垫层22顶面，形成如图2F所示的位线接触层28。接着，对所述位线接触层28进行回刻蚀，将所述位线接触层28的顶面降低到所述介质层21的顶面之下，如图2G所示。然后，形成覆盖所述沟槽27侧壁、所述位线接触层28顶面和所述介质层21顶面的所述扩散阻挡层29，并填充金属材料于所述沟槽27内，形成覆盖于所述扩散阻挡层29表面的所述位线30，即所述位线30的底面和侧壁被所述扩散阻挡层29包围、覆盖，如图2H所示。其中，覆盖于所述位线30侧壁的所述扩散阻挡层29可以有效的防止金属向所述介质层21扩散；覆盖于所述位线30底面的所述扩散阻挡层29，则可以作为连接所述位线30(金属材料)与所述位线接触层28(多晶硅材料)的功函数层，起到过渡作用。之后，回刻蚀所述位线30和所述扩散阻挡层29，降低所述位线30和所述扩散阻挡层29的顶面至所述介质层21的顶面之下，即降低所述位线30和所述扩散阻挡层29的高度，使得所述位线30的顶面与所述扩散阻挡层29的顶面平齐，形成如图2I所示的结构。通过形成所述位线接触层28，可以降低所述位线接触区201与所述位线30之间的接触电阻。
由于本具体实施方式中的所述位线接触层28与所述位线30均是通过沟槽填充工艺形成，一方面，确保了所述位线接触层28与所述位线30的竖直形貌，避免了所述位线接触层28和所述位线30的特征尺寸过小而易发生弯曲的现象；另一方面，无需光阻灰化工艺及对位线接触层材料进行湿法清洗，避免了所述位线接触层28出现侧蚀以及侧壁自然氧化等问题，从而降低了半导体存储器内部的电阻，改善了半导体存储器的性能。
步骤S14，填充绝缘材料于所述沟槽27内，形成位于所述位线30顶面的位线盖层31，如图2L所示。
具体来说，在降低所述位线30和所述扩散阻挡层29的顶面至所述介质层21的顶面之下之后，采用绝缘材料填充满所述沟槽27并覆盖所述衬垫层22顶面，形成如图2J所示的位线盖层31。然后，对所述位线盖层31进行回刻蚀或者化学机械研磨等工艺，去除覆盖于所述衬垫层22顶面的所述位线盖层31，暴露所述衬垫层22，如图2K所示。接着，采用湿法刻蚀工艺去除所述衬垫层22，形成如图2L所示的结构。
可选的，所述位线盖层31延伸出所述介质层；形成位于所述位线30顶面的位线盖层31之后，还包括如下步骤：
形成覆盖所述位线盖层31侧壁的隔离层32；
以所述隔离层32为掩膜图形刻蚀所述介质层21，暴露所述衬底20，残留于所述位线30表面的介质层21作为侧壁保护层33，如图2N所示。
具体来说，在去除所述衬垫层22之后，所述位线盖层31延伸出所述介质层21的表面暴露，此时，采用原子层沉积工艺沉积所述隔离层32与暴露的所述介质层21和暴露的所述位线盖层31表面，如图2M所示。然后，回刻蚀所述隔离层32，去除覆盖于所述位线盖层31顶面和暴露的所述介质层21表面的所述隔离层32，仅保留覆盖于所述位线盖层31侧壁的所述隔离层32。之后，以覆盖于所述位线盖层31侧壁的所述隔离层32为掩膜图形刻蚀所述介质层21，仅保留覆盖于所述位线30侧壁和部分所述位线盖层31侧壁的所述介质层21，形成所述侧壁保护层33，即通过分隔所述介质层21，形成与多个所述位线30一一对应的多个所述侧壁保护层33。在刻蚀所述介质层21的过程中，还会同步刻蚀掉部分所述隔离层32和部分所述位线盖层31，使得所述隔离层32和所述位线盖层31的高度降低，刻蚀掉的所述位线盖层31的高度可以与所述介质层21的厚度相当。
可选的，所述隔离层32的材料、所述位线盖层31及所述介质层21的材料相同。例如，所述隔离层32、所述位线盖层31和所述介质层21的材料可以均为氮化物材料(例如氮化硅)。
不仅如此，本具体实施方式还提供了一种半导体存储器。本具体实施方式提供的半导体存储器的结构可参见图2N，所述半导体存储器可以采用如图1、图2A-图2N所示的方法形成。如图1、图2A-图2N所示，本具体实施方式提供的半导体存储器，包括：
衬底20，所述衬底20内具有位线接触区201；
介质层21，位于所述衬底20表面，所述介质层21中具有贯穿所述介质层21并暴露所述位线接触区201的沟槽27；
扩散阻挡层29，至少覆盖所述沟槽27的部分侧壁；
位线30，填充于所述沟槽27内且至少所述位线30的侧壁被所述扩散阻挡 层29包围，所述位线30与所述位线接触区201电连接，且所述位线30的顶面位于所述介质层21的顶面之下；
位线盖层31，填充于所述沟槽27内，且位于所述位线30顶面。
可选的，所述沟槽27延伸至所述衬底20内；所述半导体存储器还包括：
位线接触层28，填充于所述沟槽27内，且位于所述位线接触区201顶面；
所述扩散阻挡层29还位于所述位线接触层28与所述位线30之间，所述位线30通过所述位线接触层28与所述位线接触区201电连接。
可选的，所述位线30的材料为金属材料，所述位线接触层28的材料为多晶硅材料。
可选的，所述位线盖层31延伸出所述介质层21；所述半导体存储器还包括：
隔离层32，覆盖于所述位线盖层31延伸出的所述介质层21的侧壁表面。
可选的，所述隔离层32的材料、所述位线盖层31的材料及所述介质层21的材料均相同。
本具体实施方式提供的半导体存储器及其形成方法，通过形成贯穿介质层的沟槽作为位线轮廓，然后在所述沟槽内填充第一导电材料来形成位线，相较于现有技术中通过沉积导电膜层以及后续对导电膜层刻蚀来形成位线的方法，一方面，由于位线是通过沟槽填充形成，所以不会因为位线的线宽较小而发生弯曲现象；另一方面，由于无需对位线金属或多晶硅进行湿法清洗，避免了位线侧蚀以及侧壁氧化等问题，提高了较佳的电子传导路径，从而降低了半导体存储器内部的电阻。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (15)

  1. 一种半导体存储器的形成方法，其特征在于，包括如下步骤：
    提供一衬底，所述衬底内具有位线接触区，所述衬底表面覆盖有介质层；
    形成贯穿所述介质层并暴露所述位线接触区的沟槽；
    填充第一导电材料于所述沟槽内，形成位线，所述位线的顶面位于所述介质层的顶面之下；
    填充绝缘材料于所述沟槽内，形成位于所述位线顶面的位线盖层。
  2. 根据权利要求1所述的半导体存储器的形成方法，其特征在于，形成贯穿所述介质层并暴露所述位线接触区的沟槽的具体步骤包括：
    形成衬垫层于所述介质层表面；
    形成第一掩膜层于所述衬垫层表面，所述第一掩膜层中具有暴露所述衬垫层的开口；
    形成填充满所述开口的第二掩膜层；
    回刻蚀所述第一掩膜层，于所述第二掩膜层中形成暴露所述衬垫层的刻蚀窗口；
    沿所述刻蚀窗口刻蚀所述介质层，形成贯穿所述介质层与所述衬垫层并暴露所述位线接触区的沟槽。
  3. 根据权利要求2所述的半导体存储器的形成方法，其特征在于，形成第一掩膜层于所述衬垫层表面的具体步骤包括：
    形成光阻层于所述衬垫层表面，所述光阻层中具有暴露所述衬垫层的初始开口；
    形成覆盖所述初始开口侧壁的所述第一掩膜层；
    去除所述光阻层，于所述第一掩膜层中形成暴露所述衬垫层的开口。
  4. 根据权利要求2所述的半导体存储器的形成方法，其特征在于，所述衬垫层的材料为氧化物材料，所述介质层的材料为氮化硅，所述第一掩膜层的材料为非晶硅材料，所述第二掩膜层的材料为有机掩膜材料。
  5. 根据权利要求2所述的半导体存储器的形成方法，其特征在于，形成位线之前还包括如下步骤：
    填充第二导电材料于所述沟槽内，形成位于所述位线接触区顶面的位线接触层。
  6. 根据权利要求5所述的半导体存储器的形成方法，其特征在于，所述沟槽延伸至所述衬底内，所述位线接触层延伸出所述衬底，且所述位线接触层的顶面位于所述介质层的顶面之下。
  7. 根据权利要求5所述的半导体存储器的形成方法，其特征在于，形成所述位线的具体步骤包括：
    形成覆盖所述沟槽侧壁以及所述位线接触层顶面的扩散阻挡层；
    填充第一导电材料于所述沟槽内，形成覆盖于所述扩散阻挡层表面的位线。
  8. 根据权利要求7所述的半导体存储器的形成方法，其特征在于，所述第一导电材料为金属材料，所述第二导电材料为多晶硅材料。
  9. 根据权利要求1所述的半导体存储器的形成方法，其特征在于，所述位线盖层延伸出所述介质层；形成位于所述位线顶面的位线盖层之后，还包括如下步骤：
    形成覆盖所述位线盖层侧壁的隔离层；
    以所述隔离层为掩膜图形刻蚀所述介质层，暴露所述衬底，残留于所述位线表面的介质层作为侧壁保护层。
  10. 根据权利要求9所述的半导体存储器的形成方法，其特征在于，所述隔离层的材料、所述位线盖层的材料及所述介质层材料均相同。
  11. 一种半导体存储器，其特征在于，包括：
    衬底，所述衬底内具有位线接触区；
    介质层，位于所述衬底表面，所述介质层中具有贯穿所述介质层并暴露所述位线接触区的沟槽；
    扩散阻挡层，至少覆盖所述沟槽的部分侧壁；
    位线，填充于所述沟槽内且至少所述位线的侧壁被所述扩散阻挡层包围，所述位线与所述位线接触区电连接，且所述位线的顶面位于所述介质层的顶面之下；
    位线盖层，填充于所述沟槽内，且位于所述位线顶面。
  12. 根据权利要求11所述的半导体存储器，其特征在于，所述沟槽延伸至所述衬底内；所述半导体存储器还包括：
    位线接触层，填充于所述沟槽内，且位于所述位线接触区顶面；
    所述扩散阻挡层还位于所述位线接触层与所述位线之间，所述位线通过所述位线接触层与所述位线接触区电连接。
  13. 根据权利要求12所述的半导体存储器，其特征在于，所述位线的材料为金属材料，所述位线接触层的材料为多晶硅材料。
  14. 根据权利要求11所述的半导体存储器，其特征在于，所述位线盖层延伸出所述介质层；所述半导体存储器还包括：
    隔离层，覆盖于所述位线盖层延伸出的所述介质层的侧壁表面。
  15. 根据权利要求14所述的半导体存储器，其特征在于，所述隔离层的材料、所述位线盖层的材料及所述介质层的材料均相同。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571521B (zh) * 2021-07-26 2023-09-26 长鑫存储技术有限公司 位线结构、半导体结构及位线结构的制作方法
CN113594097B (zh) * 2021-07-29 2023-09-26 长鑫存储技术有限公司 埋入式位线结构及其制作方法、半导体结构
CN113658955B (zh) * 2021-08-12 2024-03-29 长鑫存储技术有限公司 一种半导体结构及其形成方法
CN113690188B (zh) * 2021-08-20 2023-10-20 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN116568024A (zh) * 2022-01-27 2023-08-08 芯盟科技有限公司 半导体结构及其制造方法
CN117529101B (zh) * 2024-01-03 2024-05-14 长鑫新桥存储技术有限公司 半导体结构及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101197375A (zh) * 2007-12-28 2008-06-11 上海宏力半导体制造有限公司 一种掩膜只读存储器及其制造方法
CN101271867A (zh) * 2007-03-19 2008-09-24 茂德科技股份有限公司 位线上电容器及其下电极的制造方法
CN108933136A (zh) * 2018-08-22 2018-12-04 长鑫存储技术有限公司 半导体结构、存储器结构及其制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116784A1 (en) * 2001-12-21 2003-06-26 International Business Machines Corporation DRAM array bit contact with relaxed pitch pattern
KR100439038B1 (ko) * 2002-08-23 2004-07-03 삼성전자주식회사 스터드형태의 캡핑층을 구비한 반도체 장치의 비트라인 및그의 형성방법
KR101076881B1 (ko) * 2008-12-26 2011-10-25 주식회사 하이닉스반도체 반도체 소자의 배선 및 형성 방법
KR101119774B1 (ko) * 2009-08-11 2012-03-26 주식회사 하이닉스반도체 반도체 소자 및 그 형성방법
KR20110055912A (ko) * 2009-11-20 2011-05-26 주식회사 하이닉스반도체 반도체 소자의 콘택홀 형성방법
US8507353B2 (en) * 2010-08-11 2013-08-13 Samsung Electronics Co., Ltd. Method of forming semiconductor device having self-aligned plug
US9418867B2 (en) * 2014-01-10 2016-08-16 Applied Materials, Inc. Mask passivation using plasma
CN108701645B (zh) * 2016-03-30 2023-10-10 太浩研究有限公司 减成图案化的互连下方的自对准通孔
CN107240586B (zh) * 2017-07-26 2018-03-06 睿力集成电路有限公司 存储器及其形成方法、半导体器件
CN109979940B (zh) * 2017-12-27 2021-03-26 长鑫存储技术有限公司 半导体存储器件及其制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101271867A (zh) * 2007-03-19 2008-09-24 茂德科技股份有限公司 位线上电容器及其下电极的制造方法
CN101197375A (zh) * 2007-12-28 2008-06-11 上海宏力半导体制造有限公司 一种掩膜只读存储器及其制造方法
CN108933136A (zh) * 2018-08-22 2018-12-04 长鑫存储技术有限公司 半导体结构、存储器结构及其制备方法

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