WO2022193546A1 - 半导体存储器及其形成方法 - Google Patents

半导体存储器及其形成方法 Download PDF

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Publication number
WO2022193546A1
WO2022193546A1 PCT/CN2021/114014 CN2021114014W WO2022193546A1 WO 2022193546 A1 WO2022193546 A1 WO 2022193546A1 CN 2021114014 W CN2021114014 W CN 2021114014W WO 2022193546 A1 WO2022193546 A1 WO 2022193546A1
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WIPO (PCT)
Prior art keywords
peripheral
layer
bit line
isolation layer
conductive layer
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PCT/CN2021/114014
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English (en)
French (fr)
Inventor
于业笑
刘忠明
方嘉
陈龙阳
武宏发
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长鑫存储技术有限公司
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Priority to US17/452,541 priority Critical patent/US20220302125A1/en
Publication of WO2022193546A1 publication Critical patent/WO2022193546A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor memory and a method for forming the same.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or write data information into the capacitor.
  • Some embodiments of the present application provide a semiconductor memory and a method for forming the same, which are used to solve the problems of complex manufacturing steps and high manufacturing cost of the semiconductor memory, and improve the performance of the semiconductor memory.
  • the present application provides a method for forming a semiconductor memory, comprising the steps of:
  • a substrate is provided, the substrate includes a storage region and a peripheral region located outside the storage region, the substrate interior has a plurality of bit line contacts and a plurality of capacitor contacts located in the storage region, and the peripheral gate contact portion and the peripheral circuit contact portion of the peripheral region;
  • bit line isolation layer covering at least the side wall of the bit line, and simultaneously forming a peripheral gate isolation layer covering at least the side wall of the peripheral gate;
  • a first capacitive conductive layer in contact with the capacitor contact portion is formed above the storage region, and a first peripheral conductive layer in contact with the peripheral circuit contact portion is formed above the peripheral region at the same time.
  • the first capacitor The conductive layer fills the gap between the adjacent bit lines, and the first peripheral conductive layer covers the sidewall of the peripheral gate isolation layer;
  • a first air gap is formed in the bit line isolation layer, and a second air gap is formed in the peripheral gate isolation layer at the same time.
  • the present application also provides a semiconductor memory, including:
  • a substrate comprising a storage region and a peripheral region outside the storage region, the substrate interior having a plurality of bit line contacts and a plurality of capacitance contacts located in the storage region, and peripheral gate contacts and peripheral circuit contacts of the peripheral region;
  • bit lines located above the storage region and in contact with a plurality of the bit line contact portions respectively;
  • bit line isolation layer covering at least the side wall of the bit line
  • peripheral gate isolation layer covering at least the sidewalls of the peripheral gate
  • a first capacitive conductive layer located above the storage region and in contact with the capacitive contact portion, the first capacitive conductive layer filling the gap between the adjacent bit lines;
  • a first peripheral conductive layer is located above the peripheral region and in contact with the peripheral circuit contact portion, and the first peripheral conductive layer covers the sidewall of the peripheral gate isolation layer.
  • Some embodiments of the present application provide a semiconductor memory and a method for forming the same, by forming a bit line in a storage region, forming a peripheral gate in a peripheral region, and simultaneously forming a bit line covering the sidewall of the bit line and having a first air gap
  • the line isolation layer and the peripheral gate isolation layer covering the sidewall of the peripheral gate and having the second air gap simplify the manufacturing steps of the semiconductor memory and reduce the manufacturing cost of the semiconductor memory.
  • the formation of the first air gap and the second air gap greatly reduces the parasitic capacitance of the bit line and the peripheral gate, and improves the electrical performance of the semiconductor memory.
  • FIG. 1 is a flowchart of a method for forming a semiconductor memory in a specific embodiment of the present application
  • 2A-2L are schematic cross-sectional views of the storage area in the process of forming the semiconductor memory according to the specific embodiment of the present application;
  • 3A-3I are schematic cross-sectional views of peripheral regions in a process of forming a semiconductor memory according to an embodiment of the present application.
  • FIG. 1 is a flowchart of the method for forming a semiconductor memory in the specific embodiment of the present application
  • FIGS. 2A-2L are the process of forming the semiconductor memory in the specific embodiment of the present application.
  • Schematic cross-sectional views of the storage region FIGS. 3A-3I are schematic cross-sectional views of the peripheral region in the process of forming the semiconductor memory according to the specific embodiment of the present application.
  • the method for forming a semiconductor memory includes the following steps:
  • Step S11 a substrate is provided, the substrate includes a storage area 21 and a peripheral area 41 located outside the storage area 21, and the substrate has a plurality of bit line contacts 212 and a plurality of bit line contacts located in the storage area 21 inside.
  • the substrate may be, but not limited to, a silicon substrate.
  • the substrate includes the storage area 21 and the peripheral area 41 located at the periphery of the storage area.
  • the peripheral area 41 may only be located on one side of the storage area 21 or may be distributed around the storage area 21 .
  • the storage area 21 is used for storing data information, and the peripheral area 41 includes structures such as CMOS circuits for transmitting control signals to the storage area 21 .
  • the storage region 21 in the substrate includes a plurality of the bit line contacts 212 and a plurality of the capacitor contacts 213, and the bit line contacts 212 and the capacitor contacts 213 are located on the substrate.
  • the bit line contact portion 212 is used for electrical connection with the subsequently formed bit line
  • the capacitor contact portion 213 is used for electrical connection with the subsequently formed capacitor contact structure.
  • the peripheral region 41 in the substrate includes the peripheral gate contact portion 413 and the peripheral circuit contact portion 414, and the peripheral gate contact portion 413 is used for electrical connection with the subsequently formed peripheral gate, so The peripheral circuit contact portion 414 is used for electrical connection with the peripheral circuit formed later.
  • Step S12 forming a plurality of bit lines 36 over the storage region 21 in contact with the bit line contact portions 212 respectively, and simultaneously forming a plurality of bit lines 36 over the peripheral region 41 in contact with the peripheral gate contact portion 413
  • the peripheral gate 43 is shown in FIGS. 2C and 3C.
  • a plurality of bit lines 26 are formed over the storage region 21 in contact with a plurality of the bit line contacts 212 respectively, and at the same time, a plurality of bit lines 26 are formed over the peripheral region 41 in contact with the peripheral gate.
  • the specific steps of the peripheral gate 43 contacted by the portion 413 include:
  • bit line material layer is formed on the surface of the substrate, and the bit line material layer covers at least the bit line contact portion 212 of the storage region 21 and the peripheral gate contact portion 413 of the peripheral region 41 , such as 2B and 3B;
  • the bit line material layer 23 is patterned to form a bit line 26 in the storage region 21 in contact with the bit line contact portion 212 , and at the same time, in the peripheral region 41 to form contact with the peripheral gate contact portion 413
  • the peripheral gate 43 is shown in FIGS. 2C and 3C.
  • bit line material layer is formed on the substrate surface.
  • the specific steps of the substrate surface include:
  • a first conductive layer 23 is formed on the surface of the substrate, and the first conductive layer 23 at least covers the bit line contact portion 212 of the storage region 21 and the peripheral gate contact portion 413 of the peripheral region 41 , as shown in Figure 2A and Figure 3A;
  • a first dielectric layer 25 covering the second conductive layer 24 is formed, as shown in FIG. 2B and FIG. 3B .
  • the specific step of patterning the bit line material layer includes:
  • the first dielectric layer 25 , the second conductive layer 24 and the first conductive layer 23 are etched to form a bit line 26 in the storage region 21 in contact with the bit line contact portion 212 and
  • the bit line capping layer 251 on the top surface of the bit line 26 and the peripheral gate 43 in contact with the peripheral gate contact 413 and the peripheral gate covering the top surface of the peripheral gate 43 are formed in the peripheral region 41 at the same time
  • the polar cap layer 252 is etched to form a bit line 26 in the storage region 21 in contact with the bit line contact portion 212 and
  • the bit line capping layer 251 on the top surface of the bit line 26 and the peripheral gate 43 in contact with the peripheral gate contact 413 and the peripheral gate covering the top surface of the peripheral gate 43 are formed in the peripheral region 41 at the same time
  • the polar cap layer 252 is formed in the peripheral region 41 at the same time.
  • the first conductive layer 23 is deposited on the surface of the substrate, and the first conductive layer 23 covers the bits of the storage region 21 of the substrate. Line contacts 212 and the peripheral gate contact 413 of the peripheral region 41 .
  • the first conductive layer 23 may continuously cover the entire surface of the substrate, or may cover and only cover the bit line contact portion 212 of the storage region 21 and the peripheral gate of the peripheral region 41 Contact portion 413 .
  • the second conductive layer 24 is deposited on the surface of the first conductive layer 23 .
  • the material of the second conductive layer 24 may be different from the material of the first conductive layer 23, for example, the material of the first conductive layer 23 is polysilicon, and the material of the second conductive layer 24 is a metal material (such as tungsten). ).
  • the first dielectric layer 25 is deposited on the surface of the second conductive layer 24 to form the structure shown in FIG. 2B and FIG. 3B .
  • the material of the first dielectric layer 25 may be, but not limited to, a nitride material (eg, silicon nitride).
  • the first conductive layer 23 , the second conductive layer 24 and the first dielectric layer 25 together constitute the bit line material layer. Those skilled in the art can also select other materials or stacked layers of other layers as the bit line material layer according to actual needs.
  • bit line material layer is formed in the storage region 21 and the peripheral region 41.
  • a first mask layer 26 covering the bit line material layer is formed.
  • the bit line material layer is etched, and the bit line 36 and the peripheral gate 43 are formed simultaneously, and the bit line cap layer 251 on the surface of the bit line 36 is simultaneously formed and a peripheral gate capping layer 252 located on the surface of the peripheral gate 43 .
  • the bit line 36 includes a bit line contact layer 231 and a bit line body layer 241 covering the surface of the bit line contact layer 231 .
  • the bit line contact layer 231 is formed by the first conductive layer 23 remaining in the storage region 21 after etching the bit line material layer, and the bit line body layer 241 is formed by etching the bit line material layer Then, the second conductive layer 24 remaining in the storage region 21 is formed.
  • the peripheral gate 43 includes a peripheral gate contact layer 232 and a peripheral gate body layer 242 covering the surface of the peripheral gate contact layer 232.
  • the peripheral gate contact layer 232 is formed by the first conductive layer 23 remaining in the peripheral region 41 after etching the bit line material layer, and the peripheral gate body layer 242 is formed by etching the bit line After the material layer, the second conductive layer 24 remaining in the peripheral region 41 is formed.
  • Step S13 forming a bit line isolation layer covering at least the sidewall of the bit line 36 , and simultaneously forming a peripheral gate isolation layer covering at least the sidewall of the peripheral gate 43 , as shown in FIG. 2C and FIG. 3C .
  • the specific steps of forming a bit line isolation layer covering at least the sidewall of the bit line 36 and simultaneously forming a peripheral gate isolation layer covering at least the sidewall of the peripheral gate 43 include:
  • first isolation layer covering at least the sidewalls of the bit line 36 , the sidewalls of the bitline capping layer 251 , the sidewalls of the peripheral gate 43 and the sidewalls of the peripheral gate capping layer 252 ;
  • a third isolation layer covering the second isolation layer is formed, and the first isolation layer, the second isolation layer and the first isolation layer covering the sidewall of the bit line 36 and the sidewall of the bit line capping layer 251
  • Three isolation layers serve as the bit line isolation layer, the first isolation layer, the second isolation layer and the third isolation layer covering the sidewalls of the peripheral gate 43 and the peripheral gate capping layer 252
  • An isolation layer serves as the peripheral gate isolation layer.
  • the first isolation layer, the second isolation layer and the third isolation layer are sequentially deposited on the sidewalls of the bit line 36 , the sidewalls and the top surface of the bit line capping layer 251 , the The sidewalls of the peripheral gate 43 , and the sidewalls and the top surface of the peripheral gate capping layer 252 .
  • the first isolation layer, the second isolation layer and the third isolation layer are etched, and the first isolation remains on the sidewall of the bit line 36 and the sidewall of the bit line capping layer 251 layer (ie, the first sub-bit line isolation layer 271 ), the second isolation layer (ie, the second sub-bit line isolation layer 272 ) and the third isolation layer (ie, the third sub-bit line isolation layer 273 ) the bit line isolation layer, the first isolation layer (ie the first sub-peripheral gate isolation layer 421 ) covering the sidewalls of the peripheral gate 43 and the sidewalls of the peripheral gate capping layer 252 , the second The isolation layer (ie, the second sub-peripheral gate isolation layer 422 ) and the third isolation layer (ie, the third sub-peripheral gate isolation layer 423 ) serve as the peripheral gate isolation layer.
  • the materials of the first isolation layer and the third isolation layer may be the same, for example, both are nitride materials (eg, silicon nitride), and the materials of the second isolation layer may be oxide materials (eg, silicon oxide).
  • the second isolation layer should have a high etching selectivity ratio between the first isolation layer and the third isolation layer, so as to facilitate subsequent removal of the second isolation layer to form an air gap.
  • Step S14 forming a first capacitive conductive layer 291 above the storage region 21 in contact with the capacitive contact portion 213 , and simultaneously forming a first peripheral portion above the peripheral region 41 in contact with the peripheral circuit contact portion 414
  • the conductive layer 292, the first capacitive conductive layer 291 fills the gap between the adjacent bit lines 36, and the first peripheral conductive layer 292 covers the sidewall of the peripheral gate isolation layer, as shown in FIG. 2F and shown in Figure 3F.
  • a first capacitive conductive layer 291 is formed above the storage region 21 in contact with the capacitive contact portion 213 , and at the same time, a first capacitive conductive layer 291 is formed above the peripheral region 41 in contact with the peripheral circuit contact portion 414 .
  • the specific steps of the first peripheral conductive layer 292 include:
  • a third conductive layer is formed that fills the gap between the adjacent bit lines 36 and covers the capacitor contact portion 213, the peripheral circuit contact portion 414, the bit line isolation layer and the peripheral gate isolation layer layer 29, as shown in Figures 2E and 3E;
  • Part of the third conductive layer 29 is removed, so that the top surface of the third conductive layer 29 is located under the bit line capping layer 251 and the peripheral gate capping layer 252 , and remains on all parts of the storage region 21 .
  • the third conductive layer 29 is used as the first capacitive conductive layer 291
  • the third conductive layer 29 remaining in the peripheral region 41 is used as the first peripheral conductive layer 292 .
  • the storage region 21 and the peripheral region 41 of the substrate are etched, and the capacitor contact portion 213 and the peripheral circuit contact portion 414 are exposed at the same time.
  • Grooves 28 are formed in the substrate.
  • the third conductive layer 29 is deposited, so that the third conductive layer 29 fills the gap between the groove 28 and the adjacent bit line 36, and covers the capacitor contact portion 213, the Peripheral circuit contacts 414, the surface of the bit line isolation layer, and the surface of the peripheral gate isolation layer.
  • a portion of the third conductive layer 29 is etched to form the first capacitive conductive layer 291 in the storage region 21 , and the peripheral conductive layer 292 is formed in the peripheral region 41 at the same time.
  • the material of the third conductive layer 29 may be, but not limited to, polysilicon.
  • step S15 a first air gap 274 is formed in the bit line isolation layer, and a second air gap 424 is formed in the peripheral gate isolation layer at the same time, as shown in FIG. 2G and FIG. 3H .
  • the specific steps of forming the first air gap 274 in the bit line isolation layer and simultaneously forming the second air gap 424 in the peripheral gate isolation layer include:
  • the second isolation layer is removed, and the first air gap 274 is formed between the first isolation layer and the third isolation layer on the sidewall of the bit line 36 and the sidewall of the bit line capping layer 251 , and at the same time, the second air gap 424 is formed between the first isolation layer and the third isolation layer on the sidewall of the peripheral gate 43 and the sidewall of the peripheral gate capping layer 252 .
  • the third isolation layer also covers the top surface of the bit line capping layer 251 and the top surface of the peripheral gate capping layer 252; the specific steps of removing the second isolation layer include:
  • All of the second isolation layer is etched away.
  • the third sub-bit line isolation layer 273 and the third sub-peripheral gate isolation layer 423 are etched simultaneously , the second sub-bit line isolation layer 272 and the second sub-peripheral gate isolation layer 422 are exposed, as shown in FIG. 2F and FIG. 3G .
  • the second sub-bit line isolation layer 272 in the bit line isolation layer and the second sub-peripheral gate isolation layer 422 in the peripheral gate isolation layer are removed by a wet etching process, and at the same time
  • the first air gap 274 and the second air gap 424 are formed.
  • the parasitic capacitance of the bit line 36 and the peripheral gate 43 can be greatly reduced, and the Contact resistance between the first capacitive conductive layer 291 and the capacitive contact portion 213 .
  • the first air gap 274 and the first air gap 274 are directly formed through an etching process.
  • the second air gap 424 can simplify the steps of forming the air gap and improve the efficiency of the semiconductor process.
  • the top surface of the first capacitive conductive layer 291 is located under the top surface of the bit line capping layer 251 ; a first air gap 274 is formed in the bit line isolation layer, and at the same time After forming the second air gap 424 in the peripheral gate isolation layer, the following steps are also included:
  • auxiliary layer 30 covering the sidewall of the bit line isolation layer, as shown in FIG. 2H ;
  • the auxiliary layer 30 is removed to form a capacitive contact structure including the fourth conductive layer 31 and the first capacitive conductive layer 291 , as shown in FIG. 2J .
  • the auxiliary layer 30 can be removed to obtain the stepped capacitor. contact structure.
  • the width of the fourth conductive layer 31 is smaller than that of the top surface of the first capacitor conductive layer 291 (ie the first capacitor The width of the surface of the conductive layer 291 in contact with the fourth conductive layer 31 ).
  • the step-shaped capacitive contact structure helps to increase the contact area between the second capacitive conductive layer formed subsequently and the capacitive contact structure, thereby reducing the capacitive contact resistance.
  • the capacitor hole is the gap between adjacent bit lines 36 .
  • the following steps are further included:
  • a second capacitive conductive layer 32 covering the surface of the capacitive contact structure is formed, and a second peripheral conductive layer 44 covering the surface of the first peripheral conductive layer 292 is formed at the same time, as shown in FIG. 2K and FIG. 3I .
  • the first peripheral conductive layer outside the peripheral circuit contact portion 414 and part of the peripheral circuit contact portion 414 is removed.
  • layer 292 forming the first peripheral conductive layer 292 as shown in FIG. 3I.
  • a second dielectric layer 45 is deposited on the substrate surface of the peripheral region 41 , so that the second dielectric layer 45 covers the peripheral circuit contact portion 414 and the first peripheral conductive layer 292 .
  • the second dielectric layer 45 is etched, and the top surface of the first peripheral conductive layer 292 exposed in the second dielectric layer 45 is formed (that is, the first peripheral conductive layer 292 contacts away from the peripheral circuit) part 414) through holes.
  • the material of the second dielectric layer 45 may be an oxide material, such as silicon oxide. Then, a second capacitive conductive layer 32 covering the surface of the capacitive contact structure is formed, and at the same time a second peripheral conductive layer 44 that fills the through hole and covers the surface of the second dielectric layer 45 is formed, as shown in FIG. 2K and FIG. 3I is shown.
  • a third dielectric layer 33 covering both the second capacitive conductive layer 32 and the second peripheral conductive layer 44 may also be formed, and a fourth dielectric layer 34 located on the surface of the third dielectric layer 33 .
  • the material of the third dielectric layer 33 may be ACL (amorphous carbon), and the material of the fourth dielectric layer 34 may be an oxynitride material, such as silicon oxynitride.
  • the present application also provides a semiconductor memory.
  • the semiconductor memory provided by this specific embodiment can be formed by using the methods shown in FIGS. 1 , 2A-2L, and 3A-3I.
  • the specific structure of the semiconductor memory provided by this specific embodiment can refer to FIG. 2L and FIG. 3I .
  • the semiconductor memory provided by this specific embodiment includes:
  • the substrate includes a storage region 21 and a peripheral region 41 located outside the storage region 21 , and the substrate has a plurality of bit line contacts 212 and a plurality of capacitor contacts located in the storage region 21 inside the substrate 213, and the peripheral gate contact portion 413 and the peripheral circuit contact portion 414 located in the peripheral region 41;
  • bit lines 36 located above the storage region 21 and in contact with a plurality of the bit line contact portions 212 respectively;
  • peripheral gate 43 and at the same time above the peripheral region 41 and in contact with the peripheral gate contact 413;
  • bit line isolation layer covering at least the side walls of the bit line 36
  • peripheral gate isolation layer covering at least the sidewall of the peripheral gate 43;
  • the second air gap 424 is located in the outer gate isolation layer
  • the first capacitive conductive layer 291 is located above the storage region 21 and is in contact with the capacitive contact portion 213, and the first capacitive conductive layer 291 fills the gap between the adjacent bit lines 36;
  • the first peripheral conductive layer 292 is located above the peripheral region 41 and in contact with the peripheral circuit contact portion 414 , and the first peripheral conductive layer 292 covers the sidewall of the peripheral gate isolation layer.
  • the semiconductor memory further includes:
  • the bit line capping layer 251 is located on the top surface of the bit line 36, and the bit line isolation layer also covers the sidewall of the bit line capping layer 251;
  • the peripheral gate capping layer 252 is located on the top surface of the peripheral gate 43 , and the peripheral gate isolation layer also covers the sidewalls of the peripheral gate capping layer 252 .
  • the semiconductor memory further includes:
  • the fourth conductive layer 31 is located on the top surface of the first capacitive conductive layer 291.
  • the width of the fourth conductive layer 31 is smaller than that of the first capacitive conductive layer 291 in a direction parallel to the surface of the substrate.
  • the semiconductor memory further includes:
  • the second capacitive conductive layer 32 covers the surface of the fourth conductive layer 31 and the surface of the first capacitive conductive layer 291;
  • the second peripheral conductive layer 44 covers the surface of the first peripheral conductive layer 292 .
  • the bit line isolation layer includes a first sub bit line isolation layer 271 and a third sub bit line isolation layer 273 , and the first air gap 274 is located between the first sub bit line isolation layer 271 and the third sub bit line isolation layer 273 . between the third sub-bit line isolation layers;
  • the peripheral gate isolation layer includes a first sub peripheral gate isolation layer 421 and a third sub peripheral gate isolation layer 423, and the second air gap 424 is located between the first sub peripheral gate isolation layer 421 and the third sub peripheral gate isolation layer 423. between the third sub-peripheral gate isolation layers 423 .
  • the semiconductor memory and the method for forming the same provided by this specific embodiment are formed by forming the bit line in the storage region, forming the peripheral gate in the peripheral region, and simultaneously forming the bit line covering the side wall of the bit line and having the first air gap
  • the isolation layer and the peripheral gate isolation layer covering the sidewall of the peripheral gate and having the second air gap simplify the manufacturing steps of the semiconductor memory and reduce the manufacturing cost of the semiconductor memory.
  • the formation of the first air gap and the second air gap greatly reduces the parasitic capacitance of the bit line and the peripheral gate, and improves the electrical performance of the semiconductor memory.

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Abstract

本申请提供的半导体存储器的形成方法包括如下步骤：提供衬底，所述衬底包括存储区域以及位于所述存储区域外部的外围区域，所述存储区域具有多个位线接触部和多个电容接触部、所述外围区域具有外围栅极接触部和外围电路接触部；形成多条位线、并同时形成外围栅极；形成位线隔离层、并同时形成外围栅极隔离层；形成与所述电容接触部接触的第一电容导电层、并同时形成与所述外围电路接触部接触的第一外围导电层；于所述位线隔离层内形成第一空气隙、并同时于所述外围栅极隔离层内形成第二空气隙。本申请简化了半导体存储器的制造步骤，并极大的降低了位线和外围栅极的寄生电容。

Description

半导体存储器及其形成方法
相关申请引用说明
本申请要求于2021年3月19日递交的中国专利申请号202110294504.9、申请名为“半导体存储器及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体存储器及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体结构，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
动态随机存储器的发展追求高速度、高集成密度、低功耗等。随着半导体器件结构尺寸的微缩，尤其是在关键尺寸小于20nm的DRAM制造过程中，位线的材质、形貌、尺寸以及电性能等各方面有了更高的要求，例如更宽的带宽以保证绝缘性能良好、更低的介电常数以确保寄生电容小、耦合效应小，基于上述目的，各种各样的低介电常数材质被广泛的应用于半导体制造中。为了形成性能较佳的位线，将存储区域的位线与外围区域的外围结构器件分开制造，所述外围结构包括外围栅极(peripheral gate)、外围电路peripheral circuit)等，各自的制造步骤相当繁琐，制造成本较高，且制成之后的位线与逻辑门器件的性能也有待提高。
因此，如何简化半导体存储器的制造步骤，从而降低半导体存储器的制造成本，改善半导体存储器的性能，是当前亟待解决的技术问题。
发明内容
本申请一些实施例提供的一种半导体存储器及其形成方法，用于解决半导 体存储器制造步骤复杂、制造成本较高的问题，并改善半导体存储器的性能。
根据一些实施例，本申请提供了一种半导体存储器的形成方法，包括如下步骤：
提供衬底，所述衬底包括存储区域以及位于所述存储区域外部的外围区域，所述衬底内部具有位于所述存储区域的多个位线接触部和多个电容接触部、以及位于所述外围区域的外围栅极接触部和外围电路接触部；
于所述存储区域上方形成与多个所述位线接触部分别接触的多条位线、并同时于所述外围区域上方形成与所述外围栅极接触部接触的外围栅极；
形成至少覆盖于所述位线侧壁的位线隔离层、并同时形成至少覆盖于所述外围栅极侧壁的外围栅极隔离层；
于所述存储区域上方形成与所述电容接触部接触的第一电容导电层、并同时于所述外围区域上方形成与所述外围电路接触部接触的第一外围导电层，所述第一电容导电层填充满相邻所述位线之间的间隙，所述第一外围导电层覆盖所述外围栅极隔离层的侧壁；
于所述位线隔离层内形成第一空气隙、并同时于所述外围栅极隔离层内形成第二空气隙。
根据另一些实施例，本申请还提供了一种半导体存储器，包括：
衬底，所述衬底包括存储区域以及位于所述存储区域外部的外围区域，所述衬底内部具有位于所述存储区域的多个位线接触部和多个电容接触部、以及位于所述外围区域的外围栅极接触部和外围电路接触部；
多条位线，位于所述存储区域上方且与多个所述位线接触部分别接触；
外围栅极，并同时于所述外围区域上方且与所述外围栅极接触部接触；
位线隔离层，至少覆盖于所述位线侧壁；
外围栅极隔离层，至少覆盖于所述外围栅极侧壁；
第一空气隙，位于所述位线隔离层内；
第二空气隙，位于所述外围栅极隔离层内；
第一电容导电层，位于所述存储区域上方且与所述电容接触部接触、所述第一电容导电层填充满相邻所述位线之间的间隙；
第一外围导电层，位于所述外围区域上方且与所述外围电路接触部接触，所述第一外围导电层覆盖所述外围栅极隔离层的侧壁。
本申请一些实施例提供的半导体存储器及其形成方法，通过在存储区域形成位线的同时、在外围区域形成外围栅极，并同时形成覆盖于位线侧壁、且具有第一空气隙的位线隔离层以及覆盖于外围栅极侧壁、且具有第二空气隙的外围栅极隔离层，简化了半导体存储器的制造步骤，降低了半导体存储器的制造成本。而且，第一空气隙和第二空气隙的形成，极大的降低了位线和外围栅极的寄生电容，改善了半导体存储器的电学性能。
附图说明
附图1是本申请具体实施方式中半导体存储器的形成方法流程图；
附图2A-2L是本申请具体实施方式在形成半导体存储器的过程中存储区域的截面示意图；
附图3A-3I是本申请具体实施方式在形成半导体存储器的过程中外围区域的截面示意图。
具体实施方式
下面结合附图对本申请提供的半导体存储器及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体存储器的形成方法，附图1是本申请具体实施方式中半导体存储器的形成方法流程图，附图2A-2L是本申请具体实施方式在形成半导体存储器的过程中存储区域的截面示意图，附图3A-3I是本申请具体实施方式在形成半导体存储器的过程中外围区域的截面示意图。如图1、图2A-图2L、图3A-图3I所示，本具体实施方式提供的半导体存储器的形成方法，包括如下步骤：
步骤S11，提供衬底，所述衬底包括存储区域21以及位于所述存储区域21外部的外围区域41，所述衬底内部具有位于所述存储区域21的多个位线接触部212和多个电容接触部213、以及位于所述外围区域41的外围栅极接触部413和外围电路接触部414，如图2A和图3A所示。
具体来说，所述衬底可以是但不限于硅衬底。所述衬底包括所述存储区域 21和位于所述存储区域外围的所述外围区域41，所述外围区域41可以仅位于所述存储区域21的一侧，也可以环绕所述存储区域21分布。所述存储区域21用于数据信息的存储，所述外围区域41包括CMOS电路等结构，用于向所述存储区域21传输控制信号。所述衬底内的所述存储区域21包括多个所述位线接触部212和多个所述电容接触部213，所述位线接触部212与所述电容接触部213在所述衬底内部交替排布，所述位线接触部212用于与后续形成的位线电连接，所述电容接触部213用于与后续形成的电容接触结构电连接。所述衬底内的所述外围区域41包括所述外围栅极接触部413和所述外围电路接触部414，所述外围栅极接触部413用于与后续形成的外围栅极电连接，所述外围电路接触部414用于与后续形成的外围电路电连接。
步骤S12，于所述存储区域21上方形成与多个所述位线接触部212分别接触的多条位线36、并同时于所述外围区域41上方形成与所述外围栅极接触部413接触的外围栅极43，如图2C和图3C所示。
在一些实施例中，于所述存储区域21上方形成与多个所述位线接触部212分别接触的多条位线26、并同时于所述外围区域41上方形成与所述外围栅极接触部413接触的外围栅极43的具体步骤包括：
形成位线材料层于所述衬底表面，所述位线材料层至少覆盖所述存储区域21的所述位线接触部212和所述外围区域41的所述外围栅极接触部413，如图2B和图3B所示；
图案化所述位线材料层23，于所述存储区域21形成与所述位线接触部212接触的位线26、并同时于所述外围区域41形成与所述外围栅极接触部413接触的外围栅极43，如图2C和图3C所示。
为了降低位线与所述位线接触部之间以及外围栅极与外围栅极接触部之间的接触电阻，提高半导体存储器的电性能，在一些实施例中，形成位线材料层于所述衬底表面的具体步骤包括：
形成第一导电层23于所述衬底表面，所述第一导电层23至少覆盖所述存储区域21的所述位线接触部212和所述外围区域41的所述外围栅极接触部413，如图2A和图3A所示；
形成覆盖所述第一导电层23的第二导电层24，如图2B和图3B所示；
形成覆盖所述第二导电层24的第一介质层25，如图2B和图3B所示。
在一些实施例中，图案化所述位线材料层的具体步骤包括：
刻蚀所述第一介质层25、所述第二导电层24和所述第一导电层23，于所述存储区域21形成与所述位线接触部212接触的位线26以及位于所述位线26顶面的位线盖层251、并同时于所述外围区域41形成与所述外围栅极接触部413接触的外围栅极43以及覆盖于所述外围栅极43顶面的外围栅极盖层252。
具体来说，如图2A和图3A所示，沉积所述第一导电层23于所述衬底表面，所述第一导电层23覆盖所述衬底的所述存储区域21的所述位线接触部212和所述外围区域41的所述外围栅极接触部413。所述第一导电层23可以是连续覆盖所述衬底的整个表面，也可以覆盖且仅覆盖所述存储区域21的所述位线接触部212和所述外围区域41的所述外围栅极接触部413。之后，沉积所述第二导电层24于所述第一导电层23表面。所述第二导电层24的材料可以与所述第一导电层23的材料不同，例如所述第一导电层23的材料为多晶硅，所述第二导电层24的材料为金属材料(例如钨)。接着，沉积所述第一介质层25于所述第二导电层24表面，形成如图2B和图3B所示的结构。所述第一介质层25的材料可以是但不限于氮化物材料(例如氮化硅)。所述第一导电层23、所述第二导电层24和所述第一介质层25共同构成所述位线材料层。本领域技术人员也可以根据实际需要选择其他材料或者其他层数的堆叠层作为所述位线材料层。
在所述存储区域21和所述外围区域41形成所述位线材料层之后，形成覆盖所述位线材料层的第一掩模层26。图案化所述第一掩模层26之后，刻蚀所述位线材料层，同时形成位线36和所述外围栅极43，并同时形成位于所述位线36表面的位线盖层251和位于所述外围栅极43表面的外围栅极盖层252。所述位线36包括位线接触层231和覆盖于所述位线接触层231表面的位线主体层241。所述位线接触层231由刻蚀所述位线材料层之后残留于所述存储区域21的所述第一导电层23形成，所述位线主体层241由刻蚀所述位线材料层之后残留于所述存储区域21的所述第二导电层24形成。所述外围栅极43包 括外围栅极接触层232和覆盖于所述外围栅极接触层232表面的外围栅极主体层242。所述外围栅极接触层232由刻蚀所述位线材料层之后残留于所述外围区域41的所述第一导电层23形成，所述外围栅极主体层242由刻蚀所述位线材料层之后残留于所述外围区域41的所述第二导电层24形成。
步骤S13，形成至少覆盖于所述位线36侧壁的位线隔离层、并同时形成至少覆盖于所述外围栅极43侧壁的外围栅极隔离层，如图2C和图3C所示。
在一些实施例中，形成至少覆盖于所述位线36侧壁的位线隔离层、并同时形成至少覆盖于所述外围栅极43侧壁的外围栅极隔离层的具体步骤包括：
形成至少覆盖所述位线36侧壁、所述位线盖层251侧壁、所述外围栅极43侧壁和所述外围栅极盖层252侧壁的第一隔离层；
形成覆盖所述第一隔离层的第二隔离层；
形成覆盖所述第二隔离层的第三隔离层，覆盖所述位线36侧壁和所述位线盖层251侧壁的所述第一隔离层、所述第二隔离层和所述第三隔离层作为所述位线隔离层、覆盖所述外围栅极43侧壁和所述外围栅极盖层252侧壁的所述第一隔离层、所述第二隔离层和所述第三隔离层作为所述外围栅极隔离层。
具体来说，依次沉积所述第一隔离层、所述第二隔离层和所述第三隔离层于所述位线36侧壁、所述位线盖层251侧壁和顶面、所述外围栅极43侧壁、以及所述外围栅极盖层252侧壁和顶面。之后，刻蚀所述第一隔离层、所述第二隔离层和所述第三隔离层，残留于所述位线36侧壁和所述位线盖层251侧壁的所述第一隔离层(即第一子位线隔离层271)、所述第二隔离层(即第二子位线隔离层272)和所述第三隔离层(即第三子位线隔离层273)作为所述位线隔离层、覆盖所述外围栅极43侧壁和所述外围栅极盖层252侧壁的所述第一隔离层(即第一子外围栅极隔离层421)、所述第二隔离层(即第二子外围栅极隔离层422)和所述第三隔离层(即第三子外围栅极隔离层423)作为所述外围栅极隔离层。所述第一隔离层和所述第三隔离层的材料可以相同，例如均为氮化物材料(例如氮化硅)，所述第二隔离层的材料可以为氧化物材料(例如氧化硅)。所述第二隔离层应该与所述第一隔离层、以及所述第三隔离层之间具有较高的刻蚀选择比，便于后续去除所述第二隔离层，形成空气隙。
步骤S14，于所述存储区域21上方形成与所述电容接触部213接触的第一电容导电层291、并同时于所述外围区域41上方形成与所述外围电路接触部414接触的第一外围导电层292，所述第一电容导电层291填充满相邻所述位线36之间的间隙，所述第一外围导电层292覆盖所述外围栅极隔离层的侧壁，如图2F和图3F所示。
在一些实施例中，于所述存储区域21上方形成与所述电容接触部213接触的第一电容导电层291、并同时于所述外围区域41上方形成与所述外围电路接触部414接触的第一外围导电层292的具体步骤包括：
刻蚀所述衬底的所述存储区域21和所述外围区域41，同时暴露所述电容接触部213和所述外围电路接触部414，如图2D和图3D所示；
形成填充满相邻所述位线36之间的间隙、并覆盖所述电容接触部213、所述外围电路接触部414、所述位线隔离层和所述外围栅极隔离层的第三导电层29，如图2E和图3E所示；
去除部分所述第三导电层29，使得所述第三导电层29的顶面位于所述位线盖层251和所述外围栅极盖层252之下，残留于所述存储区域21的所述第三导电层29作为所述第一电容导电层291、残留所述外围区域41的所述第三导电层29作为所述第一外围导电层292。
具体来说，刻蚀所述衬底的所述存储区域21和所述外围区域41，同时暴露所述电容接触部213和所述外围电路接触部414，在刻蚀所述存储区域21时，在所述衬底中形成凹槽28。之后，沉积所述第三导电层29，使得所述第三导电层29填充满所述凹槽28和相邻所述位线36之间的间隙、并盖所述电容接触部213、所述外围电路接触部414、所述位线隔离层的表面和所述外围栅极隔离层的表面。接着，刻蚀部分所述第三导电层29，于所述存储区域21形成所述第一电容导电层291、并同时于所述外围区域41形成所述外围导电层292。所述第三导电层29的材料可以是但不限于多晶硅。
步骤S15，于所述位线隔离层内形成第一空气隙274、并同时于所述外围栅极隔离层内形成第二空气隙424，如图2G和图3H所示。
在一些实施例中，于所述位线隔离层内形成第一空气隙274、并同时于所 述外围栅极隔离层内形成第二空气隙424的具体步骤包括：
去除所述第二隔离层，于所述位线36侧壁和所述位线盖层251侧壁的所述第一隔离层和所述第三隔离层之间形成所述第一空气隙274、并同时于所述外围栅极43侧壁和所述外围栅极盖层252侧壁的所述第一隔离层和所述第三隔离层之间形成所述第二空气隙424。
在一些实施例中，所述第三隔离层还覆盖所述位线盖层251的顶面和所述外围栅极盖层252的顶面；去除所述第二隔离层的具体步骤包括：
去除覆盖于所述位线盖层251和所述外围栅极盖层252顶面的所述第三隔离层，暴露所述第二隔离层；
刻蚀掉全部的所述第二隔离层。
具体来说，在形成所述第一电容导电层291和所述第一外围导电层292之后，同步刻蚀所述第三子位线隔离层273和所述第三子外围栅极隔离层423，暴露所述第二子位线隔离层272和所述第二子外围栅极隔离层422，如图2F和图3G所示。之后，采用湿法刻蚀工艺去除所述位线隔离层中的所述第二子位线隔离层272和所述外围栅极隔离层中的所述第二子外围栅极隔离层422，同时形成所述第一空气隙274和所述第二空气隙424。
在本具体实施方式中，通过形成所述第一空气隙274和所述第二空气隙424，能够大幅度的减少所述位线36和所述外围栅极43的寄生电容，并降低所述第一电容导电层291于所述电容接触部213之间的接触电阻。而且，由于在直接填充所述第三导电层29、并形成所述第一电容导电层291和所述第一外围导电层292之后，通过刻蚀工艺直接形成所述第一空气隙274和所述第二空气隙424，可以简化空气隙的形成步骤，提高了半导体制程的效率。
在一些实施例中，所述第一电容导电层291的顶面位于所述位线盖层251的顶面之下；于所述位线隔离层内形成第一空气隙274、并同时于所述外围栅极隔离层内形成第二空气隙424之后，还包括如下步骤：
形成覆盖所述位线隔离层侧壁的辅助层30，如图2H所示；
形成覆盖所述第一电容导电层291顶面和所述辅助层30侧壁的第四导电层31，如图2I所示；
去除所述辅助层30，形成包括所述第四导电层31和所述第一电容导电层291的电容接触结构，如图2J所示。
具体来说，通过在所述位线隔离层的侧壁形成所述辅助层30之后、再沉积所述第四导电层31，可以再去除所述辅助层30之后，得到台阶状的所述电容接触结构。在台阶状的所述电容接触结构中，在沿平行于所述衬底的方向上，所述第四导电层31的宽度小于所述第一电容导电层291顶面(即所述第一电容导电层291于所述第四导电层31接触的表面)的宽度。台阶状的所述电容接触结构有助于增大后续形成的第二电容导电层与所述电容接触结构之间的接触面积，从而降低电容接触电阻。在本具体试试方式中，所述电容孔即为相邻所述位线36之间的间隙。
在一些实施例中，形成包括所述第四导电层31和所述第一电容导电层291的电容接触结构之后，还包括如下步骤：
形成覆盖所述电容接触结构表面的第二电容导电层32、并同时形成覆盖于所述第一外围导电层292表面的第二外围导电层44，如图2K和图3I所示。
具体来说，在形成如图3H所示的所述第一外围导电层292之后，去除所述外围电路接触部414之外、以及部分所述外围电路接触部414上方的所述第一外围导电层292，形成如图3I所示的所述第一外围导电层292。之后，沉积第二介质层45于所述外围区域41的所述衬底表面，使得所述第二介质层45覆盖所述外围电路接触部414和所述第一外围导电层292。接着，刻蚀所述第二介质层45，在所述第二介质层45中形成暴露所述第一外围导电层292的顶面(即所述第一外围导电层292背离所述外围电路接触部414的表面)的通孔。所述第二介质层45的材料可以是氧化物材料，例如氧化硅。然后，形成覆盖所述电容接触结构表面的第二电容导电层32、并同时形成填充满所述通孔并覆盖所述第二介质层45表面的第二外围导电层44，如图2K和图3I所示。
在形成所述第二电容导电层32和所述第二外围导电层44之后，还可以形成同时覆盖所述第二电容导电层32和所述第二外围导电层44的第三介质层33，以及位于所述第三介质层33表面的第四介质层34。所述第三介质层33的材料可以是ACL(无定型碳)，所述第四介质层34的材料可以是氮氧化物材 料，例如氮氧化硅。
不仅如此，本申请还提供了一种半导体存储器。本具体实施方式提供的所述半导体存储器可以采用如图1、图2A-图2L和图3A-图3I所示的方法形成。本具体实施方式提供的半导体存储器的具体结构可参见图2L和图3I。如图2A-图2L和图3A-图3I所示，本具体实施方式提供的半导体存储器，包括：
衬底，所述衬底包括存储区域21以及位于所述存储区域21外部的外围区域41，所述衬底内部具有位于所述存储区域21的多个位线接触部212和多个电容接触部213、以及位于所述外围区域41的外围栅极接触部413和外围电路接触部414；
多条位线36，位于所述存储区域21上方且与多个所述位线接触部212分别接触；
外围栅极43，并同时于所述外围区域41上方且与所述外围栅极接触部413接触；
位线隔离层，至少覆盖于所述位线36侧壁；
外围栅极隔离层，至少覆盖于所述外围栅极43侧壁；
第一空气隙274，位于所述位线隔离层内；
第二空气隙424，位于所述外围栅极隔离层内；
第一电容导电层291，位于所述存储区域21上方且与所述电容接触部213接触、所述第一电容导电层291填充满相邻所述位线36之间的间隙；
第一外围导电层292，位于所述外围区域41上方且与所述外围电路接触部414接触，所述第一外围导电层292覆盖所述外围栅极隔离层的侧壁。
在一些实施例中，所述半导体存储器还包括：
位线盖层251，位于所述位线36顶面，所述位线隔离层还覆盖所述位线盖层251的侧壁；
外围栅极盖层252，位于所述外围栅极43顶面，所述外围栅极隔离层还覆盖所述外围栅极盖层252的侧壁。
在一些实施例中，所述半导体存储器还包括：
第四导电层31，位于所述第一电容导电层291顶面，在沿平行于所述衬底 表面的方向上，所述第四导电层31的宽度小于所述第一电容导电层291。
在一些实施例中，所述半导体存储器还包括：
第二电容导电层32，覆盖所述第四导电层31表面和所述第一电容导电层291表面；
第二外围导电层44，覆盖于所述第一外围导电层292表面。
在一些实施例中，所述位线隔离层包括第一子位线隔离层271和第三子位线隔离层273，所述第一空气隙274位于所述第一子位线隔离层271和所述第三子位线隔离层之间；
所述外围栅极隔离层包括第一子外围栅极隔离层421和第三子外围栅极隔离层423，所述第二空气隙424位于所述第一子外围栅极隔离层421和所述第三子外围栅极隔离层423之间。
本具体实施方式提供的半导体存储器及其形成方法，通过在存储区域形成位线的同时、在外围区域形成外围栅极，并同时形成覆盖于位线侧壁、且具有第一空气隙的位线隔离层以及覆盖于外围栅极侧壁、且具有第二空气隙的外围栅极隔离层，简化了半导体存储器的制造步骤，降低了半导体存储器的制造成本。而且，第一空气隙和第二空气隙的形成，极大的降低了位线和外围栅极的寄生电容，改善了半导体存储器的电学性能。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种半导体存储器的形成方法，包括如下步骤：
    提供衬底，所述衬底包括存储区域以及位于所述存储区域外部的外围区域，所述衬底内部具有位于所述存储区域的多个位线接触部和多个电容接触部、以及位于所述外围区域的外围栅极接触部和外围电路接触部；
    于所述存储区域上方形成与多个所述位线接触部分别接触的多条位线、并同时于所述外围区域上方形成与所述外围栅极接触部接触的外围栅极；
    形成至少覆盖于所述位线侧壁的位线隔离层、并同时形成至少覆盖于所述外围栅极侧壁的外围栅极隔离层；
    于所述存储区域上方形成与所述电容接触部接触的第一电容导电层、并同时于所述外围区域上方形成与所述外围电路接触部接触的第一外围导电层，所述第一电容导电层填充满相邻所述位线之间的间隙，所述第一外围导电层覆盖所述外围栅极隔离层的侧壁；
    于所述位线隔离层内形成第一空气隙、并同时于所述外围栅极隔离层内形成第二空气隙。
  2. 根据权利要求1所述的半导体存储器的形成方法，其中，于所述存储区域上方形成与多个所述位线接触部分别接触的多条位线、并同时于所述外围区域上方形成与所述外围栅极接触部接触的外围栅极的具体步骤包括：
    形成位线材料层于所述衬底表面，所述位线材料层至少覆盖所述存储区域的所述位线接触部和所述外围区域的所述外围栅极接触部；
    图案化所述位线材料层，于所述存储区域形成与所述位线接触部接触的位线、并同时于所述外围区域形成与所述外围栅极接触部接触的外围栅极。
  3. 根据权利要求2所述的半导体存储器的形成方法，其中，形成位线材料层于所述衬底表面的具体步骤包括：
    形成第一导电层于所述衬底表面，所述第一导电层至少覆盖所述存储区域的所述位线接触部和所述外围区域的所述外围栅极接触部；
    形成覆盖所述第一导电层的第二导电层；
    形成覆盖所述第二导电层的第一介质层。
  4. 根据权利要求3所述的半导体存储器的形成方法，其中，图案化所述位线材料层的具体步骤包括：
    刻蚀所述第一介质层、所述第二导电层和所述第一导电层，于所述存储区域形成与所述位线接触部接触的位线以及位于所述位线顶面的位线盖层、并同时于所述外围区域形成与所述外围栅极接触部接触的外围栅极以及覆盖于所述外围栅极顶面的外围栅极盖层。
  5. 根据权利要求4所述的半导体存储器的形成方法，其中，形成至少覆盖于所述位线侧壁的位线隔离层、并同时形成至少覆盖于所述外围栅极侧壁的外围栅极隔离层的具体步骤包括：
    形成至少覆盖所述位线侧壁、所述位线盖层侧壁、所述外围栅极侧壁和所述外围栅极盖层侧壁的第一隔离层；
    形成覆盖所述第一隔离层的第二隔离层；
    形成覆盖所述第二隔离层的第三隔离层，覆盖所述位线侧壁和所述位线盖层侧壁的所述第一隔离层、所述第二隔离层和所述第三隔离层作为所述位线隔离层、覆盖所述外围栅极侧壁和所述外围栅极盖层侧壁的所述第一隔离层、所述第二隔离层和所述第三隔离层作为所述外围栅极隔离层。
  6. 根据权利要求5所述的半导体存储器的形成方法，其中，于所述位线隔离层内形成第一空气隙、并同时于所述外围栅极隔离层内形成第二空气隙的具体步骤包括：
    去除所述第二隔离层，于所述位线侧壁和所述位线盖层侧壁的所述第一隔离层和所述第三隔离层之间形成所述第一空气隙、并同时于所述外围栅极侧壁和所述外围栅极盖层侧壁的所述第一隔离层和所述第三隔离层之间形成所述第二空气隙。
  7. 根据权利要求6所述的半导体存储器的形成方法，其中，所述第一隔离层还覆盖所述位线盖层的顶面和所述外围栅极盖层的顶面；去除所述第二隔离层的具体步骤包括：
    去除覆盖于所述位线盖层和所述外围栅极盖层顶面的所述第三隔离层，暴 露所述第二隔离层；
    刻蚀掉全部的所述第二隔离层。
  8. 根据权利要求1所述的半导体存储器的形成方法，其中，于所述存储区域上方形成与所述电容接触部接触的第一电容导电层、并同时于所述外围区域上方形成与所述外围电路接触部接触的第一外围导电层的具体步骤包括：
    刻蚀所述衬底的所述存储区域和所述外围区域，同时暴露所述电容接触部和所述外围电路接触部；
    形成填充满相邻所述位线之间的间隙、并覆盖所述电容接触部、所述外围电路接触部、所述位线隔离层和所述外围栅极隔离层的第三导电层；
    去除部分所述第三导电层，使得所述第三导电层的顶面位于所述位线盖层和所述外围栅极盖层之下，残留于所述存储区域的所述第三导电层作为所述第一电容导电层、残留所述外围区域的所述第三导电层作为所述第一外围导电层。
  9. 根据权利要求8所述的半导体存储器的形成方法，其中，所述第一电容导电层的顶面位于所述位线盖层的顶面之下；于所述位线隔离层内形成第一空气隙、并同时于所述外围栅极隔离层内形成第二空气隙之后，还包括如下步骤：
    形成覆盖所述位线隔离层侧壁的辅助层；
    形成覆盖所述第一电容导电层顶面和所述辅助层侧壁的第四导电层；
    去除所述辅助层，形成包括所述第四导电层和所述第一电容导电层的电容接触结构。
  10. 根据权利要求9所述的半导体存储器的形成方法，其中，形成包括所述第四导电层和所述第一电容导电层的电容接触结构之后，还包括如下步骤：
    形成覆盖所述电容接触结构表面的第二电容导电层、并同时形成覆盖于所述第一外围导电层表面的第二外围导电层。
  11. 一种半导体存储器，包括：
    衬底，所述衬底包括存储区域以及位于所述存储区域外部的外围区域，所述衬底内部具有位于所述存储区域的多个位线接触部和多个电容接触部、以及位于所述外围区域的外围栅极接触部和外围电路接触部；
    多条位线，位于所述存储区域上方且与多个所述位线接触部分别接触；
    外围栅极，并同时于所述外围区域上方且与所述外围栅极接触部接触；
    位线隔离层，至少覆盖于所述位线侧壁；
    外围栅极隔离层，至少覆盖于所述外围栅极侧壁；
    第一空气隙，位于所述位线隔离层内；
    第二空气隙，位于所述外围栅极隔离层内；
    第一电容导电层，位于所述存储区域上方且与所述电容接触部接触、所述第一电容导电层填充满相邻所述位线之间的间隙；
    第一外围导电层，位于所述外围区域上方且与所述外围电路接触部接触，所述第一外围导电层覆盖所述外围栅极隔离层的侧壁。
  12. 根据权利要求11所述的半导体存储器，还包括：
    位线盖层，位于所述位线顶面，所述位线隔离层还覆盖所述位线盖层的侧壁；
    外围栅极盖层，位于所述外围栅极顶面，所述外围栅极隔离层还覆盖所述外围栅极盖层的侧壁。
  13. 根据权利要求11所述的半导体存储器，还包括：
    第四导电层，位于所述第一电容导电层顶面，在沿平行于所述衬底表面的方向上，所述第四导电层的宽度小于所述第一电容导电层。
  14. 根据权利要求13所述的半导体存储器，还包括：
    第二电容导电层，覆盖所述第四导电层表面和所述第一电容导电层表面；
    第二外围导电层，覆盖于所述第一外围导电层表面。
  15. 根据权利要求11所述的半导体存储器，其中，所述位线隔离层包括第一子位线隔离层和第三子位线隔离层，所述第一空气隙位于所述第一子位线隔离层和所述第三子位线隔离层之间；
    所述外围栅极隔离层包括第一子外围栅极隔离层和第三子外围栅极隔离层，所述第二空气隙位于所述第一子外围栅极隔离层和所述第三子外围栅极隔离层之间。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130248950A1 (en) * 2012-03-20 2013-09-26 Samsung Electronics Co., Ltd. Semiconductor devices and method of manufacturing the same
CN103383935A (zh) * 2012-05-03 2013-11-06 三星电子株式会社 半导体器件及其制造方法
CN108389861A (zh) * 2017-02-03 2018-08-10 联华电子股份有限公司 半导体元件及其形成方法
CN109216383A (zh) * 2017-07-07 2019-01-15 联华电子股份有限公司 半导体存储装置的形成方法
CN112951769A (zh) * 2021-03-19 2021-06-11 长鑫存储技术有限公司 半导体存储器及其形成方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363702B1 (ko) * 2000-12-29 2002-12-05 주식회사 하이닉스반도체 반도체장치의 스토리지노드 전극용 콘택 플러그 및 그제조 방법
TW480663B (en) * 2001-02-15 2002-03-21 Winbond Electronics Corp Method for combining self-aligned contact processing and salicide processing
US7462534B2 (en) * 2005-08-02 2008-12-09 Micron Technology, Inc. Methods of forming memory circuitry
KR20140130594A (ko) * 2013-05-01 2014-11-11 삼성전자주식회사 콘택 플러그를 포함하는 반도체 소자 및 그 제조 방법
KR20160067618A (ko) * 2014-12-04 2016-06-14 삼성전자주식회사 트랜지스터들을 포함하는 반도체 소자

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130248950A1 (en) * 2012-03-20 2013-09-26 Samsung Electronics Co., Ltd. Semiconductor devices and method of manufacturing the same
CN103383935A (zh) * 2012-05-03 2013-11-06 三星电子株式会社 半导体器件及其制造方法
CN108389861A (zh) * 2017-02-03 2018-08-10 联华电子股份有限公司 半导体元件及其形成方法
CN109216383A (zh) * 2017-07-07 2019-01-15 联华电子股份有限公司 半导体存储装置的形成方法
CN112951769A (zh) * 2021-03-19 2021-06-11 长鑫存储技术有限公司 半导体存储器及其形成方法

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