US20060199332A1 - Method of forming storage node of capacitor in semiconductor memory, and structure therefor - Google Patents
Method of forming storage node of capacitor in semiconductor memory, and structure therefor Download PDFInfo
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- US20060199332A1 US20060199332A1 US11/419,314 US41931406A US2006199332A1 US 20060199332 A1 US20060199332 A1 US 20060199332A1 US 41931406 A US41931406 A US 41931406A US 2006199332 A1 US2006199332 A1 US 2006199332A1
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- 238000003860 storage Methods 0.000 title claims abstract description 98
- 239000003990 capacitor Substances 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title description 38
- 239000010410 layer Substances 0.000 claims abstract description 108
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000009413 insulation Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 abstract description 23
- 125000006850 spacer group Chemical group 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
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- 238000001312 dry etching Methods 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
Definitions
- the present invention relates to semiconductor devices, and more particularly, to a method of forming a storage node of capacitor in a semiconductor memory such as a DRAM (Dynamic Random Access Memory) and a structure thereof.
- a semiconductor memory such as a DRAM (Dynamic Random Access Memory) and a structure thereof.
- a memory cell of DRAM is generally constructed of one access transistor and one storage capacitor.
- the capacitor is largely classified as a laminated type or a trench type depending on its formed position on a semiconductor substrate.
- Capacitors are generally composed of a storage node as a lower electrode node and a plate node as an upper electrode. High integration causes the bottom critical dimension (CD) of the storage node to be too small which causes a leaning phenomenon resulting in the collapse of the storage node.
- CD bottom critical dimension
- First is the method of increasing the bottom CD of straight type storage node.
- Second is the a method of lowering the height of storage node.
- the straight type method is undesirable because it is difficult to increase the bottom CD after a design rule was first decided, and the latter method is undesirable because it is unlikely to obtain the desired capacitance.
- the former method was recently improved to provide a larger bottom CD and reduce the occurrence rate of the leaning phenomenon within a limited area.
- this improved method and in forming the storage node of the capacitor, an active region, a gate, a bit line contact, a storage node contact or buried contact, and bit line patterns are formed in a diagonal direction slightly slanted as compared with the existing straight structure, and thereon, the capacitor storage node is formed.
- This improved method significantly increases the bottom CD of the storage node as compared with the storage node of the existing straight type, and this is known in this field as a diagonal structure. However, this diagonal structure has severely complicated manufacturing processes in forming the storage node.
- a new method for forming a storage node of square type was recently developed which shared advantages of the straight structure and the diagonal structure.
- an active region, a gate, a bit line and a capacitor storage node contact etc. are formed by the existing straight structure.
- a buffer layer is formed, and a contact is formed in the buffer layer, to thus connect the capacitor storage node of square type with a capacitor storage node contact of the straight structure.
- This new method has been regarded as increasing the storage node of the square type so that the bottom CD of the capacitor storage node is largely increased to about twice that of the storage node of the straight type based on the straight structure.
- FIGS. 1 through 6 The method of manufacturing the storage node of square type in the prior art will be described referring to FIGS. 1 through 6 , as follows, only to provide a thorough understanding of the present invention to be described later.
- FIG. 1 is a plan view illustrating a disposed relationship for storage nodes of capacitor based on a square type in a semiconductor memory according to an example of the prior art.
- FIGS. 2 to 6 are sectional views showing sequential processes in manufacturing the storage node referred to FIG. 1 .
- FIG. 1 vertically on the drawing, six word line patterns 13 as gates of a plurality of access transistors are formed, and horizontally on the drawing, four bit line patterns 16 connected to drains of the access transistors are formed.
- Storage nodes 23 of square type of the capacitors form an oblong structure in a diagonal direction to the bit line patterns 16 and the word line patterns 13 .
- each contact 17 of the storage node of capacitor and its lower structure are formed by a straight structure as the afore-mentioned.
- a reference number 14 indicates a bit line contact for connecting a bit line with a drain, and 14 a designates a bit line pad.
- FIGS. 2 to 6 are sectional views taken along A-A′ and B-B′ cutting lines shown in FIG. 1 .
- FIGS. 2 through 6 cross-sectional views taken along A-A′ cutting line direction of FIG. 1 , namely, the direction of a word line connected to a gate of access transistor, are illustrated per process.
- FIGS. 2 to 6 cross-sectional views taken along B-B′ cutting line direction of FIG. 1 , namely, the direction of a bit line connected to a drain of the access transistor, are illustrated per process.
- FIG. 2 illustrates a structure before forming a storage node of capacitor having a square type in a DRAM based on a capacitor over bitline (COB) structure.
- a device separate layer 3 is formed on a determined region of a semiconductor substrate 11 to define a plurality of active regions.
- a gate oxide layer 5 is formed on the active regions.
- a plurality of parallel word line patterns 13 traversing the active regions are formed.
- the word line pattern 13 contains a word line 7 b and a capping layer pattern 7 c laminated sequentially.
- An impurity ion is implanted into the active regions by using the word line pattern 13 and the device separate layer 3 as an ion implantation mask, to form impurity regions 4 s , 4 d .
- the active impurity regions 4 d between one pair of word line patterns 13 traversing the respective active regions are pertinent to a common drain region of a DRAM cell transistor. Further, the impurity region 4 s formed on both sides of each common drain region 4 d is pertinent to a source region of the DRAM cell transistor.
- a word line spacer 7 a is formed on a sidewall of the gate oxide layer 5 and the word line patterns 13 .
- a first interlayer insulation layer 13 a is formed on an entire face of the semiconductor substrate containing the word line spacer 7 a . The first interlayer insulation layer 13 a is etched by using an etch mask pattern, to form the bit line pad 14 a connected with the common drain region 4 d and a capacitor storage node pad 12 connected with the source region 4 s .
- a second interlayer insulation layer 16 a is formed on an entire face of the semiconductor substrate containing the bit line pad 14 a and the capacitor storage node pad 12 .
- the second interlayer insulation layer 16 a is patterned to form the bit line contact 14 referred to FIG. 1 .
- the bitline contact 14 is connected with the plurality of bit line patterns 16 having a sidewall spacer 15 .
- the bit line patterns 16 are formed, involving a bit line 16 b and a bit line capping layer pattern 16 c each laminated sequentially and traversing the word line patterns 13 .
- Each bit line 16 b is electrically connected to the bit line pad 14 a through the bit line contact 14 .
- a third interlayer insulation layer 15 a is formed on an entire face of the semiconductor substrate containing the bit line spacer 15 .
- the third interlayer insulation layer 15 a and the second interlayer insulation layer 16 a are continuously patterned to form a capacitor storage node contact 17 .
- the lower structure of semiconductor substrate composed of the active region 4 s , 4 d , the bitline contact 14 , the capacitor storage node pad 12 , the bitline pattern 16 , the word line pattern 13 and the capacitor storage node contact 17 etc., is formed by the straight structure.
- a buffer layer 18 is formed on the semiconductor substrate 11 having the capacitor storage node contact 17 .
- An aperture for connecting the storage node of square type with the capacitor storage node contact 17 is formed through a photolithography and etching process.
- Metallic material such as tungsten etc. is deposited in the aperture and then a flattening is performed to form a pad contact 19 .
- film material such as silicon nitride layer etc. is deposited to form an etching stop layer 20 on the semiconductor substrate having the pad contact 19 .
- a mold oxide layer 21 for a formation of the storage node of capacitor is formed by a thick thickness.
- an etching mask pattern is formed in the mold oxide layer 21 , and an aperture part 22 is formed to expose an upper part of the pad contact 19 connected with the storage node of the capacitor, through an etching process.
- a chemical vapor deposition (CVD) process is performed on an entire face of the semiconductor substrate having the aperture part 22 , to form a conductive layer 23 of polysilicon etc.
- the conductive layer remained on an upper part of the mold oxide layer is removed through a process such as a flattening etc., to form the capacitor storage node of square type.
- the capacitor storage node 23 a through 23 e of square type provides a sectional face of the storage node of the capacitor based on the square type referred to FIG. 1 .
- a buffer layer is adapted.
- an additional step of forming a pad contact on the buffer layer the pad contact being for connecting the storage node of square type with a storage node contact of straight structure.
- an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer.
- the interlayer insulation layer includes a conductive region formed therein.
- the mold layer is partially etched to expose a top surface of the etching stop layer.
- the exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region.
- the conductive region exposed in the first aperture part is etched to form a second aperture part.
- a conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts.
- the conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.
- FIG. 1 is a plan view illustrating a disposed relationship of storage nodes of capacitors based on a square type in a semiconductor memory according to the prior art.
- FIGS. 2 through 6 are cross-sectional views of sequential processes for manufacturing the storage node referred to FIG. 1 .
- FIG. 7 is a plan view illustrating a disposed relationship of storage nodes of capacitors based on a square type in a semiconductor memory according to an exemplary embodiment of the present invention.
- FIGS. 8 through 13 are cross-sectional views of sequential processes for a manufacturing of the storage node referred to FIG. 7 .
- FIG. 7 is a plan view showing a capacitor storage nodes of a square type in a semiconductor memory according to an exemplary embodiment of the present invention.
- FIGS. 8 through 13 are cross-sectional views of sequential processes for manufacturing the storage node referred to in FIG. 7 .
- FIG. 7 vertically on the drawing, six word line patterns 113 as gates of a plurality of access transistors are formed, and horizontally on the drawing, four bit line patterns 116 connected to drains of the access transistors are formed.
- Storage nodes 123 of the capacitors based on a square type form an oblong structure in a diagonal direction to the bit lines 116 and the word lines 113 .
- a storage node contact 117 of each capacitor storage node, an interlayer insulation layer and its below structure are formed by a straight structure as the afore-mentioned.
- the capacitor storage node 123 is in contact with an inner face of an aperture part 125 that is formed at a portion of the storage node contact 117 based on the straight structure, to be thus electrically connected to the storage node contact 117 .
- a reference number 114 indicates a bit line contact for connecting a bit line with a drain, and 114 a designates a bit line pad.
- FIGS. 8 to 13 are cross-sectional views taken along C-C′ and D-D′ cutting lines referred to FIG. 7 .
- FIGS. 8 through 13 cross-sectional views taken along line C-C′ of FIG. 7 , namely, a direction of a word line connected to a gate of access transistor, are illustrated per process.
- FIGS. 8 to 13 cross-sectional views taken along line D-D′ of FIG. 7 , namely, a direction of a bit line connected to a drain of the access transistor, are illustrated per process.
- FIG. 8 illustrates a structure before forming a storage node of capacitor having a square type in a DRAM based on a capacitor over bitline (COB) structure.
- a device separate layer 103 is formed on a determined region of a semiconductor substrate 111 to define a plurality of active regions.
- a gate oxide layer 105 is formed on the active regions.
- a conductive layer and a word line capping layer are formed sequentially.
- the conductive layer is formed of polysilicon layer or metallic polycide layer.
- the word line capping layer can be desirably formed of silicon nitride layer.
- the word line capping layer and the conductive layer are continuously patterned to form a plurality of parallel word line patterns 113 traversing the active regions.
- the word line pattern 113 contains a word line 107 b and a capping layer pattern 107 c laminated sequentially.
- An impurity ion is implanted into the active regions by using the word line patterns 113 and the device separate layer 103 as an ion implantation mask, to form impurity regions 104 s , 104 d .
- the active impurity regions 104 d between one pair of word line patterns 113 traversing the respective active regions are pertinent to a common drain region of a DRAM cell transistor. Further, the impurity regions 104 s formed on both sides of the common drain region 104 d are pertinent to a source region of the DRAM cell transistor.
- a word line spacer 107 a is formed on a sidewall of the gate oxide layer 105 and the word line patterns 113 through a general method.
- the word line spacer 107 a can be desirably formed of material layer same as the word line capping layer pattern 107 c .
- a first interlayer insulation layer 113 a is formed on an entire face of the semiconductor substrate containing the word line spacer 107 a .
- the first interlayer insulation layer 113 a is etched by using an etch mask pattern, to form the bit line pad 114 a connected with the common drain region 104 d and a capacitor storage node pad 112 connected with the source region 104 s .
- a second interlayer insulation layer 116 a is formed on an entire face of the semiconductor substrate containing the bit line pad 114 a and the capacitor storage node pad 112 .
- the second interlayer insulation layer 116 a is patterned to form the bit line contact 114 referred to FIG. 7 .
- the plurality of bit line patterns 116 having a sidewall spacer 115 are formed being connected with the bitline contact 114 .
- the bit line patterns 116 are formed traversing the word line patterns 113 .
- the bit line pattern 116 involves a bit line 116 b and a bit line capping layer pattern 116 c laminated sequentially.
- the bitline 116 b is formed of a conductive layer such as a tungsten layer or tungsten polycide layer, and the bitline capping layer pattern 116 c is formed of silicon nitride layer.
- the bitline spacer 115 is formed at a sidewall of the bitline 116 b .
- the bitline spacer 115 is formed of a nitride layer having an etch selection rate for silicon oxide.
- Each bitline 116 b is electrically connected to the bit line pad 114 a through the bit line contact 114 .
- a third interlayer insulation layer 115 a is formed on an entire face of the semiconductor substrate containing the bit line spacer 115 .
- the third interlayer insulation layer 115 a and the second interlayer insulation layer 116 a are continuously patterned to form the capacitor storage node contact 117 .
- the capacitor storage node contact 117 may be formed of polysilicon.
- the lower structure of semiconductor substrate constructed of the active regions 104 s , 104 d , the bitline contact 114 , the capacitor storage node pad 112 , the bitline pattern 116 , the word line pattern 113 and the capacitor storage node contact 117 may be formed by the straight structure.
- a buffer layer 118 made of PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) is formed on the semiconductor substrate having the capacitor storage node contact 117 .
- the buffer layer 118 can be formed to prevent the structure below the buffer layer from being damaged.
- an etching stop layer 120 is formed on the buffer layer 118 .
- a mold oxide layer 121 having a high etch selection rate as compared with the etching stop layer is formed.
- the etching stop layer 120 can be formed of silicon nitride layer if the mold oxide layer 121 is made of PE-TEOS material.
- the mold oxide layer 121 on which a capacitor storage node of square type will be formed, e.g., a single layer of PE-TEOS or a multilayer containing the PE-TEOS layer, is formed thick.
- FIG. 10 illustrates a process of forming a first aperture part 122 , that is, after etching a portion of the mold oxide layer until a top surface of the etching stop layer is exposed, to be overlapped with an upper portion of the conductive region, by using an etch mask pattern (not shown) formed by, for example, a square type. To prevent an excessive etching, the etching is preferably stopped at the etching stop layer 120 .
- the etch mask can be formed of polysilicon.
- the etching stop layer 120 is removed, and the buffer layer 118 is etched to form the first aperture part 122 for exposing the capacitor storage node contact 117 .
- the conductive region 117 exposed in the first aperture part 122 is illustrated as the capacitor storage node contact 117 in the drawing. This conductive region may be in communication with a source region of the transistor.
- the capacitor storage node contact 117 exposed in the first aperture part 122 is selectively etched, to form a second aperture part 125 in which the capacitor storage node 123 of square type will be formed.
- the second aperture part is formed by highly determining an etch selection rate for the mold oxide layer 121 , the etching stop layer 120 and the bitline spacer 115 and by selectively dry etching only the capacitor storage node contact 117 exposed in the first aperture part 122 .
- the etching process to form the second aperture part can be appropriately formed to a depth of about 100 ⁇ through about 3000 ⁇ .
- the capacitor storage node contact is formed of polysilicon, and when the capacitor storage node contact 117 is etched to form the second aperture part 125 , the polysilicon used as the etch mask when forming the first aperture part is removed together, thus eliminating the additional step of removing the etch mask when separating the capacitor storage node 123 .
- a conductive layer for a formation of the capacitor storage node of square type is deposited on the semiconductor substrate having the first aperture part 122 and the second aperture part 125 .
- the conductive layer is preferably formed of a material such as amorphous silicon or polysilicon through a conventional technique such as a CVD process.
- a residual conductive layer on the mold oxide layer is removed by a planarization process to form the capacitor storage node of square type.
- the planarization process may be a CMP (Chemical and Mechanical Polishing) process or an etch back process, or can employ an anisotropic etching process.
- the capacitor storage nodes 123 a to 123 e referred to in FIG.
- FIG. 13 are cross-sectional views from the capacitor storage nodes 123 a to 123 e referred to FIG. 7 .
- the capacitor storage node 123 a to 123 e is electrically contacted with a sidewall of the selectively etched storage node contact 117 .
- the capacitor storage node 123 of square type can be widely applied to a semiconductor memory device for a DRAM cell. Further, the capacitor storage node of square type can be formed by a box shape based on a solid stack structure, a cylinder type or a hemisphere (HSG) type, or others.
- HSG hemisphere
- an etch mask and a storage node contact are formed of polysilicon, and in selectively etching the storage node contact, the etch mask is etched together, and thus the step of removing the etch mask in separating the capacitor storage node can be omitted. Therefore, the number of processes can be reduced.
- the capacitor storage node may be formed in such a way that a lower face of the storage node is contacted with an upper part of the etched conductive region, because of the recess at an edge portion of upper portion of the interlayer insulation layer.
- an area of the storage node is extended by the contacted area. As a result, capacitance can be increased.
- the capacitor storage node may be formed by a square type to increase a bottom critical dimension of the storage node, thus reducing the leaning phenomenon.
- the capacitor storage node is formed being contacted with a sidewall through an aperture part formed in a storage node contact extending the contact area connected electrically, thus increasing process stability.
- the storage node may be formed of variously varied type and material and the number of manufacturing processes may be added or reduced. Accordingly, these and other changes and modifications are seen to be within the true spirit and scope of the invention as defined by the appended claims.
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Abstract
In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.
Description
- This application is a Divisional of U.S. patent Ser. No. 10/871,322, filed on Jun. 18, 2004, now pending, which claims priority from Korean Patent Application No. 2003-39786, filed on Jun. 19, 2003, both of which are hereby incorporated by reference in their entirety.
- 1. Field of the Invention
- The present invention relates to semiconductor devices, and more particularly, to a method of forming a storage node of capacitor in a semiconductor memory such as a DRAM (Dynamic Random Access Memory) and a structure thereof.
- 2. Description of the Related Art
- A memory cell of DRAM is generally constructed of one access transistor and one storage capacitor. The capacitor is largely classified as a laminated type or a trench type depending on its formed position on a semiconductor substrate.
- Semiconductor manufacturers for manufacturing a semiconductor memory that employs the laminated-type capacitor have continuously researched producing capacitors with a higher capacitance in a limited area in conformity with various requirements of semiconductor users. The need for this continuous research is derived from the high integration of memory cells that produces a tightened critical dimension which results in low capacitance of the memory cells. However, in order to guarantee a refresh operating period within a range of regulated value, the capacitance must instead be increased.
- Capacitors are generally composed of a storage node as a lower electrode node and a plate node as an upper electrode. High integration causes the bottom critical dimension (CD) of the storage node to be too small which causes a leaning phenomenon resulting in the collapse of the storage node.
- To prevent the leaning phenomenon, two methods have widely been used in this field. First is the method of increasing the bottom CD of straight type storage node. Second is the a method of lowering the height of storage node. However, the straight type method is undesirable because it is difficult to increase the bottom CD after a design rule was first decided, and the latter method is undesirable because it is unlikely to obtain the desired capacitance.
- The former method was recently improved to provide a larger bottom CD and reduce the occurrence rate of the leaning phenomenon within a limited area. In this improved method, and in forming the storage node of the capacitor, an active region, a gate, a bit line contact, a storage node contact or buried contact, and bit line patterns are formed in a diagonal direction slightly slanted as compared with the existing straight structure, and thereon, the capacitor storage node is formed. This improved method significantly increases the bottom CD of the storage node as compared with the storage node of the existing straight type, and this is known in this field as a diagonal structure. However, this diagonal structure has severely complicated manufacturing processes in forming the storage node.
- To avoid the complicated manufacturing processes of the diagonal structure, a new method for forming a storage node of square type was recently developed which shared advantages of the straight structure and the diagonal structure. In this method for the square type, an active region, a gate, a bit line and a capacitor storage node contact etc. are formed by the existing straight structure. Then, entirely thereon, a buffer layer is formed, and a contact is formed in the buffer layer, to thus connect the capacitor storage node of square type with a capacitor storage node contact of the straight structure. This new method has been regarded as increasing the storage node of the square type so that the bottom CD of the capacitor storage node is largely increased to about twice that of the storage node of the straight type based on the straight structure.
- The method of manufacturing the storage node of square type in the prior art will be described referring to
FIGS. 1 through 6 , as follows, only to provide a thorough understanding of the present invention to be described later. -
FIG. 1 is a plan view illustrating a disposed relationship for storage nodes of capacitor based on a square type in a semiconductor memory according to an example of the prior art. FIGS. 2 to 6 are sectional views showing sequential processes in manufacturing the storage node referred toFIG. 1 . - Referring first to
FIG. 1 , vertically on the drawing, sixword line patterns 13 as gates of a plurality of access transistors are formed, and horizontally on the drawing, fourbit line patterns 16 connected to drains of the access transistors are formed.Storage nodes 23 of square type of the capacitors form an oblong structure in a diagonal direction to thebit line patterns 16 and theword line patterns 13. Herewith, eachcontact 17 of the storage node of capacitor and its lower structure are formed by a straight structure as the afore-mentioned. Areference number 14 indicates a bit line contact for connecting a bit line with a drain, and 14 a designates a bit line pad. FIGS. 2 to 6 are sectional views taken along A-A′ and B-B′ cutting lines shown inFIG. 1 . - On the left drawings of
FIGS. 2 through 6 , cross-sectional views taken along A-A′ cutting line direction ofFIG. 1 , namely, the direction of a word line connected to a gate of access transistor, are illustrated per process. On the right drawings of FIGS. 2 to 6, cross-sectional views taken along B-B′ cutting line direction ofFIG. 1 , namely, the direction of a bit line connected to a drain of the access transistor, are illustrated per process. -
FIG. 2 illustrates a structure before forming a storage node of capacitor having a square type in a DRAM based on a capacitor over bitline (COB) structure. A deviceseparate layer 3 is formed on a determined region of asemiconductor substrate 11 to define a plurality of active regions. Agate oxide layer 5 is formed on the active regions. Thereon, a plurality of parallelword line patterns 13 traversing the active regions are formed. Theword line pattern 13 contains aword line 7 b and acapping layer pattern 7 c laminated sequentially. An impurity ion is implanted into the active regions by using theword line pattern 13 and the deviceseparate layer 3 as an ion implantation mask, to formimpurity regions active impurity regions 4 d between one pair ofword line patterns 13 traversing the respective active regions are pertinent to a common drain region of a DRAM cell transistor. Further, theimpurity region 4 s formed on both sides of eachcommon drain region 4 d is pertinent to a source region of the DRAM cell transistor. Aword line spacer 7 a is formed on a sidewall of thegate oxide layer 5 and theword line patterns 13. A firstinterlayer insulation layer 13 a is formed on an entire face of the semiconductor substrate containing theword line spacer 7 a. The firstinterlayer insulation layer 13 a is etched by using an etch mask pattern, to form thebit line pad 14 a connected with thecommon drain region 4 d and a capacitorstorage node pad 12 connected with thesource region 4 s. Then, a secondinterlayer insulation layer 16 a is formed on an entire face of the semiconductor substrate containing thebit line pad 14 a and the capacitorstorage node pad 12. The secondinterlayer insulation layer 16 a is patterned to form thebit line contact 14 referred toFIG. 1 . Then, thebitline contact 14 is connected with the plurality ofbit line patterns 16 having asidewall spacer 15. Thebit line patterns 16 are formed, involving abit line 16 b and a bit linecapping layer pattern 16 c each laminated sequentially and traversing theword line patterns 13. Eachbit line 16 b is electrically connected to thebit line pad 14 a through thebit line contact 14. A thirdinterlayer insulation layer 15 a is formed on an entire face of the semiconductor substrate containing thebit line spacer 15. The thirdinterlayer insulation layer 15 a and the secondinterlayer insulation layer 16 a are continuously patterned to form a capacitorstorage node contact 17. - The lower structure of semiconductor substrate composed of the
active region bitline contact 14, the capacitorstorage node pad 12, thebitline pattern 16, theword line pattern 13 and the capacitorstorage node contact 17 etc., is formed by the straight structure. - Referring to
FIG. 3 , abuffer layer 18 is formed on thesemiconductor substrate 11 having the capacitorstorage node contact 17. An aperture for connecting the storage node of square type with the capacitorstorage node contact 17 is formed through a photolithography and etching process. Metallic material such as tungsten etc. is deposited in the aperture and then a flattening is performed to form apad contact 19. - Referring to
FIG. 4 , film material such as silicon nitride layer etc. is deposited to form anetching stop layer 20 on the semiconductor substrate having thepad contact 19. Thereon, amold oxide layer 21 for a formation of the storage node of capacitor is formed by a thick thickness. - In
FIG. 5 , an etching mask pattern is formed in themold oxide layer 21, and anaperture part 22 is formed to expose an upper part of thepad contact 19 connected with the storage node of the capacitor, through an etching process. - In
FIG. 6 , a chemical vapor deposition (CVD) process is performed on an entire face of the semiconductor substrate having theaperture part 22, to form aconductive layer 23 of polysilicon etc. The conductive layer remained on an upper part of the mold oxide layer is removed through a process such as a flattening etc., to form the capacitor storage node of square type. Thecapacitor storage node 23 a through 23 e of square type provides a sectional face of the storage node of the capacitor based on the square type referred toFIG. 1 . - In the prior art described above, in order to form a capacitor storage node of square type on a semiconductor substrate based on a conventional straight lower structure, a buffer layer is adapted. Thus, there is a problem of an additional step of forming a pad contact on the buffer layer, the pad contact being for connecting the storage node of square type with a storage node contact of straight structure.
- In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.
- The above and other features of exemplary embodiments of the present invention will become readily apparent from the description of the exemplary embodiment that follows, Referring to the attached drawings in which:
-
FIG. 1 is a plan view illustrating a disposed relationship of storage nodes of capacitors based on a square type in a semiconductor memory according to the prior art. -
FIGS. 2 through 6 are cross-sectional views of sequential processes for manufacturing the storage node referred toFIG. 1 . -
FIG. 7 is a plan view illustrating a disposed relationship of storage nodes of capacitors based on a square type in a semiconductor memory according to an exemplary embodiment of the present invention. -
FIGS. 8 through 13 are cross-sectional views of sequential processes for a manufacturing of the storage node referred toFIG. 7 . - It will be understood by those skilled in the art that the present invention can be embodied by numerous different types and is not limited to the following described embodiments. The following various embodiments are exemplary in nature.
-
FIG. 7 is a plan view showing a capacitor storage nodes of a square type in a semiconductor memory according to an exemplary embodiment of the present invention.FIGS. 8 through 13 are cross-sectional views of sequential processes for manufacturing the storage node referred to inFIG. 7 . - Referring to
FIG. 7 , vertically on the drawing, sixword line patterns 113 as gates of a plurality of access transistors are formed, and horizontally on the drawing, fourbit line patterns 116 connected to drains of the access transistors are formed.Storage nodes 123 of the capacitors based on a square type form an oblong structure in a diagonal direction to thebit lines 116 and the word lines 113. Herewith, astorage node contact 117 of each capacitor storage node, an interlayer insulation layer and its below structure are formed by a straight structure as the afore-mentioned. Thecapacitor storage node 123 is in contact with an inner face of anaperture part 125 that is formed at a portion of thestorage node contact 117 based on the straight structure, to be thus electrically connected to thestorage node contact 117. Areference number 114 indicates a bit line contact for connecting a bit line with a drain, and 114 a designates a bit line pad. FIGS. 8 to 13 are cross-sectional views taken along C-C′ and D-D′ cutting lines referred toFIG. 7 . - On the left drawings of
FIGS. 8 through 13 , cross-sectional views taken along line C-C′ ofFIG. 7 , namely, a direction of a word line connected to a gate of access transistor, are illustrated per process. On the right drawings of FIGS. 8 to 13, cross-sectional views taken along line D-D′ ofFIG. 7 , namely, a direction of a bit line connected to a drain of the access transistor, are illustrated per process. -
FIG. 8 illustrates a structure before forming a storage node of capacitor having a square type in a DRAM based on a capacitor over bitline (COB) structure. A deviceseparate layer 103 is formed on a determined region of asemiconductor substrate 111 to define a plurality of active regions. Agate oxide layer 105 is formed on the active regions. Thereon, a conductive layer and a word line capping layer are formed sequentially. The conductive layer is formed of polysilicon layer or metallic polycide layer. The word line capping layer can be desirably formed of silicon nitride layer. The word line capping layer and the conductive layer are continuously patterned to form a plurality of parallelword line patterns 113 traversing the active regions. Theword line pattern 113 contains aword line 107 b and acapping layer pattern 107 c laminated sequentially. An impurity ion is implanted into the active regions by using theword line patterns 113 and the deviceseparate layer 103 as an ion implantation mask, to formimpurity regions active impurity regions 104 d between one pair ofword line patterns 113 traversing the respective active regions are pertinent to a common drain region of a DRAM cell transistor. Further, theimpurity regions 104 s formed on both sides of thecommon drain region 104 d are pertinent to a source region of the DRAM cell transistor. Aword line spacer 107 a is formed on a sidewall of thegate oxide layer 105 and theword line patterns 113 through a general method. Theword line spacer 107 a can be desirably formed of material layer same as the word linecapping layer pattern 107 c. A firstinterlayer insulation layer 113 a is formed on an entire face of the semiconductor substrate containing theword line spacer 107 a. The firstinterlayer insulation layer 113 a is etched by using an etch mask pattern, to form thebit line pad 114 a connected with thecommon drain region 104 d and a capacitorstorage node pad 112 connected with thesource region 104 s. Then, a secondinterlayer insulation layer 116 a is formed on an entire face of the semiconductor substrate containing thebit line pad 114 a and the capacitorstorage node pad 112. The secondinterlayer insulation layer 116 a is patterned to form thebit line contact 114 referred toFIG. 7 . Then, the plurality ofbit line patterns 116 having asidewall spacer 115 are formed being connected with thebitline contact 114. Thebit line patterns 116 are formed traversing theword line patterns 113. Thebit line pattern 116 involves abit line 116 b and a bit linecapping layer pattern 116 c laminated sequentially. Thebitline 116 b is formed of a conductive layer such as a tungsten layer or tungsten polycide layer, and the bitlinecapping layer pattern 116 c is formed of silicon nitride layer. Thebitline spacer 115 is formed at a sidewall of thebitline 116 b. Thebitline spacer 115 is formed of a nitride layer having an etch selection rate for silicon oxide. Eachbitline 116 b is electrically connected to thebit line pad 114 a through thebit line contact 114. A thirdinterlayer insulation layer 115 a is formed on an entire face of the semiconductor substrate containing thebit line spacer 115. The thirdinterlayer insulation layer 115 a and the secondinterlayer insulation layer 116 a are continuously patterned to form the capacitorstorage node contact 117. The capacitorstorage node contact 117 may be formed of polysilicon. - The lower structure of semiconductor substrate constructed of the
active regions bitline contact 114, the capacitorstorage node pad 112, thebitline pattern 116, theword line pattern 113 and the capacitorstorage node contact 117 may be formed by the straight structure. - Referring to
FIG. 9 , abuffer layer 118 made of PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) is formed on the semiconductor substrate having the capacitorstorage node contact 117. Thebuffer layer 118 can be formed to prevent the structure below the buffer layer from being damaged. Subsequently, anetching stop layer 120 is formed on thebuffer layer 118. Then, amold oxide layer 121 having a high etch selection rate as compared with the etching stop layer is formed. Theetching stop layer 120 can be formed of silicon nitride layer if themold oxide layer 121 is made of PE-TEOS material. - That is, the
mold oxide layer 121, on which a capacitor storage node of square type will be formed, e.g., a single layer of PE-TEOS or a multilayer containing the PE-TEOS layer, is formed thick. -
FIG. 10 illustrates a process of forming afirst aperture part 122, that is, after etching a portion of the mold oxide layer until a top surface of the etching stop layer is exposed, to be overlapped with an upper portion of the conductive region, by using an etch mask pattern (not shown) formed by, for example, a square type. To prevent an excessive etching, the etching is preferably stopped at theetching stop layer 120. The etch mask can be formed of polysilicon. - Referring to
FIG. 11 , after etching a portion of themold oxide layer 121, theetching stop layer 120 is removed, and thebuffer layer 118 is etched to form thefirst aperture part 122 for exposing the capacitorstorage node contact 117. Theconductive region 117 exposed in thefirst aperture part 122 is illustrated as the capacitorstorage node contact 117 in the drawing. This conductive region may be in communication with a source region of the transistor. - Referring to
FIG. 12 , the capacitorstorage node contact 117 exposed in thefirst aperture part 122 is selectively etched, to form asecond aperture part 125 in which thecapacitor storage node 123 of square type will be formed. The second aperture part is formed by highly determining an etch selection rate for themold oxide layer 121, theetching stop layer 120 and thebitline spacer 115 and by selectively dry etching only the capacitorstorage node contact 117 exposed in thefirst aperture part 122. The etching process to form the second aperture part can be appropriately formed to a depth of about 100 Å through about 3000 Å. In addition, if the capacitor storage node contact is formed of polysilicon, and when the capacitorstorage node contact 117 is etched to form thesecond aperture part 125, the polysilicon used as the etch mask when forming the first aperture part is removed together, thus eliminating the additional step of removing the etch mask when separating thecapacitor storage node 123. - Referring to
FIG. 13 , a conductive layer for a formation of the capacitor storage node of square type is deposited on the semiconductor substrate having thefirst aperture part 122 and thesecond aperture part 125. The conductive layer is preferably formed of a material such as amorphous silicon or polysilicon through a conventional technique such as a CVD process. Further, a residual conductive layer on the mold oxide layer is removed by a planarization process to form the capacitor storage node of square type. The planarization process may be a CMP (Chemical and Mechanical Polishing) process or an etch back process, or can employ an anisotropic etching process. Thecapacitor storage nodes 123 a to 123 e referred to inFIG. 13 are cross-sectional views from thecapacitor storage nodes 123 a to 123 e referred toFIG. 7 . Thecapacitor storage node 123 a to 123 e is electrically contacted with a sidewall of the selectively etchedstorage node contact 117. - The
capacitor storage node 123 of square type can be widely applied to a semiconductor memory device for a DRAM cell. Further, the capacitor storage node of square type can be formed by a box shape based on a solid stack structure, a cylinder type or a hemisphere (HSG) type, or others. - According to this embodiment of the present invention, the following advantages can be provided in forming a capacitor storage node of square type.
- First, there is no need to perform a process of forming a contact through a buffer layer, as in the prior art where a precise photolithography and etching process is required in the process of forming the contact through use of the buffer layer. In addition, an etch mask and a storage node contact are formed of polysilicon, and in selectively etching the storage node contact, the etch mask is etched together, and thus the step of removing the etch mask in separating the capacitor storage node can be omitted. Therefore, the number of processes can be reduced.
- Second, the capacitor storage node may be formed in such a way that a lower face of the storage node is contacted with an upper part of the etched conductive region, because of the recess at an edge portion of upper portion of the interlayer insulation layer. Thus, an area of the storage node is extended by the contacted area. As a result, capacitance can be increased.
- Third, the capacitor storage node may be formed by a square type to increase a bottom critical dimension of the storage node, thus reducing the leaning phenomenon.
- Fourth, the capacitor storage node is formed being contacted with a sidewall through an aperture part formed in a storage node contact extending the contact area connected electrically, thus increasing process stability.
- It will be apparent to those skilled in the art that modifications and variations can be made in the present invention without deviating from the spirit or scope of the invention. Thus, it is intended that the present invention cover any such modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. For instance, the storage node may be formed of variously varied type and material and the number of manufacturing processes may be added or reduced. Accordingly, these and other changes and modifications are seen to be within the true spirit and scope of the invention as defined by the appended claims.
Claims (2)
1. A semiconductor device comprising:
a transistor formed on a semiconductor substrate;
an interlayer insulating layer covering the transistor, the interlayer insulating layer having a contact pad electrically connected with an active region of the transistor; and
a capacitor storage node having a lower portion that is in contact with the contact pad, wherein the contact pad has a recessed portion adjacent an edge portion of an upper portion of the interlayer insulation layer.
2. The device as claimed in 1, wherein the contact pad is a capacitor storage node contact.
Priority Applications (1)
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US11/419,314 US20060199332A1 (en) | 2003-06-19 | 2006-05-19 | Method of forming storage node of capacitor in semiconductor memory, and structure therefor |
Applications Claiming Priority (4)
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KR10-2003-0039786A KR100526869B1 (en) | 2003-06-19 | 2003-06-19 | Method for forming storage node of capacitor for use in semiconductor memory |
KR2003-39786 | 2003-06-19 | ||
US10/871,322 US7074670B2 (en) | 2003-06-19 | 2004-06-18 | Method of forming storage node of capacitor in semiconductor memory, and structure therefore |
US11/419,314 US20060199332A1 (en) | 2003-06-19 | 2006-05-19 | Method of forming storage node of capacitor in semiconductor memory, and structure therefor |
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US10/871,322 Division US7074670B2 (en) | 2003-06-19 | 2004-06-18 | Method of forming storage node of capacitor in semiconductor memory, and structure therefore |
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US20060199332A1 true US20060199332A1 (en) | 2006-09-07 |
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US10/871,322 Expired - Fee Related US7074670B2 (en) | 2003-06-19 | 2004-06-18 | Method of forming storage node of capacitor in semiconductor memory, and structure therefore |
US11/419,314 Abandoned US20060199332A1 (en) | 2003-06-19 | 2006-05-19 | Method of forming storage node of capacitor in semiconductor memory, and structure therefor |
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US10/871,322 Expired - Fee Related US7074670B2 (en) | 2003-06-19 | 2004-06-18 | Method of forming storage node of capacitor in semiconductor memory, and structure therefore |
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Cited By (3)
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US20100200901A1 (en) * | 2009-02-12 | 2010-08-12 | Kim Gil-Sub | Semiconductor memory device having cylinder-type capacitor lower electrode and associated methods |
US20130102151A1 (en) * | 2007-12-17 | 2013-04-25 | Jang-Ho Park | Methods of manufacturing nand flash memory devices |
US9070448B2 (en) | 2008-08-11 | 2015-06-30 | Samsung Electronics Co., Ltd. | Methods of forming fine patterns in semiconductor devices |
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KR100668833B1 (en) * | 2004-12-17 | 2007-01-16 | 주식회사 하이닉스반도체 | Emthod for fabricating capacitor in semiconductor device |
JP2009016596A (en) * | 2007-07-05 | 2009-01-22 | Elpida Memory Inc | Semiconductor device and its manufacturing method |
KR100985409B1 (en) * | 2008-08-29 | 2010-10-06 | 주식회사 하이닉스반도체 | Method for fabricating capasitor of semiconductor device |
KR20100087915A (en) * | 2009-01-29 | 2010-08-06 | 삼성전자주식회사 | Semiconductor memory device with cylinder type storage node and method of fabricating the same |
US8283715B2 (en) * | 2010-08-12 | 2012-10-09 | Rexchip Electronics Corporation | Method and apparatus for buried word line formation |
CN109962068B (en) * | 2017-12-14 | 2020-09-08 | 联华电子股份有限公司 | Memory unit |
CN110707085B (en) * | 2018-09-07 | 2022-05-03 | 联华电子股份有限公司 | Semiconductor device and method of forming the same |
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Also Published As
Publication number | Publication date |
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KR100526869B1 (en) | 2005-11-09 |
KR20040110454A (en) | 2004-12-31 |
US20050032304A1 (en) | 2005-02-10 |
US7074670B2 (en) | 2006-07-11 |
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