KR100604854B1 - Memory device having storage node of box-type under structure and method of fabricating the same - Google Patents

Abstract

A memory device having a storage node of a box-type infrastructure and a method of manufacturing the same are disclosed. The memory device according to the present invention includes a storage node buffer pad between a storage node and a storage node plug in forming a storage node contact. The storage node is connected to the source through storage node buffer pads, storage node plugs, and source cell pads. The storage node has a structure in which a cylindrical upper structure and a boxed lower structure are connected. The storage node of the box-type infrastructure is formed without an additional photoresist pattern forming process by using a hard mask pattern and an etch stop layer to form a storage node buffer pad.

Description

Memory device having a storage node of a box-type infrastructure and a method of manufacturing the same

1A is a plan view illustrating a memory device having a conventional cylindrical storage node.

FIG. 1B is a cross-sectional view taken along line II ′ of FIG. 1A.

FIG. 2A is a plan view illustrating a memory device having a storage node of a box-type infrastructure according to the present invention. FIG.

2B is a cross-sectional view taken along line AA ′ of FIG. 2A, and FIG. 2C is a cross-sectional view taken along line BB ′ of FIG. 2A.

3A through 9A are cross-sectional views taken along line AA ′ of FIG. 2A illustrating a method of manufacturing a memory device having a storage node of a box-type substructure according to the present invention.

3B through 9B are cross-sectional views taken along line BB ′ of FIG. 2A illustrating a method of fabricating a memory device having a storage node having a box-shaped substructure according to the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a memory device having a storage node and a method of manufacturing the same.

As the integration of memory devices increases, the spacing between the structures of the devices generally decreases, and process margins also decrease. However, in order to manufacture a high capacity memory device, particularly a high capacity dynamic random access memory (DRAM), a capacitance of a storage node used as a storage electrode of a capacitor must be increased despite a lack of space in the device.

To increase the capacitance of the storage node, it is a good idea to increase the cross-sectional area of the storage node in addition to increasing the dielectric constant of the dielectric film. Trench capacitors, stack capacitors, and combinations thereof have been developed to increase the cross-sectional area of storage nodes. Stack capacitors are widely used because they can be manufactured utilizing conventional process techniques. Moreover, stack capacitors having a capacitor over bit line (COB) are used.

In addition, in COB stack capacitors, metal-dielectric-metal (MIM) capacitors, metal storage node plugs, or buried contacts are used to reduce contact resistance as the contact sizes decrease rapidly. Several new processes are being developed, such as buried contacts (BC), and storage node buffer pads or buffer buried contacts (BBCs).

FIG. 1A is a plane view illustrating a memory device having a conventional cylindrical storage node, and FIG. 1B is a cross-sectional view taken along line II ′ of FIG. 1A.

1A and 1B, an active region 105 defined by an isolation region 103 in a semiconductor substrate 100, word lines 115 crossing the active region 105, and the word line Sources 119 and the active region, which are provided in the common drain 121 provided in the active region 105 between the first and second 115, and the active region 105 outside the word lines 115, respectively. A bit line 137 that is parallel to 105 and crosses the word lines 115, and storage nodes 160 that are connected to the sources 119.

The word line 115 includes a word line insulating layer 107, a word line electrode layer 109, and a word line capping layer 111, and a word line spacer 117 is provided on sidewalls of the word line 115. It is.

The storage node 160 is connected to the source 119 through a source cell pad 125, a storage node plug 140, and a storage node buffer pad 145. The storage node buffer pad 145 is configured to prevent an increase in contact resistance due to a decrease in contact area due to misalignment between the storage node 160 and the storage node plug 140.

The bit line 137 is connected to the common drain 121 through the drain cell pad 130 and the bit line plug 127. The drain cell pads 130 and the source cell pads 125 are provided in a self-aligned structure by the word line 115 and the pad isolation pattern 123 having the word line spacers 117 formed on sidewalls.

The storage node plug 140 is provided through the interlayer insulating layer 135, and the storage node 160 is provided in a cylindrical shape in the capacitor mold oxide layer 150. In some cases, the capacitor mold oxide layer 150 may be removed, and a dielectric layer may surround both sides of the storage node 160.

In order to further lower the contact resistance, the storage node plug 140, the storage node buffer pad 145, and the storage node 160 may be formed of a metal other than polysilicon.

As described above, according to the related art using a metal storage node buffer pad, an increase in contact resistance due to a decrease in contact area due to misalignment between the two, which may occur when a storage node is directly connected to an existing storage node plug, or the like. Can solve the problem. In addition, according to the prior art in which the storage node plug is formed of metal, the storage node contact resistance can be further reduced.

However, even in the related art using the metal storage node buffer pad, the cross-sectional area of the storage node must be increased to increase the capacitance of the storage node. In recent years, COB-structured memory capacitors use hemi-spherical grain (HSG) nodes to increase the cross-sectional area of storage nodes, but the height of storage nodes is increasing.

Therefore, according to the above-described prior art, the gap between storage nodes in the highly integrated memory device is narrowed, and the height thereof is increased, so that the occurrence of failure due to the collapse of the storage node pattern is an important problem.

An object of the present invention is to provide a memory device having a storage node capable of high capacity and high integration of the device in a structure using a storage node buffer pad to lower the storage node contact resistance.

Another technical problem to be achieved by the present invention is to provide a method of manufacturing a memory device having a storage node that can increase the capacitance of the storage node and can effectively prevent collapse due to its high integration.

According to another aspect of the present invention, there is provided a memory device having a storage node having a box-type substructure, the active area being defined by an isolation region of a semiconductor substrate; A pair of parallel word lines across the active region; A pair of sources respectively provided in the common drain provided in the active region between the word lines and in the active regions outside the word lines; A bit line parallel to the active region, across the word lines, and connected to the common drain; And a pair of storage nodes connected to the source and having a structure in which a box-shaped substructure and a cylindrical superstructure are connected on the source.

The pair of source and the storage node may be respectively a source cell pad provided on the source, a storage node plug provided on the source cell pad, and a storage node buffer pad provided on the storage node plug and connected to the storage node. It is preferred to be connected via.

Furthermore, it is preferable that the storage node buffer pad has a lower cross-sectional area than the storage node plug. Furthermore, the cross-sectional area of the box-shaped substructure of the storage node is more preferably larger than that of the cylindrical superstructure.

In addition, the storage node preferably has a structure in which an etch stop film surrounds a circumference of the box-shaped substructure, and more preferably, a hard mask layer is interposed between one surface of the circumference of the box-shaped substructure of the storage node and the etch stop layer. . Further, the etch stop layer may be a nitride layer, and the hard mask layer may be an oxide layer.

In addition, the cross-sectional area of the connection portion of the box-shaped substructure and the cylindrical superstructure of the storage node is preferably smaller than the cylindrical superstructure and the box-shaped substructure.

In addition, the storage node plug is W or TiN, the storage node buffer pad and the storage node is preferably one of W, WN, TiN or Ru.

According to another aspect of the present invention, there is provided a method of manufacturing a memory device having a storage node having a box-type lower structure, the method including: forming an isolation region defining an active region on a semiconductor substrate; Forming a pair of parallel word lines across the active region; Forming a common drain in the active regions between the word lines and sources in the active regions on both outer sides of the word lines; Forming source cell pads on the sources and drain cell pads on the common drain; Forming a bit line plug on the drain cell pad, and forming a bit line parallel to the active region covering the bit line plug on a resultant product on which the bit line plug is formed; Forming storage node plugs insulated from the bit line on the source cell pads; Forming storage node buffer pads covering the storage node plugs on a product on which the storage node plugs are formed; And forming storage nodes connected to the box-type substructure and the cylindrical superstructure on the storage node buffer pads.

The forming of the source cell pads and the drain cell pad may include forming a pad isolation pattern that crosses the word line and is parallel to the active region, and deposits a cell pad layer on the entire surface of the product on which the pad isolation pattern is formed. It is preferable to form a cell pad layer in a self-aligned manner by the word line and the pad isolation pattern, including planarizing the cell pad layer until the word line is exposed.

The forming of the storage node buffer pads may include forming a storage node buffer pad layer on a resultant of the storage node plugs, and a pair of hard masks covering the storage node plugs on the storage node buffer pad layer. And forming a film pattern, and etching the storage node buffer pad layer by using the hard mask layers as an etch protective layer.

Further, the forming of the storage nodes may include forming an etch stop layer on a resultant product on which the hard mask layer patterns are formed, forming a capacitor mold oxide layer on the etch stop layer, the capacitor mold oxide layer, an etch stop layer, and a hard layer. Forming cylindrical storage node holes penetrating through a mask layer to expose a portion of the storage node buffer pad, extending storage node holes in the hard mask layer to form a lower portion of the storage node hole as a box trench; and More preferably, the method includes forming a storage node layer on the resultant formed storage node hole of the box-type trench infrastructure.

Further, the etch stop film is more preferably a nitride film. The forming of the storage node hole may include forming a storage node hole photoresist pattern on the capacitor mold oxide layer and using the storage node hole photoresist pattern as an etch protective layer. More preferably, etching the mask film.

The etching of the hard mask layer may be performed at the same time as the etching stop layer is etched.

In addition, the hard mask layer is preferably an oxide layer, and further, forming the lower portion of the storage node hole into a box trench may be performed by wet etching using a dilute HF solution or a buffered oxide etchant (BOE) solution. Further, the wet etching is more preferably performed by adjusting the time so that the contact portion of the storage node hole with the etch stop layer does not leave the upper portion of the etch stop layer.

In addition, the storage node buffer pad and the storage node is preferably one of W, WN, TiN, or Ru.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions are highlighted for clarity.

FIG. 2A is a plan view illustrating a memory device having a storage node of a box-type substructure for solving the technical problem of the present invention.

2B is a cross-sectional view taken along line AA ′ of FIG. 2A, and FIG. 2C is a cross-sectional view taken along line BB ′ of FIG. 2A. 2A is a cross section along the bit line direction, and a cross section along BB 'in FIG. 2A is a cross section along the word line direction.

2A to 2C, a memory device having a storage node having a box-type understructure according to an embodiment of the present invention is an active region 305 defined by an isolation region 303 of a semiconductor substrate 300. Parallel word lines 315 crossing the active region 305, and a common drain 323 and the word lines 315 provided in the active region 305 between the word lines 315. Source bits 320 in the active region 305 outside the bit, parallel to the active region 305 and across the word lines 315, and connected to the common drain 323. And a storage node 365 connected to the line 335 and the source 320 and to which the box-shaped substructure 363 and the cylindrical superstructure 364 are connected.

The word line 315 includes a word line insulating layer 307, a word line electrode layer 309, and a word line capping layer 311, and a word line spacer 317 is disposed on sidewalls of the word line 315.

The sources 320 and the common drain 323 may be formed by impurity ion implantation and heat treatment. The source 320 and the storage node 365 are source cell pads 327 provided on the source 320, storage node plugs 340 provided on the source cell pad 327, and the storage node. The storage node buffer pad 345 is provided between the plug 340 and the storage node 365.

In addition, the bit line 335 is connected to the common drain 323 through the drain cell pad 330 on the common drain 323 and the bit line plug 334 on the drain cell pad 330.

The drain cell pads 330 and the storage node pads 327 are provided in a self-aligned structure by the pad isolation pattern 325 and the word line 315. In addition, the bit lines 335 and the storage node plugs 340 are provided in or through the first interlayer insulating layer 333 and the second interlayer insulating layer 337.

The box-shaped substructure 363 of the storage node 365 is surrounded by an etch stop layer 355 and a hard mask layer 350, and may exist on the storage node buffer pad 345. In some cases, the hard mask layer 350 does not exist at all and may be surrounded by only the etch stop layer 355 and the storage node buffer pad 345. In addition, the cylindrical upper structure 364 of the storage node 365 may be formed in the capacitor mold oxide layer 357 and may be connected to the box-shaped lower structure 363 at an opening of the etch stop layer 355. In some cases, in order to increase capacitance, the capacitor mold oxide layer 357 may be selectively removed, and a dielectric layer may surround the storage node 365.

In the above structure, when the word line 315 is in an ON state, the charge stored in the storage node 365 is the storage node buffer pad 345, the storage node plug 340, the source cell pad 327, And the common drain 323, the drain cell pad 330, the bit line plug 334, and the bit line 335 through the source 320, thereby enabling operations such as memory storage and erasing. .

3A to 9A are cross-sectional views taken along line AA ′ of FIG. 2A, which illustrates a method of manufacturing a memory device having a storage node having a box-shaped substructure to solve another technical problem of the present invention, and FIGS. 3B to 9B are FIGS. Sectional drawing along BB 'of 2a.

3A and 3B, an isolation region 303 is formed in the semiconductor substrate 300 to define the active region 305. The device isolation region 303 may have a shallow trench isolation (STI) structure in which an insulating layer is filled in the device isolation trench.

Subsequently, parallel word lines 315 are formed across the active region 305. The word line 315 may be formed by forming a word line insulating layer 307, a word line electrode layer 309, and a word line capping layer 311, and then patterning the photolithography and etching techniques. The word line electrode layer 309 may be a doped polysilicon or a composite layer of doped polysilicon and a metal silicide, and the word line capping layer 311 may be formed of an insulating layer such as a nitride layer.

Subsequently, word line spacers 317 are formed on sidewalls of the word line 315 using conventional insulating film deposition and etching techniques. The common drain 323 and the source 320 are formed through ion implantation and heat treatment.

Subsequently, the pad isolation pattern 325 is formed using an insulating film, for example, an oxide film. In addition, the cell pad layers 327 and 330 are deposited on a resultant product on which the pad isolation pattern 325 is formed, and the cell pad layers 327 and 330 are planarized until the word line 315 is exposed. The source cell pads 327 and the drain cell pad 330 are formed in a self-aligned structure by the word line 315 on which the pad isolation pattern 325 and the word line spacer 317 are formed.

4A and 4B, a first interlayer insulating layer 333 is deposited on a resultant product on which the drain cell pads 330 and the source cell pads 327 are formed, and on the first interlayer insulating layer 333. A bit line plug 334 of FIG. 2A is connected to the drain cell pad 330. The bit line plug 334 of FIG. 2A is covered to form a bit line 335 parallel to the active region 305. The bit line 335 may be formed of doped polysilicon or metal, for example, W or TiN.

Subsequently, a second interlayer insulating layer 337 is deposited, and a storage node plug 340 is formed through the second interlayer insulating layer 337 and the first interlayer insulating layer 333 and connected to the source cell pad 327. . The storage node plug 340 may be formed of doped polysilicon or metal, but is preferably formed of W or TiN to lower contact resistance.

Referring to FIGS. 5A and 5B, a hard mask layer pattern 350 may be deposited on a resultant in which the storage node plug 340 is formed, and then cover the storage node plug 340. To form. The hard mask layer pattern 350 may be formed by depositing a hard mask layer and then using photolithography and etching techniques.

The storage node buffer pad layer 345 may be any one of W, WN, TiN, or Ru, and the hard mask layer 350 may be an oxide that may be removed during wet cleaning. In addition, the hard mask layer 350 may be between 100 kHz and 10000 Å to form a lower structure of the storage node.

6A and 6B, a storage node buffer pad 345 is formed by etching the storage node buffer pad layer by using the hard mask layer pattern 350 as an etch protection layer. The lower cross-sectional size of the storage node buffer pad 345 may be larger than the storage node plug 340 to prevent misalignment with the storage node plug 340.

Subsequently, an etch stop layer 355 is formed on the resultant product on which the storage node buffer pad 345 is formed. The etching stop layer 355 may be formed of a nitride layer to have a selectivity with respect to etching when the hard mask layer 350 is an oxide layer.

Referring to FIGS. 7A and 7B, a capacitor mold oxide layer 357 is formed on a resultant on which the etch stop layer 355 is formed. An oxide film may be used as the insulating film of the capacitor mold oxide film 357.

Subsequently, a storage node hole 360 is formed through the capacitor mold oxide layer 357, the etch stop layer 355, and the hard mask layer 350 and connected to the storage node buffer pad layer 345. The storage node hole 360 forms a photoresist pattern on the capacitor mold oxide layer 357, and uses the photoresist pattern as an etch protective layer to form the capacitor mold oxide layer 357, the etch stop layer 355, and the hard mask. The film 350 is formed by etching. In this case, holes are formed first to the capacitor mold oxide layer 357, holes through the etch stop layer 355 are formed second, and holes through the hard mask layer 350 are formed third. The storage node hole 360 can be completed. Alternatively, the storage node hole 360 may be formed by first forming a hole up to the capacitor mold oxide layer 357 and then simultaneously etching the etch stop layer 355 and the hard mask layer 350.

8A and 8B, after the storage node hole 360 is formed, the storage node hole 360 is expanded by wet etching. The wet etching is selected to remove the hard mask layer 350 without etching the etch stop layer 355. When the hard mask layer 350 is an oxide layer, a dilute HF or BOE solution is used. It is preferable. By etching, the upper hole of the storage node hole 360 becomes larger, and the lower part has a box-shaped trench structure surrounded by the etch stop layer 355. However, since the lower etching speed is faster than the upper portion, the lower box is larger than the upper hole. In addition, depending on the etching degree, the hard mask layer 350 may remain on one side of the etch stop layer 355 to form one side of the box trench.

After the etching process, the hard mask layer 350 does not remain on the storage node buffer pad 345 which is the bottom of the storage node hole 360, and the storage node hole 360 is etched in the lateral direction. It is preferable that the stop film 355 is adjusted so as not to deviate from the top. In some cases, it is preferable that no hard mask layer 350 remains on the side of the box-shaped lower trench, or less than 2000 kPa.

The wet etching may also be done with subsequent storage node precleans.

9A and 9B, a storage node 365 is formed on a resultant product in which the storage node hole 360 is formed. As mentioned above, pre-cleaning may be performed before the storage node 365 is formed. The pre-cleaning is preferably performed in a solution having a selectivity with respect to the nitride film and the metal / oxide film. The lower portion of the storage node 365 has a box structure 363 and the upper portion has a cylindrical structure 364. The storage node 365 may be polysilicon or metal, and preferably may be one of W, WN, TiN, or Ru. The storage node 365 may be formed by forming and planarizing the storage node layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD), which has excellent edge coating properties. In addition, the capacitor mold oxide layer 357 may be removed after the storage node 365 is formed.

Thereafter, although not shown, a capacitor dielectric layer and an electrode are formed in accordance with a conventional method known to those skilled in the art to complete the formation of a capacitor, and an insulating layer and a wiring layer are formed to manufacture a memory device having a storage node having a box-type substructure. can do. In addition, after the storage node 365 is formed to further increase capacitance, the capacitor mold oxide layer 357 may be removed, a dielectric layer may be formed, and an electrode may be formed.

 The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. The present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit of the present invention.

The memory device having a storage node having a box-type substructure according to the present invention employs a storage node buffer pad to prevent an increase in contact resistance due to storage node contact and misalignment between storage nodes due to integration of the device, and the storage node buffer pad. Contact resistance can be lowered by forming a storage node with a box-type substructure having a large contact area. In addition, by forming a lower portion in the box-shaped upper structure of the existing cylindrical structure, the capacitance of the storage node can be increased, enabling high capacity of the memory device. In addition, there is an advantage of improving the pattern collapse of the storage node due to the decrease in the width and height of the storage node due to the high capacity of the memory device.

Claims (19)

delete An active region defined by an isolation region of the semiconductor substrate; A pair of parallel word lines across the active region; A pair of sources respectively provided in the common drain provided in the active region between the word lines and in the active regions outside the word lines; A bit line parallel to the active region, across the word lines, and connected to the common drain; And A pair of storage nodes each connected to the pair of sources, the pair of storage nodes having a box-shaped substructure and a cylindrical superstructure connected to the pair of sources, Each of the source and the storage node pairs includes a source cell pad provided on the source, a storage node plug provided on the source cell pad, and a storage node buffer provided on the storage node plug and connected to the storage node. A memory device having a storage node of a box-type infrastructure, which is connected through a pad. The method of claim 2, And the storage node buffer pad has a lower cross-sectional area than that of the storage node plug. The method of claim 3, wherein And the cross-sectional area of the box-shaped substructure of the storage node is greater than the cross-sectional area of the cylindrical superstructure. The method of claim 2, The storage node is a memory device having a storage node of the box-type infrastructure, characterized in that the etch stop film surrounds the periphery of the box-type infrastructure. The method of claim 5, And a hard mask layer is interposed between one surface of the box-type substructure of the storage node and the etch stop layer. The method of claim 6, And the etch stop layer is a nitride layer, and the hard mask layer is an oxide layer. The method of claim 5, And a cross-sectional area of a connection portion of the boxed substructure and the cylindrical superstructure of the storage node is smaller than the cylindrical superstructure and the boxed substructure. The method of claim 2, And the storage node plug is W or TiN, and the storage node buffer pad and the storage node are one of W, WN, TiN, or Ru. Forming an isolation region defining an active region in the semiconductor substrate; Forming a pair of parallel word lines across the active region; Forming a common drain in the active regions between the word lines and sources in the active regions on both outer sides of the word lines; Forming source cell pads on the sources and drain cell pads on the common drain; Forming a bit line plug on the drain cell pad, and forming a bit line parallel to the active region covering the bit line plug on a resultant product on which the bit line plug is formed; Forming storage node plugs insulated from the bit line on the source cell pads; Forming storage node buffer pads covering the storage node plugs on a product on which the storage node plugs are formed; And Forming storage nodes connected to the boxed substructure and the cylindrical superstructure on the storage node buffer pads. The method of claim 10, Forming the source cell pads and the drain cell pad, Forming a pad isolation pattern across the word line and parallel to the active region; And Depositing a pad film on the entire surface of the resultant product on which the pad isolation pattern is formed, and planarizing the pad layer until the upper portion of the word line is exposed to form a self-aligning method by the word line and the pad isolation pattern. A method of manufacturing a memory device having a storage node of a boxed infrastructure. The method of claim 10, The forming of the storage node buffer pads may include: Forming a storage node buffer pad layer on a product on which the storage node plugs are formed; Forming a hard mask layer pattern covering the storage node plugs on the storage node buffer pad layer; And And etching the storage node buffer pad layer using the hard mask layers as an etch passivation layer. In claim 12, Forming the storage nodes, Forming an etch stop layer on a resultant product on which the hard mask layer patterns are formed; Forming a capacitor mold oxide layer on the etch stop layer; Forming cylindrical storage node holes through the capacitor mold oxide layer, an etch stop layer, and a hard mask layer to expose a portion of the storage node buffer pad; Expanding a storage node hole in the hard mask layer to form a lower portion of the storage node hole as a box trench; And Forming a storage node layer on a resultant in which the storage node holes of the box-type trench infrastructure are formed. The method of claim 13, The method of claim 1, wherein the etch stop layer is a nitride layer. The method of claim 13, Forming the storage node hole, Forming a storage node hole photoresist pattern on the capacitor mold oxide layer; And And etching the capacitor mold oxide layer, the etch stop layer, and the hard mask layer by using the storage node hole photoresist pattern as a protective layer. The method of claim 15, The etching of the hard mask layer is performed at the same time during the etching stop layer etching method of manufacturing a memory device having a storage node of the box-type lower structure. The method of claim 12, The hard mask film is a method of manufacturing a memory device having a storage node of the box-type lower structure, characterized in that the oxide film. The method of claim 17, And forming a lower portion of the storage node hole into a box-type trench by wet etching using a dilute HF solution or a buffered oxide etchant (BOE) solution. The method of claim 18, The wet etching is performed by adjusting a time so that a contact portion of the storage node hole with the etch stop layer does not leave the upper portion of the etch stop layer, wherein the wet etching is performed.

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