WO2022037273A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022037273A1
WO2022037273A1 PCT/CN2021/103670 CN2021103670W WO2022037273A1 WO 2022037273 A1 WO2022037273 A1 WO 2022037273A1 CN 2021103670 W CN2021103670 W CN 2021103670W WO 2022037273 A1 WO2022037273 A1 WO 2022037273A1
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Prior art keywords
bit line
conductive
dielectric layer
layer
peripheral circuit
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PCT/CN2021/103670
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English (en)
French (fr)
Inventor
舒月姣
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长鑫存储技术有限公司
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Priority to US17/467,603 priority Critical patent/US12068247B2/en
Publication of WO2022037273A1 publication Critical patent/WO2022037273A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present application relates to the technical field of semiconductor memory devices, and in particular, to a semiconductor structure and a preparation method thereof.
  • peripheral circuit contact connection process is to dig holes to connect the metal layer and the active area, but due to the small distance between the gates (Periphery Gate, PG) in the peripheral circuit area, to pass the PC The Contact) process connects the active region between the two gates without short-circuiting with the gates of the transistors in the peripheral circuit region, which has extremely high requirements on the overlay error.
  • Another purpose of the PC is to connect with the bit line BL, but because the size of the BL is too small, the critical dimension of the W part of the main metal layer is about 11 nm, so the BL sidewall will be damaged during the etching process of the PC on BL severe.
  • a semiconductor structure and a method of fabricating the same are provided.
  • the present application provides a method for fabricating a semiconductor structure, including:
  • a first insulating medium layer and a second insulating medium layer are formed in the memory cell array region and the peripheral circuit region, the first insulating medium layer is formed with spaced bit line structures, and the second insulating medium A conductive structure arranged at intervals is formed in the layer, wherein the bit line structure includes a bit line conductive structure and an isolation structure covering the top and sidewalls of the bit line conductive structure;
  • the first void at least partially exposes the bit line conductive structure
  • the second void exposes the substrate between the conductive structures in the peripheral circuit region
  • a third insulating dielectric layer is formed on the sidewall of the first void and the sidewall of the second void, and the third insulating dielectric layer on the sidewall of the first void and all the sidewalls of the bit line structure
  • the thicknesses of the isolation structures may be the same or different.
  • Embodiments of the present application also provide a semiconductor structure, including:
  • the substrate has a memory cell array region, and a first insulating medium layer is formed on the substrate of the memory cell array region;
  • bit line structure is formed in the first insulating dielectric layer
  • the bit line structure includes a bit line conductive structure and an isolation structure located on the sidewall of the bit line conductive structure, the bit line conductive structure including a first conductive structure and a second conductive structure connected to the top of the first conductive structure, the isolation structure includes a first bit line isolation structure and a second bit line isolation structure located above the first bit line isolation structure , the thicknesses of the first bit line isolation structure and the second bit line isolation structure on the sidewall of the bit line conductive structure may be the same or different.
  • FIG. 1 is a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present application
  • FIGS 2-6 are schematic structural diagrams of the stepwise formed semiconductor structure provided by the embodiments of the present application.
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including:
  • a substrate 100 is provided, and the substrate 100 has a single memory array area (array) and a peripheral circuit area (periphery);
  • Step S120 forming a first insulating dielectric layer 310 and a second insulating dielectric layer 320 in the memory cell array region and the peripheral circuit region, and forming the bit line structures 200 arranged at intervals in the first insulating dielectric layer 310 , the second insulating dielectric layer 320 is formed with conductive structures 210 arranged at intervals, wherein the bit line structure 200 includes the bit line conductive structure 210 and the first bit line isolation covering the top and sidewalls of the bit line conductive structure Structure 2201, wherein the bit line conductive structure 210 may include a first conductive layer 2101 and a second conductive layer 2102 in sequence from bottom to top, as shown in FIG. 2 ;
  • Step S130 using the bit line conductive structure 210 as an etch stop layer, etch the first bit line isolation structure 2201 in the memory cell array area to form a first gap 510a, through which at least the first gap 510a is exposed.
  • Part of the surface of the bit line conductive structure 210 and the second insulating dielectric layer 320 are etched in the peripheral circuit region to form a second void 520 a exposing the substrate 100 between the spaced conductive structures 210 .
  • the spacing between the conductive structures 210 in the circuit area is getting smaller and smaller, which may cause at least one sidewall of the conductive structures 210 to be exposed at the same time during etching, as shown in FIG. 3 ;
  • Step S140 forming a third insulating dielectric layer 400, and the third insulating dielectric layer 400 covers the sidewalls of the first void 510a and the second void 520a, as shown in FIG. 4 and FIG. 5 ;
  • step S150 the first void 510a and the second void 520a are filled to form a first connection structure 510 and a second connection structure 520, respectively, to achieve electrical connection, see FIG. 6 .
  • a part of the sidewall of the conductive structure 210 may be exposed or a part of the first bit line isolation structure 2201 may be damaged during the PC process.
  • a short circuit occurs between the second connection structure 520 and the conductive structures 210 in the peripheral circuit area.
  • a first void 510a and a sidewall of the second void 520a are formed to cover the first void hole 510a and the second void 520a.
  • the third insulating dielectric layer 400 is used to protect the sidewalls of the conductive structure 210, so as to isolate the second connection structure 520 from the conductive structure 210, and prevent the second connection structure 520 in the peripheral circuit area from being connected to the conductive structure 210.
  • a short circuit occurs between the conductive structures 210 in the peripheral circuit area, and leakage contact between the capacitive contact hole wires and the bit line conductive structures 210 in the memory cell array area is prevented in the memory cell array area; and the third insulating medium is used.
  • the layer 400 fills the gap formed between the bit line conductive structure 210 and the first insulating dielectric layer 310 because the first bit line isolation structure 2201 is partially etched away to form the second isolation structure 2202, which is connected with the first bit line isolation structure 2202.
  • the line isolation structure 2201 constitutes a new bit line isolation structure 220, which realizes the repair of the bit line isolation structure damaged in the PC process, so as to solve the current problem that the side wall of the bit line is damaged due to the PC process, and further improve the quality of the semiconductor structure.
  • the substrate 100 includes a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator substrate, but not limited thereto. Those skilled in the art can select the type of the semiconductor substrate according to the semiconductor device to be formed on the substrate, so the type of the semiconductor substrate should not limit the protection scope of the present application.
  • the substrate 100 is a P-type crystalline silicon substrate.
  • the substrate 100 includes a base and a shallow trench structure formed in the base, a plurality of active regions arranged in parallel and staggered are defined by the shallow trench structure, and the shallow trench structure is filled with a plurality of active regions. insulating material to form shallow trench isolation structures.
  • the substrate 100 further includes a word line structure and a bit line structure 200 , wherein the word line structure is a buried word line structure, an extension method of the buried word line structure and an extension direction of the bit line structure 200 cross.
  • the bit line structure 200 includes a bit line conductive structure 210 and an isolation structure 220 covering the top and sidewalls of the bit line conductive structure.
  • bit line conductive structure and the conductive structure are formed simultaneously, and the step of forming the bit line conductive structure and the conductive structure includes:
  • the first conductive material layer and the second conductive material layer are etched, and the bit line conductive structure and the conductive structure are simultaneously formed in the memory cell array region and the peripheral circuit region.
  • the steps of forming the bit line structure 200 and the conductive structure 210 in this embodiment include:
  • an insulating material is deposited on the memory cell array region and the peripheral circuit region of the substrate 100 simultaneously by a deposition process to form a spacer layer (not shown);
  • the insulating material can be silicon oxide, silicon nitride, nitrogen Silicon oxide, etc., the specific material can be selected according to the process requirements.
  • silicon nitride is used to form the spacer layer.
  • the deposition process may include chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), and the like.
  • the spacer layer completely covers the surface of the substrate 100 , and the top is relatively flat.
  • a semiconductor conductive material, a metal material and an insulating material are sequentially deposited through a deposition process to form the first conductive material layer, the second conductive material layer and the insulating material layer, respectively.
  • polysilicon, low temperature polysilicon, etc. are used to make the first conductive material layer, and any one or any combination of titanium nitride, titanium, tungsten silicide, and tungsten nitride is used to make the second conductive material layer,
  • the insulating material is made of the silicon nitride.
  • a first organic mask material layer and a first hard mask material layer are sequentially formed on the insulating material layer, and a layer of photoresist is coated on the surface of the first hard mask material layer to form a first layer of photoresist.
  • a photoresist layer wherein, the material of the first hard mask material layer can be nitride, oxide, such as silicon oxynitride, silicon oxide carbon, etc., and the first organic mask material layer can be anti-reflection materials, organic carbon materials, etc.
  • the first photoresist layer is exposed, cleaned, etc., to form patterns defining the bit line structure 200 and the conductive structure 210 .
  • the first organic mask material layer and the first hard mask material layer are etched until the insulating material layer is exposed, and the patterned first photoresist layer is etched. Transferred to the first organic mask material layer and the first hard mask material layer, and the remaining first organic mask material layer and the first hard mask material layer constitute a first hard mask layer. Finally, the photoresist layer is removed.
  • Step 4 Using the first hard mask layer as a mask, the first conductive material layer, the second conductive material layer and the insulating material layer are etched, and the bit line structure 200 and the conductive material layer are formed at the same time. Structure 210.
  • a first bit line isolation structure 2201 covering the sidewall of the bit line structure 200 needs to be formed.
  • the step of forming the first bit line isolation structure 2201 includes:
  • an isolation material layer is formed, and the isolation material layer covers the side wall, the top of the bit line structure 200 and the surface of the substrate 100;
  • the isolation material layer is etched, and the isolation material layer located on the surface of the substrate 100 and the top of the bit line structure 200 is removed, and the remaining isolation material located on the side wall of the bit line structure 200 is used as the isolation material layer.
  • the first bit line isolation structure 2201 is described.
  • the step of forming the first bit line isolation structure 2201 includes: first, forming an isolation material layer covering the surface of the bit line structure 200 and the surface of the substrate 100 by depositing an insulating material.
  • the isolation material layer is made of silicon nitride.
  • the isolation material layer can be made of the same material as the insulating material layer on the top of the bit line structure; The isolation material layer is etched by the etching process, the isolation material layer located on the top of the bit line structure 200 and the surface of the substrate 100 is removed, and the isolation material layer located on the sidewall of the bit line structure 200 and the isolation material layer located on the side wall of the bit line structure 200 are retained.
  • the insulating material layer on the top of the bit line structure 200 , the insulating material layer on the top of the bit line structure 200 and the isolation material layer on the sidewalls of the bit line structure 200 together serve as the first bit line isolation structure 2201 .
  • a first insulating dielectric layer 310 is usually formed in the memory cell array region by a deposition process and an etching/chemical mechanical polishing process.
  • the step of forming the first insulating dielectric layer 310 includes:
  • a first insulating filling material layer is formed in the memory cell array region, and the first insulating filling material layer fills the spaces between the first bit line isolation structures 2201 gap, and cover the top of the bit line structure 200;
  • the first insulating filling material layer is ground until the top of the bit line structure 200 is exposed, and the first insulating dielectric layer 310 is formed.
  • a second insulating filling material layer is formed in the peripheral circuit area, the second insulating filling material layer fills the gaps between the conductive structures 210 and covers the On top of the conductive structure 210, a second insulating dielectric layer 320 is formed.
  • the first insulating dielectric layer 310 and the second insulating dielectric layer 320 are respectively formed. specific:
  • the memory cell array region is first covered, a silicon nitride material is deposited in the peripheral circuit region, and a second insulating filling material layer is formed in the peripheral circuit region, the second insulating filling material The layer fills the gaps between the conductive structures 210 and covers the tops of the conductive structures 210 , as shown in (b) of FIG. 2 .
  • the peripheral circuit region is covered, and a first insulating filling material is deposited in the memory cell array region to form a first insulating filling material layer, the first insulating filling material layer Filling the gaps between the bit line isolation structures 220 and covering the top of the bit line structures 200; then using an etching process or a chemical mechanical polishing process to remove a partial height of the first insulating filling material layer until exposed On the top of the bit line structure 200 , the remaining first insulating filling material layer serves as the first insulating dielectric layer 310 , as shown in (a) of FIG. 2 .
  • the first insulating dielectric layer 310 can be formed first, and then the second insulating dielectric layer 320 can be formed after the first bit line isolation structure 2201 of the memory cell array region is formed;
  • the second insulating medium layer 320 is formed in the peripheral circuit region together, and then the first insulating medium layer 310 is formed.
  • This embodiment does not limit any specific implementation steps and manners of the first insulating medium layer and the second insulating medium layer.
  • the step of forming the first void 510a includes:
  • the first bit line isolation structure 2201 is etched to remove the top of the bit line conductive structure 210 above the plane.
  • the first gap 510a is formed by the first bit line isolation structure 2201 and a part of the first bit line isolation structure 2201 located on the sidewall of the bit line conductive structure 210.
  • the same etching process is used to form the first void 510a and the second void 520a in this embodiment, as long as the selection ratio of the second conductive material layer (ie, metal tungsten) and silicon nitride is pulled.
  • the etching is basically stopped after the first void 510a in the memory cell array area is completed, but the etching will continue in the peripheral circuit area. etch to fix the depth.
  • the process of forming the first void 510a and the second void 520a specifically includes:
  • a second hard mask layer is formed on the first insulating medium layer 310 and the second insulating medium layer 320 , and the second hard mask layer has voids, and the first voids 510 a can be defined by the voids and the second void 520a.
  • the gap is located directly above the first bit line isolation structure 2201 ; in the peripheral circuit region, the gap is located directly above the region between the two conductive structures 210 .
  • the first bit line isolation located above the bit line conductive structure 210 is removed by using the etching ratio of silicon nitride to silicon oxide.
  • part of the bit line conductive structure 210 and the first Part of the first bit line isolation structure 2201 between the insulating dielectric layers 310 causes the bottom of the first void 510a formed to be W-shaped, as shown in (a) of FIG. 3; and, limited by the overlay error, Part of the second insulating dielectric layer 320 and the substrate 100 are etched away in the peripheral circuit region, exposing part of the sidewall of the conductive structure 210 and the active region of the substrate, as shown in (b) of FIG. 3 .
  • the first void 510a is formed by using an etching selectivity ratio of the first bit line isolation structure 2201 relative to the first insulating dielectric layer 310 .
  • the first bit line isolation structure 2201 is made of silicon nitride
  • the first insulating dielectric layer 310 is made of silicon oxide
  • tungsten is used as the bit line conductive structure 210 and the conductive structure 210.
  • the first line isolation structure 2201 , the insulating layer 400 and the second insulating dielectric layer 320 may use the same insulating material, such as silicon nitride, in another embodiment of the present application Among them, the first line isolation structure 2201, the third insulating medium layer 400 and the second insulating medium layer 320 are silicon nitride, and the first insulating medium layer 310 is silicon oxide.
  • a third insulating dielectric layer 400 is formed to insulate and isolate the conductive structure 210 in the peripheral circuit region from the second connection structure 520 .
  • the step of forming the third insulating dielectric layer 400 includes:
  • a third insulating material layer 400a is formed, and the third insulating material layer 400a covers the surfaces of the first voids 510a and the second voids 520a and the tops of the first insulating dielectric layer 310 and the second insulating dielectric layer 320 ;
  • the third insulating material layer 400a Etching the third insulating material layer 400a to remove the third insulating layer on top of the bit line structure 200 , the substrate 100 and the first insulating dielectric layer 310 and the second insulating dielectric layer 320 Material layer 400a, the third insulating material layer 400a remaining on the sidewalls of the first void 510a and the second void 520a is used as the third insulating dielectric layer 400, wherein the first void 510a sidewalls
  • the three insulating dielectric layers 400 are the second bit line isolation structure 2202 , which is in contact with the first bit line isolation structure 2201 to form isolation for the bit line conductive structure 210 .
  • the third insulating dielectric layer 400 is formed by using silicon nitride material, and the specific process includes:
  • the third insulating material layer 400a covers the surfaces of the first void 510a and the second void 520a and the first insulating dielectric layer 310 and the top of the second insulating dielectric layer 320, please refer to FIG. 4, wherein (a) in FIG. 4 is used to illustrate the semiconductor structure after forming the third insulating material layer 400a in the memory cell array region, in FIG.
  • FIG. 4 Figure (b) is used to illustrate the semiconductor structure after the formation of the third insulating material layer 400a in the peripheral circuit area; it is understood that the third insulating material layer 400a will cover the exposed sidewalls of the bit line conductive structure 210 and top, and at least partially fills the gap between the conductive structure 210 and the second insulating dielectric layer 320 .
  • the third insulating material layer 400a is etched by an etching process to remove the top surface of the bit line conductive structure 210, the substrate 100, the first insulating dielectric layer 310 and the second insulating dielectric layer 320
  • the third insulating material layer 400a located on the sidewalls of the first void 510a and the second void 520a is reserved as the third insulating dielectric layer 400; please refer to FIG. 5 , (a) in FIG. 5 is used to illustrate the semiconductor structure after the third insulating dielectric layer 400 is formed in the memory cell array area, and (b) in FIG. 5 is used to illustrate the semiconductor structure in the peripheral circuit area.
  • the width of the third insulating dielectric layer 400 (ie, the second bit line isolation structure 2202 ) in the memory cell array region is the same as the width of the first bit line isolation structure 2201
  • the width may be the same or different; in this embodiment, the width of the second bit line isolation structure 2202 is the same as the width of the first bit line isolation structure 2201, located above the first bit line isolation structure, and the two are in contact with each other .
  • the third insulating dielectric layer 400 is formed in the first void 510a and the second void 520a, in order to remove the third insulating dielectric layer 400 and the periphery formed on the top surface of the bit line conductive structure 210
  • the third insulating dielectric layer 400 on the substrate surface of the circuit area is dry-etched and controlled by etching conditions to obtain a very high selectivity ratio of silicon nitride, silicon oxide and metal tungsten, so as to ensure that the conductive structure of the bit line is not damaged.
  • the thickness of the third insulating dielectric layer 400 remaining on the sidewall of the first gap 510a can also be adjusted by controlling the etching conditions, for example, using an etching method containing difluoromethane, oxygen and argon.
  • the etching selectivity ratio between silicon nitride, metal tungsten and silicon oxide is about 10:3:2.
  • the thickness of the third insulating dielectric layer 400 in the sidewalls of the first void 510a and the second void 520a is 2 ⁇ 4 nm.
  • the thickness of the third insulating dielectric layer 400 can effectively insulate and isolate the bit line conductive structure/conductive structure 210, and at the same time, the thickness of the third insulating medium layer 400 can be controlled to be smaller than that of the first bit line.
  • the isolation structure avoids occupying the space of the first connection structure 510 and the second connection structure 520 due to the thickness too large, thereby reducing the resistance of the first connection structure 510 and the second connection structure 520 .
  • the thickness of the third insulating dielectric layer 400 may also be greater than that of the first bit line isolation structure 2201.
  • the thickness of the additional layer 400 may be 2.5 nm, 3.0 nm and 3.5 nm .
  • a metal material is deposited through a deposition process to form a connecting material layer, the connecting material layer covers the third insulating dielectric layer 400 and the first insulating dielectric layer 310 and the first insulating dielectric layer 310
  • the tops of the second insulating dielectric layers 320 are filled with the first voids 510a and the second voids 520a; then, an etching process or a chemical mechanical process is used to remove a part of the height of the connecting material layer until the third insulating layer is exposed
  • the dielectric layer 400 and the tops of the first insulating dielectric layer 310 and the second insulating dielectric layer 320 form a first connection structure 510 and a second connection structure 520 .
  • Embodiments of the present application also provide a semiconductor structure fabricated by using the method provided in any of the preceding embodiments, please continue to refer to FIG. 6 .
  • the semiconductor structure includes: a substrate 100 , a bit line structure 200 and a first insulating dielectric layer 310 .
  • the substrate 100 has a memory cell array region and a peripheral circuit region, and a first insulating medium layer 310 is formed on the substrate of the memory cell array region.
  • the bit line structure 200 is formed in the first insulating dielectric layer 310, and the bit line structure 200 includes a bit line conductive structure and an isolation structure 220 located on the sidewall of the bit line conductive structure.
  • the bit line conductive structure The isolation structure 220 includes a first conductive structure 210 and a second conductive structure 230 connected to the top of the first conductive structure.
  • the thicknesses of the two bit line isolation structures 2202 , the first bit line isolation structures 2201 and the second bit line isolation structures 2202 on the sidewalls of the bit line conductive structures 210 may be the same or different.
  • the semiconductor structure is provided by the method provided in any of the above embodiments. Therefore, the isolation structure 220 is used to repair the bit line isolation structure damaged in the PC process, so as to solve the problem of the current bit line isolation structure caused by the PC process. The problem that the line sidewalls are damaged further improves the quality of the semiconductor structure.
  • the semiconductor structure further includes a peripheral circuit region, a second insulating dielectric layer 320 , a conductive structure 210 and a third isolation structure 2203 .
  • the peripheral circuit area is formed on the substrate 100, and a second insulating dielectric layer 320 is formed on the substrate of the peripheral circuit area; the conductive structure 210 is formed in the second insulating dielectric layer 320, so A third isolation structure 2203 is also formed on the periphery of at least one sidewall of the conductive structure, and the third isolation structure is of the same material as the second isolation structure.
  • the third isolation structure includes a third isolation structure formed in direct contact with the sidewall of the conductive structure 210 and a third isolation structure deposited on the surface of the second insulating medium layer on the sidewall of the conductive structure. Three isolation structures.
  • an interconnection structure is also included, and the interconnection structure in this application is the second connection structure 520 formed above.
  • the interconnection structure is formed in the second insulating dielectric layer 320, and is isolated from the conductive structure 210 by the third isolation structure 2203 to prevent the second insulating dielectric layer 320 in the peripheral circuit region from being etched. Exposing the surface of the conductive structure 210 leads to the problem that the interconnection structure is in direct contact with the conductive structure 210 .
  • the bottom of the interconnect structure also extends into the substrate to connect with the active area of the peripheral circuit area.
  • the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • the manufacturing method includes: providing a substrate, the substrate having a memory cell array region and a peripheral circuit region; forming a first insulating medium layer and a second insulating medium layer in the memory cell array region and the peripheral circuit region , the first insulating medium layer is formed with a bit line structure arranged at intervals, and the second insulating medium layer is formed with a conductive structure arranged at intervals, wherein the bit line structure includes a bit line conductive structure and a cover isolation structures on the top and sidewalls of the bit line conductive structure; etching the isolation structure and the second insulating dielectric layer between the conductive structures in the peripheral circuit region, so as to be in the memory cell array region respectively forming a first gap and a second gap with the peripheral circuit region, the first gap at least partially exposing the bit line conductive structure, and the second gap exposing between the conductive structures in the peripheral circuit region the substrate; a third insulating dielectric layer
  • a third insulating medium layer is formed covering the sidewalls of the first void hole and the second void, and the conductive structure is protected by the third insulating medium layer sidewalls, thereby isolating the second connection structure from the conductive structure, avoiding a short circuit between the second connection structure in the peripheral circuit area and the conductive structure in the peripheral circuit area, and preventing capacitor contact holes in the memory cell array area Leakage contact occurs between the conductive line and the bit line conductive structure in the memory cell array region; and the third insulating medium layer is used to fill the first bit line isolation structure between the bit line conductive structure and the first insulating medium layer.
  • the gap formed after being partially etched away is used to repair the damaged bit line isolation structure in the PC process, so as to solve the current problem that the side wall of the bit line is damaged due to the PC process, and further improve the quality of the semiconductor structure.

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Abstract

一种半导体结构及其制作方法。其中方法包括：提供衬底，所述衬底具有存储单元阵列区和周边电路区（S110）；在存储单元阵列区和周边电路区形成第一绝缘介质层和第二绝缘介质层，第一绝缘介质层中形成有间隔排布的位线结构，第二绝缘介质层中形成有间隔排布的导电结构，其中，位线结构包括位线导电结构和覆盖位线导电结构顶部和侧壁的隔离结构（S120）；蚀刻隔离结构以及周边电路区的导电结构之间的第二绝缘介质层，以分别在存储单元阵列区和周边电路区形成第一空隙和第二空隙，第一空隙至少部分暴露出位线导电结构，第二空隙暴露出周边电路区的导电结构之间的衬底（S130）；在第一空隙的侧壁和第二空隙的侧壁形成第三绝缘介质层（S140）。

Description

半导体结构及其制作方法
相关申请的交叉引用
本申请要求于2020年8月21日提交中国专利局、申请号为202010847669X、发明名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体存储器件技术领域，特别是涉及一种半导体结构及其制备方法。
技术背景
随着半导体存储器件尺寸微缩，存储单元阵列区和周边电路区的晶体管的尺寸都越来越小，导致对套刻误差的要求越来越高，也越接近套刻误差控制的极限。周边电路接触连接工艺的目的之一是挖洞将金属层和有源区连接起来，但是由于在周边电路区内栅极(Periphery Gate,PG)之间的距离较小，要想通过PC(Periphery Contact)工艺在两个栅极之间连接有源区，又不与周边电路区的晶体管的栅极发生短路，这对套刻误差的要求极高。此外，PC另外一个目的是与位线BL连接起来，但是由于BL的尺寸太小，主体金属层W部分的关键尺寸大概11nm左右,因此PC on BL的刻蚀过程中会使得BL侧壁被损坏严重。
发明内容
根据本申请的各种实施例，提供一种半导体结构及其制作方法。
本申请提供了一种半导体结构的制作方法，包括：
提供衬底，所述衬底具有存储单元阵列区和周边电路区；
在所述存储单元阵列区和所述周边电路区形成第一绝缘介质层和第二绝 缘介质层，所述第一绝缘介质层中形成有间隔排布的位线结构，所述第二绝缘介质层中形成有间隔排布的导电结构，其中，所述位线结构包括位线导电结构和覆盖所述位线导电结构顶部和侧壁的隔离结构；
蚀刻所述隔离结构以及所述周边电路区的所述导电结构之间的所述第二绝缘介质层，以分别在所述存储单元阵列区和所述周边电路区形成第一空隙和第二空隙，所述第一空隙至少部分暴露出所述位线导电结构，所述第二空隙暴露出所述周边电路区的所述导电结构之间的所述衬底；及
在所述第一空隙的侧壁和所述第二空隙的侧壁形成第三绝缘介质层，所述第一空隙侧壁的所述第三绝缘介质层与所述位线结构侧壁的所述隔离结构的厚度可以相同或不同。
本申请实施例还提供了一种半导体结构，包括：
衬底，所述衬底具有存储单元阵列区，所述存储单元阵列区的所述衬底上形成有第一绝缘介质层；
位线结构，所述位线结构形成在所述第一绝缘介质层中，所述位线结构包括位线导电结构以及位于所述位线导电结构侧壁的隔离结构，所述位线导电结构包括第一导电结构以及与所述第一导电结构顶部连接的第二导电结构，所述隔离结构包括第一位线隔离结构和位于所述第一位线隔离结构上方的第二位线隔离结构，所述第一位线隔离结构和所述第二位线隔离结构在所述位线导电结构的侧壁上的厚度可以相同或不同。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种半导体结构的制备方法的流程图；
图2-图6为本申请实施例提供的逐步形成的半导体结构的结构示意图。
附图标记说明：衬底-100，位线结构-200，位线导电结构/导电结构/第一导电结构-210，第二导电结构-230，第一导电层-2101，第二导电层2102，隔离结构220，第一位线隔离结构-2201，第二位线隔离结构-2202，第三隔离结构-2203，第二导电结构-230，第一绝缘介质层-310，第二绝缘介质层-320，第三绝缘材料层-400a，第三绝缘介质层400，第一连接结构-510，第一空隙-510a，第二连接结构-520，第二空隙-520a。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
请参见图1，本申请实施例提供了一种半导体结构的制作方法，包括：
步骤S110，提供衬底100，所述衬底100具有存储单阵列区(array)和周边电路区(periphery)；
步骤S120，在所述存储单元阵列区和所述周边电路区形成第一绝缘介质层310和第二绝缘介质层320，所述第一绝缘介质层310中形成有间隔排布的位线结构200，所述第二绝缘介质层320中形成有间隔排布的导电结构210，其中，位线结构200包括位线导电结构210和覆盖所述位线导电结构顶部和侧壁的第一位线隔离结构2201，其中，该位线导电结构210由下至上可以依次包括第一导电层2101和第二导电层2102，如图2所示；
步骤S130，以位线导电结构210为蚀刻停止层，对存储单元阵列区内的第一位线隔离结构2201进行刻蚀以形成第一空隙510a，通过所述第一空隙510a至少暴露出所述位线导电结构210的部分表面，以及在所述周边电路区 内对第二绝缘介质层320进行蚀刻，在间隔的导电结构210之间形成暴露衬底100的第二空隙520a，其中，由于周边电路区的导电结构210之间的间距越来越小，在蚀刻时，可能导致所述导电结构210的至少一侧壁也同时暴露出来，如图3所示；
步骤S140，形成第三绝缘介质层400，所述第三绝缘介质层400覆盖所述第一空隙510a和所述第二空隙520a的侧壁，如图4和图5所示；
步骤S150，填充所述第一空隙510a和所述第二空隙520a，分别形成第一连接结构510和第二连接结构520，实现电性连接，请参见图6。
可以理解，由于刻蚀工艺受到套刻误差的限制，在PC工艺中可能会暴露出导电结构210部分侧壁或损坏部分第一位线隔离结构2201。当在周边电路区内的导电结构210的侧壁被暴露出时，则会导致第二连接结构520与周边电路区的导电结构210之间发生短路。为解决该问题，本实施例中在通过上述步骤S110至步骤S130形成第一空隙510a和第二空隙520a后，形成覆盖所述第一空隙孔510a和所述第二空隙520a的侧壁的第三绝缘介质层400，利用第三绝缘介质层400保护所述导电结构210的侧壁，从而将第二连接结构520与所述导电结构210隔离，避免周边电路区内的第二连接结构520与周边电路区的导电结构210之间发生短路，以及在存储单元阵列区内防止电容接触孔导线与存储单元阵列区的位线导电结构210之间发生漏电接触；并且，利用所述第三绝缘介质层400填充所述位线导电结构210与第一绝缘介质层310之间的由于第一位线隔离结构2201被部分刻蚀掉后所形成的间隙，形成第二隔离结构2202，与第一位线隔离结构2201组成新的位线隔离结构220，实现对PC工艺中被损坏的位线隔离结构修复，以解决目前因PC工艺导致位线侧壁被损坏的问题，进一步提高半导体结构的品质。
本实施例中，所述衬底100包括硅基底、外延硅基底、硅锗基底、碳化硅基底或硅覆绝缘基底，但不以此为限。本领域的技术人员可以根据需要在衬底上形成的半导体器件选择所述半导体衬底的类型，因此所述半导体衬底的类型不应限制本申请的保护范围。本实施例中，所述衬底100为P型晶体 硅衬底。
所述衬底100包括基底和形成于基底内形成的浅沟槽结构，通过所述浅沟槽结构定出多个平行交错设置的多个有源区，且所述浅沟槽结构内填充有绝缘材料以形成浅沟槽隔离结构。所述衬底100还包括字线结构和位线结构200，其中所述字线结构为埋入式字线结构，该埋入式字线结构的延伸方法与所述位线结构200的延伸方向交叉。所述位线结构200包括位线导电结构210和覆盖所述位线导电结构顶部和侧壁的隔离结构220。
在其中一个实施例中，所述位线导电结构和所述导电结构同时形成，形成所述位线导电结构和所述导电结构的步骤包括：
在所述存储单元阵列区和所述周边电路区形成第一导电材料层；
形成覆盖所述第一导电材料层的第二导电材料层；
刻蚀所述第一导电材料层和所述第二导电材料层，在所述存储单元阵列区和所述周边电路区同时形成所述位线导电结构和所述导电结构。
本实施例中形成位线结构200和导电结构210的步骤包括：
步骤一，同时在衬底100的存储单元阵列区和周边电路区上利用沉积工艺沉积绝缘材料材料，以形成间隔层(未图示)；所述绝缘材料可以为氧化硅、氮化硅、氮氧化硅等，具体材料可根据工艺需求进行选择。本实施例中，采用氮化硅形成所述间隔层。另外，所述沉积工艺可以包括化学气相沉积(CVD)、低压CVD(LPCVD)、等离子体增强CVD(PECVD)、原子层沉积(ALD)以及等离子体增强ALD(PEALD)等。本实施例中，所述间隔层完全覆盖所述衬底100的表面，且顶部比较平坦。
步骤二，通过沉积工艺依次沉积半导体导电材料、金属材料和绝缘材料，分别形成所述第一导电材料层、第二导电材料层和所述绝缘材料层。本实施例中，采用多晶硅、低温多晶硅等制作所述第一导电材料层，利用氮化钛、钛、硅化钨、氮化钨中的任一中或任意组合制作所述第二导电材料层，利用所述氮化硅制作所述绝缘材料。
步骤三，在所述绝缘材料层上依次形成第一有机掩膜材料层、第一硬掩 膜材料层，并在所述第一硬掩膜材料层表面涂覆一层光刻胶，形成第一光刻胶层；其中，所述第一硬掩膜材料层的材料可以为氮化物、氧化物，例如氮氧化硅、氧化硅碳等，所述第一有机掩膜材料层可以为抗反射材料、有机碳材料等。然后，对所述第一光刻胶层进行曝光、清洗等步骤后形成定义所述位线结构200和导电结构210的图案。再然后，以图案化第一光刻胶层为掩膜，对所述第一有机掩膜材料层和所述第一硬掩膜材料层进行刻蚀，直至露出所述绝缘材料层，将图案转移到所述第一有机掩膜材料层和所述第一硬掩膜材料层中，剩余的第一有机掩膜材料层和第一硬掩膜材料层构成第一硬掩膜层。最后，去除所述光刻胶层。
步骤四，以第一硬掩膜层为掩膜，对所述第一导电材料层、所述第二导电材料层和所述绝缘材料层进行刻蚀，同时形成所述位线结构200和导电结构210。
在形成位线结构200以后，为了防止位线导电结构210与后续形成的电容接触孔导线之间的漏电接触，需要形成覆盖位线结构200侧壁的第一位线隔离结构2201。在其中一个实施例中，形成所述第一位线隔离结构2201的步骤包括：
在形成所述位线结构200后，形成隔离材料层，所述隔离材料层覆盖所述位线结构200侧壁、顶部以及所述衬底100表面；
对所述隔离材料层进行刻蚀，去除位于所述衬底100表面和所述位线结构200顶部的隔离材料层，保留的位于所述位线结构200侧壁上的所述隔离材料作为所述第一位线隔离结构2201。
本实施例中，形成第一位线隔离结构2201的步骤包括：首先，通过沉积绝缘材料形成覆盖所述位线结构200的表面以及所述衬底100表面的隔离材料层。本实施例中，采用氮化硅制作所述隔离材料层，在本申请的另一个实施例中，该隔离材料层可以与位于位线结构顶部的绝缘材料层采用相同的材质；然后，利用刻蚀工艺对所述隔离材料层进行刻蚀，去除位于所述位线结构200顶部以及所述衬底100表面的隔离材料层，保留位于所述位线结构200 侧壁上的隔离材料层和位于位线结构200顶部的绝缘材料层，位线结构200顶部的绝缘材料层和位线结构200侧壁的隔离材料层一起作为所述第一位线隔离结构2201。
在形成位线隔离结构2201后，通常利用沉积工艺和刻蚀/化学机械研磨工艺在存储单元阵列区形成第一绝缘介质层310。在其中一个实施例中，形成所述第一绝缘介质层310的步骤包括：
在形成所述第一位线隔离结构2201后，在所述存储单元阵列区内形成第一绝缘填充材料层，所述第一绝缘填充材料层填满所述第一位线隔离结构2201之间的间隙，并覆盖所述位线结构200的顶部；
对所述第一绝缘填充材料层进行研磨，直至露出所述位线结构200的顶部，保形成所述第一绝缘介质层310。
在形成周边电路区的导电结构210后，在所述周边电路区内形成第二绝缘填充材料层，所述第二绝缘填充材料层填满所述导电结构210之间的间隙，并覆盖所述导电结构210的顶部，形成第二绝缘介质层320。
本实施例中分别形成第一绝缘介质层310和第二绝缘介质层320。具体的：
在形成第一位线隔离结构2201后，首先遮住存储单元阵列区，在周边电路区内沉积氮化硅材料，在周边电路区内形成第二绝缘填充材料层，所述第二绝缘填充材料层填满所述导电结构210之间的间隙，并覆盖所述导电结构210的顶部，如图2中的(b)图所示。
在形成第二绝缘介质层320后，遮住所述周边电路区，在所述存储单元阵列区内沉积第一绝缘填充材料，以形成第一绝缘填充材料层，所述第一绝缘填充材料层填满所述位线隔离结构220之间的间隙，并覆盖所述位线结构200的顶部；然后利用刻蚀工艺或化学机械研磨工艺去除部分高度的所述第一绝缘填充材料层，直至露出所述位线结构200的顶部，保留的所述第一绝缘填充材料层作为所述第一绝缘介质层310，如图2中的(a)图所示。
可以理解，在其它一些实施例中还可以在形成存储单元阵列区的第一位 线隔离结构2201之后，先形成第一绝缘介质层310，再形成第二绝缘介质层320；或者，在形成存储单元阵列区的第一位线隔离结构2201时，一并在周边电路区形成第二绝缘介质层320，然后再形成第一绝缘介质层310。本实施例对第一绝缘介质层和第二绝缘介质层的具体实现步骤和方式不做任何限制。
在形成位线结构200、第一位线隔离结构2201和第一绝缘介质层310和第二绝缘介质层320后，利用刻蚀工艺分别在周边电路区和存储单元阵列区形成空隙。在其中一个实施例中，形成所述第一空隙510a的步骤，包括：
在所述存储单元阵列区内，以所述位线导电结构210为刻蚀停止层，对所述第一位线隔离结构2201进行刻蚀，去除位于所述位线导电结构210顶部所在平面上方的所述第一位线隔离结构2201以及位于所述位线导电结构210侧壁的部分第一位线隔离结构2201，形成所述第一空隙510a。
可以理解，本实施例中利用同一刻蚀工序形成第一空隙510a和第二空隙520a，只要拉开第二导电材料层(即金属钨)和氮化硅的选择比即可。这样在存储单元阵列区内第一空隙510a做好后基本停止了刻蚀，但是在周边电路区还会接着往下刻蚀，在接触到衬底100表面时，如按照预设时间往下刻蚀，即可固定好深度。形成第一空隙510a和第二空隙520a的过程具体包括：
第一步，在第一绝缘介质层310和第二绝缘介质层320上形成第二硬掩膜层，所述第二硬掩膜层中具有空隙，通过所述空隙可定义出第一空隙510a和第二空隙520a。其中，在存储单元阵列区内，所述空隙位于所述第一位线隔离结构2201的正上方；在所述周边电路区内，所述空隙位于两个导电结构210之间区域的正上方。
第二步，以第二硬掩膜层为掩膜，在存储单元阵列区内，利用氮化硅相对氧化硅的刻蚀比，去除位于所述位线导电结构210上方的第一位线隔离结构2201以及位于位线导电结构210侧壁的部分第一位线隔离结构2201，形成第一空隙510a；以及，在周边电路区内去除位于两个导电结构210之间的第二绝缘介质层320，以形成第二空隙520a。可以理解，受刻蚀工艺的限制， 在存储单元阵列区内，为了完全暴露出所述位线导电结构210的顶部，实际刻蚀工艺中会刻蚀掉部分位于位线导电结构210与第一绝缘介质层310之间的部分第一位线隔离结构2201，导致形成的第一空隙510a的底部呈W型，如图3中的(a)图所示；以及，受套刻误差的限制，在周边电路区内刻蚀掉了部分第二绝缘介质层320以及衬底100，暴露出了导电结构210的部分侧壁和衬底有源区，如图3中的(b)图所示。
在其中一个实施例中，利用所述第一位线隔离结构2201相对于所述第一绝缘介质层310的刻蚀选择比形成所述第一空隙510a。本实施例中，采用氮化硅制作第一位线隔离结构2201，利用氧化硅制作所述第一绝缘介质层310，采用钨作为位线导电结构210和导电结构210，通过控制蚀刻条件，将位线导电结构210顶部及侧壁的部分第一位线隔离结构2201蚀刻掉并停止在位线导电结构210上面，形成第一空隙510a，同时在周边电路区中形成第二空隙520a。
另外，本实施例中所述第一位线隔离结构2201、所述绝缘层400和所述第二绝缘介质层320可以采用相同的绝缘材料，例如氮化硅，在本申请的另一个实施例中，第一位线隔离结构2201、第三绝缘介质层400以及第二绝缘介质层320为氮化硅，第一绝缘介质层310为氧化硅。
可以理解，位线导电结构210与第一绝缘介质层310之间的第一位线隔离结构2201被部分刻蚀后，可能会导致后续形成的电容接触孔导线与位线导电结构210之间发生漏电接触；以及，周边电路区内导电结构210侧壁的部分第二绝缘介质层320被刻蚀掉后，会导致第二连接结构520与导电结构210直接接触，二者之间发生短路。为了解决该问题，本实施例中通过形成第三绝缘介质层400，将周边电路区的导电结构210与第二连接结构520绝缘隔离。
在其中一个实施例中，形成所述第三绝缘介质层400的步骤包括：
形成第三绝缘材料层400a，所述第三绝缘材料层400a覆盖所述第一空隙510a和所述第二空隙520a的表面以及所述第一绝缘介质层310和第二绝缘介 质层320的顶部；
对所述第三绝缘材料层400a进行刻蚀，去除位于所述位线结构200、所述衬底100以及所述第一绝缘介质层310和第二绝缘介质层320顶部的所述第三绝缘材料层400a，保留的位于所述第一空隙510a和所述第二空隙520a侧壁上的所述第三绝缘材料层400a作为第三绝缘介质层400，其中，第一空隙510a侧壁的第三绝缘介质层400为第二位线隔离结构2202，其与第一位线隔离结构2201抵接，以对位线导电结构210形成隔离。
本实施例中，利用氮化硅材料形成所述第三绝缘介质层400，具体工艺包括：
1)利用沉积工艺沉积氮化硅材料，以形成第三绝缘材料层400a，所述第三绝缘材料层400a覆盖所述第一空隙510a和所述第二空隙520a的表面以及第一绝缘介质层310和第二绝缘介质层320的顶部，请参见图4，其中图4中的(a)图用于示意在存储单元阵列区内的形成第三绝缘材料层400a后的半导体结构，图4中的(b)图用于示意在周边电路区内的形成第三绝缘材料层400a后的半导体结构；可以理解，所述第三绝缘材料层400a会覆盖露出的位线导电结构210的侧壁和顶部，以及至少填充部分位于导电结构210与第二绝缘介质层320之间的间隙。
2)利用刻蚀工艺对所述第三绝缘材料层400a进行刻蚀，去除位于所述位线导电结构210顶表面、所述衬底100以及第一绝缘介质层310和第二绝缘介质层320顶部的所述第三绝缘材料层400a，保留位于所述第一空隙510a和所述第二空隙520a侧壁上的所述第三绝缘材料层400a作为所述第三绝缘介质层400；请参见图5，其中图5中的(a)图用于示意在存储单元阵列区内的形成第三绝缘介质层400后的半导体结构，图5的(b)图用于示意在周边电路区内的形成第三绝缘介质层400后的半导体结构。图5中的(a)图所示的剖面图中，在所述存储单元阵列区内第三绝缘介质层400(即第二位线隔离结构2202)的宽度与第一位线隔离结构2201的宽度可以相同也可以不同；本实施例中，第二位线隔离结构2202的宽度与第一位线隔离结构2201 的宽度相同，位于所述第一位线隔离结构的上方，且二者抵接。
在本申请的另一个实施例中，在第一空隙510a以及第二空隙520a中形成第三绝缘介质层400后，为了除去形成在位线导电结构210顶表面的第三绝缘介质层400以及周边电路区的衬底表面的第三绝缘介质层400，利用干法蚀刻，通过控制蚀刻条件，得到非常高的氮化硅、氧化硅以及金属钨的选择比，从而在保证不损坏位线导电结构210以及衬底上的有源区的情况下去除位于位线导电结构210顶表面以及周边电路区衬底有源面上的第三绝缘介质层400，同时不破坏形成在第一空隙510a侧壁的第三绝缘介质层400，此外，还可以通过控制蚀刻条件，调节保留在第一空隙510a侧壁的第三绝缘介质层400的厚度，例如，利用包含二氟甲烷、氧气和氩气的刻蚀气体进行刻蚀时，氮化硅、金属钨和氧化硅之间的刻蚀选择比约为10:3:2。
在其中一个实施例中，所述第三绝缘介质层400在第一空隙510a以及第二空隙520a侧壁的厚度为2～4nm。
可以理解，将所述第三绝缘介质层400的厚度范围设置在2～4nm内，可有效对位线导电结构/导电结构210起到绝缘隔离作用，同时还可以控制其厚度小于第一位线隔离结构，避免因厚度太大而挤占第一连接结构510和第二连接结构520的空间，从而降低第一连接结构510和第二连接结构520的电阻。在本申请的另一个实施例中，该第三绝缘介质层400的厚度也可以大于第一位线隔离结构2201，优选的，所述附加层400的厚度可以为2.5nm、3.0nm和3.5nm。
请参见图6，在形成第三绝缘介质层400之后，通过沉积工艺沉积金属材料以形成连接材料层，所述连接材料层覆盖所述第三绝缘介质层400和第一绝缘介质层310和第二绝缘介质层320的顶部，且填满所述第一空隙510a和所述第二空隙520a；然后，利用刻蚀工艺或化学机械工艺去除部分高度的连接材料层，直至露出所述第三绝缘介质层400和所述第一绝缘介质层310和第二绝缘介质层320的顶部，形成第一连接结构510和第二连接结构520。
本申请实施例还提供了利用上任一实施例提供的方法制作的半导体结 构，请继续参见图6。所述半导体结构包括：衬底100、位线结构200和第一绝缘介质层310。
所述衬底100具有存储单阵列区和周边电路区，所述存储单元阵列区的所述衬底上形成有第一绝缘介质层310。
所述位线结构200形成在所述第一绝缘介质层310中，所述位线结构200包括位线导电结构以及位于所述位线导电结构侧壁的隔离结构220，所述位线导电结构包括第一导电结构210以及与所述第一导电结构顶部连接的第二导电结构230，所述隔离结构220包括第一位线隔离结构2201和位于所述第一位线隔离结构2201上方的第二位线隔离结构2202，所述第一位线隔离结构2201和所述第二位线隔离结构2202在所述位线导电结构210的侧壁上的厚度可以相同或不同。
本实施例中，该半导体结构是通过上述任一实施例提供的方法提供的，因此，通过所述隔离结构220对PC工艺中被损坏的位线隔离结构修复，以解决目前因PC工艺导致位线侧壁被损坏的问题，进一步提高半导体结构的品质。
在其中一个实施例中，所述半导体结构还包括周边电路区、第二绝缘介质层320、导电结构210和第三隔离结构2203。
所述周边电路区形成在所述衬底100上，所述周边电路区的所述衬底上形成有第二绝缘介质层320；所述第二绝缘介质层320中形成有导电结构210，所述导电结构至少一侧壁外围还形成有第三隔离结构2203，所述第三隔离结构与所述第二隔离结构材质相同。本实施例中，所述第三隔离结构包括直接与所述导电结构210侧壁接触的形成所述第三隔离结构和沉积在位于所述导电结构侧壁上的第二绝缘介质层表面的第三隔离结构。
在其中一个实施例中，还包括互连结构，本申请中所述互连结构即上述形成的第二连接结构520。所述互连结构形成在所述第二绝缘介质层320中，且通过所述第三隔离结构2203与所述导电结构210隔离，避免周边电路区域内的第二绝缘介质层320被刻蚀后露出导电结构210表面进而导致产生所述 互连结构与导电结构210直接接触的问题。
在其中一个实施例中，所述互连结构的底部还延伸至所述衬底中，与周边电路区的有源区连接。
综上，本申请实施例提供了一种半导体结构及其制作方法。其中所述制作方法包括：提供衬底，所述衬底具有存储单元阵列区和周边电路区；在所述存储单元阵列区和所述周边电路区形成第一绝缘介质层和第二绝缘介质层，所述第一绝缘介质层中形成有间隔排布的位线结构，所述第二绝缘介质层中形成有间隔排布的导电结构，其中，所述位线结构包括位线导电结构和覆盖所述位线导电结构顶部和侧壁的隔离结构；蚀刻所述隔离结构以及所述周边电路区的所述导电结构之间的所述第二绝缘介质层，以分别在所述存储单元阵列区和所述周边电路区形成第一空隙和第二空隙，所述第一空隙至少部分暴露出所述位线导电结构，所述第二空隙暴露出所述周边电路区的所述导电结构之间的所述衬底；在所述第一空隙的侧壁和所述第二空隙的侧壁形成第三绝缘介质层，所述第一空隙侧壁的所述第三绝缘介质层与所述位线结构侧壁的所述隔离结构的厚度可以相同或不同。本申请中，在形成第一空隙和第二空隙后，形成覆盖所述第一空隙孔和所述第二空隙的侧壁的第三绝缘介质层，利用第三绝缘介质层保护所述导电结构的侧壁，从而将第二连接结构与所述导电结构隔离，避免周边电路区内的第二连接结构与周边电路区的导电结构之间发生短路，以及在存储单元阵列区内防止电容接触孔导线与存储单元阵列区的位线导电结构之间发生漏电接触；并且，利用所述第三绝缘介质层填充所述位线导电结构与第一绝缘介质层之间的由于第一位线隔离结构被部分刻蚀掉后所形成的间隙，实现对PC工艺中被损坏的位线隔离结构修复，以解决目前因PC工艺导致位线侧壁被损坏的问题，进一步提高半导体结构的品质。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术 语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种半导体结构的制作方法，包括：
    提供衬底，所述衬底具有存储单元阵列区和周边电路区；
    在所述存储单元阵列区和所述周边电路区形成第一绝缘介质层和第二绝缘介质层，所述第一绝缘介质层中形成有间隔排布的位线结构，所述第二绝缘介质层中形成有间隔排布的导电结构，其中，所述位线结构包括位线导电结构和覆盖所述位线导电结构顶部和侧壁的隔离结构；
    蚀刻所述隔离结构以及所述周边电路区的所述导电结构之间的所述第二绝缘介质层，以分别在所述存储单元阵列区和所述周边电路区形成第一空隙和第二空隙，所述第一空隙至少部分暴露出所述位线导电结构，所述第二空隙暴露出所述周边电路区的所述导电结构之间的所述衬底；及
    在所述第一空隙的侧壁和所述第二空隙的侧壁形成第三绝缘介质层，所述第一空隙侧壁的所述第三绝缘介质层与所述位线结构侧壁的所述隔离结构的厚度可以相同或不同。
  2. 如权利要求1所述的半导体结构的制作方法，其中，所述第二空隙还延伸至所述衬底中。
  3. 如权利要求1所述的半导体结构的制作方法，其中，所述第一空隙还延伸至所述位线导电结构的侧壁与所述第一绝缘介质层之间。
  4. 如权利要求1所述的半导体结构的制作方法，其中，所述位线导电结构和所述导电结构同时形成，形成所述位线导电结构和所述导电结构的步骤包括：
    在所述存储单元阵列区和所述周边电路区形成第一导电材料层；
    形成覆盖所述第一导电材料层的第二导电材料层；
    刻蚀所述第一导电材料层和所述第二导电材料层，在所述存储单元阵列区和所述周边电路区同时形成所述位线导电结构和所述导电结构。
  5. 如权利要求4所述的半导体结构的制作方法，其中，形成所述隔离结构的步骤包括：
    在所述第二导电材料层上形成所述第二绝缘介质层，蚀刻所述存储单元阵列区的所述第一导电材料、所述第二导电材料以及所述第二绝缘介质层，形成所述位线结构，并保留所述位线结构上表面的所述第二绝缘介质层；
    在所述位线结构的侧壁形成第二绝缘介质层，形成覆盖所述位线结构顶部和侧部的所述隔离结构。
  6. 如权利要求1所述的半导体结构的制作方法，还包括：
    分别于所述第一空隙和所述第二空隙内形成第一连接结构和第二连接结构。
  7. 一种半导体结构，包括：
    衬底，所述衬底具有存储单元阵列区，所述存储单元阵列区的所述衬底上形成有第一绝缘介质层；
    位线结构，所述位线结构形成在所述第一绝缘介质层中，所述位线结构包括位线导电结构以及位于所述位线导电结构侧壁的隔离结构，所述位线导电结构包括第一导电结构以及与所述第一导电结构顶部连接的第二导电结构，所述隔离结构包括第一位线隔离结构和位于所述第一位线隔离结构上方的第二位线隔离结构，所述第一位线隔离结构和所述第二位线隔离结构在所述位线导电结构的侧壁上的厚度可以相同或不同。
  8. 如权利要求7所述的半导体结构，还包括：
    周边电路区，所述周边电路区形成在所述衬底上，所述周边电路区的所述衬底上形成有第二绝缘介质层；
    所述第二绝缘介质层中形成有导电结构，所述导电结构至少一侧壁外围还形成有第三隔离结构，所述第三隔离结构与所述第二隔离结构材质相同。
  9. 如权利要求8所述的半导体结构，还包括互连结构，所述互连结构形成在所述第二绝缘介质层中，且通过所述第三隔离结构与所述导电结构隔离。
  10. 如权利要求9所述的半导体结构，其中，所述互连结构的底部还延伸至所述衬底中。
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