WO2023070884A1 - 一种半导体器件的制备方法及半导体器件 - Google Patents

一种半导体器件的制备方法及半导体器件 Download PDF

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Publication number
WO2023070884A1
WO2023070884A1 PCT/CN2021/138457 CN2021138457W WO2023070884A1 WO 2023070884 A1 WO2023070884 A1 WO 2023070884A1 CN 2021138457 W CN2021138457 W CN 2021138457W WO 2023070884 A1 WO2023070884 A1 WO 2023070884A1
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layer
insulating material
capping
semiconductor device
region
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PCT/CN2021/138457
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English (en)
French (fr)
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郭帅
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长鑫存储技术有限公司
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Priority to US18/314,844 priority Critical patent/US20230282572A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor device and the semiconductor device.
  • the node contact hole formed in the boundary area Due to the influence of the pattern loading effect in the etching process, there is a certain difference between the pattern density of the boundary area of the memory array area and the pattern density of the internal area, so that the node contact hole formed in the boundary area will contact the node formed in the internal area Hole consistency is poor. Therefore, when forming the node contact hole in the prior art, the node contact hole originally to be formed in the boundary area is made into a dummy contact hole, which is not used as a component of the circuit, thereby avoiding the problem caused by the poor consistency of the node contact hole. The problem.
  • the embodiments of the present disclosure provide a method for manufacturing a semiconductor device and a semiconductor device in order to solve at least one problem existing in the background art.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor device.
  • the method includes: providing a substrate, the substrate includes a memory array area, a plurality of bit lines are formed on the memory array area, and a plurality of bit lines are formed on the memory array area.
  • the lines are filled with a first insulating material, and the first insulating material has a plurality of trenches intersecting with the bit lines; wherein, the memory array area includes an inner area and a boundary area outside the inner area ;
  • performing an etching process to form a node contact hole including: etching the capping material layer to form a capping layer, the capping layer covering the bit line, the spacer line and the first insulating material located in the boundary region ; using the capping layer as a mask, etching and removing the first insulating material in the inner region to form the node contact hole.
  • An embodiment of the present disclosure also provides a semiconductor device, the device comprising: a substrate, the substrate including a memory array region, the memory array region including an inner region and a boundary region outside the inner region;
  • a capping layer covers the bit line, the spacer line and the first insulating material in the boundary region.
  • the method for manufacturing a semiconductor device and the semiconductor device provided by the embodiments of the present disclosure, wherein the method includes: providing a substrate, the substrate includes a memory array region, and a plurality of bit lines are formed on the memory array region, and a plurality of bit lines are formed on the memory array region.
  • a first insulating material is filled between the bit lines, and there are a plurality of trenches intersecting the bit lines in the first insulating material; wherein, the memory array area includes an inner area and a The outer boundary region; fill the second insulating material in the trench to form a spacer line, and the second insulating material is also deposited on the bit line, the spacer line and the first insulating material to form a cap material layer; performing an etching process to form a node contact hole, including: etching the capping material layer to form a capping layer, and the capping layer covers the bit line, the spacer line and the first insulating material; using the capping layer as a mask, etching and removing the first insulating material in the inner region to form the node contact hole.
  • the embodiment of the present disclosure optimizes the process flow of the node contact hole, so that the final etching step to form the node contact hole can be completed in the same process and in the same machine, which can save machine procurement costs and improve
  • FIG. 1 is a schematic top view of an exemplary semiconductor device
  • FIG. 2a-2d are detailed cross-sectional views along the B1-B2 direction of FIG. 1 during the fabrication process of an exemplary semiconductor device
  • FIG. 3 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic top view of a semiconductor device provided by an embodiment of the present disclosure.
  • FIG. 5a, Fig. 6a, Fig. 7a, Fig. 8a, Fig. 9a, Fig. 10a are detailed cross-sectional views along the A1-A2 direction of Fig. 4 during the preparation process of the semiconductor device provided by the embodiment of the present disclosure
  • Fig. 5b, Fig. 6b, Fig. 7b, 8 b , FIG. 9 b , and FIG. 10 b are detailed cross-sectional views along the B1 - B2 direction of FIG. 4 during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • FIG. 1 is a schematic top view of an exemplary semiconductor device
  • FIGS. 2a-2d are detailed cross-sectional views along the B1-B2 direction of FIG. 1 during the fabrication process of the exemplary semiconductor device.
  • a substrate 10 is provided, the substrate 10 includes a storage array area and a peripheral area, and the storage array area includes an inner area and a border area; a plurality of bit lines 13; a first insulating material 18 is filled between the plurality of bit lines 13; a capping material layer 16 is also formed above the storage array area and the peripheral area.
  • an etching process is performed on the capping material layer 16 to form a capping layer 16 a covering only above the peripheral region.
  • a resist material layer (not shown in the figure) is formed on the memory array region and the peripheral region, and the resist material layer (not shown in the figure) is trimmed. , forming a resist layer 19 located above the boundary region and the peripheral region of the memory array region, as shown in FIG. 2c.
  • the first insulating material 18 is not removed in the boundary region of the memory array region, forming a dummy contact hole 14a.
  • the preparation method of the above-mentioned exemplary semiconductor device when forming the node contact hole, the etching of the capping material layer needs to be carried out in a plasma etching device, and the formation of the resist layer needs to be carried out in a glue coating device, a photolithography device, and a developing device.
  • removing the first insulating material layer needs to be carried out in a plasma etching device, and removing the resist layer needs to be carried out in a wet cleaning device, that is, the preparation method of the above-mentioned exemplary semiconductor device needs to be carried out in multiple devices And transfer, which increases the complexity of the process and reduces the production efficiency.
  • An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, please refer to FIG. 3 for details. As shown in the figure, the method includes the following steps:
  • Step 310 Provide a substrate, the substrate includes a storage array area, a plurality of bit lines are formed on the storage array area, and a first insulating material is filled between the plurality of bit lines, and the first insulating material There are a plurality of trenches intersecting the bit lines; wherein, the memory array area includes an inner area and a boundary area outside the inner area;
  • Step 320 filling the trench with a second insulating material to form a spacer line, and the second insulating material is also deposited on the bit line, the spacer line and the first insulating material to form a capping material layer;
  • Step 330 Perform an etching process to form a node contact hole, including: etching the capping material layer to form a capping layer, and the capping layer covers the bit line, the spacer line and the first an insulating material; using the capping layer as a mask, etching and removing the first insulating material in the inner region to form the node contact hole.
  • the embodiment of the present disclosure optimizes the process flow of the node contact hole, so that the final etching step to form the node contact hole can be completed in the same process and in the same machine, which can save machine procurement costs and improve chip output efficiency.
  • FIG. 4 is a schematic top view of the semiconductor device provided by the embodiment of the present disclosure
  • FIG. 5a, FIG. 6a, FIG. 7a, FIG. 8a, FIG. 9a, and FIG. 10a are along A1 of FIG. -Detailed cross-sectional view in direction A2
  • Figure 5b, Figure 6b, Figure 7b, Figure 8b, Figure 9b, Figure 10b are detailed cross-sectional views along the B1-B2 direction of Figure 4 during the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.
  • step 310 is performed to provide a substrate 20, the substrate 20 includes a storage array area, and the storage array area also includes an inner area and an inner area outside the inner area. border area.
  • a plurality of bit lines 23 are formed on the memory array area, and a first insulating material 28 is filled between the plurality of bit lines 23 .
  • the first insulating material 28 includes but not limited to materials such as silicon oxide.
  • the substrate 20 may also include a peripheral region adjacent to the memory array region.
  • the substrate may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (for example, silicon (Si) substrate, germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (for example, nitrogen gallium (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other known in the art Semiconductor material.
  • the substrate is a silicon substrate.
  • the substrate 20 is provided with a plurality of active regions 201 , and insulating spacers 21 are filled between the plurality of active regions 201 , wherein the insulating spacers 21 include but not limited to materials such as silicon oxide.
  • the bit line 23 may include a polysilicon layer 231 , an anti-diffusion barrier layer 232 and a metal layer 233 stacked sequentially from bottom to top.
  • the material forming the anti-diffusion barrier layer 232 includes but not limited to titanium nitride; the material forming the metal layer 233 includes but not limited to metal tungsten, metal silicide, and tungsten nitride.
  • a dielectric layer 22 may also be formed above the substrate 20, and the dielectric layer 22 is used for electrically isolating the substrate 20 and being formed on the substrate 20. other structures.
  • the bit line 23 may also include a bit line capping layer 234 on the top of the metal layer 233 and cover the polysilicon layer 231, the anti-diffusion barrier layer 232, the metal layer 233 and the bit line capping layer.
  • the spacer 235 on the surface of the 234 , the bit line capping layer 234 and the sidewall 235 can be used to maintain electrical insulation between the polysilicon layer 231 , the diffusion barrier layer 232 and the metal layer 233 and other structures.
  • the material forming the bit line capping layer 234 and the sidewall 235 may be the same.
  • the bit line capping layer 234 and the sidewall 235 are formed by including but not limited to silicon nitride, silicon carbide and the like.
  • the memory array region may further include word lines 27 buried in the substrate 20 .
  • the structure of the word line 27 includes a gate dielectric layer 271 , a conductive layer 272 and a word line capping layer 273 stacked sequentially from bottom to top.
  • the material forming the conductive layer 272 includes but not limited to polysilicon layer and metal layer, the material forming the metal layer includes but not limited to metal tungsten, metal silicide and tungsten nitride etc.;
  • the material of 273 may be the same as that of the bit line capping layer 234 , which will not be repeated here.
  • the first insulating material 28 has a plurality of grooves 211 in it.
  • the trench 211 crosses the bit line 23 and is located above the word line 27 .
  • step 320 is performed, as shown in FIGS.
  • the cap material layer 26 is formed above the wire 274 and the first insulating material 28 .
  • the capping material layer 26 has a thickness ranging from 12nm to 20nm, for example, from 15nm to 18nm.
  • the capping material layer 26 can also be deposited on the peripheral region.
  • the second insulating material includes but not limited to silicon oxide, silicon nitride, silicon carbide and the like. In a specific embodiment, the second insulating material is silicon nitride.
  • the deposition process of the second insulating material includes but not limited to chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, atomic layer deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • the intersection of the bit line 23 and the spacer line 274 in the memory array area defines the area where the first insulating material 28 is located.
  • step 330 perform an etching process to form a node contact hole 24, including: etching the capping material layer 26 to form a capping layer 26a, and the capping layer 26a is located in the boundary region above the bit line 23, the spacer line 274 and the first insulating material 28, as shown in FIGS. 8a to 9b; using the capping layer 26a as a mask, the An etching process is performed to remove the first insulating material 28 in the inner region to form the node contact hole 24, as shown in FIGS. 10a and 10b.
  • the first insulating material 28 is not removed in the boundary area of the memory array area, forming a dummy contact hole 24a.
  • the node contact hole is only formed in the inner area of the memory array area, because this area is less affected by pattern loading effects (Pattern Loading Effects), so the consistency of the formed node contact hole is better, there is It is beneficial to the subsequent formation of semiconductor devices with good electrical quality.
  • this step can be performed in the same manufacturing process and in the same machine, which can save machine purchase costs and improve chip output efficiency.
  • the same machine may be, for example, a plasma etching device.
  • the etching process of the cap material layer and the first insulating material is completed in a plasma etching device.
  • the materials to be etched are different, it is only necessary to change the type of the etching gas fed into the plasma etching device and optimize the etching parameters.
  • the cap material layer is silicon nitride and the first insulating material is silicon oxide
  • the cap is etched using a mixed gas containing carbon fluoride (CF 4 ) and argon (Ar).
  • CF 4 carbon fluoride
  • Ar argon
  • Material layer using a mixed gas containing hydrogen fluoride (HF) and nitrogen trifluoride (NF 3 ) to remove the first insulating material.
  • the method before performing the etching process, as shown in FIGS. 7 a to 7 b , the method further includes: forming a resist layer 29 on the capping material layer 26 in the boundary region.
  • the resist layer 29 may be a photoresist layer.
  • the resist layer 29 is also formed over the peripheral region.
  • the formation process of the capping layer 26a will be described in detail below with reference to FIGS. 8a to 9b.
  • the cap material layer 26 located in the inner region is thinned by an etching process, so that the inner region and the boundary region
  • the upper cap material layer 26 forms a preset height difference h.
  • the cap material layer 26 is thinned by using a plasma etching process.
  • the capping material layer is thinned using a plasma etching gas including carbon fluoride (CF 4 ) and argon (Ar).
  • CF 4 carbon fluoride
  • Ar argon
  • the flow rate of the carbon fluoride (CF 4 ) is 200 sccm
  • the flow rate of the argon gas is 400 sccm.
  • the resist layer 29 is removed by etching. Specifically, the resist layer 29 is removed by using a plasma etching process. In a specific embodiment, the resist layer 29 is removed using a plasma etching gas containing oxygen (O 2 ) at a temperature of 200°C.
  • O 2 oxygen
  • the capping material layer 26 is etched using a plasma etching process.
  • the capping layer 26 a is formed by etching with a plasma etching gas including carbon fluoride (CF 4 ) and argon (Ar).
  • a plasma etching gas including carbon fluoride (CF 4 ) and argon (Ar).
  • the flow rate of the carbon fluoride (CF 4 ) is 200 sccm
  • the flow rate of the argon gas is 400 sccm.
  • the first insulating material 28 in the inner region is removed by using the capping layer 26a as a mask. Specifically, the first insulating material 28 is removed by using a plasma etching process. In a specific embodiment, the first insulating material 28 is removed by using a plasma etching gas containing hydrogen fluoride (HF) and nitrogen trifluoride (NF 3 ) at a temperature of 80°C.
  • HF hydrogen fluoride
  • NF 3 nitrogen trifluoride
  • the range of the preset height difference is between 6nm-10nm, and the preset height difference can be used to ensure that the first insulating layer located in the boundary region is Material 28 is not exposed.
  • the method further includes: filling the node contact hole 24 with a conductive material to form a node contact plug.
  • the conductive material forming the node contact plug includes but not limited to polysilicon layer and metal layer, and the material used to form the metal layer includes but not limited to metal tungsten, metal silicide (such as TiSi 2 , CoSi 2 , NISi 2 , etc. ) and tungsten nitride, etc.
  • the processes of removing the resist layer by etching, forming the cap layer by etching and forming the node contact hole by etching can be completed on the same machine and in the same process. Therefore, the embodiment of the present disclosure optimizes the process flow of forming the node contact hole, improves the utilization rate of the machine so as to save the cost of machine procurement, and can improve the output efficiency of the chip.
  • An embodiment of the present disclosure also provides a semiconductor device, as shown in FIG. 10a to FIG. 10b , the semiconductor device includes:
  • the substrate 20 includes a memory array area, the memory array area includes an inner area and a boundary area outside the inner area; a plurality of bit lines 23 located in the memory array area; a plurality of spacing lines 274, located in the memory array area and intersecting with the plurality of bit lines 23 to form a plurality of hole structures; wherein, the hole structures located in the inner region are node contact holes 24; the first insulating material 28 is filled in the In the hole structure in the boundary region; a capping layer 26a covering the bit line 23, the spacer line 274 and the first insulating material 28 in the boundary region.
  • the first insulating material 28 is filled in the hole structure in the boundary region to form a dummy contact hole 24a.
  • the first insulating material 28 includes but not limited to materials such as silicon oxide.
  • the first insulating material 28 is silicon oxide.
  • the thickness of the capping layer 26a is between 6nm-10nm.
  • the material forming the capping layer 26a includes but not limited to silicon oxide, silicon nitride, silicon carbide, etc., specifically, the material is silicon nitride.
  • the presence of the capping layer 26a can protect the underlying structure from damage and contamination in subsequent processes.
  • the inner region will subsequently form a node contact plug and a landing pad located above the node contact plug.
  • the presence of the capping layer 26a can reduce the height difference between the inner region and the boundary region, which is beneficial to subsequent The process is carried out stably.
  • the material used to form the spacing lines 274 may be the same as the material used to form the capping layer 26a, such as silicon oxide, silicon nitride, silicon carbide, etc.
  • the material is silicon nitride.
  • the formation of the capping layer 26a and the spacer lines 274 can be formed using one or more thin film deposition processes; the multiple thin film deposition processes include but are not limited to chemical vapor deposition (CVD) process, plasma Volume Enhanced Chemical Vapor Deposition (PECVD) process, Atomic Layer Deposition (ALD) process or a combination thereof.
  • CVD chemical vapor deposition
  • PECVD plasma Volume Enhanced Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the semiconductor device further includes a peripheral area adjacent to the boundary area of the memory array area.
  • the capping layer 26a also covers the peripheral region.
  • the substrate 20 also includes a plurality of active regions 201 and insulating spacers 21 filled between the active regions 201, wherein the insulating spacers 21 include but not limited to materials such as silicon oxide.
  • the bit line 23 may include a polysilicon layer 231, an anti-diffusion barrier layer 232 and a metal layer 233 stacked sequentially from bottom to top, wherein the material forming the anti-diffusion barrier layer 232 includes but is not limited to Titanium nitride, etc.; the material for forming the metal layer 233 includes but not limited to metal tungsten, metal silicide, and tungsten nitride.
  • the bit line 23 may further include a bit line capping layer 234 on the top of the metal layer 233 and cover the polysilicon layer 231, the anti-diffusion barrier layer 232, the metal layer 233 and the bit line capping layer 234.
  • the sidewall 235 on the surface, the bit line cap layer 234 and the sidewall 235 can be used to maintain electrical insulation between the polysilicon layer 231 , the diffusion barrier layer 232 and the metal layer 233 and other structures.
  • the material of the side wall 235 includes but not limited to silicon nitride, silicon carbide and the like.
  • a dielectric layer 22 is further formed between the bit line 23 and the substrate 20 , and the dielectric layer 22 is used to electrically isolate the bit line 23 from the substrate 20 .
  • the semiconductor device may further include a word line 27, the word line 27 is buried in the substrate 20, and the word line 27 is located between the spacer lines 274. below.
  • the word line 27 includes a gate dielectric layer 271, a conductive layer 272, and a word line cap layer 273 stacked sequentially from bottom to top, wherein the material forming the conductive layer 272 includes but is not limited to a polysilicon layer and a metal layer, etc.,
  • the material forming the metal layer includes but not limited to metal tungsten, metal silicide and tungsten nitride.
  • a conductive material may be disposed in the node contact hole 24 to form a node contact plug, and the node contact plug is used to realize the electrical connection between the information storage structure and the active region 201 .
  • the conductive material forming the node contact plug includes but not limited to polysilicon layer and metal layer, and the material used to form the metal layer includes but not limited to metal tungsten, metal silicide (such as, TiSi 2 , CoSi 2 and NISi 2 etc.) and tungsten nitride etc.
  • the method for manufacturing a semiconductor device provided by the embodiments of the present disclosure can be applied to a DRAM structure or other semiconductor devices, and there is no excessive limitation here.
  • the embodiment of the semiconductor device manufacturing method provided by the present disclosure belongs to the same idea as the embodiment of the semiconductor device; the technical features in the technical solutions recorded in each embodiment can be combined arbitrarily if there is no conflict.
  • the embodiment of the present disclosure optimizes the process flow of the node contact hole, so that the final etching step to form the node contact hole can be completed in the same process and in the same machine, which can save machine procurement costs and improve chip output efficiency.

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Abstract

本公开实施例公开了一种半导体器件的制备方法，所述方法包括：提供衬底，衬底包括存储阵列区，存储阵列区上形成有多条位线，多条位线之间填充有第一绝缘材料，第一绝缘材料内具有多条与位线交叉的沟槽；其中，存储阵列区包括内部区域以及位于内部区域外的边界区域；在沟槽内填充第二绝缘材料形成间隔线，第二绝缘材料还沉积在位线、间隔线及第一绝缘材料的上方构成盖帽材料层；执行刻蚀工艺，形成节点接触孔，包括：刻蚀盖帽材料层形成盖帽层，盖帽层覆盖位于边界区域的位线、间隔线及第一绝缘材料；以盖帽层为掩膜，刻蚀移除内部区域的第一绝缘材料，形成节点接触孔。

Description

一种半导体器件的制备方法及半导体器件
相关申请的交叉引用
本公开基于申请号为202111264789.8、申请日为2021年10月28日、发明名称为“一种半导体器件的制备方法及半导体器件”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体制造领域，尤其涉及一种半导体器件的制备方法及半导体器件。
背景技术
由于受刻蚀工艺中图案负载效应的影响，存储阵列区的边界区域的图案密度与内部区域的图案密度存在一定的差异，使得后续形成在边界区域的节点接触孔与形成在内部区域的节点接触孔的一致性较差。因此，现有技术在形成节点接触孔时，将原本要形成在边界区域的节点接触孔做成虚拟接触孔，不作为电路的组成部分，从而可以避免因节点接触孔一致性较差所带来的问题。
然而，采用上述现有技术的方法制造节点接触孔，其工艺流程过于复杂，芯片的产出效率不高。
发明内容
有鉴于此，本公开实施例为解决背景技术中存在的至少一个问题而提供一种半导体器件的制备方法及半导体器件。
为达到上述目的，本公开的技术方案是这样实现的：
本公开实施例提供了一种半导体器件的制备方法，所述方法包括：提供衬底，所述衬底包括存储阵列区，所述存储阵列区上形成有多条位线，多条所述位线之间填充有第一绝缘材料，所述第一绝缘材料内具有多条与所述位线交叉的沟槽；其中，所述存储阵列区包括内部区域以及位于所述内部区域外的边界区域；
在所述沟槽内填充第二绝缘材料形成间隔线，所述第二绝缘材料还沉积在所述位线、所述间隔线及所述第一绝缘材料的上方构成盖帽材料层；
执行刻蚀工艺，形成节点接触孔，包括：刻蚀所述盖帽材料层形成盖帽层，所述盖帽层覆盖位于所述边界区域的所述位线、所述间隔线及所述第一绝缘材料；以所述盖帽层为掩膜，刻蚀移除所述内部区域的所述第一绝缘材料，形成所述节点接触孔。
本公开实施例还提供了一种半导体器件，所述器件包括：衬底，所述衬底包括存储阵列区，所述存储阵列区包括内部区域以及位于所述内部区域外的边界区域；
多条位线，位于所述存储阵列区；
多条间隔线，位于所述存储阵列区且与所述多条位线相互交叉形成多个孔结构；其中，位于所述内部区域的孔结构为节点接触孔；
第一绝缘材料，填充于所述边界区域的所述孔结构内；
盖帽层，覆盖所述边界区域的所述位线、所述间隔线及所述第一绝缘材料。
本公开实施例所提供的半导体器件的制备方法及半导体器件，其中，所述方法包括：提供衬底，所述衬底包括存储阵列区，所述存储阵列区上形成有多条位线，多条所述位线之间填充有第一绝缘材料，所述第一绝缘材料内具有多条与所述位线交叉的沟槽；其中，所述存储阵列区包括内部区域以及位于所述内部区域外的边界区域；在所述沟槽内填充第二绝缘材料形成间隔线，所述第二绝缘材料还沉积在所述位线、所述间隔线及所述 第一绝缘材料的上方构成盖帽材料层；执行刻蚀工艺，形成节点接触孔，包括：刻蚀所述盖帽材料层形成盖帽层，所述盖帽层覆盖位于所述边界区域的所述位线、所述间隔线及所述第一绝缘材料；以所述盖帽层为掩膜，刻蚀移除所述内部区域的所述第一绝缘材料，形成所述节点接触孔。本公开实施例对节点接触孔的工艺流程进行优化，使得最后刻蚀形成节点接触孔的步骤可以在同一制程、同一机台内完成，可以节省机台采购成本，提高芯片的产出效率。
本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为示例性半导体器件的俯视示意图；
图2a-图2d为示例性半导体器件在制备过程中沿图1的B1-B2方向的细节剖视图；
图3为本公开实施例提供的半导体器件的制备方法的流程框图；
图4为本公开实施例提供的半导体器件的俯视示意图；
图5a、图6a、图7a、图8a、图9a、图10a为本公开实施例提供的半导体器件在制备过程中沿图4的A1-A2方向细节剖视图，图5b、图6b、图7b、图8b、图9b、图10b为本公开实施例提供的半导体器件在制备过程中沿图4的B1-B2方向的细节剖视图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
在形成半导体器件，如存储器的工艺过程中，由于受到刻蚀工艺中图案负载效应(Pattern Loading Effects)的影响，存储阵列区的内部区域的图案密度与边界区域的图案密度存在一定的差异，使得最终形成在内部区域和边界区域的节点接触孔的一致性较差，影响器件的电性品质。
为了提高节点接触孔的一致性，请参阅图1-图2d提供的示例性半导体器件的制备方法，该方法在形成节点接触孔时，将原本要形成在边界区域的节点接触孔做成虚拟接触孔，不作为电路的组成部分，从而可以提高节点接触孔的一致性。图1为示例性半导体器件的俯视示意图，图2a-图2d为示例性半导体器件在制备过程中沿图1的B1-B2方向的细节剖视图。
首先，如图1和图2a所示，提供衬底10，所述衬底10包括存储阵列 区和外围区，所述存储阵列区包括内部区域和边界区域；所述存储阵列区内形成有多条位线13；所述多条位线13之间填充有第一绝缘材料18；所述存储阵列区和所述外围区上方还形成有盖帽材料层16。
接着，如图2b所示，对所述盖帽材料层16执行刻蚀工艺形成仅覆盖所述外围区上方的盖帽层16a。
接下来，在所述存储阵列区和所述外围区上方形成抗蚀剂材料层(图中未示出)，并对所述抗蚀剂材料层(图中未示出)进行修整(trim)，形成位于所述存储阵列区的所述边界区域和所述外围区上方的抗蚀剂层19，如图2c所示。
然后，以所述抗蚀剂层19为掩膜，对所述存储阵列区的所述内部区域执行刻蚀工艺，去除所述内部区域中的所述第一绝缘材料层18，以在所述内部区域中形成节点接触孔14，如图2c所示。
最后，如图2d所示，去除所述抗蚀剂层19。
可以看出，所述存储阵列区的所述边界区域内第一绝缘材料18未被移除，构成虚拟接触孔14a。
然而，上述示例性半导体器件的制备方法在形成节点接触孔时，刻蚀盖帽材料层需要在等离子体刻蚀装置中进行，形成抗蚀剂层需要在涂胶装置、光刻装置、显影装置中进行，移除第一绝缘材料层需要在等离子体刻蚀装置中进行，移除抗蚀剂层需要在湿法清洗装置中进行，即上述示例性半导体器件的制备方法需要在多个装置中进行及转移，增加了工艺制程的复杂性，降低了生产效率。
基于此，提出了本公开实施例的以下技术方案。
本公开实施例提供了一种半导体器件的制备方法，具体请参见图3。如图所示，所述方法包括了如下步骤：
步骤310：提供衬底，所述衬底包括存储阵列区，所述存储阵列区上形成有多条位线，多条所述位线之间填充有第一绝缘材料，所述第一绝缘材 料内具有多条与所述位线交叉的沟槽；其中，所述存储阵列区包括内部区域以及位于所述内部区域外的边界区域；
步骤320：在所述沟槽内填充第二绝缘材料形成间隔线，所述第二绝缘材料还沉积在所述位线、所述间隔线及所述第一绝缘材料的上方构成盖帽材料层；
步骤330：执行刻蚀工艺，形成节点接触孔，包括：刻蚀所述盖帽材料层形成盖帽层，所述盖帽层覆盖位于所述边界区域的所述位线、所述间隔线及所述第一绝缘材料；以所述盖帽层为掩膜，刻蚀移除所述内部区域的所述第一绝缘材料，形成所述节点接触孔。
本公开实施例对节点接触孔的工艺流程进行优化，使得最后刻蚀形成节点接触孔的步骤可以在同一制程、同一机台内完成，可以节省机台采购成本，提高芯片的产出效率。
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图对本公开的具体实施方式做详细的说明。在详述本公开实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本公开的保护范围。
图4为本公开实施例提供的半导体器件的俯视示意图；图5a、图6a、图7a、图8a、图9a、图10a为本公开实施例提供的半导体器件在制备过程中沿图4的A1-A2方向细节剖视图，图5b、图6b、图7b、图8b、图9b、图10b为本公开实施例提供的半导体器件在制备过程中沿图4的B1-B2方向的细节剖视图。
首先，如图4、图5a及图5b所示，执行步骤310，提供衬底20，所述衬底20包括存储阵列区，所述存储阵列区还包括内部区域以及位于所述内部区域外的边界区域。在所述存储阵列区上形成有多条位线23，所述多条位线23之间填充有第一绝缘材料28。其中，所述第一绝缘材料28包括但不限于硅氧化物等材料。
所述衬底20还可以包括临近所述存储阵列区的外围区。
这里，所述衬底可以为半导体衬底；具体包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底等)、至少一个III-V化合物半导体材料(例如为氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底等)、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料。在一具体实施例中，所述衬底为硅衬底。
所述衬底20中设置有多个有源区201，多个有源区201之间填充有绝缘间隔物21，其中，所述绝缘间隔物21包括但不限于硅氧化物等材料。
在一实施例中，所述位线23可以包括从下往上依次层叠的多晶硅层231、防扩散阻挡层232及金属层233。其中，形成所述防扩散阻挡层232的材料包括但不限于氮化钛；形成所述金属层233的材料包括但不限于金属钨、金属硅化物及氮化钨等。
应当理解，在形成所述位线23之前，还可以在所述衬底20上方先形成介质层22，所述介质层22用于电隔离所述衬底20及形成于所述衬底20上的其他结构。
在实际工艺中，所述位线23还可以包括位于所述金属层233顶部的位线盖层234及覆盖所述多晶硅层231、防扩散阻挡层232、金属层233及所述位线盖层234表面的侧墙235，所述位线盖层234及所述侧墙235可用于保持多晶硅层231、防扩散阻挡层232及金属层233与其他结构之间的电绝缘。这里，形成所述位线盖层234和所述侧墙235的材料可以相同。具体的，形成所述位线盖层234和所述侧墙235的包括但不限于氮化硅、碳化硅等。
在一些实施例中，所述存储阵列区还可以包括字线27，所述字线27埋设在衬底20中。所述字线27的结构包括从下往上依次层叠的栅极介质层271、导电层272及字线盖层273。其中，形成所述导电层272的材料包括 但不限于多晶硅层及金属层，形成所述金属层的材料包括但不限于金属钨、金属硅化物及氮化钨等；形成所述字线盖层273的材料可以与形成所述位线盖层234的材料相同，在此不做赘述。
继续参见图5a，所述第一绝缘材料28内具有多条沟槽211。在实际工艺中，所述沟槽211与所述位线23交叉且位于所述字线27上方。
接着，执行步骤320，如图6a至图6b所示，在所述沟槽211内填充第二绝缘材料形成间隔线274，所述第二绝缘材料还沉积在所述位线23、所述间隔线274及所述第一绝缘材料28的上方构成盖帽材料层26。可选的，所述盖帽材料层26的厚度范围在12nm-20nm之间，例如15nm-18nm之间。
可以理解，所述盖帽材料层26还可以沉积在所述外围区的上方。
所述第二绝缘材料包括但不限于氧化硅、氮化硅、碳化硅等。在一具体实施例中，所述第二绝缘材料为氮化硅。
所述第二绝缘材料的沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
至此，所述位线23和所述间隔线274在存储阵列区中交叉限定出了第一绝缘材料28所在的区域。
继续执行步骤330，如图8a至图10b所示，执行刻蚀工艺，形成节点接触孔24，包括：刻蚀所述盖帽材料层26形成盖帽层26a，所述盖帽层26a位于所述边界区域的所述位线23、所述间隔线274及所述第一绝缘材料28的上方，如图8a至图9b所示；以所述盖帽层26a为掩膜，对所述第一绝缘材料28执行刻蚀工艺，以移除所述内部区域的所述第一绝缘材料28，形成所述节点接触孔24，如图10a和图10b所示。
其中，所述存储阵列区的所述边界区域内第一绝缘材料28未被移除，构成虚拟接触孔24a。
在该步骤中，所述节点接触孔仅形成在存储阵列区的内部区域，因该 区域受图案负载效应(Pattern Loading Effects)的影响较小，因此形成的节点接触孔的一致性较好，有利于后续形成具有良好电性品质的半导体器件。同时，该步骤可以在同一制程、同一机台内执行，可以节省机台采购成本，提高芯片的产出效率。在本实施例中，所述同一机台例如可以是等离子体刻蚀装置。换句话说，本公开实施例中，在等离子体刻蚀装置中完成所述盖帽材料层及所述第一绝缘材料的刻蚀工艺。可以理解地，当刻蚀的材料不同时，只需要改变通入所述等离子体刻蚀装置内的刻蚀气体的种类、优化刻蚀参数即可。例如，当所述盖帽材料层的材料为氮化硅，所述第一绝缘材料为氧化硅时，采用包含氟化碳(CF 4)和氩气(Ar)的混合气体来刻蚀所述盖帽材料层，采用包含氟化氢(HF)和三氟化氮(NF 3)的混合气体来移除所述第一绝缘材料。
在一实施例中，在所述执行刻蚀工艺之前，如图7a至图7b所示，所述方法还包括：在所述边界区域的所述盖帽材料层26上方形成抗蚀剂层29。具体的，所述抗蚀剂层29可以为光刻胶层。在一些实施例中，所述抗蚀剂层29还形成在所述外围区上方。
下面结合图8a至图9b，详细描述所述盖帽层26a的形成过程。
首先，如图8a至图8b所示，以所述抗蚀剂层29为掩膜，通过刻蚀工艺减薄位于所述内部区域的盖帽材料层26，使所述内部区域和所述边界区域上的盖帽材料层26形成预设高度差h。具体的，采用等离子体刻蚀工艺减薄所述盖帽材料层26。在一具体的实施例中，采用包含氟化碳(CF 4)及氩气(Ar)的等离子刻蚀气体来减薄所述盖帽材料层。可选的，所述氟化碳(CF 4)的流速为200sccm，所述氩气的流速为400sccm。
接着，如图9a至图9b所示，刻蚀移除所述抗蚀剂层29。具体的，采用等离子体刻蚀工艺移除所述抗蚀剂层29。在一个具体的实施例中，在200℃温度下，采用包含氧气(O 2)的等离子体刻蚀气体来移除所述抗蚀剂层29。
然后，继续刻蚀所述盖帽材料层26，移除位于所述内部区域的所述位线23、所述间隔线274及所述第一绝缘材料28上方的盖帽材料层26，形成覆盖所述边界区域的所述位线23、所述间隔线274及所述第一绝缘材料28的盖帽层26a。具体的，采用等离子体刻蚀工艺刻蚀所述盖帽材料层26。在一具体的实施例中，采用包含氟化碳(CF 4)及氩气(Ar)的等离子刻蚀气体来刻蚀形成所述盖帽层26a。可选的，所述氟化碳(CF 4)的流速为200sccm，所述氩气的流速为400sccm。
可以理解地，在形成盖帽层26a后，以所述盖帽层26a为掩膜，移除所述内部区域的所述第一绝缘材料28。具体的，采用等离子体刻蚀工艺移除所述第一绝缘材料28。在一个具体的实施例中，在80℃温度下，采用包含氟化氢(HF)和三氟化氮(NF 3)的等离子刻蚀气体来移除所述第一绝缘材料28。
在一些实施例中，所述预设高度差的范围在6nm-10nm之间，所述预设高度差可用于保证后续刻蚀所述盖帽材料层时，位于所述边界区域内的第一绝缘材料28不被暴露出来。
根据一些实施例，所述方法还包括：在所述节点接触孔24内填充导电材料，形成节点接触插塞。所述形成节点接触插塞的导电材料包括但不限于多晶硅层及金属层，用于形成所述金属层的材料包括但不限于金属钨、金属硅化物(如TiSi 2、CoSi 2、NISi 2等)及氮化钨等。
本公开实施例在刻蚀形成节点接触孔的步骤中，刻蚀移除抗蚀剂层、刻蚀形成盖帽层和刻蚀形成节点接触孔的工艺过程可以在同一机台、同一制程内完成。因此，本公开实施例优化了形成节点接触孔的工艺流程，提高了机台的利用率从而节省机台采购成本，并且可以提高芯片的产出效率。
本公开实施例还提供了一种半导体器件，如图10a至图10b所示，所述半导体器件包括：
衬底20，所述衬底20包括存储阵列区，所述存储阵列区包括内部区域 以及位于所述内部区域外的边界区域；多条位线23，位于所述存储阵列区；多条间隔线274，位于所述存储阵列区且与所述多条位线23相互交叉形成多个孔结构；其中，位于所述内部区域的孔结构为节点接触孔24；第一绝缘材料28，填充于所述边界区域的所述孔结构内；盖帽层26a，覆盖所述边界区域的所述位线23、所述间隔线274及所述第一绝缘材料28。
所述第一绝缘材料28填充在所述边界区域的所述孔结构内构成虚拟接触孔24a。所述第一绝缘材料28包括但不限于硅氧化物等材料，可选的，所述第一绝缘材料28为氧化硅。
根据一些实施例，所述盖帽层26a的厚度在6nm-10nm之间。形成所述盖帽层26a的材料包括但不限于氧化硅、氮化硅、碳化硅等，具体的，所述材料为氮化硅。
所述盖帽层26a的存在可以保护其下方的结构免受后续工艺的损伤和污染。此外，所述内部区域后续会形成节点接触插塞和位于节点接触插塞上方的着落垫，所述盖帽层26a的存在可以降低所述内部区域和所述边界区域的的高度差，有利于后续制程稳定执行。
应当理解，形成所述间隔线274所用的材料可以与形成所述盖帽层26a所用的材料相同，比如，氧化硅、氮化硅、碳化硅等，可选的，所述材料为氮化硅。
在实际工艺中，所述盖帽层26a及所述间隔线274的形成可以使用一种或多种薄膜沉积工艺形成；所述多种薄膜沉积工艺包括但不限于化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺或其组合。
另外，所述半导体器件还包括外围区，所述外围区与所述存储阵列区的所述边界区域相邻接。在实际工艺中，所述盖帽层26a还覆盖在所述外围区上方。
所述衬底20中还包括多个有源区201以及填充在所述有源区201之间 的绝缘间隔物21，其中，所述绝缘间隔物21包括但不限于硅氧化物等材料。
参考图10b所示，所述位线23可以包括从下往上依次层叠的多晶硅层231、防扩散阻挡层232及金属层233，其中，形成所述防扩散阻挡层232的材料包括但不限于氮化钛等；形成所述金属层233的材料包括但不限于金属钨、金属硅化物及氮化钨等。
在一些实施例中，所述位线23还可以包括位于所述金属层233顶部的位线盖层234及覆盖所述多晶硅层231、防扩散阻挡层232、金属层233及位线盖层234表面的侧墙235，所述位线盖层234及所述侧墙235可用于保持多晶硅层231、防扩散阻挡层232及金属层233与其他结构之间的电绝缘。其中，所述侧墙235的材料包括但不限于氮化硅、碳化硅等。
应当理解，所述位线23和所述衬底20之间还形成有介质层22，所述介质层22用于电隔离所述位线23与所述衬底20。
在一些实施例中，如图10a所示，所述半导体器件还可以包括字线27，所述字线27埋设在所述衬底20中，且所述字线27位于所述间隔线274的下方。所述字线27包括从下往上依次层叠的栅极介质层271、导电层272及字线盖层273，其中，形成所述导电层272的材料包括但不限于多晶硅层及金属层等，形成所述金属层的材料包括但不限于金属钨、金属硅化物及氮化钨等。
根据一些实施例，可将导电材料设置于所述节点接触孔24内以构成节点接触插塞，所述节点接触插塞用于实现信息存储结构与有源区201之间的电连接。所述形成节点接触插塞的导电材料包括但不限于多晶硅层及金属层，用于形成所述金属层的材料包括但不限于金属钨、金属硅化物(如，TiSi 2、CoSi 2及NISi 2等)及氮化钨等。
需要说明的是，本公开实施例提供的半导体器件的制备方法可应用于DRAM结构或其他半导体器件中，在此不做过多限定。本公开提供的半导体器件制备方法的实施例与半导体器件的实施例属于同一构思；各实施例 所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例对节点接触孔的工艺流程进行优化，使得最后刻蚀形成节点接触孔的步骤可以在同一制程、同一机台内完成，可以节省机台采购成本，提高芯片的产出效率。

Claims (15)

  1. 一种半导体器件的制备方法，所述方法包括：
    提供衬底，所述衬底包括存储阵列区，所述存储阵列区上形成有多条位线，多条所述位线之间填充有第一绝缘材料，所述第一绝缘材料内具有多条与所述位线交叉的沟槽；其中，所述存储阵列区包括内部区域以及位于所述内部区域外的边界区域；
    在所述沟槽内填充第二绝缘材料形成间隔线，所述第二绝缘材料还沉积在所述位线、所述间隔线及所述第一绝缘材料的上方构成盖帽材料层；
    执行刻蚀工艺，形成节点接触孔，包括：刻蚀所述盖帽材料层形成盖帽层，所述盖帽层覆盖位于所述边界区域的所述位线、所述间隔线及所述第一绝缘材料；以所述盖帽层为掩膜，刻蚀移除所述内部区域的所述第一绝缘材料，形成所述节点接触孔。
  2. 根据权利要求1所述的方法，其中，所述执行刻蚀工艺，包括：采用等离子体刻蚀装置执行所述刻蚀工艺。
  3. 根据权利要求1所述的方法，其中，在所述执行刻蚀工艺之前，所述方法还包括：在所述边界区域的所述盖帽材料层上形成抗蚀剂层。
  4. 根据权利要求3所述的方法，其中，刻蚀所述盖帽材料层形成盖帽层，包括：以所述抗蚀剂层为掩膜，刻蚀减薄所述内部区域的所述盖帽材料层，使所述内部区域和所述边界区域上的盖帽材料层形成预设高度差；刻蚀移除所述抗蚀剂层；继续刻蚀所述盖帽材料层，移除位于所述内部区域的所述位线、所述间隔线及所述第一绝缘材料上方的盖帽材料层，形成覆盖所述边界区域的所述位线、所述间隔线及所述第一绝缘材料的盖帽层。
  5. 根据权利要求4所述的方法，其中，采用包含氟化碳的刻蚀气体 刻蚀所述盖帽材料层；采用包含氧气的刻蚀气体刻蚀移除所述抗蚀剂层；采用包含氟化氢和三氟化氮的刻蚀气体刻蚀移除所述内部区域的所述第一绝缘材料。
  6. 根据权利要求4所述的方法，其中，所述预设高度差的范围在6-10nm之间。
  7. 根据权利要求1所述的方法，其中，所述盖帽材料层的厚度范围在12-20nm之间。
  8. 根据权利要求1所述的方法，其中，所述方法还包括：在所述节点接触孔内填充导电材料，形成节点接触插塞。
  9. 一种半导体器件，包括：
    衬底，所述衬底包括存储阵列区，所述存储阵列区包括内部区域以及位于所述内部区域外的边界区域；
    多条位线，位于所述存储阵列区；
    多条间隔线，位于所述存储阵列区且与所述多条位线相互交叉形成多个孔结构；其中，位于所述内部区域的孔结构为节点接触孔；
    第一绝缘材料，填充于所述边界区域的所述孔结构内；
    盖帽层，覆盖所述边界区域的所述位线、所述间隔线及所述第一绝缘材料。
  10. 根据权利要求9所述的半导体器件，其中，所述第一绝缘材料包括氧化硅；所述盖帽层的材料包括氮化硅。
  11. 根据权利要求9所述的半导体器件，其中，所述盖帽层的厚度在6-10nm之间。
  12. 根据权利要求9所述的半导体器件，其中，所述半导体器件还包括：外围区，所述外围区与所述存储阵列区的所述边界区域邻接；
    所述盖帽层还覆盖所述外围区。
  13. 根据权利要求9所述的半导体器件，其中，所述半导体器件还 包括：埋设于所述衬底内的多条字线，所述字线位于所述间隔线的下方。
  14. 根据权利要求9所述的半导体器件，其中，所述间隔线的材料与所述盖帽层的材料相同。
  15. 根据权利要求9所述的半导体器件，其中，所述半导体器件还包括：导电材料，所述导电材料设置于所述节点接触孔内以构成节点接触插塞。
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CN108520876A (zh) * 2018-06-26 2018-09-11 睿力集成电路有限公司 集成电路存储器及其制备方法、半导体器件
CN111048467A (zh) * 2018-10-11 2020-04-21 长鑫存储技术有限公司 半导体器件位线形成方法、半导体器件
CN113192954A (zh) * 2021-04-26 2021-07-30 福建省晋华集成电路有限公司 半导体器件及其制备方法

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