WO2023004937A1 - 埋入式位线结构及其制作方法、半导体结构 - Google Patents

埋入式位线结构及其制作方法、半导体结构 Download PDF

Info

Publication number
WO2023004937A1
WO2023004937A1 PCT/CN2021/116915 CN2021116915W WO2023004937A1 WO 2023004937 A1 WO2023004937 A1 WO 2023004937A1 CN 2021116915 W CN2021116915 W CN 2021116915W WO 2023004937 A1 WO2023004937 A1 WO 2023004937A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
initial
buried
active region
top surface
Prior art date
Application number
PCT/CN2021/116915
Other languages
English (en)
French (fr)
Inventor
冯伟
卢经文
朱柄宇
崔兆培
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/650,702 priority Critical patent/US20230032351A1/en
Publication of WO2023004937A1 publication Critical patent/WO2023004937A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present disclosure relates to but not limited to a buried bit line structure, a manufacturing method thereof, and a semiconductor structure.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) has the advantages of small size, high integration, low power consumption, etc., and the data reading speed of DRAM is faster than that of read only memory (ROM, Read Only Memory).
  • ROM Read Only Memory
  • the DRAM process shrinks, and the bit line structure shrinks accordingly.
  • the operation window (Process Window) of the bit line structure process decreases, and the bit line is easy to tilt and collapse during the process, which affects the structural yield. .
  • the disclosure provides a buried bit line structure, a manufacturing method thereof, and a semiconductor structure.
  • a first aspect of the present disclosure provides a method for manufacturing a buried bit line structure, the method comprising:
  • the initial structure includes a base and a protective layer disposed on the base, the base includes an active region structure and a dielectric layer;
  • the conductive structure is located at the bottom of the initial bit line trench
  • bit line contact structure covers the conductive structure, and the top surface of the bit line contact structure is lower than the top surface of the active region structure;
  • An insulating structure is formed, the insulating structure covers the bit line contact structure, and the top surface of the insulating structure is flush with the top surface of the protection layer.
  • a second aspect of the present disclosure provides a buried bit line structure, the buried bit line structure comprising:
  • the base includes an active region structure and a dielectric layer; the top surface of the active region structure is flush with the top surface of the dielectric layer;
  • bit line trench disposed in the dielectric layer and the active region structure
  • the conductive structure covers the bottom surface of the bit line trench and is at a preset distance from the bottom surface of the bit line trench;
  • bit line contact structure covers the conductive structure, and the top surface of the bit line contact structure is lower than the top surface of the active region structure;
  • a third aspect of the present disclosure provides a semiconductor structure including the buried bit line structure as described in the second aspect.
  • FIG. 1 is a flow chart of a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 2 is a flow chart of a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 3 is a flow chart of forming a conductive structure in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 4 is a flow chart showing a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 5 is a flow chart of providing an initial structure in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 6 is a flow chart of forming an initial bit line trench in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 7 is a schematic diagram of a substrate provided in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 8 is a schematic diagram of forming a shallow trench structure on a substrate in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • FIG. 9 is a schematic diagram of filling a dielectric layer in a shallow trench structure and forming a base in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • FIG. 10 is a schematic diagram of forming a second patterned mask on the top surface of a substrate in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 11 is a schematic diagram of forming word line trenches in a substrate in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 12 is a schematic diagram of forming a buried word line in a substrate in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 13 is a cross-sectional view of the A-A section of the initial structure provided in the method of fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 14 is a cross-sectional view of the B-B section of the initial structure provided in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 15 is a top view of an initial structure provided in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 16 is a cross-sectional view of the A-A section where a mask layer is formed on the top surface of the initial structure in the method for fabricating the buried bit line structure shown in Fig. 18 according to an exemplary embodiment;
  • Fig. 17 is a cross-sectional view of the B-B section where a mask layer is formed on the top surface of the initial structure in the method for fabricating the buried bit line structure shown in Fig. 18 according to an exemplary embodiment;
  • Fig. 18 is a top view of forming a mask layer on the top surface of an initial structure in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 19 is a cross-sectional view of the A-A section where an initial bit line trench is formed in the initial structure in the method for fabricating a buried bit line structure shown in Fig. 15 according to an exemplary embodiment;
  • Fig. 20 is a cross-sectional view of the B-B section of the initial bit line trench formed in the initial structure in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment
  • Fig. 21 is a cross-sectional view of the A-A cross-section of the isolation structure in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment
  • Fig. 22 is a partial enlarged view of place A in Fig. 21;
  • Fig. 23 is a cross-sectional view of the B-B section of the isolation structure in the method of manufacturing the buried bit line structure shown in Fig. 15 according to an exemplary embodiment
  • Fig. 24 is a cross-sectional view of the A-A section of the barrier structure formed in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment
  • Fig. 25 is a partial enlarged view of place A in Fig. 24;
  • Fig. 26 is a cross-sectional view of the B-B section of the barrier structure formed in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment
  • Fig. 27 is a cross-sectional view of the A-A section of the initial conductive structure formed in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment
  • Fig. 28 is a partial enlarged view of place A in Fig. 27;
  • Fig. 29 is a cross-sectional view of the B-B cross-section of the initial conductive structure in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment
  • Fig. 30 is a cross-sectional view of the A-A section of the conductive structure formed by removing part of the initial conductive structure in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment;
  • Figure 31 is a partial enlarged view at A in Figure 30;
  • Fig. 32 is a cross-sectional view of the B-B section of the conductive structure formed by removing part of the initial conductive structure in the method for fabricating the buried bit line structure shown in Fig. 15 according to an exemplary embodiment;
  • Fig. 33 is a cross-sectional view of the A-A section in which the barrier structure partially covering the sidewall of the initial bit line trench is removed in the method of fabricating the buried bit line structure shown in an exemplary embodiment;
  • Fig. 34 is a partial enlarged view of place A in Fig. 33;
  • Fig. 35 is a cross-sectional view of the B-B section in which the barrier structure partially covering the sidewall of the initial bit line trench is removed in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 36 is a cross-sectional view of the A-A section in which the isolation structure covering the sidewall of the initial bit line trench is removed in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 37 is a partial enlarged view of place A in Fig. 36;
  • Fig. 38 is a cross-sectional view of the B-B section in which the isolation structure covering the sidewall of the initial bit line trench is removed in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 39 is a cross-sectional view of the A-A section of the deposited polysilicon layer in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 40 is a partial enlarged view of place A in Fig. 39;
  • Fig. 41 is a cross-sectional view of a B-B section of a polysilicon layer deposited in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 42 is a cross-sectional view of the A-A section of the bit line contact structure formed in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Figure 43 is a partial enlarged view at A in Figure 42;
  • Fig. 44 is a cross-sectional view of the B-B section for forming a bit line contact structure in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 45 is a cross-sectional view of the A-A section of the deposited insulating structure in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 46 is a cross-sectional view of the B-B section of the deposited insulating structure in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 47 is a cross-sectional view of an A-A cross-section of an insulating structure in a method for fabricating a buried bit line structure according to an exemplary embodiment
  • Fig. 48 is a partial enlarged view of place A in Fig. 47;
  • Fig. 49 is a cross-sectional view of the B-B section of the insulating structure formed in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 50 is a cross-sectional view of the A-A section with the protection layer removed in the method for fabricating the buried bit line structure according to an exemplary embodiment
  • Fig. 51 is a cross-sectional view of the B-B section with the protective layer removed in the method of fabricating the buried bit line structure according to an exemplary embodiment.
  • Initial structure 101. Substrate; 102. First patterned mask; 103. First pattern; 104. Second patterned mask; 105. Second pattern; 110. Base; 111. Active region structure ; 112, dielectric layer; 120, protective layer; 130, initial bit line trench; 140, shallow trench structure; 160, word line trench;
  • Isolation structure 220. Barrier structure; 230. Conductive structure; 231. Initial conductive structure; 240. Bit line contact structure; 241. Polysilicon layer; 250. Insulation structure;
  • bit line contact structure In the existing method for manufacturing a bit line structure, a bit line contact structure, a barrier metal layer, and a conductive metal layer are sequentially deposited to form a stacked structure, and then the stacked structure is sequentially etched to form a linear bit line structure, and then sequentially formed on the side walls of the bit line structure Nitride layer-oxide layer-nitride layer to protect the bit line structure.
  • bit line structure shrinks, and the bit line structure becomes thinner and thinner.
  • the etching process it is prone to tilting, collapse, etc., and the etching may damage the bit line structure. Cause bit line damage and affect product yield.
  • an exemplary embodiment of the present disclosure provides a method for fabricating a buried bit line structure, as shown in FIG. 1 , which shows a buried bit line structure provided according to an exemplary embodiment of the present disclosure.
  • the flow chart of the manufacturing method of the line structure is shown below, and the manufacturing method of the buried bit line structure is introduced below.
  • Figure 13 is a schematic cross-sectional view of the initial structure provided by this embodiment along the A-A section (see Figure 15), and Figure 14 is a schematic cross-sectional view of the initial structure provided by this embodiment along the B-B section (see Figure 15).
  • Fig. 15 is a top view of the initial structure provided by this embodiment.
  • the initial structure 100 includes a substrate 110 and a protective layer 120 disposed on the substrate 110 , and the substrate 110 includes an active region structure 111 and a dielectric layer 112 .
  • the substrate 110 includes several separate active region structures 111 separated by the dielectric layer 112 , and the top surfaces of the active region structures 111 and the top surface of the dielectric layer 112 are flush.
  • the material of the active region structure 111 is a semiconductor material, and the material of the active region structure 111 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); Silicon (SOI), germanium on insulator (GOI); or other materials, such as III-V group compounds such as gallium arsenide.
  • the material of the active region structure in this embodiment is silicon.
  • the material of the dielectric layer 112 may be insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and the like. In this embodiment, the material of the dielectric layer 112 is silicon oxide.
  • the material of the protective layer 120 may be insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and the like. In this embodiment, the material of the protection layer 120 is silicon oxide.
  • S120 Partially remove the protection layer, the active region structure and the dielectric layer to form an initial bit line trench, and the initial bit line trench exposes the active area structure.
  • Fig. 19 is a schematic cross-sectional view of the initial bit line trench formed in the initial structure in this embodiment along the A-A section (refer to Fig. 15), and Fig. 20 is a cross-sectional view along the B-B section of the initial bit line trench formed in the initial structure in this embodiment Schematic diagram (refer to Figure 15).
  • part of the protective layer 120 is etched first to expose the substrate 110 , and then the substrate 110 is etched to remove part of the active region structure 111 and part of the dielectric layer 112 to form the initial bit line trench 130 . That is, part of the formed initial bit line trench 130 is located in the substrate 110 , and the other part is located in the passivation layer 120 .
  • Figure 30 is a schematic cross-sectional view of the conductive structure formed by removing part of the initial conductive structure in this embodiment (refer to Figure 15),
  • Figure 31 is a partial enlarged view of A in Figure 30, and
  • Figure 32 is a part of the initial conductive structure removed in this embodiment
  • a schematic cross-sectional view of the formed conductive structure along the B-B section (refer to FIG. 15 ).
  • the material of the conductive structure 230 includes one or more of conductive metal, conductive metal nitride, and conductive alloy.
  • the material of the conductive structure can be titanium (Titanium), Tantalum (tantalum), tungsten (Tungsten).
  • bit line contact structure covers the conductive structure, and the top surface of the bit line contact structure is lower than the top surface of the active region structure.
  • Figure 42 is a schematic cross-sectional view of the bit line contact structure formed in this embodiment along the A-A section (refer to Figure 15)
  • Figure 43 is a partial enlarged view of A in Figure 42
  • Figure 44 is a B-B cross-sectional view of the bit line contact structure formed in this embodiment
  • the cross-sectional schematic diagram see Figure 15).
  • the material of the bit line contact structure 240 includes polysilicon.
  • S150 forming an insulating structure, the insulating structure covers the bit line contact structure, and the top surface of the insulating structure is flush with the top surface of the protective layer.
  • Figure 47 is a schematic cross-sectional view of the insulating structure formed in the embodiment along the A-A section (refer to Figure 15)
  • Figure 48 is a partial enlarged view at A in Figure 47
  • Figure 49 is a schematic cross-sectional view of the insulating structure formed in the embodiment along the B-B section (refer to Figure 15).
  • the material of the insulating structure 250 may be insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of the insulating structure 250 is silicon nitride, and one or more mixed gases of NH 3 (ammonia), N 2 (nitrogen) or H 2 (hydrogen) are used as the reaction gas.
  • the atomic layer deposition process deposits silicon nitride to form the insulating structure 250 .
  • the bit line structure is formed in the initial bit line trench.
  • the formed bit line structure can be guaranteed to be a linear structure, and the bit line structure does not need to be etched to avoid the etching process. Damage the bit line structure, ensure the integrity of the formed bit line structure, and improve the structural yield.
  • FIG. 2 shows a buried bit line provided according to an exemplary embodiment of the present disclosure.
  • the initial structure includes a base and a protection layer arranged on the base, and the base includes an active region structure and a dielectric layer.
  • S220 Partially remove the protection layer, the active area structure and the dielectric layer to form an initial bit line trench, and the initial bit line trench exposes the active area structure.
  • Figure 21 is a schematic cross-sectional view of the isolation structure formed in this embodiment along the A-A section (refer to Figure 15)
  • Figure 22 is a partial enlarged view of A in Figure 21
  • Figure 23 is a schematic cross-sectional view of the isolation structure formed in this embodiment along the B-B section ( Refer to Figure 15).
  • the isolation structure 210 may be formed by using an atomic layer deposition process (Atomic Layer Deposition, ALD).
  • ALD atomic layer deposition
  • the material of the isolation structure 210 may be any one or a combination of any two or more of silicon nitride, silicon oxynitride, and silicon carbonitride.
  • the material of the isolation structure 210 is silicon nitride, and one or a mixture of two or more of NH 3 (ammonia), N 2 (nitrogen) or H 2 (hydrogen) is used as the reaction gas.
  • the isolation structure 210 is formed by depositing silicon nitride by an atomic layer deposition process.
  • Figure 24 is a schematic cross-sectional view of the barrier structure formed in this embodiment along the A-A section (refer to Figure 15)
  • Figure 25 is a partial enlarged view of A in Figure 24
  • Figure 26 is a schematic cross-sectional view of the barrier structure formed in this embodiment along the B-B section ( Refer to Figure 15).
  • the barrier structure 220 can be formed by atomic layer deposition (Atomic Layer Deposition, ALD), and the material of the barrier structure 220 can be titanium nitride.
  • ALD atomic layer deposition
  • Figure 27 is a schematic cross-sectional view of the initial conductive structure formed in this embodiment along the A-A section (refer to Figure 15),
  • Figure 28 is a partial enlarged view of A in Figure 27, and
  • Figure 29 is a section along the B-B line of the initial conductive structure formed in this embodiment
  • the cross-sectional schematic diagram see Figure 15).
  • an initial conductive structure 231 may be formed by using an atomic layer deposition process (Atomic Layer Deposition, ALD), and the initial conductive structure 231 covers the barrier structure 220 .
  • ALD atomic layer deposition
  • S260 forming a conductive structure, the conductive structure is located at the bottom of the initial bit line trench.
  • bit line contact structure Form a bit line contact structure, the bit line contact structure covers the conductive structure, and the top surface of the bit line contact structure is lower than the top surface of the active region structure.
  • S280 Form an insulating structure, the insulating structure covers the bit line contact structure, and the top surface of the insulating structure is flush with the top surface of the protection layer.
  • the conductive structure is embedded in the substrate.
  • an isolation structure is formed to isolate the conductive structure from the substrate, so as to avoid direct contact between the formed conductive structure and the substrate.
  • this embodiment is an illustration of the implementation of step S260 in the foregoing embodiment.
  • FIG. 3 shows a flowchart of step S260 in the method for fabricating a buried bit line structure according to this embodiment, as shown in FIG. 3 .
  • Form conductive structures including:
  • Figure 30 is a schematic cross-sectional view of the conductive structure formed by removing part of the initial conductive structure in this embodiment (refer to Figure 15),
  • Figure 31 is a partial enlarged view of A in Figure 30, and
  • Figure 32 is a part of the initial conductive structure removed in this embodiment
  • a schematic cross-sectional view of the conductive structure along the line B-B is formed (refer to FIG. 15 ).
  • the initial conductive structure 231 covering the top surface of the protective layer 120 and the initial Part of the initial conductive structure 231 in the bit line trench 130 forms a conductive structure 230
  • the top surface of the conductive structure 230 is lower than the top surface of the active region structure 111 .
  • Fig. 33 is a schematic cross-sectional view along the A-A section of this embodiment where the barrier structure partially covering the sidewall of the initial bit line trench is removed (refer to Fig. 15),
  • Fig. 34 is a partial enlarged view of A in Fig. 33, and
  • Fig. 35 is an embodiment of this embodiment A schematic cross-sectional view along section B-B of removing the barrier structure partially covering the sidewall of the initial bit line trench (refer to FIG. 15 ).
  • the barrier structure 220 covering the top surface of the protective layer 120 and part of the barrier structure located in the initial bit line trench 130 are etched and removed by dry or wet etching. 220 , the top surface of the remaining barrier structure 220 is flush with the top surface of the conductive structure 230 , so that the barrier structure 220 covers the sidewall of the conductive structure 230 .
  • SF 6 sulfur hexafluoride
  • CF 4 carbon tetrafluoride
  • CHF 3 trifluoromethane
  • O 2 oxygen
  • Ar bromine
  • More than one mixed gas is used as an etching gas to etch and remove part of the conductive structure 231 .
  • step S261 and step S262 can be performed simultaneously to simplify the process and improve production efficiency.
  • FIG. 4 shows the flow of the manufacturing method of the buried bit line structure provided according to an exemplary embodiment of the present disclosure Figure, as shown in Figure 4, the method includes:
  • the initial structure includes a base and a protective layer arranged on the base, and the base includes an active region structure and a dielectric layer.
  • S320 Partially remove the protective layer, the active region structure and the dielectric layer to form an initial bit line trench, and the initial bit line trench exposes the active area structure.
  • S330 forming an isolation structure, the isolation structure covers the sidewall and the bottom wall of the initial bit line trench, and the top surface of the protective layer.
  • S360 forming a conductive structure, the conductive structure is located at the bottom of the initial bit line trench.
  • S370 remove the isolation structure covering the sidewall of the initial bit line trench and the top surface of the protective layer, and retain a part of the isolation structure at the bottom of the initial bit line trench, so as to be between the conductive structure and the side wall of the initial bit line trench A gap is formed.
  • Fig. 36 is a schematic cross-sectional view along section AA of this embodiment showing the removal of the isolation structure covering the sidewall of the initial bit line trench (refer to Fig. 15),
  • Fig. 37 is a partial enlarged view of A in Fig. 36, and
  • Fig. 38 is a schematic diagram of this embodiment removing A schematic cross-sectional view of the isolation structure covering the sidewall of the initial bit line trench along section BB (refer to FIG. 15 ).
  • the isolation structure 210 covering the top surface of the protection layer 120 and all or part of the isolation structure covering the sidewall of the initial bit line trench 130 are etched and removed by a dry etching process.
  • isolation structure 210 retaining the isolation structure 210 covering the bottom of the initial bit line trench 130 , and the remaining isolation structure 210 isolates the conductive structure 230 from the substrate 110 to avoid direct contact between the conductive structure 230 and the substrate 110 .
  • one or a mixture of two or more of SIH 4 (silane), NH 3 (phosphine), N 2 (nitrogen) or H 2 (hydrogen) is used as the etching gas, through dry
  • the isolation structure 210 covering the top surface of the passivation layer 120 and all or part of the isolation structure 210 covering the sidewall of the initial bit line trench 130 are etched and removed by a method etching process.
  • the isolation structure 210 covering the sidewall of the initial bit line trench 130 when the isolation structure 210 covering the sidewall of the initial bit line trench 130 is removed, a part of the isolation structure 210 at the bottom of the initial bit line trench 130 that is at the same height as the conductive structure 230 can be retained, exposing the initial bit line above the conductive structure 230
  • the sidewalls of the trenches 130, so that the formed bit line contact structure 240 can directly contact the substrate 110; the isolation structure 210 covering the sidewalls of the initial bit line trenches 130 can also be completely removed, and only the initial bit line trenches are left
  • the isolation structure 210 on the bottom wall of 130 after the isolation structure 210 originally located between the conductive structure 230 and the sidewall of the initial bit line trench 130 is removed, the two sides of the conductive structure 230 and the side wall of the initial bit line trench 130 gaps between.
  • bit line contact structure Form a bit line contact structure, the bit line contact structure covers the conductive structure, and the top surface of the bit line contact structure is lower than the top surface of the active region structure;
  • S390 Form an insulating structure, the insulating structure covers the bit line contact structure, and the top surface of the insulating structure is flush with the top surface of the protection layer.
  • the buried bit line structure formed in this embodiment forms a gap between the two sides of the conductive structure and the sidewall of the initial bit line trench, the dielectric constant of air is smaller, and the conduction is separated by air.
  • the structure and substrate can reduce parasitic capacitance between bit line structures.
  • this embodiment is an illustration of the implementation of step S380 in the above embodiment.
  • Forming the bit line contact structure includes: depositing the bit line contact structure through a low pressure chemical vapor deposition process, and the bit line contact structure closes the opening of the gap to form an air gap.
  • Figure 39 is a schematic cross-sectional view of the deposited polysilicon layer along the A-A section in this embodiment (refer to Figure 15)
  • Figure 40 is a partial enlarged view at A in Figure 39
  • Figure 41 is a schematic cross-sectional view of the deposited polysilicon layer along the B-B section in this embodiment (Refer to Figure 15).
  • Figure 42 is a schematic cross-sectional view along the A-A section of the bit line contact structure formed in this embodiment (refer to Figure 15)
  • Figure 43 is a partial enlarged view at A in Figure 42
  • Figure 44 is a section along the bit line contact structure formed in this embodiment A schematic cross-sectional view of the B-B section (refer to FIG. 15 ).
  • a bit line contact structure 240 is formed, and a polysilicon layer 241 is first deposited by a low pressure chemical vapor deposition process (Low Pressure Chemical Vapor Deposition, LPCVD).
  • the polysilicon layer 241 closes the opening of the gap, fills the initial bit line trench 130 above the conductive structure 230 and covers the top surface of the protective layer 120, and removes part of the polysilicon layer 241 through a dry or wet etching process, and the remaining polysilicon layer 241
  • the top surface is lower than the top surface of the active region structure 111 .
  • the mixed gas of SIH 4 (silane) and PH 3 (phosphine) is used as the reaction gas, and the polysilicon is deposited by low-pressure chemical vapor deposition process, and the PH3 (phosphorus hydrogen peroxide) as doping gas for doping polysilicon, PH 3 thermally decomposed P element doping polysilicon to form P-doped polysilicon, depositing P-doped polysilicon in the initial bit line trench 130 to form a bit line contact structure 240, In order to make the bit line contact structure 240 have good electrical conductivity.
  • SIH 4 silane
  • PH 3 phosphine
  • this embodiment is an illustration of the implementation of step S310 in the above embodiment.
  • FIG. 5 shows a flow chart of step S310 in the method for fabricating a buried bit line structure according to this embodiment.
  • an initial structure including:
  • the material of the substrate 101 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator ( GOI); or other materials, such as III-V group compounds such as gallium arsenide.
  • the material of the substrate 101 in this embodiment is silicon.
  • the substrate 101 can be doped with certain impurity ions as required, and the impurity ions can be N-type impurity ions or P-type impurity ions.
  • S312 Etching the substrate to form a plurality of active region structures arranged in an array.
  • a first patterned mask 102 is formed on a substrate 101, the first patterned mask 102 defines a first pattern 103, according to the first pattern 103 by dry or wet etching The etch process removes part of the substrate 101 to form a shallow trench structure 140 on the substrate 101 , so as to form a plurality of active region structures 111 isolated by the shallow trench structure 140 on the substrate 101 .
  • S313 forming a dielectric layer, the dielectric layer is used to isolate each active region structure.
  • the dielectric layer 112 can be deposited by an atomic layer deposition process (Atomic Layer Deposition, ALD), and the dielectric layer 112 fills the shallow trench structure 140 to pass through the dielectric layer 112 in the shallow trench structure 140
  • ALD atomic layer deposition
  • the active region structure 111 is isolated to form the substrate 110 .
  • the material of the dielectric layer 112 may be silicon oxide, silicon nitride, silicon oxynitride, and in this embodiment, the material of the dielectric layer 112 is silicon oxide.
  • S314 Form a buried word line, the buried word line is arranged in the dielectric layer and the active region structure, wherein the buried word line includes an insulating part, the insulating part extends along the thickness direction of the dielectric layer, and the top surface of the insulating part flush with the top surface of the dielectric layer.
  • a second patterned mask 104 is formed on the top surface of the substrate 110, the second patterned mask 104 defines a second pattern 105, and the second pattern 105 exposes part of the active region structure 111 and part of the top surface of the dielectric layer 112 , part of the substrate 110 is removed according to the second pattern 105 to form a word line trench 160 , and the word line trench 160 exposes part of the active region structure 111 and part of the dielectric layer 112 .
  • forming a buried word line 300 in the word line trench 160 includes depositing a word line metal 310 in the word line trench 160 , and depositing an insulating part in the word line trench 160 320 , the insulating part 320 covers the word line metal 310 , the top surface of the insulating part 320 is flush with the dielectric layer 112 , so as to expose the top surface of the active region structure 111 , so as to form the buried word line 300 .
  • S315 forming a protection layer, the protection layer covers the dielectric layer, the active region structure and the buried word line.
  • the protective layer 120 can be deposited by atomic layer deposition (Atomic Layer Deposition, ALD), and the protective layer 120 and the substrate 110 form the initial structure 100.
  • ALD atomic layer deposition
  • the material of the protection layer 120 may be silicon oxide, silicon nitride, silicon oxynitride, and in this embodiment, the material of the protection layer 120 is silicon oxide.
  • the initial structure provided in this embodiment includes a substrate and a protective layer on the substrate, so that part of the initial bit line trench formed on the initial structure is located in the substrate and the other part is located in the protective layer, and the initial structure can be formed without etching.
  • a complete bit line structure is formed in the bit line trench.
  • this embodiment is an illustration of the implementation of step S320 in the foregoing embodiment.
  • FIG. 6 shows a flow chart of step S320 in the method for fabricating a buried bit line structure according to this embodiment.
  • Forming an initial bit line trench including:
  • S321 Form a mask layer, the mask layer covers part of the protective layer, and the mask layer has openings exposing a part of the protective layer.
  • FIG. 16 is a schematic cross-sectional view of forming a mask layer along the A-A section on the top surface of the initial structure in this embodiment (refer to Fig. 18), and Fig. 17 is a schematic cross-sectional view of forming a mask layer along the B-B section on the top surface of the initial structure in this embodiment (refer to Figure 18).
  • FIG. 18 is a top view of forming a mask layer on the top surface of the initial structure in this embodiment.
  • a mask layer 400 is formed on the top surface of the protective layer 120, the mask layer 400 defines an opening 410, and the opening 410 exposes part of the protective layer 120 .
  • the initial structure is partially removed to expose a part of the active region structure, a part of the protective layer, and a part of the dielectric layer, to form an initial bit line trench.
  • the protective layer 120 corresponding to the opening 410 is removed, and then the part of the substrate 110 corresponding to the opening 410 is removed to form the initial bit line trench 130 .
  • the initial bit line trench formed in this embodiment extends from the top surface of the protective layer to the substrate, and the initial bit line trench exposes part of the active region structure and part of the dielectric layer of the substrate, so that the formed buried bit line and The active area structure is connected.
  • the bottom surface of the initial bit line trench 130 is higher than the bottom surface of the insulating portion 320 of the buried word line 300, so as to avoid contact between the formed bit line structure and the word line metal 310 of the buried word line 300, and prevent the formed bit line The structure and the buried word line 300 interfere with each other.
  • the bottom surface of the initial bit line trench 130 is lower than four fifths of the height of the insulating portion 320 of the buried word line 300 . That is, in this embodiment, the formed buried bit line structure and the word line metal 310 of the buried word line 300 are separated by at least one-fifth of the distance of the insulating portion 320 to reduce the buried bit line structure. interference with the buried word line 300 .
  • step 390 after forming the insulating structure in step 390 , it further includes: removing the protection layer to expose the insulating structure and the active region structure.
  • Fig. 50 is a schematic cross-sectional view along section A-A of this embodiment for removing the protective layer (see Fig. 15)
  • Fig. 51 is a schematic cross-sectional view of section B-B for removing the protective layer of this embodiment (see Fig. 15). As shown in FIG. 50 and FIG. 51, referring to FIG. 47 and FIG.
  • the protective layer 120 is removed by a dry or wet etching process, exposing the top surface of the active region structure 111 and the dielectric layer 112, and the conductive structure 230, bit
  • the line contact structure 240 and the insulating structure 250 form a buried bit line structure, the conductive structure 230 and the bit line contact structure 240 are buried in the substrate 110, part of the insulating structure 250 is buried in the substrate 110, and another part of the insulating structure 250 extends out.
  • the substrate 110 forms a linear structure, and the bit line structure of the semiconductor structure formed in this embodiment is complete, and the structure yield is high.
  • this exemplary embodiment provides a buried bit line structure, as shown in FIG. 50 and FIG. , the conductive structure 230 covering the bottom surface of the bit line trench 130 , the bit line contact structure 240 covering the conductive structure 230 , and the insulating structure 250 covering the bit line contact structure 240 .
  • the substrate 110 includes an active region structure 111 and a dielectric layer 112, the top surface of the active region structure 111 is flush with the top surface of the dielectric layer 112, and the bit line trench 130 exposes part of the dielectric layer 112 and part of the active region structure 111 .
  • the conductive structure 230 is disposed at the bottom of the bit line trench 130 at a preset distance from the bottom surface of the bit line trench 130, the bit line contact structure 240 covers the conductive structure and the top surface of the bit line contact structure 240 is lower than the top of the active region structure 111 On the other hand, the insulating structure 250 covers the bit line contact structure 240 .
  • the conductive structure 230 , the bit line contact structure 240 and the insulating structure 250 form a bit line structure buried in the substrate 110 .
  • the conductive structure 230 and the bit line contact structure 240 are embedded in the substrate 110 upside down, so that the bit line structure is complete and the structure yield is high.
  • bit line structure 250 is higher than the top surface of active region structure 111 .
  • Part of the insulating structure 250 is embedded in the base 110 , and another part extends out of the base 110 to form a linear structure.
  • the embedded bit line structure further includes: an isolation structure 210 covering part of the bottom of the bit line trench 130 and a blocking structure 220 covering the side and bottom of the conductive structure 230 .
  • the isolation structure 210 covers the bottom wall of the bit line trench 130
  • the barrier structure 220 covers the side wall and the bottom wall of the conductive structure 230
  • the conductive structure 230 is disposed on the isolation structure 210
  • the conductive structure 230 and the bottom wall and The isolation structures 210 are separated by barrier structures 220 .
  • bit line structure of this embodiment is the same as the above embodiment, the difference between this embodiment and the above embodiment is that, as shown in Figure 50 and Figure 51, the barrier An air gap is formed between the structure 220 and the sidewall of the bit line trench 130 .
  • both sides of the conductive structure 230 are separated from the substrate 110 by an air gap, and the dielectric constant of air is small, which can reduce the parasitic capacitance between adjacent bit line structures.
  • the substrate also includes embedded word The line 300 and the buried word line 300 are disposed in the dielectric layer 112 and the active region structure 111 .
  • the buried word line 300 extends along a second direction, and the bit line structure extends along a first direction perpendicular to the second direction.
  • the first direction is the Y direction in Fig. 15 and Fig. 18, and the second direction is the X direction in Fig. 15 and Fig. 18 .
  • Each buried word line 300 intersects with the active region structure 111, and each buried bit line structure intersects with the active region structure 111, making full use of the space of the substrate 110, and setting more buried bit line structures and Buried word line 300 .
  • this exemplary embodiment provides a semiconductor structure, and the semiconductor structure includes the buried bit line structure in the above embodiments.
  • the semiconductor structure according to an embodiment of the present disclosure may be included in a memory cell and a memory cell array, and a read operation or a write operation is performed through the buried bit line structure in the above-described embodiments of the present disclosure.
  • the memory cell and the memory cell array may be included in a memory device, and the memory device may be used in a Dynamic Random Access Memory (DRAM).
  • DRAM Dynamic Random Access Memory
  • SRAM static random-access memory
  • flash memory flash EPROM
  • ferroelectric random-access memory FeRAM
  • magnetic random-access memory Magnetic Random-Access Memory, MRAM
  • phase change random-access memory Phase change Random-Access Memory, PRAM
  • the embedded bit line structure and its manufacturing method and semiconductor structure provided by the embodiments of the present disclosure form the bit line structure in the initial bit line trench without etching process, and even if the size of the bit line structure is small, it will not appear. Bit line structure tilt, collapse, etc. lead to the problem of bit line collapse.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开提供了一种埋入式位线结构的制作方法及埋入式位线结构，埋入式位线结构的制作方法包括，提供初始结构，初始结构有源区结构；形成初始位线沟槽，初始位线沟槽暴露有源区结构；形成导电结构，导电结构位于初始位线沟槽的底部；形成位线接触结构，位线接触结构覆盖导电结构，且位线接触结构的顶面低于有源区结构的顶面；形成绝缘结构，绝缘结构覆盖位线接触结构。

Description

埋入式位线结构及其制作方法、半导体结构
本公开基于申请号为202110862614.0，申请日为2021年07月29日，申请名称为“埋入式位线结构及其制作方法、半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种埋入式位线结构及其制作方法、半导体结构。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)具有体积小、集成度高、功耗低等优点，且DRAM的数据读取速度比只读存储器(ROM，Read Only Memory)快。
随着DRAM集成度越来越高，DRAM制程微缩，位线结构也随之微缩，位线结构制程的操作窗口(Process Window)减小，位线在制程中容易倾斜、倒塌，影响结构良率。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种埋入式位线结构及其制作方法、半导体结构。
本公开的第一方面提供了一种埋入式位线结构的制作方法，所述制作方法包括：
提供初始结构，所述初始结构包括基底以及设置在所述基底上的保护层，所述基底包括有源区结构和介质层；
部分去除所述保护层、有源区结构以及介质层以形成初始位线沟槽，所述初始位线沟槽暴露所述有源区结构；
形成导电结构，所述导电结构位于所述初始位线沟槽的底部；
形成位线接触结构，所述位线接触结构覆盖所述导电结构，且所述位线接触结构的顶面低于所述有源区结构的顶面；
形成绝缘结构，所述绝缘结构覆盖所述位线接触结构，所述绝缘结构的顶面与所述保护层的顶面平齐。
本公开的第二方面提供了一种埋入式位线结构，所述埋入式位线结构包括：
基底，所述基底包括有源区结构和介质层；所述有源区结构的顶面和所述介质层的顶面平齐；
位线沟槽，设置在所述介质层和所述有源区结构中；
导电结构，所述导电结构覆盖所述位线沟槽的底面，且距离所述位线沟槽的底面预设距离；
位线接触结构，所述位线接触结构覆盖所述导电结构，所述位线接触结构的顶面低于所述有源区结构的顶面；
绝缘结构，所述绝缘结构覆盖所述位线接触结构。
本公开的第三方面提供了一种半导体结构，所述半导体结构包括如第二方面所述的埋入式位线结构。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种埋入式位线结构的制作方法的流程图；
图2是根据一示例性实施例示出的一种埋入式位线结构的制作方法的流程图；
图3是根据一示例性实施例示出的埋入式位线结构的制作方法中形成 导电结构的流程图；
图4是根据一示例性实施例示出的一种埋入式位线结构的制作方法的流程图；
图5是根据一示例性实施例示出的埋入式位线结构的制作方法中提供初始结构的流程图；
图6是根据一示例性实施例示出的埋入式位线结构的制作方法中形成初始位线沟槽的流程图；
图7是根据一示例性实施例示出的埋入式位线结构的制作方法的提供的衬底的示意图；
图8是根据一示例性实施例示出的埋入式位线结构的制作方法中在衬底上形成浅沟槽结构的示意图；
图9是根据一示例性实施例示出的埋入式位线结构的制作方法中在浅沟槽结构中填充介质层、形成基底的示意图；
图10是根据一示例性实施例示出的埋入式位线结构的制作方法中在基底顶面形成第二图案化掩膜的示意图；
图11是根据一示例性实施例示出的埋入式位线结构的制作方法中在基底中形成字线沟槽的示意图；
图12是根据一示例性实施例示出的埋入式位线结构的制作方法中在基底中形成埋入式字线的示意图；
图13是根据一示例性实施例示出的埋入式位线结构的制作方法中提供的初始结构的A-A截面的剖视图；
图14是根据一示例性实施例示出的埋入式位线结构的制作方法中提供的初始结构的B-B截面的剖视图；
图15是根据一示例性实施例示出的埋入式位线结构的制作方法中提供的初始结构的俯视图；
图16是图18所示的根据一示例性实施例示出的埋入式位线结构的制作方法中在初始结构顶面形成掩膜层的A-A截面的剖视图；
图17是图18所示的根据一示例性实施例示出的埋入式位线结构的制作方法中在初始结构顶面形成掩膜层的B-B截面的剖视图；
图18是根据一示例性实施例示出的埋入式位线结构的制作方法中在 初始结构顶面形成掩膜层的俯视图；
图19是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中在初始结构中形成初始位线沟槽的A-A截面的剖视图；
图20是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中在初始结构中形成初始位线沟槽的B-B截面的剖视图；
图21是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中形成隔离结构的A-A截面的剖视图；
图22是图21中A处的局部放大图；
图23是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中形成隔离结构的B-B截面的剖视图；
图24是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中形成阻挡结构的A-A截面的剖视图；
图25是图24中A处的局部放大图；
图26是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中形成阻挡结构B-B截面的剖视图；
图27是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中形成初始导电结构A-A截面的剖视图；
图28是图27中A处的局部放大图；
图29是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中形成初始导电结构的B-B截面的剖视图；
图30是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中去除部分初始导电结构形成导电结构的A-A截面的剖视图；
图31是图30中A处的局部放大图；
图32是图15所示的根据一示例性实施例示出的埋入式位线结构的制作方法中去除部分初始导电结构形成导电结构的B-B截面的剖视图；
图33是一示例性实施例示出的埋入式位线结构的制作方法中去除部分覆盖初始位线沟槽侧壁的阻挡结构的A-A截面的剖视图；
图34是图33中A处的局部放大图；
图35是根据一示例性实施例示出的埋入式位线结构的制作方法中去除部分覆盖初始位线沟槽侧壁的阻挡结构的B-B截面的剖视图；
图36是根据一示例性实施例示出的埋入式位线结构的制作方法中去除覆盖初始位线沟槽侧壁的隔离结构的A-A截面的剖视图；
图37是图36中A处的局部放大图；
图38是根据一示例性实施例示出的埋入式位线结构的制作方法中去除覆盖初始位线沟槽侧壁的隔离结构的B-B截面的剖视图；
图39是根据一示例性实施例示出的埋入式位线结构的制作方法中沉积多晶硅层的A-A截面的剖视图；
图40是图39中A处的局部放大图；
图41是根据一示例性实施例示出的埋入式位线结构的制作方法中沉积多晶硅层的B-B截面的剖视图；
图42是根据一示例性实施例示出的埋入式位线结构的制作方法中形成位线接触结构的A-A截面的剖视图；
图43是图42中A处的局部放大图；
图44是根据一示例性实施例示出的埋入式位线结构的制作方法中形成位线接触结构的B-B截面的剖视图；
图45是根据一示例性实施例示出的埋入式位线结构的制作方法中沉积绝缘结构的A-A截面的剖视图；
图46是根据一示例性实施例示出的埋入式位线结构的制作方法中沉积绝缘结构的B-B截面的剖视图；
图47是根据一示例性实施例示出的埋入式位线结构的制作方法中形成绝缘结构的A-A截面的剖视图；
图48是图47中A处的局部放大图；
图49是根据一示例性实施例示出的埋入式位线结构的制作方法中形成绝缘结构的B-B截面的剖视图；
图50是根据一示例性实施例示出的埋入式位线结构的制作方法中去除保护层的A-A截面的剖视图；
图51是根据一示例性实施例示出的埋入式位线结构的制作方法中去除保护层的B-B截面的剖视图。
附图标记：
100、初始结构；101、衬底；102、第一图案化掩膜；103、第一图案；104、第二图案化掩膜；105、第二图案；110、基底；111、有源区结构；112、介质层；120、保护层；130、初始位线沟槽；140、浅沟槽结构；160、字线沟槽；
210、隔离结构；220、阻挡结构；230、导电结构；231、初始导电结构；240、位线接触结构；241、多晶硅层；250、绝缘结构；
300、埋入式字线；310、字线金属；320、绝缘部；
400、掩膜层；410、开口。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
现有制作位线结构的方法中，依次沉积位线接触结构、阻挡金属层、导电金属层形成层叠结构，然后依次刻蚀层叠结构形成线性位线结构，然后在位线结构的侧壁依次形成氮化物层-氧化物层-氮化物层以保护位线结构。
但是，随着DRAM集成度越来越高，位线结构的尺寸微缩，位线结构越来越薄，在刻蚀过程中，容易出现倾斜、倒塌等情况，而且刻蚀可能损坏位线结构，造成位线损坏、影响产品良率。
为此，本公开示例性的实施例中提供一种埋入式位线结构的制作方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的埋入式位线结构的制作方法的流程图，下面对埋入式位线结构的制作方法进行介绍。
本实施例的埋入式位线结构的制作方法，包括：
S110：提供初始结构。
图13是本实施例提供的初始结构沿A-A截面的剖面示意图(参照图15)，图14是本实施例提供的初始结构的沿B-B截面的剖面示意图(参照图15)。图15是本实施例提供的初始结构的俯视图。如图13、图14、图15所示，初 始结构100包括基底110以及设置在基底110上的保护层120，基底110包括有源区结构111和介质层112。
基底110包括若干个分离的有源区结构111，有源区结构111被介质层112隔开，有源区结构111的顶面和介质层112的顶面平齐。
其中，有源区结构111的材料为半导体材料，有源区结构111的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中有源区结构的材料为硅。
介质层112的材料可以为氧化硅、氮化硅、氮氧化硅等绝缘材料。本实施例中，介质层112的材料为氧化硅。
保护层120的材料可以为氧化硅、氮化硅、氮氧化硅等绝缘材料。本实施例中，保护层120的材料为氧化硅。
S120：部分去除保护层、有源区结构以及介质层以形成初始位线沟槽，初始位线沟槽暴露有源区结构。
图19是本实施例在初始结构中形成初始位线沟槽沿A-A截面的剖面示意图(参照图15)，图20是本实施例在初始结构中形成初始位线沟槽的沿B-B截面的剖面示意图(参照图15)。如图19、图20所示，先刻蚀去除部分保护层120，暴露出基底110后，继续刻蚀基底110以去除部分有源区结构111以及部分介质层112，形成初始位线沟槽130。也即，形成的初始位线沟槽130一部分位于基底110中，另一部分位于保护层120中。
S130：形成导电结构，导电结构位于初始位线沟槽的底部。
图30是本实施中去除部分初始导电结构形成导电结构沿A-A截面的剖面示意图(参照图15)，图31是图30中A处的局部放大图，图32是本实施例去除部分初始导电结构形成导电结构沿B-B截面的剖面示意图(参照图15)。如图30、图31、图32所示，导电结构230的材料包括导电金属、导电金属氮化物、导电合金中的一种或二种以上，例如，导电结构的材料可以为钛(Titanium)、钽(tantalum)、钨(Tungsten)。
S140：形成位线接触结构，位线接触结构覆盖导电结构，且位线接触结构的顶面低于有源区结构的顶面。
图42是本实施例形成位线接触结构沿A-A截面的剖面示意图(参照图 15)，图43是图42中A处的局部放大图，图44是本实施例形成位线接触结构沿B-B截面的剖面示意图(参照图15)。如图42、图43、图44所示，位线接触结构240的材料包括多晶硅。
S150：形成绝缘结构，绝缘结构覆盖位线接触结构，绝缘结构的顶面与保护层的顶面平齐。
图47是实施例形成绝缘结构沿A-A截面的剖面示意图(参照图15)，图48是图47中A处的局部放大图，图49是本实施例形成绝缘结构沿B-B截面的剖面示意图(参照图15)。
如图47、图48、图49所示，示例性的，绝缘结构250的材料可以为氧化硅、氮化硅、氮氧化硅等绝缘材料。本实施例中，绝缘结构250的材料为氮化硅，以NH 3(氨气)、N 2(氮气)或H 2(氢气)中的一种或两种以上的混合气体作为反应气体，采用原子层沉积工艺沉积为氮化硅，形成绝缘结构250。
本实施例，在初始位线沟槽中形成位线结构，通过定义初始位线沟槽的形状，即可保证形成的位线结构为线性结构，无需刻蚀处理位线结构，避免刻蚀过程损害位线结构，保证形成的位线结构的完整性，提高结构良率。
根据一个示例性实施例，本示例性实施例的埋入式位线结构的制作方法，如图2所示，图2示出了根据本公开一示例性的实施例提供的埋入式位线结构的制作方法的流程图，方法包括：
S210：提供初始结构。
初始结构包括基底以及设置在基底上的保护层，基底包括有源区结构和介质层。
S220：部分去除保护层、有源区结构以及介质层以形成初始位线沟槽，初始位线沟槽暴露有源区结构。
S230：形成隔离结构，隔离结构覆盖初始位线沟槽的侧壁和底壁，以及保护层的顶面。
图21是本实施例形成隔离结构沿A-A截面的剖面示意图(参照图15)，图22是图21中A处的局部放大图，图23是本实施例形成隔离结构沿B-B截面的剖面示意图(参照图15)。如图21、图22、图23所示，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)形成隔离结构210。
示例性的，隔离结构210的材料可以为氮化硅、氮氧化硅、碳氮化硅中的任意一种或任意两种以上的组合。在本实施例中，隔离结构210的材料为氮化硅，以NH 3(氨气)、N 2(氮气)或H 2(氢气)中的一种或两种以上的混合气体作为反应气体，采用原子层沉积工艺沉积为氮化硅，形成隔离结构210。
S240：形成阻挡结构，阻挡结构覆盖隔离结构。
图24是本实施例形成阻挡结构沿A-A截面的剖面示意图(参照图15)，图25是图24中A处的局部放大图，图26是本实施例形成阻挡结构沿B-B截面的剖面示意图(参照图15)。如图24、图25、图26所示，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)形成阻挡结构220，阻挡结构220的材料可以为氮化钛。
S250：形成初始导电结构，初始导电结构填充初始位线沟槽，且覆盖阻挡结构。
图27是本实施例形成初始导电结构沿A-A截面的剖面示意图(参照图15)，图28是图27中A处的局部放大图，图29是本实施例形成初始导电结构沿B-B线剖开的剖面示意图(参照图15)。如图27、图28、图29所示，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)形成初始导电结构231，初始导电结构231覆盖阻挡结构220。
S260：形成导电结构，导电结构位于初始位线沟槽的底部。
S270：形成位线接触结构，位线接触结构覆盖导电结构，且位线接触结构的顶面低于有源区结构的顶面。
S280：形成绝缘结构，绝缘结构覆盖位线接触结构，绝缘结构的顶面与保护层的顶面平齐。
本实施例形成的埋入式位线结构，导电结构埋入在基底中，在形成导电结构之前，先形成隔离结构以隔离导电结构和基底，避免形成的导电结构和基底直接接触。
根据一个示例性实施例，本实施例是对上述实施例步骤S260的实施方式的说明。图3示出了根据本实施例提供的埋入式位线结构的制作方法中，如图3所示，步骤S260中的流程图。
形成导电结构，包括：
S261:回刻初始导电结构以形成导电结构。
图30是本实施例去除部分初始导电结构形成导电结构沿A-A截面的剖面示意图(参照图15)，图31是图30中A处的局部放大图，图32是本实施例去除部分初始导电结构形成导电结构沿B-B线剖开的剖面示意图(参照图15)。
如图30、图31、图32所示，参照图27、图28、图29，通过干法或湿法刻蚀工艺刻蚀去除覆盖在保护层120的顶面的初始导电结构231以及位于初始位线沟槽130中的部分初始导电结构231，形成导电结构230，导电结构230的顶面低于有源区结构111的顶面。在本实施例中，以SF 6(六氟化硫)、CF 4(四氟化碳)、CHF 3(三氟甲烷)、O 2(氧气)、Ar(溴气)中的一种或两种以上的混合气体作为刻蚀气体，刻蚀去除部分导电结构231。
S262：去除部分阻挡结构，以使得被保留的阻挡结构与导电结构的顶面平齐。
图33是本实施例去除部分覆盖初始位线沟槽侧壁的阻挡结构沿A-A截面的剖面示意图(参照图15)，图34是图33中A处的局部放大图，图35是本实施例去除部分覆盖初始位线沟槽侧壁的阻挡结构沿B-B截面的剖面示意图(参照图15)。
如图33、图34、图35所示，通过干法或湿法刻蚀工艺刻蚀去除覆盖在保护层120的顶面的阻挡结构220以及去除位于初始位线沟槽130中的部分阻挡结构220，保留的阻挡结构220的顶面和导电结构230的顶面平齐，以使阻挡结构220覆盖导电结构230的侧壁。在本实施例中，以SF 6(六氟化硫)、CF 4(四氟化碳)、CHF 3(三氟甲烷)、O 2(氧气)、Ar(溴气)中的一种或两种以上的混合气体作为刻蚀气体，刻蚀去除部分导电结构231。
其中，步骤S261和步骤S262可以同时进行，以简化工艺过程，提高生产效率。
根据一个示例性实施例，本示例性实施例的埋入式位线结构的制作方法，图4示出了根据本公开一示例性的实施例提供的埋入式位线结构的制作方法的流程图，如图4所示，方法包括：
S310：提供初始结构。
初始结构包括基底以及设置在基底上的保护层，基底包括有源区结构和 介质层。
S320：部分去除保护层、有源区结构以及介质层以形成初始位线沟槽，初始位线沟槽暴露有源区结构。
S330：形成隔离结构，隔离结构覆盖初始位线沟槽的侧壁和底壁，以及保护层的顶面。
S340：形成阻挡结构，阻挡结构覆盖隔离结构。
S350：形成初始导电结构，初始导电结构填充初始位线沟槽，且覆盖阻挡结构。
S360：形成导电结构，导电结构位于初始位线沟槽的底部。
S370：去除覆盖初始位线沟槽的侧壁及保护层的顶面的隔离结构，保留位于初始位线沟槽底部的部分隔离结构，以在导电结构与初始位线沟槽的侧壁之间形成间隙。
图36是本实施例示去除覆盖初始位线沟槽侧壁的隔离结构沿A-A截面的剖面示意图(参照图15)，图37是图36中A处的局部放大图，图38是本实施例去除覆盖初始位线沟槽侧壁的隔离结构沿B-B截面的剖面示意图(参照图15)。如图36、图37、图38所示，通过干法刻蚀工艺刻蚀去除覆盖在保护层120的顶面的隔离结构210以及去除覆盖初始位线沟槽130侧壁的全部或部分隔离结构210，保留覆盖在初始位线沟槽130底部的隔离结构210，保留的隔离结构210隔离导电结构230与基底110避免导电结构230与基底110直接接触。在本实施例中，以SIH 4(硅烷)、NH 3(磷化氢)、N 2(氮气)或H 2(氢气)中的一种或两种以上的混合气体作为刻蚀气体，通过干法刻蚀工艺刻蚀去除覆盖在保护层120的顶面的隔离结构210以及去除覆盖初始位线沟槽130侧壁的全部或部分隔离结构210。
其中，去除覆盖初始位线沟槽130侧壁的隔离结构210时，可以保留初始位线沟槽130底部与导电结构230等高的部分隔离结构210，暴露出位于导电结构230上方的初始位线沟槽130的侧壁，以使形成的位线接触结构240能够与基底110直接接触；还可以将覆盖初始位线沟槽130侧壁的隔离结构210全部去除，仅保留覆盖初始位线沟槽130底壁的隔离结构210，原本位于导电结构230和初始位线沟槽130的侧壁之间的隔离结构210被去除后，导电结构230的两侧与初始位线沟槽130的侧壁之间形成间隙。
S380：形成位线接触结构，位线接触结构覆盖导电结构，且位线接触结构的顶面低于有源区结构的顶面；
S390：形成绝缘结构，绝缘结构覆盖位线接触结构，绝缘结构的顶面与保护层的顶面平齐。
如图37所示，本实施例形成的埋入式位线结构，在导电结构的两侧与初始位线沟槽的侧壁之间形成间隙，空气的介电常数更小，通过空气隔离导电结构和基底能够减小位线结构间的寄生电容。
根据一个示例性实施例，本实施例是对上述实施例步骤S380的实施方式的说明。
形成位线接触结构，包括：通过低压化学气相沉积工艺沉积位线接触结构，位线接触结构封闭间隙的开口以形成空气隙。
图39是本实施例中沉积多晶硅层沿A-A截面的剖面示意图(参照图15)，图40是图39中A处的局部放大图，图41是本实施例沉积多晶硅层沿B-B截面的剖面示意图(参照图15)。图42是本实施例形成位线接触结构的沿A-A截面的剖面示意图(参照图15)，图43是图42中A处的局部放大图，图44是本实施例形成位线接触结构的沿B-B截面的剖面示意图(参照图15)。
如图42、图43、图44所示，参照图39、图40、图41，形成位线接触结构240，先通过低压化学气相沉积工艺(Low Pressure Chemical Vapor Deposition，LPCVD)沉积多晶硅层241，多晶硅层241封闭间隙的开口，填充导电结构230上方的初始位线沟槽130以及覆盖保护层120的顶面，通过干法或湿法刻蚀工艺去除部分多晶硅层241，保留的多晶硅层241的顶面低于有源区结构111的顶面。
在本实施例中，在480℃～520℃温度环境中，以SIH 4(硅烷)和PH 3(磷化氢)的混合气作为反应气体，采用低压化学气相沉积工艺沉积多晶硅，以PH3(磷化氢)作为掺杂多晶硅的掺杂气体，PH 3热分解的P元素掺杂多晶硅形成掺杂P的多晶硅，在初始位线沟槽130中沉积掺杂P的多晶硅形成位线接触结构240，以使位线接触结构240具有良好的导电性。
根据一个示例性实施例，本实施例是对上述实施例步骤S310的实施方式的说明。如图5所示，图5示出了根据本实施例提供的埋入式位线结构的制作方法中步骤S310的流程图。
提供初始结构，包括：
S311：提供衬底。
如图7所示，衬底101的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中衬底101的材料为硅。衬底101中可以根据需要掺杂一定的杂质离子，杂质离子可以为N形杂质离子或P形杂质离子。
S312：刻蚀衬底以形成阵列排布的多个有源区结构。
如图8所示，参照图7，在衬底101上形成第一图案化掩膜102，第一图案化掩膜102定义有第一图案103，根据第一图案103通过干法或湿法刻蚀工艺去除部分衬底101以在衬底101上形成浅沟槽结构140，以在衬底101上形成被浅沟槽结构140隔离的多个有源区结构111。
S313：形成介质层，介质层用于隔离各有源区结构。
如图9所示，参照图8，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积介质层112，介质层112填充浅沟槽结构140，以通过浅沟槽结构140中的介质层112隔离有源区结构111，形成基底110。示例性的，介质层112的材料可以为氧化硅、氮化硅、氮氧化硅，在本实施例中，介质层112的材料为氧化硅。
S314：形成埋入式字线，埋入式字线设置在介质层和有源区结构中，其中，埋入式字线包括绝缘部，绝缘部沿介质层厚度方向延伸，绝缘部的顶面和介质层的顶面平齐。
如图10、图11所示，首先，在基底110顶面形成第二图案化掩膜104，第二图案化掩膜104定义有第二图案105，第二图形105暴露部分有源区结构111和部分介质层112的顶面，根据第二图形105去除部分基底110，形成字线沟槽160，字线沟槽160暴露部分有源区结构111以及部分介质层112。
如图12所示，参照图11，在字线沟槽160中形成埋入式字线300，包括在字线沟槽160中沉积字线金属310，以及在字线沟槽160中沉积绝缘部320，绝缘部320覆盖字线金属310，绝缘部320的顶面和介质层112平齐，以暴露有源区结构111的顶面，以便形成埋入式字线300。
S315：形成保护层，保护层覆盖介质层、有源区结构和埋入式字线。
如图13、图14、图15所示，参照图12，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积保护层120，保护层120和基底110形成初始结构100。示例性的，保护层120的材料可以为氧化硅、氮化硅、氮氧化硅，在本实施例中，保护层120的材料为氧化硅。
本实施例提供的初始结构包括基底和位于基底上的保护层，以使在初始结构上形成的初始位线沟槽部分位于基底中和另一部分位于保护层中，无需刻蚀处理即可在初始位线沟槽中形成完整的位线结构。
根据一个示例性实施例，本实施例是对上述实施例步骤S320的实施方式的说明。如图6所示，图6示出了根据本实施例提供的埋入式位线结构的制作方法中步骤S320的流程图。
形成初始位线沟槽，包括：
S321：形成掩膜层，掩膜层覆盖部分保护层，掩膜层具有暴露保护层的部分区域的开口。
图16是本实施例在初始结构顶面形成掩膜层沿A-A截面的剖面示意图(参照图18)，图17是本实施例在初始结构顶面形成掩膜层沿B-B截面的剖面示意图(参照图18)。图18是本实施例在初始结构顶面形成掩膜层的俯视图。如图16、图17、图18所示，参照图13、图14、图15，在保护层120顶面形成掩膜层400，掩膜层400定义有开口410，开口410暴露部分保护层120。
S322：根据掩膜层定义的图案，部分去除初始结构，暴露出有源区结构的部分区域以及保护层的部分区域，以及介质层的部分区域，形成初始位线沟槽。
如图19、图20所示，根据掩膜层400的开口410去除与开口410对应的保护层120，再继续去除与开口410对应部分基底110，形成初始位线沟槽130。
本实施例形成的初始位线沟槽从保护层的顶面延伸至基底中，初始位线沟槽暴露出基底的部分有源区结构和部分介质层，以使形成的埋入式位线和有源区结构连接。
其中，初始位线沟槽130的底面高于埋入式字线300的绝缘部320的底面，以免形成的位线结构和埋入式字线300的字线金属310接触，以免形成 的位线结构和埋入式字线300互相干扰。
在本实施例中，沿初始位线沟槽130的深度方向，初始位线沟槽130的底面低于埋入式字线300的绝缘部320的高度的五分之四。也即，在本实施例中，形成的埋入式位线结构和埋入式字线300的字线金属310至少间隔五分之一个绝缘部320的距离，以减少埋入式位线结构和埋入式字线300的干扰。
根据一个示例性实施例，在步骤390形成绝缘结构之后，还包括：去除保护层，以暴露绝缘结构及有源区结构。
图50是本实施例去除保护层沿A-A截面的剖面示意图(参照图15)，图51是本实施例去除保护层的沿B-B截面的剖面示意图(参照图15)。如图50、图51所示，参照图47、图49，通过干法或湿法刻蚀工艺去除保护层120，暴露出有源区结构111和介质层112的顶面，导电结构230、位线接触结构240和绝缘结构250形成埋入式位线结构，导电结构230和位线接触结构240埋入在基底110中，部分绝缘结构250埋入在基底110中，另一部分绝缘结构250延伸出基底110形成线型结构，本实施例形成的半导体结构的位线结构完整，结构良率高。
根据一个示例性实施例，本示例性实施例提供了一种埋入式位线结构，如图50、如图51所示，其包括：基底110、设置在基底110中的位线沟槽130、覆盖位线沟槽130的底面的导电结构230、覆盖导电结构230的位线接触结构240以及覆盖位线接触结构240的绝缘结构250。其中，基底110包括有源区结构111和介质层112，有源区结构111的顶面和介质层112的顶面平齐，位线沟槽130暴露部分介质层112和部分有源区结构111。导电结构230设置在位线沟槽130底部且距离位线沟槽130的底面预设距离，位线接触结构240覆盖导电结构且位线接触结构240的顶面低于有源区结构111的顶面，绝缘结构250覆盖位线接触结构240。导电结构230、位线接触结构240和绝缘结构250形成埋入设置在基底110中的位线结构。
本实施例的埋入式位线结构，导电结构230和位线接触结构240倒置埋入在基底110中，位线结构完整、结构良率高。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图50、如图51所 示，绝缘结构250的顶面高于有源区结构111的顶面。
绝缘结构250部分埋入在基底110中，另一部分延伸出基底110形成线形结构。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图50、如图51所示，埋入式位线结构还包括：覆盖部分位线沟槽130的底面的隔离结构210以及覆盖导电结构230的侧面和底面的阻挡结构220。
在本实施例中，隔离结构210覆盖位线沟槽130的底壁，阻挡结构220覆盖导电结构230的侧壁和底壁，导电结构230设置在隔离结构210上，导电结构230和底壁和隔离结构210之间通过阻挡结构220隔开。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图50、如图51所示，阻挡结构220和位线沟槽130的侧壁之间形成空气隙。
在本实施例中，导电结构230两侧通过空气隙和基底110隔开，空气的介电常数小，能够减少相邻的位线结构之间的寄生电容。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，参照图20，基底还包括埋入式字线300，埋入式字线300设置在介质层112和有源区结构111中。
埋入式字线300沿第二方向延伸，位线结构沿垂直于第二方向的第一方向延伸。参照图15、图18，第一方向为图15、图18中的Y方向，第二方向为图15、图18中的X方向。
每条埋入式字线300和有源区结构111相交，每条埋入式位线结构和有源区结构111相交，充分的利用基底110空间，设置更多的埋入式位线结构和埋入式字线300。
根据一个示例性实施例，本示例性实施例提供了一种半导体结构，半导体结构包括上述实施例中的埋入式位线结构。
根据本公开实施例的半导体结构可以被包括在存储器单元和存储器单元阵列中，通过本公开上述实施例中的埋入式位线结构执行读取操作或写入操作。
存储器单元和存储器单元阵列可以被包括在存储器件中，存储器件可以 用在动态随机存储器DRAM(Dynamic Random Access Memory，DRAM)中。然而，也可以应用于静态随机存储器(Static Random-Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电随机存储器(Ferroelectric Random-Access Memory，FeRAM)、磁性随机存储器(Magnetic Random Access Memory，MRAM)、相变随机存储器(Phase change Random-Access Memory，PRAM)等。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的埋入式位线结构及其制作方法、半导体结构，在初始位线沟槽中形成位线结构，无需刻蚀处理，即使位线结构的尺寸微小，也不会出现位线结构倾斜、倒塌等导致位线崩溃的问题。

Claims (17)

  1. 一种埋入式位线结构的制作方法，所述方法包括：
    提供初始结构，所述初始结构包括基底以及设置在所述基底上的保护层，所述基底包括有源区结构和介质层；
    部分去除所述保护层、有源区结构以及介质层以形成初始位线沟槽，所述初始位线沟槽暴露所述有源区结构；
    形成导电结构，所述导电结构位于所述初始位线沟槽的底部；
    形成位线接触结构，所述位线接触结构覆盖所述导电结构，且所述位线接触结构的顶面低于所述有源区结构的顶面；
    形成绝缘结构，所述绝缘结构覆盖所述位线接触结构，所述绝缘结构的顶面与所述保护层的顶面平齐。
  2. 如权利要求1所述的埋入式位线结构的制作方法，其中，所述埋入式位线结构的制作方法还包括：
    形成隔离结构，所述隔离结构覆盖所述初始位线沟槽的侧壁和底壁，以及所述保护层的顶面；
    形成阻挡结构，所述阻挡结构覆盖所述隔离结构；
    形成初始导电结构，所述初始导电结构填充所述初始位线沟槽，且覆盖所述阻挡结构。
  3. 如权利要求2所述的埋入式位线结构的制作方法，其中，所述形成导电结构，包括：
    回刻所述初始导电结构以形成所述导电结构；
    去除部分所述阻挡结构，以使得被保留的所述阻挡结构与所述导电结构的顶面平齐。
  4. 如权利要求3所述的埋入式位线结构的制作方法，其中，所述埋入式位线结构的制作方法还包括：
    去除覆盖所述初始位线沟槽的侧壁及所述保护层的顶面的所述隔离结构，保留位于所述初始位线沟槽底部的部分所述隔离结构，以在所述导电结构与所述初始位线沟槽的侧壁之间形成间隙。
  5. 如权利要求4所述的埋入式位线结构的制作方法，其中，所述形成位线接触结构，包括：
    通过低压化学气相沉积工艺沉积所述位线接触结构，所述位线接触结构封闭所述间隙的开口以形成空气隙。
  6. 如权利要求1所述的埋入式位线结构的制作方法，其中，所述提供初始结构，包括：
    提供衬底；
    刻蚀所述衬底以形成阵列排布的多个有源区结构；
    形成介质层，所述介质层用于隔离各所述有源区结构；
    形成埋入式字线，所述埋入式字线设置在所述介质层和所述有源区结构中，其中，所述埋入式字线包括绝缘部，所述绝缘部沿所述介质层厚度方向延伸，所述绝缘部的顶面和所述介质层的顶面平齐；
    形成保护层，所述保护层覆盖所述基底的所述介质层、所述有源区结构和所述埋入式字线。
  7. 如权利要求6所述的埋入式位线结构的制作方法，其中，所述形成初始位线沟槽，包括：
    形成掩膜层，所述掩膜层覆盖部分所述保护层，所述掩膜层具有暴露所述保护层的部分区域的开口；
    根据所述掩膜层定义的图案，去除部分所述初始结构，暴露出所述有源区结构的部分区域以及所述保护层的部分区域，以及所述介质层的部分区域，形成所述初始位线沟槽。
  8. 如权利要求7所述的埋入式位线结构的制作方法，其中，所述初始位线沟槽的底面高于所述埋入式字线的所述绝缘部的底面。
  9. 根据权利要求8所述的埋入式位线结构的制作方法，其中，沿所述初 始位线沟槽的深度方向，所述初始位线沟槽的底面低于所述埋入式字线的所述绝缘部的高度的五分之四。
  10. 如权利要求7所述的埋入式位线结构的制作方法，其中，所述埋入式位线结构的制作方法还包括：
    去除所述保护层，以暴露所述绝缘结构及所述有源区结构。
  11. 一种埋入式位线结构，包括：
    基底，所述基底包括有源区结构和介质层；所述有源区结构的顶面和所述介质层的顶面平齐；
    位线沟槽，设置在所述介质层和所述有源区结构中；
    导电结构，所述导电结构覆盖所述位线沟槽的底面，且距离所述位线沟槽的底面预设距离；
    位线接触结构，所述位线接触结构覆盖所述导电结构，所述位线接触结构的顶面低于所述有源区结构的顶面；
    绝缘结构，所述绝缘结构覆盖所述位线接触结构。
  12. 根据权利要求11所述的埋入式位线结构，其中，所述绝缘结构的顶面高于所述有源区结构的顶面。
  13. 根据权利要求12所述的埋入式位线结构，其中，所述埋入式位线结构还包括：
    隔离结构，所述隔离结构覆盖部分所述位线沟槽的底面；
    阻挡结构，所述阻挡结构覆盖所述导电结构的侧面和底面。
  14. 根据权利要求13所述的埋入式位线结构，其中，所述阻挡结构和所述位线沟槽的侧壁之间形成空气隙。
  15. 根据权利要求11所述的埋入式位线结构，其中，所述基底还包括埋入式字线，所述埋入式字线设置在所述介质层和所述有源区结构中。
  16. 根据权利要求15所述的埋入式位线结构，其中，所述埋入式字线沿第二方向延伸，所述埋入式位线结构沿垂直于所述第二方向的第一方向延伸。
  17. 一种半导体结构，所述半导体结构包括如权利要求11至16中任一项所述的埋入式位线结构。
PCT/CN2021/116915 2021-07-29 2021-09-07 埋入式位线结构及其制作方法、半导体结构 WO2023004937A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/650,702 US20230032351A1 (en) 2021-07-29 2022-02-11 Buried bit line structure, manufacturing method thereof, and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110862614.0A CN113594097B (zh) 2021-07-29 2021-07-29 埋入式位线结构及其制作方法、半导体结构
CN202110862614.0 2021-07-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/650,702 Continuation US20230032351A1 (en) 2021-07-29 2022-02-11 Buried bit line structure, manufacturing method thereof, and semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023004937A1 true WO2023004937A1 (zh) 2023-02-02

Family

ID=78251618

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/116915 WO2023004937A1 (zh) 2021-07-29 2021-09-07 埋入式位线结构及其制作方法、半导体结构

Country Status (2)

Country Link
CN (1) CN113594097B (zh)
WO (1) WO2023004937A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114639721B (zh) * 2022-04-29 2022-08-05 长鑫存储技术有限公司 半导体结构及半导体结构的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110101435A1 (en) * 2009-11-05 2011-05-05 Taiwan Memory Corporation Buried bit line process and scheme
CN209216973U (zh) * 2018-11-27 2019-08-06 长鑫存储技术有限公司 半导体器件
CN112992775A (zh) * 2019-12-02 2021-06-18 长鑫存储技术有限公司 半导体存储器及其形成方法
CN113035872A (zh) * 2021-03-05 2021-06-25 长鑫存储技术有限公司 半导体结构及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5635415A (en) * 1994-11-30 1997-06-03 United Microelectronics Corporation Method of manufacturing buried bit line flash EEPROM memory cell
KR100843715B1 (ko) * 2007-05-16 2008-07-04 삼성전자주식회사 반도체소자의 콘택 구조체 및 그 형성방법
US7948027B1 (en) * 2009-12-10 2011-05-24 Nanya Technology Corp. Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same
US8691680B2 (en) * 2011-07-14 2014-04-08 Nanya Technology Corp. Method for fabricating memory device with buried digit lines and buried word lines
KR20130020333A (ko) * 2011-08-19 2013-02-27 삼성전자주식회사 수직형 채널 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
KR20130075348A (ko) * 2011-12-27 2013-07-05 에스케이하이닉스 주식회사 매립비트라인을 구비한 반도체장치 및 그 제조 방법
KR20140083745A (ko) * 2012-12-26 2014-07-04 에스케이하이닉스 주식회사 매립비트라인을 구비한 반도체장치 및 그 제조 방법
CN108878424B (zh) * 2018-06-25 2024-03-29 长鑫存储技术有限公司 一种采用埋入式位线的晶体管结构及其制造方法
CN110943032B (zh) * 2018-09-21 2022-03-29 长鑫存储技术有限公司 半导体器件形成方法
CN208767278U (zh) * 2018-10-11 2019-04-19 长鑫存储技术有限公司 半导体器件
CN111048467A (zh) * 2018-10-11 2020-04-21 长鑫存储技术有限公司 半导体器件位线形成方法、半导体器件
CN111128895A (zh) * 2018-10-30 2020-05-08 长鑫存储技术有限公司 半导体器件及其制作方法
KR20210037211A (ko) * 2019-09-27 2021-04-06 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110101435A1 (en) * 2009-11-05 2011-05-05 Taiwan Memory Corporation Buried bit line process and scheme
CN209216973U (zh) * 2018-11-27 2019-08-06 长鑫存储技术有限公司 半导体器件
CN112992775A (zh) * 2019-12-02 2021-06-18 长鑫存储技术有限公司 半导体存储器及其形成方法
CN113035872A (zh) * 2021-03-05 2021-06-25 长鑫存储技术有限公司 半导体结构及其制作方法

Also Published As

Publication number Publication date
CN113594097B (zh) 2023-09-26
CN113594097A (zh) 2021-11-02

Similar Documents

Publication Publication Date Title
US8685821B2 (en) Vertical channel memory devices with nonuniform gate electrodes and methods of fabricating the same
TWI458068B (zh) 垂直通道電晶體陣列及其製造方法
US7670901B2 (en) Method of fabricating a bottle trench and a bottle trench capacitor
TWI469323B (zh) 垂直通道電晶體陣列及其製造方法
US8120103B2 (en) Semiconductor device with vertical gate and method for fabricating the same
US20130292792A1 (en) Semiconductor device with buried bit lines and method for fabricating the same
CN113035872B (zh) 半导体结构及其制作方法
US11257841B2 (en) Three-dimensional semiconductor memory device
US8643098B2 (en) Method for fabricating semiconductor device with side contact
TW202143391A (zh) 具有氣隙結構的半導體元件結構及其製備方法
WO2023015641A1 (zh) 半导体结构的制作方法及半导体结构
WO2023004937A1 (zh) 埋入式位线结构及其制作方法、半导体结构
TWI830993B (zh) 半導體元件
US11404433B2 (en) Vertical memory devices
US20230187482A1 (en) Method of manufacturing semiconductor structure and semiconductor structure
KR20230119405A (ko) 반도체 소자
US20230032351A1 (en) Buried bit line structure, manufacturing method thereof, and semiconductor structure
JP2013098532A (ja) 半導体素子及びその形成方法
CN100446257C (zh) 动态随机存取存储器及其制造方法
TWI818247B (zh) 積體電路裝置
US11908797B2 (en) Integrated circuit device having a bit line and a main insulating spacer with an extended portion
TWI819787B (zh) 半導體裝置
US20240023319A1 (en) Semiconductor device
WO2023097901A1 (zh) 半导体结构及其制作方法
WO2022088850A1 (zh) 半导体结构及半导体结构的制作方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE