WO2023015641A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2023015641A1
WO2023015641A1 PCT/CN2021/116921 CN2021116921W WO2023015641A1 WO 2023015641 A1 WO2023015641 A1 WO 2023015641A1 CN 2021116921 W CN2021116921 W CN 2021116921W WO 2023015641 A1 WO2023015641 A1 WO 2023015641A1
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Prior art keywords
trench
isolation structure
word line
isolation
sacrificial
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PCT/CN2021/116921
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English (en)
French (fr)
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卢经文
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长鑫存储技术有限公司
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Priority to US17/652,338 priority Critical patent/US20230047893A1/en
Publication of WO2023015641A1 publication Critical patent/WO2023015641A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Definitions

  • the present disclosure relates to but not limited to a method for fabricating a semiconductor structure and the semiconductor structure.
  • Dynamic random access memory (Dynamic random access memory, referred to as DRAM) has the advantages of small size, high integration, and low power consumption, and its read and write speeds are faster than read-only memory (ROM, Read Only Memory).
  • the DRAM is composed of multiple repeated memory cells, and each memory cell usually includes a capacitor structure and a transistor, the gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor structure.
  • the disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure.
  • a first aspect of the present disclosure provides a method of fabricating a semiconductor structure, the fabricating method comprising:
  • a substrate is provided, the substrate includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed on the substrate, and the word line trench exposes part of the active region and the active region. Shallow trench isolation structure;
  • a first intermediate structure is formed in the word line trench, the first intermediate structure covers sidewalls and bottom walls of the word line trench, the first intermediate structure is formed with a first trench, and the first intermediate structure is formed with a first trench.
  • the horizontal portion of the sacrificial structure is removed, and the first trench is closed to form an air cavity.
  • a second aspect of the present disclosure provides a semiconductor structure comprising:
  • the substrate comprising an active region and a shallow trench isolation structure separating the active region;
  • a word line trench formed in the substrate and intersecting the active region and the shallow trench isolation structure
  • a word line structure is formed in the word line trench, the word line structure includes a conductive layer, a top isolation structure, and an air cavity, and the air cavity is arranged between the conductive layer and the top isolation structure between.
  • Fig. 1 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a flow chart of forming a second intermediate structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 4 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 5 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 6 is a schematic structural view of a substrate provided in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 7 is a schematic cross-sectional view of the substrate provided in FIG. 6 along the x direction.
  • FIG. 8 is a schematic cross-sectional view of the word line trench of the substrate provided in FIG. 6 along the y direction.
  • Fig. 9 is a schematic diagram of forming a gate dielectric layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 10 is a schematic cross-sectional view of FIG. 9 along the x direction.
  • FIG. 11 is a schematic cross-sectional view of the word line trench in FIG. 9 along the y direction.
  • Fig. 12 is a schematic diagram of forming a barrier layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 13 is a schematic cross-sectional view of FIG. 12 along the x direction.
  • FIG. 14 is a schematic cross-sectional view of the word line trench in FIG. 12 along the y direction.
  • Fig. 15 is a schematic diagram of forming an initial conductive layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 16 is a schematic cross-sectional view of FIG. 15 along the x direction.
  • FIG. 17 is a schematic cross-sectional view of the word line trench in FIG. 15 along the y direction.
  • Fig. 18 is a schematic diagram of forming a conductive layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 19 is a schematic cross-sectional view of FIG. 18 along the x direction.
  • FIG. 20 is a schematic cross-sectional view of the word line trench in FIG. 20 along the y direction.
  • Fig. 21 is a schematic diagram of forming a first isolation structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 22 is a schematic cross-sectional view of FIG. 21 along the x direction.
  • FIG. 23 is a schematic cross-sectional view of the word line trench in FIG. 21 along the y direction.
  • Fig. 24 is a schematic diagram of forming a sacrificial structure in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 25 is a schematic cross-sectional view of FIG. 24 along the x direction.
  • FIG. 26 is a schematic cross-sectional view of the second trench in FIG. 24 along the y direction.
  • Fig. 27 is a schematic diagram of forming a second isolation structure in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 28 is a schematic cross-sectional view of Fig. 27 along the x direction.
  • FIG. 29 is a schematic cross-sectional view of the first trench in FIG. 27 along the y direction.
  • Fig. 30 is a schematic diagram of forming a third trench in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 31 is a schematic cross-sectional view of FIG. 30 along the x direction.
  • FIG. 32 is a schematic cross-sectional view of the third trench in FIG. 30 along the y direction.
  • Fig. 33 is a schematic diagram of forming a fourth trench in a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 34 is a schematic cross-sectional view of Fig. 33 along the x direction.
  • FIG. 35 is a schematic cross-sectional view of the fourth trench in FIG. 33 along the y direction.
  • Fig. 36 is a schematic diagram of forming a word line structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 37 is a schematic cross-sectional view of Fig. 36 along the x direction.
  • FIG. 38 is a schematic cross-sectional view of the word line structure in FIG. 36 along the y direction.
  • Fig. 39 is a schematic diagram of forming a word line structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 40 is a schematic cross-sectional view of FIG. 39 along the x direction.
  • FIG. 41 is a schematic cross-sectional view of the word line structure in FIG. 39 along the y direction.
  • Fig. 42 is a schematic diagram of forming a word line structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Figure 43 is a schematic cross-sectional view of Figure 42 along the x direction
  • Fig. 44 is a schematic diagram of forming a photoresist mask layer on the top surface of a substrate in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 45 is a schematic diagram showing the projection of a photoresist mask layer on a substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 46 is a schematic diagram of forming shallow trenches in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 47 is a schematic diagram of forming a shallow trench isolation structure in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 48 is a schematic projection view showing the formation of a first mask layer on a substrate in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • 200 word line structure; 200A, first intermediate structure; 200B, second intermediate structure; 210, gate dielectric layer; 220, barrier layer; 230, conductive layer; 231, initial conductive layer; 240, first isolation structure; 250 , the sacrificial structure; 251, the horizontal portion of the sacrificial structure; 252, the vertical portion of the sacrificial structure; 260, the second isolation structure; 270, the third isolation structure; 280, the top isolation structure;
  • FIG. 1 shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 6 - FIG. 38 is a schematic diagram of various stages of the manufacturing method of the semiconductor structure, and the manufacturing method of the semiconductor structure will be introduced below in conjunction with FIGS. 6-38 .
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • the X direction is the extending direction of the active region 110
  • the Y direction is the extending direction of the word line trench 130 .
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S110 providing a substrate, the substrate includes an active region and a shallow trench isolation structure separating the active region, the substrate is formed with a word line trench, and the word line trench exposes part of the active region and the shallow trench isolation structure.
  • providing the substrate 100 includes the following steps:
  • the substrate 101 may be made of a semiconductor material.
  • the semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.
  • a photoresist mask layer 103 is formed, and the photoresist mask layer 103 covers part of the substrate 101 top surface, as shown in Figure 45, the photoresist mask layer 103 is on the substrate
  • the projection on 101 includes a plurality of independently arranged mask units 1031 .
  • the portion of the substrate 101 exposed by the photoresist mask layer 103 is removed by dry or wet etching, as shown in FIG. 46 , to form a shallow trench 102 .
  • the photoresist mask layer 103 is removed, and the substrate 101 covered by the photoresist mask layer 103 forms a plurality of independently arranged active regions 110 , and the plurality of active regions 110 are separated by shallow trenches 102 .
  • a deposition process is adopted in this embodiment.
  • a chemical vapor deposition or an atomic layer deposition (Atomic layer deposition, ALD) process may be used to deposit a low-k dielectric material to fill the shallow trench.
  • ALD atomic layer deposition
  • the trench 102 forms a shallow trench isolation structure 120
  • the shallow trench isolation structure 120 separates a plurality of active regions 110 .
  • silicon oxide is deposited into the shallow trench 102 to form the shallow trench isolation structure 120 to isolate the active region 110 .
  • a first mask layer 104 is formed on the top surface of the active region 110 and the shallow trench isolation structure 120. As shown in FIG. 48, the projection of the first mask layer 104 on the substrate 101 exposes a portion The active region 110 and part of the shallow trench isolation structure 120 .
  • part of the active region 110 and part of the shallow trench isolation structure 120 exposed by the first mask layer 104 are removed to form a word line trench 130 .
  • the depth of removing the active region 110 and the shallow trench isolation structure 120 according to the first mask layer 104 is smaller than the depth of the shallow trench 102 .
  • the substrate 100 includes an active region 110 and a shallow trench isolation structure 120, wherein a plurality of active regions 110 are arranged at intervals in an array, and the shallow trench isolation structure 120 separates phases.
  • the adjacent active region 110 The shallow trench isolation structure 120 separates the active regions 110 , and adjacent active regions 110 are independent from each other, so as to avoid interference between adjacent active regions 110 .
  • Step S120 forming a first intermediate structure in the word line trench, the first intermediate structure covers sidewalls and bottom walls of the word line trench, the first intermediate structure is formed with a first trench, the first intermediate structure includes a sacrificial structure, The sacrificial structure includes a horizontal portion.
  • the first intermediate structure 200A is an intermediate process structure formed during the process of forming the word line structure 200 .
  • the first intermediate structure 200A is a laminated structure
  • the first intermediate structure 200A includes a sacrificial structure 250
  • the sacrificial structure 250 includes a horizontal portion 251 .
  • the first intermediate structure 200A forms the first trench 01 in the word line trench 130
  • the horizontal portion 251 of the sacrificial structure 250 serves as the bottom wall of the first trench 01 .
  • Step S130 removing the horizontal portion of the sacrificial structure, and sealing the first trench to form an air cavity.
  • the horizontal portion 251 of the sacrificial structure 250 may be removed by an etching process, or the horizontal portion 251 of the sacrificial structure 250 may also be removed by plasma reaction release.
  • the first trench 01 can be closed by chemical vapor deposition (Chemical Vapor Deposition, CVD) process or physical vapor deposition (Physical Vapor Deposition, PVD), so that the horizontal portion 251 of the original sacrificial structure 250 is located An air cavity 300 is formed.
  • an air cavity is formed above the conductive layer.
  • the existence of the air cavity reduces the parasitic capacitance between the wires of the semiconductor structure, reduces the interference intensity between the wires caused by the parasitic capacitance, and improves Electrical properties of semiconductor structures.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 2 , which shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S210 providing a substrate, the substrate includes an active region and a shallow trench isolation structure separating the active region, the substrate is formed with a word line trench, and the word line trench exposes part of the active region and the shallow trench isolation structure.
  • Step S210 in this embodiment is implemented in the same manner as step S110 in the above embodiment, and details are not repeated here.
  • Step S220 forming a second intermediate structure, the second intermediate structure includes a sacrificial structure, and the sacrificial structure forms a second trench.
  • the second intermediate structure 200B is an intermediate process structure formed in the process of forming the word line structure 200.
  • the second intermediate structure 200B is a stacked structure, and the second intermediate structure 200B A sacrificial structure 250 is included.
  • the sacrificial structure 250 includes a horizontal portion 251 and a vertical portion 252 .
  • the second intermediate structure 200B is located in the word line trench 130, and forms the second trench 02 in the word line trench 130.
  • the horizontal part 251 of the sacrificial structure 250 serves as the bottom surface of the second trench 02, and the vertical part of the sacrificial structure 250
  • the portion 252 serves as the groove wall of the second groove 02 .
  • Step S230 Depositing a second isolation structure in the second trench to form a first intermediate structure, the second isolation structure covers the bottom wall and the sidewall of the second trench, and the second isolation structure forms the first trench.
  • the second isolation structure 260 and the second intermediate structure 200B form a first intermediate structure 200A, and the first intermediate structure 200A is formed during the process of forming the word line structure 200 Intermediate process structure.
  • the second isolation structure 260 may be deposited and formed by using an atomic layer deposition (Atomic layer deposition, ALD) process.
  • ALD atomic layer deposition
  • the second isolation structure 260 covers the inner wall of the second trench 02 , and the first trench 01 is formed in the second trench 02 .
  • the width of the first trench 01 is narrower than that of the horizontal portion 251 of the sacrificial structure 250 .
  • the material of the second isolation structure 260 is different from that of the sacrificial structure 250.
  • the material of the second isolation structure 260 may be silicon nitride or silicon oxynitride.
  • the material of the second isolation structure 260 is silicon nitride, and the thickness of the second isolation structure 260 is 2nm-4nm.
  • Step S240 removing the horizontal portion of the sacrificial structure, and closing the first trench to form an air cavity.
  • the horizontal portion 251 of the sacrificial structure 250 can be removed by etching, so that after the first trench 01 is closed, as shown in FIG. 36 or 39 , the original sacrificial structure 250 The position of the horizontal portion 251 forms an air cavity 300 .
  • the semiconductor structure formed in this embodiment undergoes a subsequent process to form a bit line structure, a capacitive contact structure, or other wire structures.
  • the parasitic capacitance between the wire structures formed in the manufacturing process can avoid the interference between the wires caused by the parasitic capacitance, and improve the electrical performance and stability of the semiconductor structure.
  • step S220 in this embodiment is described, as shown in FIG. 3 , forming the second intermediate structure includes the following steps:
  • Step S221 forming a gate dielectric layer covering the bottom wall and sidewall of the word line trench.
  • the gate dielectric layer 210 can be deposited and formed by using an atomic layer deposition (Atomic layer deposition, ALD) process, and the material of the gate dielectric layer 210 can be Silicon monoxide, Hafnium oxide, Lanthanum(III) oxide, etc.
  • ALD atomic layer deposition
  • Step S222 forming a conductive layer, the conductive layer covers the bottom wall of the gate dielectric layer and the upper surface of the conductive layer is lower than the upper surface of the substrate.
  • the process of forming the conductive layer 230 includes: as shown in FIG. 15, FIG. 16, and FIG.
  • the dielectric layer 210 forms an initial conductive layer 231 .
  • the initial conductive layer 231 is etched by a dry or wet etching process, the initial conductive layer 231 covering the gate dielectric layer 210 is removed and the initial conductive layer 231 is etched back to Below the top surface of the substrate 100 , the retained initial conductive layer 231 forms a conductive layer 230 , and a space for forming an air cavity 300 is reserved above the conductive layer 230 .
  • the conductive layer 230 is located at the bottom of the word line trench 130 and covers the bottom wall of the gate dielectric layer 210 , and the conductive layer 230 exposes part of the sidewall of the gate dielectric layer 210 .
  • the material of the conductive layer 230 can be one or more of conductive metal, conductive metal nitride, and conductive alloy.
  • the material of the conductive layer 230 can be titanium (Titanium), tantalum (tantalum), tungsten (Tungsten). In this embodiment, the material of the conductive layer 230 is metal tungsten.
  • Step S223 forming a first isolation structure, the first isolation structure covers the top surface of the conductive layer.
  • the first isolation structure 240 may be deposited and formed by using an atomic layer deposition (Atomic layer deposition, ALD) process.
  • ALD atomic layer deposition
  • the material of the first isolation structure 240 may be silicon nitride or silicon oxynitride.
  • the material of the first isolation structure 240 is silicon nitride, and the thickness of the first isolation structure 240 is 2nm-4nm.
  • Step S224 Depositing a sacrificial structure to form a second intermediate structure, the sacrificial structure covering the bottom wall and the side wall of the first isolation structure.
  • an atomic layer deposition (Atomic layer deposition, ALD) process may be used to deposit a sacrificial material, and the sacrificial material covers the bottom wall and sidewall of the first isolation structure 240 to form a sacrificial structure 250 .
  • ALD atomic layer deposition
  • the sacrificial structure 250 covering the bottom wall of the first isolation structure 240 is the horizontal portion 25 of the sacrificial structure 250
  • the sacrificial structure 250 covering the side wall of the first isolation structure 240 is the sacrificial structure 250.
  • Vertical portion 252 of structure 250 is shown in FIG. 24 , referring to FIG. 21 , an atomic layer deposition (Atomic layer deposition, ALD) process may be used to deposit a sacrificial material, and the sacrificial material covers the bottom wall and sidewall of the first isolation structure 240 to form a sacrificial structure 250 .
  • the bottom wall of the first isolation structure 240 is reserved to protect the conductive layer 230.
  • the material of the sacrificial structure 250 is the same as that of the first isolation structure 240.
  • the materials of the isolation structure 240 are different, so that when the horizontal portion 251 of the sacrificial structure 250 is etched away, the horizontal portion 251 of the sacrificial structure 250 can be removed by selecting the etching selectivity ratio between the sacrificial structure 250 and the first isolation structure 240 without damaging the first isolation structure 240 .
  • the material of the sacrificial structure 250 may be silicon monoxide.
  • the thickness of the sacrificial structure 250 affects the volume of the air cavity 300 formed in the semiconductor structure.
  • the thickness of the sacrificial structure 250 is 4nm-6nm.
  • a step of forming a barrier layer 220 using an atomic layer deposition (Atomic layer deposition, ALD) process is also included.
  • ALD atomic layer deposition
  • the barrier layer 220 is formed to cover the gate dielectric layer 210 .
  • the material of the barrier layer 220 may be, for example, titanium nitride.
  • step S222 as described above is completed, as shown in FIG. 18 and FIG. 19, referring to FIG. 15 and FIG. Part of the sidewall of the gate dielectric layer 210 is exposed.
  • the retained initial conductive layer 231 forms the conductive layer 230
  • the barrier layer 220 is located between the conductive layer 230 and the gate dielectric layer 210 to prevent the material of the conductive layer 230 from penetrating into the substrate 100 and affecting the yield of the semiconductor structure.
  • the second intermediate structure formed in this embodiment includes a conductive layer and a sacrificial structure located above the conductive layer, and the horizontal portion of the sacrificial structure is separated from the conductive layer by the first isolation structure.
  • the An air cavity with a low dielectric constant is formed above the conductive layer, and the air cavity can change the electrical properties of the isolation structure above the conductive layer and reduce the parasitic capacitance between wires in the semiconductor structure.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 4 , which shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S310 providing a substrate, the substrate includes an active region and a shallow trench isolation structure separating the active region, the substrate is formed with a word line trench, and the word line trench exposes part of the active region and the shallow trench isolation structure.
  • Step S310 in this embodiment is implemented in the same manner as step S110 in the above embodiment, and details are not repeated here.
  • Step S320 forming a second intermediate structure, the second intermediate structure includes a sacrificial structure, and the sacrificial structure forms a second trench.
  • the second intermediate structure 200B is an intermediate process structure formed during the process of forming the word line structure 200 .
  • the second intermediate structure 200B is a stacked structure, and the second intermediate structure 200B includes a gate dielectric layer 210 covering the word line trench 130, a conductive layer 230 covering the bottom wall of the gate dielectric layer 210 and having a top surface lower than the top surface of the substrate 100, and The barrier layer 220 between the conductive layer 230 and the gate dielectric layer 210, the first isolation structure 240 covering the top surface of the conductive layer 230 and the gate dielectric layer 210 exposed by the conductive layer 230, and the sacrificial structure covering the first isolation structure 240 250.
  • the sacrificial structure 250 includes a horizontal portion 251 and a vertical portion 252 , and the sacrificial structure 250 encloses the second trench 02 in the word line trench 130 .
  • the horizontal portion 251 of the sacrificial structure 250 serves as the bottom surface of the second trench 02
  • the vertical portion 252 of the sacrificial structure 250 serves as the wall of the second trench 02 .
  • Step S330 Depositing a second isolation structure in the second trench to form a first intermediate structure, the second isolation structure covers the bottom wall and the sidewall of the second trench, and the second isolation structure forms the first trench.
  • a second isolation structure 260 is formed in the second intermediate structure 200B.
  • the second isolation structure 260 covers the sacrificial structure 250, and the second isolation structure 260 and The second intermediate structure 200B forms the first intermediate structure 200A.
  • the first trench 01 formed by the second isolation structure is narrower than the second trench 02 formed by the sacrificial structure 250 .
  • Step S340 removing part of the second isolation structure to form a third trench, and the third trench exposes a part of the horizontal portion of the sacrificial structure.
  • a part of the bottom wall of the second isolation structure 260 can be etched and removed by a dry or wet etching process, exposing the sacrificial structure 250.
  • Part of the horizontal portion 251 of the sacrificial structure 250 so that the third trench 03 is formed, and the width of the third trench 03 is narrower than that of the horizontal portion 251 of the sacrificial structure 250 .
  • Step S350 removing the horizontal portion of the sacrificial structure, and sealing the first trench to form an air cavity.
  • the horizontal portion 251 of the sacrificial structure 250 is removed, and the original position of the horizontal portion 251 of the sacrificial structure 250 forms a trench communicating with the third trench 03 .
  • the filling material is deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD) process or physical vapor deposition (Physical Vapor Deposition, PVD) to close the trench, and the deposition process is limited by the inner wall of the trench Due to the impact of the topography, the bottom of the first trench 01 where it is originally located is firstly sealed by the filling material, and the unfilled area in the trench forms an air cavity 300 .
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • the original position of the horizontal portion of the sacrificial structure forms a trench communicating with the third trench
  • the deposition process of filling the trench is affected by the topography of the inner wall of the trench, forming a deposition void above the conductive layer to form an air cavity, the air cavity has a low dielectric constant, and the existence of the air cavity can reduce the word line structure and other components of the semiconductor structure.
  • the parasitic capacitance between the wires improves the electrical performance and stability of the semiconductor structure.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG. 5 , which shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S410 providing a substrate, the substrate includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed on the substrate, and the word line trench exposes part of the active region and the shallow trench isolation structure.
  • Step S420 forming a second intermediate structure, the second intermediate structure includes a sacrificial structure, and the sacrificial structure forms a second trench.
  • Step S430 Depositing a second isolation structure in the second trench to form a first intermediate structure, the second isolation structure covers the bottom wall and the sidewall of the second trench, and the second isolation structure forms the first trench.
  • Steps S410-S430 in this embodiment are implemented in the same way as steps S310-S330 in the above-mentioned embodiment, and will not be repeated here.
  • Step S440 removing part of the second isolation structure to form a third trench, and the third trench exposes a part of the horizontal part of the sacrificial structure.
  • the second isolation structure 260 covering the horizontal portion 251 of the sacrificial structure 250 is removed to form the third trench 03 .
  • the etching rate of the etching gas in the vertical direction is greater than that in the horizontal direction
  • the etching speed is high, the bottom wall of the second isolation structure 260 is etched and removed by the etching gas to expose a part of the horizontal portion 251 of the sacrificial structure 250 , so that the depth of the first trench 01 is increased to form the third trench 03 .
  • the etching gas can be sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), chlorine (Cl 2 ), trifluoromethane (CHF 3 ), oxygen (O 2 ), bromine (Ar) One or more than two or mixed gases.
  • Step S450 injecting an etching solution into the third trench, removing the horizontal portion of the sacrificial structure to form an air layer, and the air layer communicates with the third trench to form a fourth trench.
  • the horizontal portion 251 of the sacrificial structure 250 is removed to form an air layer 310 .
  • a wet etching process is used to remove the horizontal portion 251 of the sacrificial structure 250 .
  • An etching solution is injected into the third trench 03, the etching solution has a high etching selectivity to the sacrificial material and the second isolation material, and the etching solution has a high etching selectivity to the sacrificial material and the first isolation material.
  • a hydrofluoric acid solution is used as an etching solution, and the hydrofluoric acid solution is injected into the third trench 03, and the hydrofluoric acid solution removes the horizontal portion 251 of the sacrificial structure 250 so that the horizontal portion of the original sacrificial structure 250 251 forms an air layer 310 , and the air layer 310 communicates with the third groove 03 to form the fourth groove 04 .
  • the width of the air layer 310 is larger than the width of the third groove 03, and the cross section of the fourth groove 04 is "convex" shape.
  • Step S460 forming a third isolation structure, the third isolation structure fills part of the fourth trench to form an air cavity.
  • a third isolation layer material can be deposited by a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process to form a third isolation structure 270 .
  • the third isolation structure 270 fills part of the fourth trench 04 , forming a closed air cavity 300 at the bottom of the fourth trench 04 .
  • the process of depositing the third isolation layer material to fill the fourth trench 04 is affected by the topography of the inner wall of the fourth trench 04.
  • the third isolation layer material is the first to seal the bottom of the third trench 03 to form a seal at the bottom of the fourth trench 04.
  • the air cavity 300 includes at least an air layer 310 formed by removing the horizontal portion 251 of the sacrificial structure 250 (see FIG. 36 ), and the air cavity 300 may also include part of the third groove 03 (see FIG. 39 or FIG. 41 ).
  • the third isolation structure 270 and the first intermediate structure 200A form the word line structure 200 , and the word line structure 200 is formed with an air cavity 300 closed and disposed above the conductive layer 230 .
  • an etching reagent is used to etch and remove the horizontal portion of the sacrificial structure, and a fourth trench with a "convex" cross-section is formed in the word line trench, so that when the fourth trench is filled, the filling process is affected by the first Influenced by the shape of the inner wall of the four trenches, an air cavity is formed at the bottom of the fourth trench, and finally the formed semiconductor structure has an air cavity above the conductive layer of the word line structure, and the air with a low dielectric constant reduces the isolation above the conductive layer.
  • the electrical properties of the structure are improved, thereby reducing the parasitic capacitance between the word line structure and other wire structures of the semiconductor structure.
  • the semiconductor structure includes: a substrate 100, a word line trench 130 formed in the substrate 100, and a word line The word line structure 200 in the trench 130 .
  • the substrate 100 includes an active region 110 and a shallow trench isolation structure 120 separating the active region 110 , and a word line trench 130 intersects the active region 110 and the shallow trench isolation structure 120 .
  • the word line structure 200 includes a conductive layer 230 , a top isolation structure 280 and an air cavity 300 disposed between the conductive layer 230 and the top isolation structure 280 .
  • an air cavity 300 is provided between the conductive layer 230 of the word line structure 200 and the upper top isolation structure 280.
  • the existence of the air cavity 300 changes the electrical characteristics of the top isolation structure 280, thereby reducing the word
  • the parasitic capacitance between the wire structure 200 and other wires of the semiconductor structure reduces the capacitive interference between the conductive structures of the semiconductor structure, and improves the electrical performance and stability of the semiconductor structure.
  • the word line structure 200 further includes a gate dielectric layer 210 and a first isolation structure 240, the gate dielectric layer 210 covers the bottom wall and the side wall of the word line trench 130, and the first isolation structure
  • the structure 240 covers the top surface of the conductive layer 230 and the sidewall of the gate dielectric layer 210 exposed by the conductive layer 230 , and the air cavity 300 is disposed between the top isolation structure 280 and the first isolation structure 240 .
  • the top isolation structure 280 includes a second isolation structure 260 and a third isolation structure 270 , and an air cavity 300 is formed between the bottom surface of the third isolation structure 270 and the first isolation structure 240 .
  • the bottom surface of the third isolation structure 270 is equal to the bottom surface of the second isolation structure 260
  • the height of the formed air cavity 300 is equal to the bottom surface of the second isolation structure 260 . high.
  • the bottom surface of the third isolation structure 270 is higher than the bottom surface of the second isolation structure 260 .
  • the bottom surface of the third isolation structure 270 is higher than the bottom surface of the second isolation structure 260
  • the cross section of the formed air cavity 300 is a "convex" structure.
  • the bottom surface of the third isolation structure 270 is higher than the bottom surface of the second isolation structure 260 , forming an irregular cross-sectional structure of the air cavity 300 .
  • the ratio of the width of the third isolation structure 270 to the width of the word line trench 130 ranges from 0.1 to 0.3.
  • the word line structure 200 includes a sacrificial structure 250, the sacrificial structure 250 covers the sidewall of the first isolation structure 240, the sacrificial structure 250 is arranged between the sidewall of the first isolation structure 240 and the second isolation structure 260, and the second isolation structure 260 The sacrificial structure 250 is covered.
  • the word line structure 200 further includes a barrier layer 220, which is disposed between the conductive layer 230 and the gate dielectric layer 210 to prevent the material of the conductive layer 230 from penetrating into the substrate 100 to contaminate the substrate 100 and affect the performance of the semiconductor structure.
  • an air cavity 300 is provided between the conductive layer 230 of the word line structure 200 and the top isolation structure 280.
  • the existence of the air cavity 300 affects the electrical performance of the top isolation structure 280, thereby reducing the word line of the semiconductor structure.
  • the parasitic capacitance between structure 200 and other conductive structures improves the electrical performance and stability of the semiconductor structure.
  • an air cavity is formed above the conductive layer of the semiconductor structure to reduce the parasitic capacitance between the conductors of the semiconductor structure, reduce the interference of the parasitic capacitance on the conductors of the semiconductor structure, and improve the performance of the semiconductor structure. Electrical properties and stability of structures.

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Abstract

本公开提供了一种半导体结构的制作方法及半导体结构，半导体结构的制作方法包括，提供基底，基底包括有源区及将有源区隔开的浅沟槽隔离结构，基底形成有字线沟槽，字线沟槽暴露部分有源区和浅沟槽隔离结构；在字线沟槽内形成第一中间结构，第一中间结构覆盖字线沟槽的侧壁和底壁，第一中间结构形成有第一沟槽，第一中间结构包括牺牲结构，牺牲结构包括水平部；去除牺牲结构的水平部，并封闭第一沟槽，形成空气腔。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202110918051.2，申请日为2021年08月11日，申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
动态随机存储器(Dynamic random access memory，简称DRAM)具有体积小、集成度高、功耗低的优点，其读取速度和写入速度比只读存储器(ROM，Read Only Memory)更快。
动态随机存储器由多个重复的存储单元组成，每个存储单元通常包括电容结构和晶体管，晶体管的栅极与字线相连，晶体管的漏极与位线相连，晶体管的源极与电容结构相连。随着动态随机存储器的集成度不断提高，动态随机存储器的字线与字线之间的间距，以及字线与位线之间的间距越来越小，从而造成字线与字线之间以及字线与位线之间容易产生较大的寄生电容，导致导线间互相干扰，影响动态随机存储器的电性能。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供一种半导体结构的制作方法，所述制作方法包括：
提供基底，所述基底包括有源区及将所述有源区隔开的浅沟槽隔离结构，所述基底形成有字线沟槽，所述字线沟槽暴露部分所述有源区和浅沟槽隔离结构；
在所述字线沟槽内形成第一中间结构，所述第一中间结构覆盖所述字线沟槽的侧壁和底壁，所述第一中间结构形成有第一沟槽，所述第一中间结构包括牺牲结构，所述牺牲结构包括水平部；
去除所述牺牲结构的水平部，并封闭所述第一沟槽，形成空气腔。
本公开的第二方面提供一种半导体结构，所述半导体结构包括：
基底，所述基底包括有源区以及将所述有源区隔开的浅沟槽隔离结构；
字线沟槽，所述字线沟槽形成于所述基底中，且与所述有源区和所述浅沟槽隔离结构相交；
字线结构，所述字线结构形成于所述字线沟槽中，所述字线结构包括导电层、顶部隔离结构和空气腔，所述空气腔设置于所述导电层和顶部隔离结构之间。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图3是根据一示例性实施例示出的一种半导体结构的制作方法中形成第二中间结构的流程图。
图4是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图5是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图6是根据一示例性实施例示出的一种半导体结构的制作方法中提供 的基底的结构示意图。
图7是图6提供的基底沿x方向的截面示意图。
图8是图6提供的基底的字线沟槽沿y方向的截面示意图。
图9是根据一示例性实施例示出的一种半导体结构的制作方法中形成栅介质层的示意图。
图10是图9沿x方向的截面示意图。
图11是图9中字线沟槽沿y方向的截面示意图。
图12是根据一示例性实施例示出的一种半导体结构的制作方法中形成阻挡层的示意图。
图13是图12沿x方向的截面示意图。
图14是图12中字线沟槽沿y方向的截面示意图。
图15是根据一示例性实施例示出的一种半导体结构的制作方法中形成初始导电层的示意图。
图16是图15沿x方向的截面示意图。
图17是图15中字线沟槽沿y方向的截面示意图。
图18是根据一示例性实施例示出的一种半导体结构的制作方法中形成导电层的示意图。
图19是图18沿x方向的截面示意图。
图20是图20中字线沟槽沿y方向的截面示意图。
图21是根据一示例性实施例示出的一种半导体结构的制作方法中形成第一隔离结构的示意图。
图22是图21沿x方向的截面示意图。
图23是图21中字线沟槽沿y方向的截面示意图。
图24是根据一示例性实施例示出的一种半导体结构的制作方法中形成牺牲结构的示意图。
图25是图24沿x方向的截面示意图。
图26是图24中第二沟槽沿y方向的截面示意图。
图27是根据一示例性实施例示出的一种半导体结构的制作方法中形成第二隔离结构的示意图。
图28是图27沿x方向的截面示意图。
图29是图27中第一沟槽沿y方向的截面示意图。
图30是根据一示例性实施例示出的一种半导体结构的制作方法中形成第三沟槽的示意图。
图31是图30沿x方向的截面示意图。
图32是图30中第三沟槽沿y方向的截面示意图。
图33是根据一示例性实施例示出的一种半导体结构的制作方法中形成第四沟槽的示意图。
图34是图33沿x方向的截面示意图。
图35是图33中第四沟槽沿y方向的截面示意图。
图36是根据一示例性实施例示出的一种半导体结构的制作方法中形成字线结构的示意图。
图37是图36沿x方向的截面示意图。
图38是图36中字线结构沿y方向的截面示意图。
图39是根据一示例性实施例示出的一种半导体结构的制作方法中形成字线结构的示意图。
图40是图39沿x方向的截面示意图。
图41是图39中字线结构沿y方向的截面示意图。
图42是根据一示例性实施例示出的一种半导体结构的制作方法中形成字线结构的示意图。
图43是图42沿x方向的截面示意图
图44是根据一示例性实施例示出的一种半导体结构的制作方法中在衬底顶面形成光刻胶掩膜层的示意图。
图45是根据一示例性实施例示出的一种半导体结构的制作方法中光刻胶掩膜层在衬底上的投影示意图。
图46是根据一示例性实施例示出的一种半导体结构的制作方法中形成浅沟槽的示意图。
图47是根据一示例性实施例示出的一种半导体结构的制作方法中形成浅沟槽隔离结构的示意图。
图48是根据一示例性实施例示出的一种半导体结构的制作方法中第一掩膜层在衬底上形成的投影示意图。
附图标记：
01、第一沟槽；02、第二沟槽；03、第三沟槽；04、第四沟槽；
100、基底；101、衬底；102、浅沟槽；103、光刻胶掩膜层；1031、掩膜单元；104、第一掩膜层；110、有源区；120、浅沟槽隔离结构；130、字线沟槽；
200、字线结构；200A、第一中间结构；200B、第二中间结构；210、栅介质层；220、阻挡层；230、导电层；231、初始导电层；240、第一隔离结构；250、牺牲结构；251、牺牲结构的水平部；252、牺牲结构的竖直部；260、第二隔离结构；270、第三隔离结构；280、顶部隔离结构；
300、空气腔；310、空气层。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图6-图38为半导体结构的制作方法的各个阶段的示意图，下面结合图6-图38对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
在本公开的实施例中，X方向为有源区110的延伸方向，Y方向为字线沟槽130的延伸方向。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S110：提供基底，基底包括有源区及将有源区隔开的浅沟槽隔离结构，基底形成有字线沟槽，字线沟槽暴露部分有源区和浅沟槽隔离结构。
其中，提供基底100包括以下步骤：
S111、提供衬底。
如图44所示，衬底101可以由半导体材料制成，示例性的，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
S112、刻蚀衬底以在衬底中形成浅沟槽，浅沟槽将衬底隔离成阵列排布的多个有源区。
如图45所示，参照图44，形成光刻胶掩膜层103，光刻胶掩膜层103覆盖部分衬底101顶面，如图45所示，光刻胶掩膜层103在衬底101上的投影包括多个独立设置的掩膜单元1031。通过干法或湿法刻蚀去除光刻胶掩膜层103暴露出的部分衬底101，如图46所示，形成浅沟槽102。去除光刻胶掩膜层103，被光刻胶掩膜层103覆盖的衬底101形成多个独立设置的有源区110，多个有源区110被浅沟槽102隔开。
S113、填充浅沟槽以形成浅沟槽隔离结构。
如图47所示，参照图46，本实施例中采用沉积工艺，示例性的，可以采用化学气相沉积、或原子层沉积(Atomic layer deposition，ALD)工艺，沉积低k介电材料填充浅沟槽102形成浅沟槽隔离结构120，浅沟槽隔离结构120将多个有源区110隔开。在本实施例中，向浅沟槽102中沉积氧化硅形成浅沟槽隔离结构120以隔离有源区110。
S114、形成第一掩膜层。
如图47所示，在有源区110和浅沟槽隔离结构120顶面形成第一掩膜层104，如图48所示，第一掩膜层104在衬底101上的投影暴露出部分有源区110以及部分浅沟槽隔离结构120。
S115、根据第一掩膜层部分去除有源区和浅沟槽隔离结构，形成字线沟槽。
如图6所示，去除第一掩膜层104暴露出的部分有源区110和部分浅沟槽隔离结构120，形成字线沟槽130。其中，根据第一掩膜层104去除有源区110和浅沟槽隔离结构120的深度小于浅沟槽102的深度。
如图6、图7、图8所示，基底100包括有源区110以及浅沟槽隔离结构 120，其中，多个有源区110呈阵列式间隔排布，浅沟槽隔离结构120分隔相邻的有源区110。浅沟槽隔离结构120将有源区110隔开，相邻的有源区110相互独立，避免相邻的有源区110之间产生干扰。
步骤S120：在字线沟槽内形成第一中间结构，第一中间结构覆盖字线沟槽的侧壁和底壁，第一中间结构形成有第一沟槽，第一中间结构包括牺牲结构，牺牲结构包括水平部。
在本实施例中，如图28所示，第一中间结构200A是形成字线结构200的过程中形成的中间过程结构。参照图29、图30，第一中间结构200A为叠层结构，第一中间200A结构包括牺牲结构250，牺牲结构250包括水平部251。第一中间结构200A在字线沟槽130中形成第一沟槽01，牺牲结构250的水平部251作为第一沟槽01的底壁。
步骤S130：去除牺牲结构的水平部，并封闭第一沟槽，形成空气腔。
如图33所示，可以通过刻蚀工艺去除牺牲结构250的水平部251，或者，还可以通过等离子体反应释放去除牺牲结构250的水平部251。如图36所示，可以通过化学气相沉积(Chemical Vapor Deposition，CVD)工艺或物理气相沉积(Physical Vapor Deposition，PVD)沉积封闭第一沟槽01，以使原牺牲结构250的水平部251所在位置形成空气腔300。
本实施例所提供的半导体结构的制作方法，在导电层的上方形成空气腔，空气腔的存在降低了半导体结构的导线之间的寄生电容，减小了寄生电容造成的导线间干扰强度，提高半导体结构的电性能。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图2所示，图2示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图2所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S210：提供基底，基底包括有源区及将有源区隔开的浅沟槽隔离结构，基底形成有字线沟槽，字线沟槽暴露部分有源区和浅沟槽隔离结构。
本实施例的步骤S210和上述实施例步骤S110的实现方式相同，在此，不再赘述。
步骤S220：形成第二中间结构，第二中间结构包括牺牲结构，牺牲结构 形成第二沟槽。
如图24所示，第二中间结构200B是形成字线结构200的过程中形成的中间过程结构，如图25、图26所示，第二中间结构200B为叠层结构，第二中间结构200B包括牺牲结构250。其中，牺牲结构250包括水平部251和竖直部252。第二中间结构200B位于字线沟槽130中，在字线沟槽130中围成第二沟槽02，牺牲结构250的水平部251作为第二沟槽02的底面，牺牲结构250的竖直部252作为第二沟槽02的槽壁。
步骤S230：在第二沟槽内沉积第二隔离结构，形成第一中间结构，第二隔离结构覆盖第二沟槽的底壁和侧壁，第二隔离结构形成第一沟槽。
如图27所示，参照图24，在本实施例中，第二隔离结构260和第二中间结构200B形成第一中间结构200A，第一中间结构200A是形成字线结构200的过程中形成的中间过程结构。如图28、29所示，参照图25、26，可以采用原子层沉积(Atomic layer deposition，ALD)工艺沉积形成第二隔离结构260。第二隔离结构260覆盖第二沟槽02的内壁，在第二沟槽02中形成第一沟槽01，第一沟槽01的宽度比牺牲结构250的水平部251的宽度窄。第二隔离结构260的材料与牺牲结构250的材料不同，在本实施例中，第二隔离结构260的材料可以为氮化硅(Silicon nitride)或氮氧化硅(Silicon oxynitride)。在本实施例中，第二隔离结构260的材料为氮化硅，第二隔离结构260的厚度为2nm-4nm。
步骤S240：去除牺牲结构的水平部，并封闭第一沟槽，形成空气腔。
如图33所示，结合图34、图35，可以刻蚀去除牺牲结构250的水平部251，以使第一沟槽01封闭后，如图36或如图39所示，在原牺牲结构250的水平部251所在位置形成空气腔300。
本实施例形成的半导体结构进行后续制程形成位线结构、电容接触结构或其它导线结构，空气腔位于字线结构的导电层和后续制程形成的导线结构之间，能够减小字线结构与后续制程形成的导线结构之间的寄生电容，避免寄生电容造成导线间互相干扰，提高了半导体结构的电性能和稳定性。
示例性的，对本实施例步骤S220的实现过程进行说明，如图3所示，形成第二中间结构包括以下步骤：
步骤S221：形成栅介质层，栅介质层覆盖字线沟槽的底壁和侧壁。
如图9、图10、图11所示，参照图6、图7、图8，可以采用原子层沉积(Atomic layer deposition，ALD)工艺沉积形成栅介质层210，栅介质层210的材料可以为氧化硅(Silicon monoxide)、氧化铪(Hafnium oxide)、氧化镧(Lanthanum(III)oxide)等。
步骤S222：形成导电层，导电层覆盖栅介质层的底壁且导电层的上表面低于基底的上表面。
在本实施例中，形成导电层230的过程包括：如图15、图16、图17所示，采用原子层沉积(Atomic layer deposition，ALD)工艺沉积导电材料填充字线沟槽130且覆盖栅介质层210形成初始导电层231。然后，如图18、图19、图20所示，通过干法或湿法刻蚀工艺刻蚀初始导电层231，去除覆盖栅介质层210的初始导电层231并将初始导电层231回刻至低于基底100顶面，被保留的初始导电层231形成导电层230，导电层230上方被保留有用于形成空气腔300的空间。导电层230位于字线沟槽130的底部、覆盖栅介质层210的底壁，导电层230暴露出栅介质层210的部分侧壁。
其中，导电层230的材料可以为导电金属、导电金属氮化物、导电合金中的一种或二种以上，示例性的，导电层230的材料可以为钛(Titanium)、钽(tantalum)、钨(Tungsten)。在本实施例中，导电层230的材料为金属钨。
步骤S223：形成第一隔离结构，第一隔离结构覆盖导电层的顶面。
如图21、图22、图23所示，参照图18、图19、图20，可以采用原子层沉积(Atomic layer deposition，ALD)工艺沉积形成第一隔离结构240。
示例性的，第一隔离结构240的材料可以为氮化硅(Silicon nitride)或氮氧化硅(Silicon oxynitride)。在本实施例中，第一隔离结构240的材料为氮化硅，第一隔离结构240的厚度为2nm-4nm。
步骤S224：沉积牺牲结构，形成第二中间结构，牺牲结构覆盖第一隔离结构的底壁和侧壁。
如图24，参照图21，可以采用原子层沉积(Atomic layer deposition，ALD)工艺沉积牺牲材料，牺牲材料覆盖第一隔离结构240的底壁和侧壁形成牺牲结构250。如图25、图26所示，覆盖在第一隔离结构240的底壁上的牺牲结构250为牺牲结构250的水平部25，覆盖在第一隔离结构240的侧壁上的牺 牲结构250为牺牲结构250的竖直部252。为了去除牺牲结构250的水平部251而不破坏第一隔离结构240的底壁，保留第一隔离结构240的底壁以保护导电层230，在本实施例中，牺牲结构250的材料与第一隔离结构240的材料不同，以使在刻蚀去除牺牲结构250的水平部251时，可通过选择刻蚀牺牲结构250和第一隔离结构240的刻蚀选择比，去除牺牲结构250的水平部251而不破坏第一隔离结构240。在本实施例中，牺牲结构250的材料可以为氧化硅(Silicon monoxide)。
牺牲结构250的厚度影响半导体结构中形成的空气腔300的体积，为了能够形成空气腔300、保证空气腔300的体积，在本实施例中，牺牲结构250的厚度为4nm-6nm。
在本实施例中，在形成栅介质层210之后，在形成导电层230之前，如图12所示，还包括采用原子层沉积(Atomic layer deposition，ALD)工艺形成阻挡层220的步骤。如图13、图14所示，形成的阻挡层220覆盖栅介质层210。在本实施例中，阻挡层220的材料比如可以为氮化钛。
如上文中记载的步骤S222完成后，如图18、图19所示，参照图15、图16，导电层230位于字线沟槽130的底部、覆盖栅介质层210的底壁，导电层230暴露出栅介质层210的部分侧壁。被保留的初始导电层231形成导电层230，阻挡层220位于导电层230和栅介质层210之间，以防止导电层230的材料向基底100中渗透影响半导体结构的良率。
本实施例形成的第二中间结构包括导电层以及位于导电层上方的牺牲结构，且牺牲结构的水平部和导电层被第一隔离结构隔开，通过去除牺牲结构的水平部在字线结构的导电层的上方形成具有低介电常数的空气腔，空气腔能够改变位于导电层上方的隔离结构的电性能，减小半导体结构中导线间的寄生电容。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图4所示，图4示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图4所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S310：提供基底，基底包括有源区及将有源区隔开的浅沟槽隔离结 构，基底形成有字线沟槽，字线沟槽暴露部分有源区和浅沟槽隔离结构。
本实施例的步骤S310和上述实施例步骤S110的实现方式相同，在此，不再赘述。
步骤S320：形成第二中间结构，第二中间结构包括牺牲结构，牺牲结构形成第二沟槽。
如图24所示，第二中间结构200B是形成字线结构200的过程中形成的中间过程结构。如图25、图26所示。第二中间结构200B为叠层结构，第二中间结构200B包括覆盖字线沟槽130的栅介质层210、覆盖栅介质层210底壁且顶面低于基底100顶面的导电层230、设置在导电层230和栅介质层210之间的阻挡层220、覆盖导电层230顶面和被导电层230暴露出的栅介质层210的第一隔离结构240以及覆盖第一隔离结构240的牺牲结构250。
其中，如图25所示，牺牲结构250包括水平部251和竖直部252，牺牲结构250在字线沟槽130中围成第二沟槽02。牺牲结构250的水平部251作为第二沟槽02的底面，牺牲结构250的竖直部252作为第二沟槽02的槽壁。
步骤S330：在第二沟槽内沉积第二隔离结构，形成第一中间结构，第二隔离结构覆盖第二沟槽的底壁和侧壁，第二隔离结构形成第一沟槽。
如图27所示，参照图24，在第二中间结构200B中形成第二隔离结构260，如图29所示，参照图26，第二隔离结构260覆盖牺牲结构250，第二隔离结构260和第二中间结构200B形成第一中间结构200A。如图28所示，参照图25，第二隔离结构形成的第一沟槽01比牺牲结构250形成的第二沟槽02窄。
步骤S340：去除部分第二隔离结构，形成第三沟槽，第三沟槽暴露出牺牲结构的部分水平部。
如图30、图31、图32所示，参照图27、图28、图29，可以通过干法或湿法刻蚀工艺刻蚀去除部分第二隔离结构260的底壁，暴露出牺牲结构250的部分水平部251，以使形成第三沟槽03，第三沟槽03的宽度比牺牲结构250的水平部251的宽度窄。
步骤S350：去除牺牲结构的水平部，并封闭第一沟槽，形成空气腔。
如图33所示，参照图30，结合图34、图35，去除牺牲结构250的水平部251，牺牲结构250的水平部251原本所在的位置与第三沟槽03形成连通的沟槽。
如图36或图39所示，参照图33，通过化学气相沉积(Chemical Vapor Deposition，CVD)工艺或物理气相沉积(Physical Vapor Deposition，PVD)沉积填充材料以封闭沟槽，沉积过程受到沟槽内壁形貌的影响，使得第一沟槽01原本所在位置的底部先被填充材料封闭，而沟槽中未被填充的区域形成空气腔300。
本实施例中，通过形成牺牲结构和第二隔离结构，再去除牺牲结构的水平部和部分第二隔离结构，使牺牲结构的水平部原本所在的位置与第三沟槽形成连通的沟槽，以使填充沟槽的沉积过程受到沟槽内壁形貌的影响，在导电层上方形成沉积空白形成空气腔，空气腔具有低介电常数，空气腔的存在能够降低字线结构与半导体结构的其它导线间的寄生电容，提高半导体结构的电性能和稳定性。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图5所示，图5示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图。
如图5所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S410：提供基底，基底包括有源区及将有源区隔开的浅沟槽隔离结构，基底形成有字线沟槽，字线沟槽暴露部分有源区和浅沟槽隔离结构。
步骤S420：形成第二中间结构，第二中间结构包括牺牲结构，牺牲结构形成第二沟槽。
步骤S430：在第二沟槽内沉积第二隔离结构，形成第一中间结构，第二隔离结构覆盖第二沟槽的底壁和侧壁，第二隔离结构形成第一沟槽。
本实施例的步骤S410-S430和上述实施例步骤S310-S330的实现方式相同，在此，不再赘述。
步骤S440：去除部分第二隔离结构，形成第三沟槽，第三沟槽暴露出牺牲结构的部分水平部。
如图30、图31、图32所示，参照图27、图28、图29，去除覆盖牺牲结构250的水平部251的第二隔离结构260，形成第三沟槽03。向第一沟槽01中通入刻蚀气体，以基底100顶面为水平方向，以第一沟槽01延伸方向为竖直方向，刻蚀气体在竖直方向的刻蚀速度大于在水平方向的刻蚀速度， 刻蚀气体刻蚀去除第二隔离结构260的底壁暴露出牺牲结构250的部分水平部251，以使第一沟槽01的深度增加形成第三沟槽03。刻蚀气体可以为六氟化硫(SF 6)、四氟化碳(CF 4)、氯气(Cl 2)、三氟甲烷(CHF 3)、氧气(O 2)、溴气(Ar)中的一种或两种以上的或混合气体。
步骤S450：向第三沟槽中注入刻蚀溶液，去除牺牲结构的水平部以形成空气层，空气层和第三沟槽连通形成第四沟槽。
如图33、图34、图35所示，参照图30、图31、图32，去除牺牲结构250的水平部251以形成空气层310。在本实施例中采用湿法刻蚀工艺去除牺牲结构250的水平部251。向第三沟槽03中注入刻蚀溶液，刻蚀溶液对牺牲材料和第二隔离材料具有高刻蚀选择比，且刻蚀溶液对牺牲材料和第一隔离材料具有高刻蚀选择比。本实施例中，以氢氟酸溶液作为刻蚀溶液，将氢氟酸溶液注入到第三沟槽03中，氢氟酸溶液去除牺牲结构250的水平部251以使原牺牲结构250的水平部251所在位置形成空气层310，空气层310和第三沟槽03连通形成第四沟槽04。如图33、图34所示，在竖直方向上，空气层310的宽度大于第三沟槽03的宽度，第四沟槽04的截面为“凸”形。
步骤S460：形成第三隔离结构，第三隔离结构填充部分第四沟槽，形成空气腔。
如图36、图37、图38所示，参照图33、图34、图35，可以通过低压化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)工艺沉积第三隔离层材料形成第三隔离结构270。第三隔离结构270填充部分第四沟槽04，在第四沟槽04底部形成封闭的空气腔300。沉积第三隔离层材料填充第四沟槽04的过程受到第四沟槽04内壁形貌的影响，第三隔离层材料率先封闭第三沟槽03底部，以在第四沟槽04底部形成封闭的空气腔300，空气腔300至少包括去除牺牲结构250的水平部251形成的空气层310(参照图36)，空气腔300可能还包括部分第三沟槽03(参照图39或图41)。第三隔离结构270和第一中间结构200A形成字线结构200，字线结构200中形成有封闭设置于导电层230上方的空气腔300。
本实施例中，采用刻蚀试剂刻蚀去除牺牲结构的水平部，在字线沟槽中形成截面呈“凸”型的第四沟槽，以使填充第四沟槽时，填充过程受到第四沟槽内壁形貌影响，在第四沟槽底部形成空气腔，进而最终形成的半导体结 构，在字线结构的导电层上方形成有空气腔，低介电常数的空气降低了导电层上方隔离结构的电性能，进而降低了半导体结构的字线结构和其它导线结构之间的寄生电容。
本公开示例性的实施例中提供一种半导体结构，如图36、或图39或图41所示，半导体结构包括：基底100、形成于基底100中的字线沟槽130以及形成于字线沟槽130中的字线结构200。基底100包括有源区110以及将有源区110隔开的浅沟槽隔离结构120，字线沟槽130与有源区110和浅沟槽隔离结构120相交。字线结构200包括导电层230、顶部隔离结构280和空气腔300，空气腔300设置于导电层230和顶部隔离结构280之间。
本实施例的半导体结构，在字线结构200的导电层230和上方的顶部隔离结构280之间设置有空气腔300，空气腔300的存在改变了顶部隔离结构280的电特性，进而降低了字线结构200与半导体结构的其它导线之间的寄生电容，减少了半导体结构的导电结构间的电容干扰，提高了半导体结构的电性能和稳定性。
如图36、或图39或图41所示，字线结构200还包括栅介质层210和第一隔离结构240，栅介质层210覆盖字线沟槽130的底壁和侧壁，第一隔离结构240覆盖导电层230的顶面和被导电层230暴露出的栅介质层210的侧壁，空气腔300设置于顶部隔离结构280和第一隔离结构240之间。
如图36、或图39或图41所示，顶部隔离结构280包括第二隔离结构260和第三隔离结构270，第三隔离结构270的底面和第一隔离结构240之间形成空气腔300。
在本实施例中，参照图36、图37、图38，第三隔离结构270的底面和第二隔离结构260的底面等高，形成的空气腔300的高度与第二隔离结构260的底面等高。在本公开其它实施例中，如图39或如图41所示，第三隔离结构270的底面高于第二隔离结构260的底面。例如，参照图39、图40、图41，第三隔离结构270的底面高于第二隔离结构260的底面，形成的空气腔300的截面为“凸”形结构。再例如，参照图41、图42，第三隔离结构270的底面高于第二隔离结构260的底面，形成的空气腔300的截面不规则结构。
其中，在本实施例中，第三隔离结构270的宽度与字线沟槽130的宽度之比范围为0.1～0.3。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图36、或图39或图41所示，字线结构200包括牺牲结构250，牺牲结构250覆盖第一隔离结构240的侧壁，牺牲结构250设置第一隔离结构240的侧壁和第二隔离结构260之间，第二隔离结构260覆盖牺牲结构250。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图36、或图39或图41所示，字线结构200还包括阻挡层220，阻挡层220设置于导电层230和栅介质层210之间，以防止导电层230的材料渗透到基底100中污染基底100影响半导体结构的性能。
本实施例的半导体结构，字线结构200的导电层230和顶部隔离结构280之间设置有空气腔300，空气腔300的存在影响顶部隔离结构280的电性能，进而降低了半导体结构的字线结构200和其它导线结构之间的寄生电容，提高半导体结构的电性能和稳定性。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开 中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的制作方法及半导体结构中，在半导体结构的导电层上方形成空气腔，降低半导体结构导线间的寄生电容，减少寄生电容对半导体结构导线间的干扰，提高半导体结构的电性能和稳定性。

Claims (15)

  1. 一种半导体结构的制作方法，所述半导体结构的制作方法包括：
    提供基底，所述基底包括有源区及将所述有源区隔开的浅沟槽隔离结构，所述基底形成有字线沟槽，所述字线沟槽暴露部分所述有源区和浅沟槽隔离结构；
    在所述字线沟槽内形成第一中间结构，所述第一中间结构覆盖所述字线沟槽的侧壁和底壁，所述第一中间结构形成有第一沟槽，所述第一中间结构包括牺牲结构，所述牺牲结构包括水平部；
    去除所述牺牲结构的水平部，并封闭所述第一沟槽，形成空气腔。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，在所述字线沟槽内形成第一中间结构，包括：
    形成第二中间结构，所述牺牲结构形成第二沟槽；
    在所述第二沟槽内沉积第二隔离结构，形成所述第一中间结构，所述第二隔离结构覆盖所述第二沟槽的底壁和侧壁，所述第二隔离结构形成所述第一沟槽。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，所述形成所述第二中间结构，包括：
    形成栅介质层，所述栅介质层覆盖所述字线沟槽的底壁和侧壁；
    形成导电层，所述导电层覆盖所述栅介质层的底壁且所述导电层的上表面低于所述基底的上表面；
    形成第一隔离结构，所述第一隔离结构覆盖所述导电层的顶面；
    沉积牺牲结构，形成所述第二中间结构，所述牺牲结构覆盖所述第一隔离结构的底壁和侧壁。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，所述半导体结构的制作方法还包括：
    去除部分所述第二隔离结构，形成第三沟槽，所述第三沟槽暴露出所述牺牲结构的部分所述水平部。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，所述去除所述牺牲结构的水平部，包括：
    向所述第三沟槽中注入刻蚀溶液，去除所述牺牲结构的水平部以形成空气层，所述空气层和所述第三沟槽连通形成第四沟槽。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，所述封闭所述第一沟槽，包括：
    形成第三隔离结构，所述第三隔离结构填充部分所述第四沟槽。
  7. 根据权利要求6所述的半导体结构的制作方法，其中，所述形成第三隔离结构，所述第三隔离结构填充部分所述第四沟槽，包括：
    通过低压化学气相沉积法沉积所述第三隔离结构，所述第三隔离结构封闭所述第三沟槽，形成空气腔。
  8. 根据权利要求3所述的半导体结构的制作方法，其中，所述形成导电层，包括：
    形成初始导电层，所述初始导电层填充所述字线沟槽，且覆盖所述栅介质层；
    回刻所述初始导电层以形成所述导电层。
  9. 根据权利要求1所述的半导体结构的制作方法，其中，所述提供基底，包括：
    提供衬底；
    刻蚀所述衬底以在所述衬底中形成浅沟槽，所述浅沟槽将所述衬底隔离成阵列排布的多个有源区；
    填充所述浅沟槽以形成浅沟槽隔离结构；
    形成第一掩膜层；
    根据第一掩膜层部分去除所述有源区和浅沟槽隔离结构，形成所述字线 沟槽。
  10. 一种半导体结构，所述半导体结构包括：
    基底，所述基底包括有源区以及将所述有源区隔开的浅沟槽隔离结构；
    字线沟槽，所述字线沟槽形成于所述基底中，且与所述有源区和所述浅沟槽隔离结构相交；
    字线结构，所述字线结构形成于所述字线沟槽中，所述字线结构包括导电层、顶部隔离结构和空气腔，所述空气腔设置于所述导电层和顶部隔离结构之间。
  11. 根据权利要求10所述的半导体结构，其中，所述字线结构包括栅介质层和第一隔离结构，所述栅介质层覆盖所述字线沟槽的底壁和侧壁，所述第一隔离结构覆盖所述导电层的顶面和所述栅介质层的部分侧壁，所述空气层设置于所述顶部隔离结构和所述第一隔离结构之间。
  12. 根据权利要求11所述的半导体结构，其中，所述字线结构包括阻挡层，所述阻挡层设置于所述导电层和所述栅介质层之间。
  13. 根据权利要求11所述的半导体结构，其特征在于，所述顶部隔离结构包括第二隔离结构和第三隔离结构，所述第三隔离结构的底面等于或高于所述第二隔离结构的底面。
  14. 根据权利要求13所述的半导体结构，其中，所述字线结构还包括牺牲结构，所述牺牲结构覆盖所述第一隔离结构的侧壁，所述第二隔离结构覆盖所述牺牲结构的侧壁。
  15. 根据权利要求13所述的半导体结构，其特征在于，所述第三隔离结构的宽度与所述字线沟槽的宽度之比范围为0.1～0.3。
PCT/CN2021/116921 2021-08-11 2021-09-07 半导体结构的制作方法及半导体结构 WO2023015641A1 (zh)

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