WO2023010606A1 - 一种半导体存储装置及形成方法 - Google Patents

一种半导体存储装置及形成方法 Download PDF

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Publication number
WO2023010606A1
WO2023010606A1 PCT/CN2021/112209 CN2021112209W WO2023010606A1 WO 2023010606 A1 WO2023010606 A1 WO 2023010606A1 CN 2021112209 W CN2021112209 W CN 2021112209W WO 2023010606 A1 WO2023010606 A1 WO 2023010606A1
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sub
conductive layer
region
wire
shallow trench
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PCT/CN2021/112209
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English (en)
French (fr)
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卢经文
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长鑫存储技术有限公司
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Priority to US17/706,333 priority Critical patent/US12108590B2/en
Publication of WO2023010606A1 publication Critical patent/WO2023010606A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to the field of semiconductor technology, and relates to but not limited to a semiconductor storage device and a forming method.
  • DRAM dynamic random access memory
  • the buried word line cuts through the passing gate area between the two active areas. During repeated reading and writing, it will generate Accumulated parasitic electrons. When parasitic electrons flow to the source/drain electrically connected to the bit line through the bottom of another buried word line adjacent to the row of buried word lines, it will cause data read and write errors on the column bit line, This phenomenon is called the traveling hammer effect.
  • Embodiments of the present application provide a semiconductor storage device and a forming method to solve the hammer effect problem.
  • the present application provides a semiconductor storage device on the one hand, including:
  • Shallow trench isolation disposed in the substrate, the shallow trench isolation surrounding the plurality of active region structures;
  • a plurality of wire structures extend parallel to each other along a first direction, the wire structure includes a first area and a second area, the first area is located above the active area structure, and the second area is located on the Above shallow trench isolation; in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region.
  • another aspect of the present application provides a method for forming a semiconductor storage device, including:
  • the first etching is performed on the active region structure and the shallow trench isolation to form a plurality of wire trenches extending parallel to each other along the first direction.
  • the active region structure is etched The etch rate is greater than the etch rate of the shallow trench isolation;
  • a wire structure is formed in the plurality of wire trenches, the wire structure includes a first region and a second region, the first region is located above the active region structure, and the second region is located in the shallow trench above the trench isolation; the first zone depth is greater than the second zone depth.
  • the semiconductor storage device in the embodiment of the present application includes a substrate; a plurality of active region structures defined on the substrate; shallow trench isolations disposed in the substrate, and the shallow trench isolation surrounds the plurality of active region structures a plurality of wire structures extending parallel to each other along the first direction, the wire structure includes a first area and a second area, the first area is located above the active area structure, the second area is located above the shallow trench isolation, and is perpendicular to In the direction of the substrate, the depth of the first region is greater than the depth of the second region. In this way, since the depth of the first region is greater than that of the second region, and by making the structures of the active regions disconnected from each other, the problem of the hammer effect can be avoided.
  • FIG. 1 is a schematic structural diagram of a semiconductor storage device in an embodiment of the present application
  • FIG. 2 is a flowchart of a method for forming a semiconductor storage device in an embodiment of the present application
  • FIG. 3 is a first schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 4 is a second schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 5 is a third schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 6 is a fourth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 7 is a fifth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 8 is a sixth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 9 is a seventh schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 10 is an eighth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 11 is a ninth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 12 is a tenth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • FIG. 13 is a schematic diagram of an eleventh structure of a semiconductor storage device in an embodiment of the present application.
  • FIG. 14 is a top view of a semiconductor storage device in an embodiment of the present application.
  • Fig. 15 is a schematic cross-sectional view of AA' in the embodiment of the present application.
  • Fig. 16 is a schematic cross-sectional view of BB' in the embodiment of the present application.
  • Dynamic random access memory (dynamic random access memory, DRAM) is a kind of volatile memory, including an array area composed of a plurality of memory cells and a peripheral area composed of control circuits. Each memory cell includes a transistor electrically connected to a capacitor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data.
  • the control circuit can be positioned to each memory cell to control its data access through word lines and bit lines that span the array area and are electrically connected to each memory cell.
  • a buried wordline (WL) structure is generally used to reduce the size of each storage unit in the DRAM.
  • the buried word line cuts through the passing gate area between the two active areas. During repeated reading and writing, it will generate Accumulated parasitic electrons. When parasitic electrons flow to the source/drain electrically connected to the bit line through the bottom of another buried word line adjacent to the row of buried word lines, it will cause data errors in the column bit line, thereby There is the problem of hammer effect.
  • an embodiment of the present application provides a semiconductor storage device including a substrate, a plurality of active region structures defined on the substrate, and shallow trench isolation disposed in the substrate, the shallow trench The isolation surrounds a plurality of active region structures, and a plurality of conductor structures extend parallel to each other along a first direction.
  • the conductor structure includes a first region and a second region, the first region is located above the active region structure, and the second region is located in the shallow Above the trench isolation, in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region. In this way, data errors between adjacent bit lines can be avoided, thereby avoiding the hammer effect problem.
  • FIG. 1 it is a schematic structural view of a semiconductor storage device in an embodiment of the present application.
  • the semiconductor storage device includes a substrate 10, for example, a semiconductor substrate 10 made of silicon, and then, Based on a plurality of active region structures 11 defined on the substrate 10, that is, the surface of the substrate 10 is connected to the surface of the active region structures 11, and a plurality of active region structures 11 are connected to the upper surface of the substrate 10,
  • the shape of each active region structure 11 is an island-shaped column.
  • Shallow trench isolation 12 is provided in substrate 10, and shallow trench isolation 12 surrounds multiple active region structures 11.
  • Shallow trench isolation 12 is used to isolate multiple active region structures 11, that is, each The active region structures 11 are isolated from each other by the shallow trench isolation 12 , and the active region structures 11 are not connected to each other.
  • the semiconductor storage device includes a plurality of wire structures, the plurality of wire structures extend parallel to each other along the first direction 90, each wire structure includes a first region 20 and a second region 30, the first region 20 is located at the active Above the region structure 11, the second region 30 is located above the shallow trench isolation 12, and the first region 20 and the second region 30 are formed by etching along a direction perpendicular to the substrate 10, and the depth of the first region 20 is greater than Second zone 30 deep.
  • the first region 20 of the wire structure includes a gate structure 21 , insulating sidewalls 24 , a second sub-conductive layer 25 and a third sub-conductive layer 26 .
  • the gate structure 21 is located at the bottom of the first region 20 of the wire structure, and the bottom of the gate structure 21 is connected to the bottom surface of the first region 20;
  • the insulating sidewall 24 is located at the bottom barrier layer 22 of the first region 20 of the wire structure Part of the upper sidewall, the second sub-conductive layer 25 is disposed in the insulating sidewall 24, and the insulating sidewall 24 is disposed around the second sub-conductive layer 25, that is, the insulating sidewall 24 is deposited on the first region 20 of the wire structure.
  • the side wall surface is arranged around the second sub-conductive layer 25 .
  • a preferred implementation mode is provided, and the insulating side wall 24 completely wraps the second sub-conductive layer 25 .
  • the bottom of the second sub-conductive layer 25 is connected to the top surface of the gate structure 21, and the top surface of the second sub-conductive layer 25 and the insulating inner wall are flush with the opening edge of the first region 20; the third sub-conductive layer 26 covers the The insulating sidewall 24 and the second sub-conductive layer 25 are connected to the second region 30 of the wire structure.
  • the gate structure 21 includes a barrier layer 22 and a first sub-conductive layer 23, the barrier layer 22 is located on a part of the sidewall of the bottom of the first region 20 of the wire structure, and the first sub-conductive layer 23 is disposed in the barrier layer 22, that is, , the barrier layer 22 is deposited on part of the sidewall and the bottom surface of the bottom of the first region 20 of the conductor structure, the bottom of the first sub-conductive layer 23 and the bottom surface of the first region 20 of the conductor structure, and is arranged in the barrier layer 22, this A preferred embodiment provided in the application examples is that the barrier layer 22 completely wraps the first sub-conductive layer 23 .
  • the semiconductor storage device further includes a cover layer 40 , and the cover layer 40 fills the inside of the second region 30 and covers the third sub-conductive layer 26 .
  • the barrier layer 22 includes metal nitride, and the insulating sidewall 24 is made of silicon nitride.
  • the material of the first sub-conductive layer 23, the second sub-conductive layer 25 and the third sub-conductive layer 26 is tungsten or polysilicon, the material of the first sub-conductive layer 23, the second sub-conductive layer 25 and the third sub-conductive layer 26 The materials are the same, and of course, the materials of the structures in the embodiments of the present application are not limited.
  • the depth of the first zone 20 and the depth of the second zone 30 can be set by itself, but the depth of the first zone 20 needs to be greater than the depth of the second zone 30, for example, the depth of the first zone 20 is equal to the depth of the second zone 30. 1/2-3/4 of the depth of 30; the height of the gate structure 21 can be set by itself, for example, the height of the gate structure 21 is 1/4 of the depth of the first region 20; the insulating sidewall 24 and the second sub-conductor The height of the layer 25 can be set by itself, for example, the height of the insulating sidewall 24 and the second sub-conductive layer 25 is 1/4 of the depth of the first region 20, and the thickness of the barrier layer 22 is greater than the thickness of the insulating sidewall 24.
  • the barrier layer 22 has a thickness of 3 nm to 5 nm, and the insulating sidewall 24 has a thickness of 5 nm to 10 nm.
  • the depth and thickness in the embodiment of the present application are not limited.
  • an adhesion layer (not shown in the figure) is provided on the third sub-conductive layer 26 , and the adhesion layer is made of titanium nitride.
  • the material of the adhesion layer is not limited in the embodiment of the present application.
  • the semiconductor storage device includes a substrate, a plurality of active region structures defined on the substrate, and shallow trench isolations arranged in the substrate, and the shallow trench isolation surrounds the plurality of active region structures , a plurality of wire structures extending parallel to each other along the first direction, the wire structure includes a first area and a second area, the first area is located above the active area structure, the second area is located above the shallow trench isolation, and is perpendicular to In the direction of the substrate, the depth of the first region is greater than the depth of the second region. In this way, since the depth of the first zone is greater than the depth of the second zone. Therefore, it is possible to prevent the adjacent active region structures from being affected by the bit line structures between the adjacent active region structures in the same direction, thereby weakening the impact of the hammer effect.
  • FIG. 2 it is a flowchart of a method for forming a semiconductor storage device in the embodiment of the present application, which specifically includes:
  • Step 200 Provide a substrate.
  • a substrate is provided.
  • the material of the substrate is silicon, but the material of the substrate is not limited in the embodiment of the present application.
  • Step 210 forming active region structures and shallow trench isolations on the substrate, the shallow trench isolations surrounding the plurality of active region structures.
  • the active region structure is formed on the substrate. After the active region structure is obtained, shallow trench isolation is formed around the active region structure. Therefore, the formed shallow trench isolation surrounds multiple active regions structure.
  • Step 210 in the embodiment of the present application will be described in detail below, specifically including:
  • S1 Form a plurality of fourth mask structures on the substrate along a second direction, and the plurality of fourth mask structures are arranged horizontally.
  • a plurality of fifth mask structures are formed on the substrate, wherein each fifth mask structure extends along the second direction, and the fifth mask structures are arranged horizontally.
  • FIG. 3 it is the first schematic diagram of the semiconductor memory device in the embodiment of the present application.
  • a plurality of fifth mask layer structures 16 are formed on the upper end surface of the substrate 10, and each fifth mask layer structure 16 are horizontally arranged on the substrate 10 along the second direction 91 .
  • the lower surfaces of the plurality of fifth mask structures 16 are connected to the upper surface of the substrate 10 .
  • the third direction is a direction perpendicular to the second direction.
  • FIG. 4 it is a second schematic diagram of the semiconductor storage device in the embodiment of the present application. Since the third direction 92 is a direction perpendicular to the second direction 91, after this etching, a dislocation arrangement can be formed.
  • a fourth mask structure 17 That is, a plurality of fourth mask structures 17 are disposed on the substrate 10 in a dislocation arrangement.
  • the substrate is etched downward along the first direction to form multiple active region structures. That is, in the embodiment of the present application, the substrate portion except for the plurality of fourth mask structures is etched downward along the first direction, thereby forming active region structures, and each active region structure includes a substrate and a fourth mask structure. mask structure, and the fourth mask structure is connected to the top of the substrate.
  • FIG. 5 it is a third schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • a plurality of active region structures 11 are formed along the first direction after forming each fourth mask structure 17 in a dislocation arrangement. 90 is formed by etching the substrate 10 downward. As shown in the figure, the lower half of each active region structure 11 is the substrate 10, the upper half is the fourth mask structure 17, and the upper surface of the substrate 10 is connected to the lower surface of the fourth mask structure 17 .
  • the fourth mask structure 17 does not need to be etched, and only the portion of the substrate 10 where the fourth mask structure 17 is not deposited is etched.
  • the isolation material is filled on the substrate until the isolation material is flush with the upper end surfaces of the active region structures, thereby forming shallow trench isolations surrounding multiple active region structures.
  • FIG. 6 it is a fourth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • an isolation material is filled on the substrate 10 so that the active region structure 11 is completely wrapped in the isolation material, so that Shallow trench isolation 12 is formed.
  • the substrate 10 includes active region structures 11 and shallow trench isolations 12, the upper end surfaces of the shallow trench isolations 12 are flush with the upper end surfaces of the active region structures 11, and the active region structures 11 pass through Shallow trench isolations 12 are isolated from each other.
  • the shallow trench isolation 12 includes silicon oxide, and the material of the shallow trench isolation is not limited in the embodiment of the present application.
  • Step 220 Perform the first etching on the active region structure and the shallow trench isolation to form a plurality of conductive trenches extending parallel to each other along the first direction, the active region in the first etching The etch rate of the structure is greater than the etch rate of the shallow trench isolation.
  • FIG. 7 it is a fifth schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • a plurality of first mask structures 13 are formed above a plurality of active region structures 11 and shallow trench isolations 12, each The first mask structure 13 is horizontally arranged above the active region structure 11 and the shallow trench isolation 12 .
  • the first direction 90 is a vertical direction
  • the active region structure 11 and the shallow trench isolation 12 are etched along the vertical direction, that is, Etching the active region structure 11 and the shallow trench isolation 12 downward along the vertical direction, and the etching rate of the active region structure 11 is greater than the etching rate of the shallow trench isolation 12, thereby forming a structure along the first direction 90 A plurality of extending wire grooves 15 .
  • the width of the first mask structure 13 is the first width
  • the first direction 90 can be, for example, a vertical direction
  • the etching rate of the active region structure 11 and the etching rate of the shallow trench isolation 12 can be set by oneself
  • the depth of the wire trench 15 obtained after etching is 1/2 of the height of the active region structure 11 , but the depth is not limited in this embodiment of the present application.
  • the depth of the wire groove is 1/2 of the height of the active region structure, therefore, the depth of the wire groove obtained by etching is 45nm.
  • the etching rate of the active region structure is higher than the etching rate of the shallow trench isolation.
  • Step 230 Form a wire structure in the plurality of wire trenches, the wire structure includes a first region and a second region, the first region is located above the active region structure, and the second region is located above the active region structure. above the shallow trench isolation; the depth of the first region is greater than the depth of the second region.
  • a wire structure is formed in a plurality of wire trenches, and the generated wire structure includes a first area and a second area, the first area is located above the active area structure, and the second area is located above the shallow trench isolation, The first zone depth is greater than the second zone depth.
  • the wire structure includes a first region and a second region, and the first region of the wire structure includes a gate structure, an insulating sidewall, and a second sub-conductive layer.
  • the steps are described in detail, including:
  • the barrier layer is deposited and formed in the wire structure through a preset deposition method.
  • a barrier layer is deposited throughout the conductive structure.
  • the first sub-conductive layer is deposited and formed in the barrier layer through a preset deposition method.
  • the barrier layer is located on part of the sidewall and the bottom surface of the bottom of the first region of the wire structure, and the first sub-conductive layer is disposed in the barrier layer.
  • the barrier layer is deposited and formed in the wire structure, and the first sub-conductive layer is deposited in the barrier layer to form the first sub-conductive layer, and then, the barrier layer and the first sub-conductive layer are etched downward by a preset etching method , and retain part of the barrier layer and the first sub-conductive layer at the bottom of the first region, thereby forming a gate structure including the barrier layer and the first sub-conductive layer. That is, the gate structure including the barrier layer and the first sub-conductive layer is formed at the bottom of the wire trench.
  • FIG. 9 is a seventh schematic diagram of a semiconductor storage device in an embodiment of the present application.
  • first deposit a barrier layer in the wiring structure and deposit and form the first sub-conductive layer in the barrier layer, etch back the barrier layer and the first sub-conductive layer, so as to form the gate structure as shown in FIG.
  • the barrier layer 22 completely surrounds the first sub-conductive layer 23 to form a gate structure 21 , that is, the gate structure 21 includes the barrier layer 22 and the first sub-conductive layer 23 .
  • the barrier layer includes metal nitride, such as titanium nitride or tantalum nitride, and titanium nitride is widely used as the barrier layer of the tungsten plug.
  • the barrier layer has a thickness of 3nm to 5nm.
  • PVD Physical Vapor Deposition
  • titanium nitride can be deposited using inorganic chemical reagents such as TiCl 4 and NH 3 at a temperature of 400°C to 700°C: 6TiCl 4 +8NH 3 ⁇ 6TiN+24HCl+N 2 , the higher the deposition temperature, the better the TiN film The higher the quality, the lower the chlorine concentration in the film, reducing the corrosive effects of chlorine.
  • inorganic chemical reagents such as TiCl 4 and NH 3 at a temperature of 400°C to 700°C: 6TiCl 4 +8NH 3 ⁇ 6TiN+24HCl+N 2
  • the material of the first sub-conductive layer includes but not limited to metal or metal alloy, for example, tungsten, aluminum, copper and their alloys, etc., which is not limited in the embodiment of the present application.
  • the first direction is a vertical direction.
  • the first region of the wire structure further includes an insulating sidewall and a second sub-conductive layer.
  • the steps of forming the insulating sidewall and the second sub-conductive layer in the embodiment of the present application are described in detail below, specifically including:
  • an insulating material is deposited in the wire structure through a preset deposition method.
  • the insulating material is etched back, and the insulating material fills the trench above the gate structure.
  • the insulating material may completely fill the trench above the gate structure, or partially fill the trench above the gate structure, which is not limited in this embodiment of the present application.
  • S3 Forming a plurality of second mask structures along a first direction above the insulating material, the width of the second mask structures is a second width, and the second width is smaller than the first width.
  • a plurality of second mask structures are formed above the insulating material along the first direction.
  • the second mask structure is used to form the insulating sidewall, and the width of the second mask structure is the second width, and the second width is smaller than the first width, so that the width of the formed insulating sidewall is larger than the width of the barrier layer.
  • S4 Etching the insulating material according to the second mask structure to form insulating sidewalls above the barrier layer in the first region.
  • the insulating material is etched along the first direction to form the insulating sidewall above the bottom barrier layer of the first region, so that the insulating material is wrapped around the first region of the wiring structure. A portion of the sidewall surface above the bottom barrier layer.
  • the material of the insulating sidewall can be silicon nitride, for example, the thickness of the insulating sidewall is greater than the thickness of the barrier layer, and the thickness of the insulating sidewall is 5nm to 10nm.
  • the insulating material it can be deposited by CVD or PVD. This is not limited in the application embodiments.
  • the second sub-conductive layer is disposed in the insulating side wall, and the insulating side wall surrounds the second sub-conductive layer.
  • the insulating sidewalls and the first region of the conducting structure form a hollow structure, and then fill the formed hollow structure with the second Sub-conductive layer, so that the second sub-conductive layer completely fills the first region of the wire structure, as shown in FIG.
  • the side wall 24 is filled with the second sub-conductive layer 25 in the insulating side wall 24 and the first region 20.
  • the second sub-conductive layer 25 is arranged in the insulating side wall 24, and the insulating side wall 24 surrounds the second sub-conductive layer 25 .
  • the second sub-conductive layer 25 when the second sub-conductive layer 25 is filled inside the insulating sidewall 24, the second sub-conductive layer 25 completely fills the first region 20, and also That is, when filling, the second sub-conductive layer 25 is flush with the edge of the opening of the first region 20 .
  • the material of the second sub-conductive layer includes but not limited to metal or metal alloy, for example, tungsten, aluminum, copper and alloys thereof, etc., which are not limited in the embodiments of the application.
  • the silicon, silicon oxide, and silicon nitride etching gases in the embodiments of the present application can use SF6/CF4/Cl2/CHF3/O2/Ar or a mixed gas to achieve a certain selectivity;
  • the material of the insulating sidewall is silicon nitride, nitride
  • the method of silicon sidewall deposition can be deposited by ALD, and the ALD reaction gas can be NH3 or N2/H2 mixed reaction gas;
  • the material of the barrier layer is titanium nitride;
  • the material of the cover layer is silicon nitride, and silicon nitride can be LPCVD or reaction
  • the gas can be SiH4 or SiH2Cl2;
  • the material of the isolation layer is silicon oxide, ALD can be used for silicon oxide deposition, and the reaction gas can be LTO520/O2 or N zero/O2.
  • the material of the barrier layer is titanium nitride, and may also be titanium, tantalum, tantalum nitride, tungsten nitride, etc. or a combination thereof, but is not limited thereto.
  • the material of the first sub-conductive layer, the second sub-conductive layer and the third sub-conductive layer are the same.
  • the material of the first sub-conductive layer, the second sub-conductive layer and the third sub-conductive layer may be aluminum, copper, gold, work function metal or low-resistance metal, but not limited thereto.
  • the depth of the first region is 1/2-3/4 of the depth of the second region
  • the height of the gate structure is 1/4 of the depth of the first region
  • the insulating sidewall and the second sub-region The height of the conductive layer is 1/4 of the depth of the first region, but not limited thereto.
  • a fourth sub-conductive layer is deposited on the insulating sidewall and the second sub-conductive layer, and the fourth sub-conductive layer fills the wire trench.
  • the fourth sub-conductive layer is deposited and formed above the insulating sidewall and the second sub-conductive layer, that is, the wire groove is filled with the fourth sub-conductive layer, so that the third sub-conductive layer and the second sub-conductive layer
  • the second sub-conductive layers are connected to each other.
  • FIG. 11 which is a ninth schematic diagram of a semiconductor storage device in an embodiment of the present application
  • the third sub-conductive layer 26 is filled so that the third sub-conductive layer 26 completely fills the wire trench 15 .
  • the fourth sub-conductive layer in order to reduce the interference between word lines, can be etched after obtaining the exposed sub-conductive layer, so that the width of the fourth sub-conductive layer is reduced, exposing the insulating side below The wall and the second sub-conductive layer, and the second sub-conductive layer and the fourth sub-conductive layer are connected in series to obtain the third sub-conductive layer, which specifically includes:
  • S1 Forming a plurality of third mask structures along a first direction above the fourth sub-conductive layer, the width of the third mask structures being smaller than the second width.
  • a plurality of third mask structures along the first direction are formed above the fourth sub-conductive layer along the first direction, and the plurality of third mask structures are used to form the third sub-conductive layer.
  • FIG. 12 is a tenth schematic diagram of a semiconductor storage device in the embodiment of the present application
  • the active region structure is etched downward along the first direction 90 11 and shallow trench isolation 12, that is, to etch the dielectric layer in the active region structure 11, when the upper surface of the active region structure 11 and shallow trench isolation 12 is flush with the upper surface of the fourth sub-conductive layer 26, obtain
  • a plurality of third mask structures are formed on the fourth sub-conductive layer 26 .
  • the width of the third mask structure is smaller than the second width.
  • S2 Etching the fourth sub-conductive layer according to the third mask structure to form a third sub-conductive layer, where the width of the third sub-conductive layer is smaller than or equal to the width of the third mask structure.
  • the fourth sub-conductive layer is etched according to the third mask structure to form the third sub-conductive layer.
  • the fourth sub-conductive layer is etched according to the third mask structure (not shown in the figure), so that the fourth sub-conductive layer The width of the sub-conductive layer is reduced, thereby forming the third sub-conductive layer 27 .
  • the fourth sub-conductive layer is etched to reduce the width of the fourth sub-conductive layer to form the third sub-conductive layer, thereby reducing the interference between the word lines.
  • the following is a schematic description of the top view of the semiconductor storage device in the embodiment of the present application. Referring to FIG. The conductive layer 25 and the third sub-conductive layer 27 , wherein the second sub-conductive layer 25 and the third sub-conductive layer 27 are connected.
  • a shallow trench isolation 12 is defined on the substrate 10, the first region includes a gate structure 21, an insulating sidewall 24 and a second sub-conductive layer 25, and the gate structure 21 includes a barrier layer 22 and a first sub-conductive layer.
  • a third sub-conductive layer 27 is disposed on the layer 23 , the insulating sidewall 24 and the second sub-conductive layer 25 .
  • the cut section in the BB' direction is obtained.
  • the BB' cross section of the semiconductor storage device in the embodiment of the present application is schematically described below.
  • the first region of the wire structure is composed of gate structure 21, insulating sidewall 24 and second sub-conductive layer 25
  • gate structure 21 is composed of barrier layer 22 and first sub-conductive layer 23
  • a third sub-conductive layer 27 is disposed on the second sub-conductive layer 25 .
  • a covering layer is deposited on the active region structure, the shallow trench isolation, and the third sub-conductive layer. That is, the active region structure, the shallow trench isolation and the third sub-conductive layer are completely covered. For example, as shown in FIG. 1 , the active region structure 11 , the shallow trench isolation 12 and the third sub-conductive layer 27 are completely covered by the capping layer.
  • a substrate is provided; an active region structure and shallow trench isolation are formed on the substrate, and the shallow trench isolation surrounds a plurality of active region structures;
  • the first etching forms a plurality of wire grooves extending parallel to each other along the first direction, and the etching rate of the active region structure in the first etching is greater than the etching rate of the shallow trench isolation;
  • Conductive material is filled into the wire trench to form a wire structure.
  • the wire structure includes a first area and a second area. The first area is located above the active area structure, and the second area is located above the shallow trench isolation; the depth of the first area is greater than that of the second area. zone depth.
  • the etching depth of the first region is greater than the etching depth of the second region, the first regions can be isolated from each other through shallow trench isolation. Therefore, when the problem of charge loss or leakage occurs, Data errors of one or more units in adjacent rows can be avoided, and the impact of the row hammer effect is weakened.

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Abstract

本申请实施例涉及半导体技术领域，尤其涉及一种半导体存储装置及形成方法，半导体存储装置包括衬底；多个有源区结构，定义在所述衬底上；浅沟槽隔离，设置于该衬底内，该浅沟槽隔离环绕所述多个有源区结构；多个导线结构，相互平行地沿着第一方向延伸，所述导线结构包括第一区和第二区，所述第一区位于所述有源区结构上方，所述第二区位于所述浅沟槽隔离上方；在垂直于所述衬底的方向上，所述第一区深度大于所述第二区深度。

Description

一种半导体存储装置及形成方法
相关申请的交叉引用
本申请要求在2021年08月05日提交中国专利局、申请号为202110894701.4、申请名称为“一种半导体存储装置及形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，涉及但不限于一种半导体存储装置及形成方法。
背景技术
随着动态随机存取存储器(dynamic random access memory，DRAM)制备工艺的发展，为了使得DRAM具有更高的密集度，从而缩小DRAM中各存储单元的尺寸，通常使用埋入式字线(buried word line)结构。
然而，现有的沟槽式栅极仍存在一些问题。当存储器的尺寸持续微缩，埋入式字线(buried word line)切过两主动区之间的通过栅极(passing gate)区域，在重复性读写时，会在两侧的主动区中产生累积的寄生电子。当寄生电子通过与该行埋入式字符线相邻的另一埋入式字线底部而流至与一位线电连接的源/漏极时，会造成该列位线数据读写错误，此现象称为行锤效应。
发明内容
本申请实施例提供一种半导体存储装置及形成方法，以解决行锤效应问题。
根据一些实施例，本申请一方面提供了一种半导体存储装置，包括：
衬底；
多个有源区结构，定义在所述衬底上；
浅沟槽隔离，设置于该衬底内，该浅沟槽隔离环绕所述多个有源区结构；
多个导线结构，相互平行地沿着第一方向延伸，所述导线结构包括第一区和第二区，所述第一区位于所述有源区结构上方，所述第二区位于所述浅沟槽隔离上方；在垂直于所述衬底的方向上，所述第一区深度大于所述第二区深度。
根据一些实施例，本申请另一方面提供了一种半导体存储装置的形成方法，包括：
提供一衬底；
在所述衬底上形成有源区结构和浅沟槽隔离，该浅沟槽隔离环绕所述多个有源区结构；
对所述有源区结构和浅沟槽隔离进行第一次刻蚀，形成相互平行地沿着第一方向延伸的多个导线沟槽，所述第一次刻蚀中有源区结构的刻蚀速率大于浅沟槽隔离的刻蚀速率；
在所述多条导线沟槽中形成导线结构，所述导线结构包括第一区和第二区，所述第一区位于所述有源区结构上方，所述第二区位于所述浅沟槽隔离上方；所述第一区深度大于所述第二区深度。
本申请实施例中的半导体存储装置包括衬底；多个有源区结构，定义在衬底上；浅沟槽隔离，设置于该衬底内，该浅沟槽隔离环绕多个有源区结构；多个导线结构，相互平行地沿着第一方向延伸，导线结构包括第一区和第二区，第一区位于有源区结构上方，第二区位于浅沟槽隔离上方，在垂直于衬底的方向上，第一区深度大于第二区深度。这样，由于第一区的深度大于第二区的深度，并通过能够使得各有源区结构之间相互不连接，因此，能够避免出现行锤效应问题。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅 仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中一种半导体存储装置的结构示意图；
图2为本申请实施例中一种半导体存储装置的形成方法的流程图；
图3为本申请实施例中半导体存储装置的第一示意图；
图4为本申请实施例中半导体存储装置的第二示意图；
图5为本申请实施例中半导体存储装置的第三示意图；
图6为本申请实施例中半导体存储装置的第四示意图；
图7为本申请实施例中半导体存储装置的第五示意图；
图8为本申请实施例中半导体存储装置的第六示意图；
图9为本申请实施例中半导体存储装置的第七示意图；
图10为本申请实施例中半导体存储装置的第八示意图；
图11为本申请实施例中半导体存储装置的第九示意图；
图12为本申请实施例中半导体存储装置的第十示意图；
图13为本申请实施例中半导体存储装置的第十一结构示意图；
图14为本申请实施例中的半导体存储装置的俯视图；
图15为本申请实施例中AA’截面示意图；
图16为本申请实施例中BB’截面示意图。
主要元件符号说明
10  衬底
11  有源区结构
12  浅沟槽隔离
13  第一掩膜结构
14  第三掩膜结构
15  导线沟槽
16  第五掩膜结构
17  第四掩膜结构
20  第一区
21  栅极结构
22  阻挡层
23  第一子导电层
24  绝缘侧壁
25  第二子导电层
26  第三子导电层
27  第四子导电层
30  第二区
40  覆盖层
90  第一方向
91  第二方向
92  第三方向
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，并不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
动态随机存取存储器(dynamic random access memory，DRAM)属于一种挥发性存储器，包含由多个存储单元构成的阵列区以及由控制电路构成的周边区。各存储单元包含一晶体管电连接至一电容器，由该晶体管控制该电容器中电荷的存储或释放来达到存储数据的目的。控制电路通过横跨阵列区并与各存储单元电连接的字符线与位线，可定位至每一存储单元以控制其数据的存取。
相关技术中，为了能够使得DRAM具有更高的密集度，一般会使用埋入式(buried wordline，WL)结构，从而缩小DRAM中各存储单元的尺寸。
然而，相关技术中的沟槽式栅极仍存在一些问题。当存储器的尺寸持续微缩，埋入式字线(buried word line)切过两主动区之间的通过栅极(passing gate)区域，在重复性读写时，会在两侧的主动区中产生累积的寄生电子。当寄生电子通过与该行埋入式字符线相邻的另一埋入式字线底部而流至与一位线电连接的源/漏极时，会造成该列位线数据发生错误，从而出现行锤效应问题。
为了解决上述问题，本申请实施例中提供了一种半导体存储装置包括衬底，多个有源区结构，定义在衬底上，浅沟槽隔离，设置于该衬底内，该浅沟槽隔离环绕多个有源区结构，多个导线结构，相互平行地沿着第一方向延伸，导线结构包括第一区和第二区，第一区位于有源区结构上方，第二区位于浅沟槽隔离上方，在垂直于衬底的方向上，第一区深度大于第二区深度。这样，能够避免邻近位线之间发生数据错误，从而避免出现行锤效应问题。
基于上述实施例，参阅图1所示，为本申请实施例中一种半导体存储装置的结构示意图，该半导体存储装置包含一衬底10，例如，由硅所构成的半导体衬底10，然后，基于衬底10上定义有多个有源区结构11，也即，衬底10的表面与有源区结构11的表面连接，在衬底10的上表面连接有多个有源区结构11，每个有源区结构11的形状为岛状柱体。在衬底10内设置有浅沟槽隔离12，该浅沟槽隔离12环绕多个有源区结构11，浅沟槽隔离12用于将多个有源区结构11隔离，也即，每个有源区结构11之间通过浅沟槽隔离12相互隔离，各有源区结构11之间相互不连接。此外，该半导体存储装置包含有多个导线结构，多个导线结构相互平行地沿着第一方向90延伸，每一导线结构包括第一区20和第二区30，第一区20位于有源区结构11上方，第二区30位于浅沟槽隔离12上方，并且，第一区20和第二区30为沿着垂直于衬底10的方向上刻蚀形成的，第一区20深度大于第二区30深度。
本申请实施例中，导线结构的第一区20包括栅极结构21、绝缘侧壁24、第二子导电层25和第三子导电层26。其中，栅极结构21位于导线结构的第一区20的底部，且栅极结构21的底部与第一区20的底部表面连接；绝缘侧壁24位于导线结构第一区20的底部阻挡层22上方的部分侧壁，第二子导电 层25设置于绝缘侧壁24内，绝缘侧壁24环绕第二子导电层25设置，也即，绝缘侧壁24沉积于导线结构的第一区20的侧壁表面，且环绕第二子导电层25设置，本申请实施例中提供了一种优选的实施方式，绝缘侧壁24将第二子导电层25完全包裹。第二子导电层25的底部与栅极结构21的顶部表面连接，且第二子导电层25与绝缘内壁的顶部表面与第一区20的开口边缘齐平；第三子导电层26覆盖在绝缘侧壁24和第二子导电层25上，与导线结构的第二区30连接。
其中，栅极结构21包括阻挡层22和第一子导电层23，阻挡层22位于导线结构第一区20的底部的部分侧壁，第一子导电层23设置于阻挡层22内，也即，阻挡层22沉积于导线结构第一区20的底部的部分侧壁和底表面，第一子导电层23的底部与导线结构第一区20的底部表面，且设置于阻挡层22内，本申请实施例中提供了一种优选的实施方式为，阻挡层22将第一子导电层23完全包裹。
此外，本申请实施例中，半导体存储装置还包括覆盖层40，覆盖层40填充于第二区30的内部，并覆盖在第三子导电层26上。
需要说明的是，本申请实施例中阻挡层22包括金属氮化物，绝缘侧壁24的材质为氮化硅。第一子导电层23、第二子导电层25和第三子导电层26的材质为钨或多晶硅，第一子导电层23的材质、第二子导电层25和第三子导电层26的材质相同，当然，并不对本申请实施例中各结构的材质进行限定。
还需要说明的是，第一区20深度和第二区30的深度可以自行设定，但第一区20的深度需大于第二区30的深度，例如，第一区20深度为第二区30深度的1/2-3/4；栅极结构21的高度可以自行设定，例如，栅极结构21的高度为第一区20深度的1/4；绝缘侧壁24和第二子导电层25的高度可以自行设定，例如，绝缘侧壁24和第二子导电层25的高度为第一区20深度的1/4，阻挡层22的厚度大于绝缘侧壁24的厚度。阻挡层22的厚度为3nm至5nm，绝缘侧壁24的厚度为5nm至10nm，当然，并不对本申请实施例中的深度和厚度进行限定。
本申请实施例中，在第三子导电层26上设有附着层(图未示出)，附着层包括为氮化钛，本申请实施例中对附着层的材质并不进行限定。
本申请实施例中，半导体存储装置包括衬底，多个有源区结构，定义在衬底上，浅沟槽隔离，设置于该衬底内，该浅沟槽隔离环绕多个有源区结构，多个导线结构，相互平行地沿着第一方向延伸，导线结构包括第一区和第二区，第一区位于有源区结构上方，第二区位于浅沟槽隔离上方，在垂直于衬底的方向上，第一区深度大于第二区深度。这样，由于第一区的深度大于第二区的深度。因此，能够避免同一方向相邻的有源区结构之间的位线结构通电时影响邻近的有源区结构，从而减弱了行锤效应的影响。
基于上述实施例，下面对本申请实施例中提供的半导体存储装置的形成方法进行详细阐述，参阅图2所示，为本申请实施例中一种半导体存储装置的形成方法的流程图，具体包括：
步骤200：提供一衬底。
本申请实施例中，提供一衬底。
其中，衬底的材质为硅，但本申请实施例中对于衬底的材质并不进行限制。
步骤210：在所述衬底上形成有源区结构和浅沟槽隔离，该浅沟槽隔离环绕所述多个有源区结构。
本申请实施例中，在衬底上形成有源区结构，在获得有源区结构之后，在围绕有源区结构形成浅沟槽隔离，因此，形成的浅沟槽隔离围绕多个有源区结构。
本申请实施例中，对形成有源区结构和浅沟槽隔离提供了一种可能的实施方式，下面对本申请实施例中的步骤210进行详细阐述，具体包括：
S1：在衬底上沿第二方向形成多个第四掩膜结构，所述多个第四掩膜结构水平排列。
本申请实施例中，首先，在衬底之上形成多个第五掩膜结构，其中每个第五掩膜结构沿第二方向延伸，且各第五掩膜结构之间呈水平排列。参阅图3 所示，为本申请实施例中半导体存储装置的第一示意图，具体实施时，在衬底10上端面形成多个第五掩膜层结构16，且每个第五掩膜层结构16均沿第二方向91水平排列在衬底10上。
多个第五掩膜结构16的下表面与衬底10的上表面连接。
然后，沿第三方向刻蚀多个第五掩膜结构，从而形成多个第四掩膜结构，各第四掩膜结构之间错位排列。其中，第三方向为与第二方向垂直的方向。参阅图4所示，为本申请实施例中半导体存储装置的第二示意图，由于第三方向92为与第二方向91垂直的方向，因此，在经过本次刻蚀后，能够形成错位排列的第四掩膜结构17。也即，多个第四掩膜结构17错位排列设于衬底10上。
S2：沿第一方向，向下刻蚀衬底，形成多个有源区结构。
本申请实施例中，沿第一方向，向下刻蚀衬底，以形成多个有源区结构。也即，本申请实施例中，沿第一方向向下刻蚀除多个第四掩膜结构以外的衬底部分，从而形成有源区结构，每个有源区结构包括衬底和第四掩膜结构，且第四掩膜结构与衬底的顶部连接。参阅图5所示，为本申请实施例中半导体存储装置的第三示意图，具体实施时，多个有源区结构11为在形成错位排列的各第四掩膜结构17之后，沿第一方向90向下刻蚀衬底10从而形成的。如图所示，每个有源区结构11的下半部分为衬底10，上半部分为第四掩膜结构17，且衬底10的上表面与第四掩膜结构17的下表面连接。
在本次刻蚀过程中，无需对第四掩膜结构17进行刻蚀，仅对未沉积有第四掩膜结构17的衬底10的部分进行刻蚀。
S3：环绕多个有源区结构形成浅沟槽隔离。
本申请实施例中，在衬底之上填充隔离材料，直至隔离材料与有源区结构的上端面齐平，从而形成环绕多个有源区结构的浅沟槽隔离。参阅图6所示，为本申请实施例中半导体存储装置的第四示意图，具体实施时，在衬底10之上填充隔离材料，以使有源区结构11被完全包裹在隔离材料内，以形成浅沟槽隔离12。如图所示，衬底10包括有源区结构11和浅沟槽隔离12，浅 沟槽隔离12的上端面与有源区结构11的上端面齐平，各有源区结构11之间通过浅沟槽隔离12相互隔离。
其中，浅沟槽隔离12包括氧化硅，本申请实施例中对与浅沟槽隔离的材质并不进行限制。
步骤220：对所述有源区结构和浅沟槽隔离进行第一次刻蚀，形成相互平行地沿着第一方向延伸的多个导线沟槽，所述第一次刻蚀中有源区结构的刻蚀速率大于浅沟槽隔离的刻蚀速率。
本申请实施例中，首先，在有源区结构和浅沟槽隔离上方沿第一方向形成多个第一掩膜结构，然后，根据第一掩膜结构对有源区结构和浅沟槽隔离进行刻蚀，从而形成相互平行地沿着第一方向延伸的多个导线沟槽。参阅图7所示，为本申请实施例中半导体存储装置的第五示意图，具体实施时，在多个有源区结构11和浅沟槽隔离12上方形成多个第一掩膜结构13，各第一掩膜结构13为水平排列在有源区结构11与浅沟槽隔离12上方。参阅图8所示，为本申请实施例中半导体存储装置的第六示意图，第一方向90为垂直方向，沿垂直方向对有源区结构11和浅沟槽隔离12进行刻蚀，也即，沿垂直方向向下刻蚀有源区结构11和浅沟槽隔离12，且对有源区结构11的刻蚀速率大于对浅沟槽隔离12的刻蚀速率，从而形成沿着第一方向90延伸的多个导线沟槽15。
其中，第一掩膜结构13的宽度为第一宽度，第一方向90例如可以为垂直方向，对有源区结构11的刻蚀速率和对浅沟槽隔离12的刻蚀速率可自行设定，例如，通过刻蚀后获得的导线沟槽15的深度为有源区结构11的高度的1/2，但本申请实施例中对深度并不进行限制。
例如，假设有源区结构的高度为90nm，导线沟槽的深度为有源区结构的高度的1/2，因此，刻蚀获得的导线沟槽的深度为45nm。
本申请实施例中，在进行第一次刻蚀时，对有源区结构的刻蚀速率大于对浅沟槽隔离的刻蚀速率。
步骤230：在所述多条导线沟槽中形成导线结构，所述导线结构包括第一 区和第二区，所述第一区位于所述有源区结构上方，所述第二区位于所述浅沟槽隔离上方；所述第一区深度大于所述第二区深度。
本申请实施例中，在多条导线沟槽中形成导线结构，生成的导线结构包括第一区和第二区，第一区位于有源区结构上方，第二区位于浅沟槽隔离上方，第一区深度大于所述第二区深度。
例如，本申请实施例中导线结构包括第一区和第二区，导线结构的第一区包括栅极结构、绝缘侧壁和第二子导电层，下面对本申请实施例中形成栅极结构的步骤进行详细阐述，具体包括：
S1：在所述导线结构侧壁上沉积形成阻挡层。
本申请实施例中，通过预设的沉积方式，在导线结构内沉积形成阻挡层。
例如，在整个导线结构内均沉积形成阻挡层。
S2：在所述阻挡层内沉积形成第一子导电层。
本申请实施例中，通过预设的沉积方式，在阻挡层内沉积形成第一子导电层。
S3：回刻蚀所述阻挡层和第一子导电层，保留位于第一区底部的部分所述阻挡层和所述第一子导电层，形成栅极结构。
其中，所述阻挡层位于所述导线结构第一区的底部的部分侧壁和底表面，所述第一子导电层设置于所述阻挡层内。
本申请实施例中，在导线结构内沉积形成阻挡层，并在阻挡层内沉积形成第一子导电层，然后，通过预设的刻蚀方式，向下刻蚀阻挡层和第一子导电层，并保留第一区底部的部分阻挡层和第一子导电层，从而形成包含有阻挡层和第一子导电层的栅极结构。也即，在导线沟槽的底部形成包含有阻挡层和第一子导电层的栅极结构。
例如，参阅图9所示，为本申请实施例中半导体存储装置的第七示意图，先在导线结构内沉积阻挡层，并在阻挡层内沉积形成第一子导电层，回刻蚀阻挡层和第一子导电层，从而形成如图9所述的栅极结构，在第一区20的底部的部分侧壁上设有阻挡层22，第一子导电层23设置于阻挡层22内，且阻 挡层22将第一子导电层23完全环绕，从而形成栅极结构21，也即，栅极结构21包括阻挡层22和第一子导电层23。
其中，阻挡层包括金属氮化物，例如可以为氮化钛或氮化钽，氮化钛被广泛作为钨栓塞的阻挡层。阻挡层的厚度为3nm至5nm。
当沉积形成阻挡层时，可以使用化学气相沉积(Chemical VaporDeposition，CVD)或物理气相沉积(Physical Vapour Deposition，PVD)。本申请实施例中的一种优选的实施方式为，使用PVD沉积形成阻挡层，这是因为，PVD沉积形成的氮化钛的薄膜的质量较高。
其中，氮化钛可以利用如TiCl 4及NH 3的无机化学试剂在400℃至700℃的温度下沉积：6TiCl 4+8NH 3→6TiN+24HCl+N 2，沉积的温度越高，TiN薄膜的质量就越高，而且薄膜中的氯浓度也就越低，能够降低氯的腐蚀影响。
其中，第一子导电层的材质包括但不限于金属或金属合金，例如，钨、铝、铜及其合金等，本申请实施例中对此并不进行限制。
其中，第一方向为垂直方向。
本申请实施例中，导线结构的第一区还包括绝缘侧壁和第二子导电层，下面对本申请实施例中形成绝缘侧壁和第二子导电层的步骤进行详细阐述，具体包括：
S1：形成所述栅极结构后，沉积绝缘材料。
本申请实施例中，在形成栅极结构后，通过预设的沉积方式，在导线结构内沉积绝缘材料。
S2：回刻蚀所述绝缘材料以填充所述栅极结构上方沟槽。
本申请实施例中，回刻蚀绝缘材料，绝缘材料将栅极结构上方沟槽填充。
绝缘材料可以将第栅极结构上方沟槽完全填充，也可以将栅极结构上方沟槽部分填充，本申请实施例中对此并不进行限制。
S3：在所述绝缘材料上方沿第一方向形成多个第二掩膜结构，所述第二掩膜结构宽度为第二宽度，所述第二宽度小于第一宽度。
本申请实施例中，沿第一方向，在绝缘材料上方形成多个第二掩膜结构。
其中，第二掩膜结构用于形成绝缘侧壁，第二掩膜结构的宽度为第二宽度，第二宽度小于第一宽度，从而形成的绝缘侧壁的宽度大于阻挡层的宽度。
S4：根据所述第二掩膜结构对绝缘材料进行刻蚀，形成位于所述第一区阻挡层上方的绝缘侧壁。
本申请实施例中，根据第二掩膜结构，沿第一方向刻蚀绝缘材料，以形成位于第一区的底部阻挡层上方的绝缘侧壁，从而使得绝缘材料包裹在导线结构第一区的位于底部阻挡层上方的部分侧壁表面。
其中，绝缘侧壁的材质例如可以为氮化硅，绝缘侧壁的厚度大于阻挡层的厚度，绝缘侧壁的厚度为5nm至10nm，当沉积形成绝缘材料时，可以使用CVD或PVD沉积，本申请实施例中对此并不进行限制。
S3：在所述绝缘侧壁内填充第二子导电层。
其中，所述第二子导电层设置于所述绝缘侧壁内，所述绝缘侧壁环绕所述第二子导电层。
本申请实施例中，当在导线结构第一区的侧壁上沉积形成绝缘侧壁之后，此时绝缘侧壁与导线结构第一区构成中空结构，然后，在形成的中空结构内填充第二子导电层，以使第二子导电层将导线结构第一区完全填充，参阅图10所示，为本申请实施例中半导体存储装置的第八示意图，在第一区20内上沉积形成绝缘侧壁24，在绝缘侧壁24与第一区20内填充第二子导电层25，此时第二子导电层25设置与绝缘侧壁24内，绝缘侧壁24环绕第二子导电层25。需要说明的是，本申请实施例中的一种优选的实施方式为，在绝缘侧壁24的内部填充第二子导电层25时，第二子导电层25将第一区20完全填充，也即，在填充时，使得第二子导电层25与第一区20的开口边缘齐平。
其中，第二子导电层的材料包括但不限于金属或金属合金，例如，钨、铝、铜及其合金等，申请实施例中对此并不进行限制。
本申请实施例中的硅、氧化硅、氮化硅蚀刻气体可用SF6/CF4/Cl2/CHF3/O2/Ar或混合气体以达到一定的选择比；绝缘侧壁的材质为氮化硅，氮化硅侧壁沉积的方式可以使用ALD沉积，ALD反应气体可为NH3或 N2/H2混合反应气体；阻挡层的材质为氮化钛；覆盖层的材质为氮化硅，氮化硅可用LPCVD或反应气体可为SiH4或SiH2Cl2；隔离层的材质为氧化硅，氧化硅沉积可使用ALD，反应气体可以为LTO520/O2或者N zero/O2。
其中，阻挡层的材质为氮化钛，还可以为钛、钽、氮化钽、氮化钨等或其组合，但不限于此。所述第一子导电层的材质、所述第二子导电层和所述第三子导电层的材质相同。第一子导电层、第二子导电层和第三子导电层的材料哈可以为铝、铜、金、功函数金属或低阻值金属等材料，但不限于此。
所述第一区深度为所述第二区深度的1/2-3/4，所述栅极结构的高度为所述第一区深度的1/4，所述绝缘侧壁和第二子导电层的高度为所述第一区深度的1/4，但并不仅限于此。
本申请实施例中，在多条导线沟槽中形成导线结构时，还包括：
在所述绝缘侧壁和第二子导电层上沉积第四子导电层，所述第四子导电层填充所述导线沟槽。
本申请实施例中，在绝缘侧壁的上方和第二子导电层的上方沉积形成第四子导电层，也即，通过第四子导电层填充导线沟槽，以使第三子导电层与第二子导电层之间相互连接。例如，参阅图11所示，为本申请实施例中半导体存储装置的第九示意图，填充第三子导电层26，以使第三子导电层26将导线沟槽15完全填充。
本申请实施例中，为了减少字线之间的干扰，可在获得裸露的子导电层之后，对第四子导电层进行刻蚀，使得第四子导电层的宽度降低，露出下面的绝缘侧壁和第二子导电层，且将第二子导电层与第四子导电层串联起来，从而获得第三子导电层，具体包括：
S1：在所述第四子导电层上方形成沿第一方向形成多个第三掩膜结构，所述第三掩膜结构宽度小于第二宽度。
本申请实施例中，沿第一方向，在第四子导电层上方形成沿第一方向的多个第三掩膜结构，多个第三掩膜结构用于形成第三子导电层。
例如，参阅图12所示，为本申请实施例中半导体存储装置的第十示意图， 当第四子导电层26将导线沟槽完全填充之后，沿第一方向90向下刻蚀有源区结构11和浅沟槽隔离12，也即刻蚀有源区结构11内的介质层，当有源区结构11和浅沟槽隔离12的上表面与第四子导电层26的上表面齐平时，获得如图12所述的半导体存储装置，并在第四子导电层26上方形成的多个第三掩膜结构(图中未示出)。
其中，第三掩膜结构宽度小于第二宽度。
S2：根据所述第三掩膜结构对所述第四子导电层进行刻蚀，形成第三子导电层，所述第三子导电层的宽度小于或等于所述第三掩膜结构宽度。
本申请实施例中，根据第三掩膜结构对第四子导电层进行刻蚀，以形成第三子导电层。
例如，参阅图13所示，为本申请实施例中半导体存储装置的第十一结构示意图，根据第三掩膜结构(图中未示出)对第四子导电层进行刻蚀，使得第四子导电层的宽度降低，从而形成第三子导电层27。这样，对第四子导电层进行刻蚀，以使第四子导电层的宽度降低，形成第三子导电层，从而能够降低字线之间的干扰。
下面对本申请实施例中半导体存储装置的俯视图进行示意性说明，参阅图14所示，为本申请实施例中的半导体存储装置的俯视图，包括有源区结构11、绝缘侧壁24、第二子导电层25和第三子导电层27，其中，第二子导电层25和第三子导电层27连接。
沿图16中的AA’方向，获得AA’方向的切截面，下面对本申请实施例中半导体存储装置的AA’截面进行示意性说明，参阅图15所示，为本申请实施例中AA’截面示意图，在衬底10上定义有浅沟槽隔离12，第一区内包括栅极结构21、绝缘侧壁24和第二子导电层25，栅极结构21包括阻挡层22和第一子导电层23，绝缘侧壁24和第二子导电层25上设有第三子导电层27。
沿图16中的BB’方向，获得BB’方向的切截面，下面对本申请实施例中半导体存储装置的BB’截面进行示意性说明，参阅图16所示，为本申请实施例中BB’截面示意图，在导线结构第一区由栅极结构21、绝缘侧壁24和第二 子导电层25组成，栅极结构21由阻挡层22和第一子导电层23组成，绝缘侧壁24和第二子导电层25上设有第三子导电层27。
当形成第三子导电层后，在所述有源区结构、所述浅沟槽隔离，以及第三子导电层上沉积形成覆盖层。也即，使得有源区结构、浅沟槽隔离和第三子导电层被完全覆盖。例如，如图1所示，有源区结构11、浅沟槽隔离12和第三子导电层27被覆盖层完全覆盖。
本申请实施例中，提供一衬底；在衬底上形成有源区结构和浅沟槽隔离，该浅沟槽隔离环绕多个有源区结构；对有源区结构和浅沟槽隔离进行第一次刻蚀，形成相互平行地沿着第一方向延伸的多个导线沟槽，第一次刻蚀中有源区结构的刻蚀速率大于浅沟槽隔离的刻蚀速率；在多条导线沟槽中填入导电材料形成导线结构，导线结构包括第一区和第二区，第一区位于有源区结构上方，第二区位于浅沟槽隔离上方；第一区深度大于第二区深度。这样，由于第一区的刻蚀深度大于第二区的刻蚀深度，因此，可以使得各第一区之间通过浅沟槽隔离相互不连通，因此，当出现电荷损失或漏电的问题时，能够避免邻近行内的一个或多个单元的数据发生错误，减弱了行锤效应的影响。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (20)

  1. 一种半导体存储装置，包括：
    衬底；
    多个有源区结构，定义在所述衬底上；
    浅沟槽隔离，设置于该衬底内，该浅沟槽隔离环绕所述多个有源区结构；
    多个导线结构，相互平行地沿着第一方向延伸，所述导线结构包括第一区和第二区，所述第一区位于所述有源区结构上方，所述第二区位于所述浅沟槽隔离上方；在垂直于所述衬底的方向上，所述第一区深度大于所述第二区深度。
  2. 如权利要求1所述的半导体存储装置，其中，所述导线结构的第一区还包括栅极结构，位于所述导线结构第一区的底部，所述栅极结构包括阻挡层和第一子导电层，所述阻挡层位于所述导线结构第一区的底部的部分侧壁和底表面，所述第一子导电层设置于所述阻挡层内。
  3. 如权利要求2所述的半导体存储装置，其中，所述导线结构的第一区还包括绝缘侧壁和第二子导电层，所述绝缘侧壁位于所述导线结构第一区的底部阻挡层上方的部分侧壁，所述第二子导电层设置于所述绝缘侧壁内，所述绝缘侧壁环绕第二子导电层设置。
  4. 如权利要求3所述的半导体存储装置，其中，所述导线结构的第一区还包括第三子导电层，所述第三子导电层覆盖在所述绝缘侧壁和第二子导电层上，与导线结构的第二区连接。
  5. 如权利要求4所述的半导体存储装置，其中，所述半导体存储装置还包括覆盖层，所述覆盖层填充于所述第二区的内部，并覆盖在所述第三子导电层上。
  6. 如权利要求1所述的半导体存储装置，其中，所述第一区深度为所述第二区深度的1/2-3/4。
  7. 如权利要求3所述的半导体存储装置，其中，所述阻挡层包括金属氮 化物。
  8. 如权利要求4所述的半导体存储装置，其中，所述第一子导电层的材质、所述第二子导电层和所述第三子导电层的材质相同。
  9. 如权利要求4所述的半导体存储装置，其中，所述阻挡层的厚度大于所述绝缘侧壁的厚度。
  10. 如权利要求1所述的半导体存储装置，其中，所述第三子导电层上设有附着层，所述附着层包括氮化钛。
  11. 一种半导体存储装置的形成方法，包括：
    提供一衬底；
    在所述衬底上形成有源区结构和浅沟槽隔离，该浅沟槽隔离环绕所述多个有源区结构；
    对所述有源区结构和浅沟槽隔离进行第一次刻蚀，形成相互平行地沿着第一方向延伸的多个导线沟槽，所述第一次刻蚀中有源区结构的刻蚀速率大于浅沟槽隔离的刻蚀速率；
    在所述多条导线沟槽中形成导线结构，所述导线结构包括第一区和第二区，所述第一区位于所述有源区结构上方，所述第二区位于所述浅沟槽隔离上方；所述第一区深度大于所述第二区深度。
  12. 如权利要求11所述的方法，其中，在所述多条导线沟槽中形成导线结构包括：
    在所述导线结构侧壁上沉积形成阻挡层；
    在所述阻挡层内沉积形成第一子导电层；
    回刻蚀所述阻挡层和第一子导电层，保留位于第一区底部的部分所述阻挡层和所述第一子导电层，形成栅极结构，其中，所述阻挡层位于所述导线结构第一区的底部的部分侧壁和底表面，所述第一子导电层设置于所述阻挡层内。
  13. 如权利要求11所述的方法，其中，所述第一次刻蚀包括，在所述有源区结构和浅沟槽隔离上方沿第一方向形成多个第一掩膜结构，根据所述第 一掩膜结构对所述有源区结构和浅沟槽隔离进行刻蚀，所述第一掩膜结构的宽度为第一宽度。
  14. 如权利要求13所述的方法，其中，在所述多条导线沟槽中形成导线结构还包括：
    形成所述栅极结构后，沉积绝缘材料；
    回刻蚀所述绝缘材料以填充所述栅极结构上方沟槽；
    在所述绝缘材料上方沿第一方向形成多个第二掩膜结构，所述第二掩膜结构宽度为第二宽度，所述第二宽度小于第一宽度；
    根据所述第二掩膜结构对绝缘材料进行刻蚀，形成位于所述第一区阻挡层上方的绝缘侧壁；
    在所述绝缘侧壁内填充第二子导电层，其中，所述第二子导电层设置于所述绝缘侧壁内。
  15. 如权利要求14所述的方法，其中，在所述多条导线沟槽中形成导线结构还包括：
    在所述绝缘侧壁和第二子导电层上沉积第四子导电层，所述第四子导电层填充所述导线沟槽。
  16. 如权利要求15所述的方法，其中，在所述多条导线沟槽中形成导线结构还包括：
    在所述第四子导电层上方形成沿第一方向形成多个第三掩膜结构，所述第三掩膜结构宽度小于第二宽度；
    根据所述第三掩膜结构对所述第四子导电层进行刻蚀，形成第三子导电层，所述第三子导电层的宽度小于或等于所述第三掩膜结构宽度。
  17. 如权利要求16所述的方法，其中，还包括：在所述多条导线沟槽中形成导线结构后，在所述有源区结构、所述浅沟槽隔离，以及第三子导电层上沉积形成覆盖层。
  18. 如权利要求11所述的方法，其中，所述第一区深度为所述第二区深度的1/2-3/4。
  19. 如权利要求12所述的方法，其中，所述阻挡层包括金属氮化物。
  20. 如权利要求16所述的方法，其中，所述第一子导电层的材质、所述第二子导电层和所述第三子导电层的材质相同。
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