WO2023097901A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2023097901A1
WO2023097901A1 PCT/CN2022/077658 CN2022077658W WO2023097901A1 WO 2023097901 A1 WO2023097901 A1 WO 2023097901A1 CN 2022077658 W CN2022077658 W CN 2022077658W WO 2023097901 A1 WO2023097901 A1 WO 2023097901A1
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Prior art keywords
semiconductor structure
circuit area
active
word line
manufacturing
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PCT/CN2022/077658
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English (en)
French (fr)
Inventor
肖德元
邵光速
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长鑫存储技术有限公司
北京超弦存储器研究院
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Application filed by 长鑫存储技术有限公司, 北京超弦存储器研究院 filed Critical 长鑫存储技术有限公司
Priority to EP22741413.3A priority Critical patent/EP4213210A4/en
Priority to US17/814,271 priority patent/US20230171952A1/en
Publication of WO2023097901A1 publication Critical patent/WO2023097901A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and method of making the same.
  • capacitors are widely used in memory chips.
  • integrated circuits are developing toward miniaturization, which requires the corresponding integrated circuits to have higher integration density and smaller feature size, that is, it is required to arrange as many devices as possible in a smaller integrated circuit area to obtain higher performance.
  • the present disclosure provides a semiconductor structure and a fabrication method thereof.
  • a first aspect of the present disclosure provides a semiconductor structure comprising:
  • bit lines extending along a first direction, the bit lines are located at the bottom of the active pillar;
  • a plurality of word lines extending along the second direction, any one of the word lines covering the sidewalls of a row of the active pillars arranged along the second direction;
  • the first direction and the second direction form a predetermined angle
  • the predetermined angle is an acute angle or an obtuse angle
  • the active pillar is in the shape of a prism, a cylinder or an ellipse.
  • the predetermined included angle is 60° or 120°.
  • the semiconductor structure further includes a capacitor structure, the capacitor structure is correspondingly arranged above each of the active pillars, and the projection of the capacitor structure on the active pillar covers all the top surface of the active pillar.
  • the semiconductor structure further includes:
  • the isolation structure fills between adjacent active pillars, between adjacent word lines, between adjacent bit lines, between the word line and the bit line, the a gap between a word line and the capacitive structure;
  • the contact layer covers the top surface of the active pillar, and the contact layer is disposed between the active pillar and the capacitance structure.
  • the semiconductor structure further includes:
  • the core circuit area is located on the periphery of the array area
  • the core circuit area has a sense amplifier circuit area, the sense amplifier circuit area has a plurality of sense amplifier devices extending along the second direction, and the sense amplifier devices are connected to the bit lines;
  • the core circuit area also has a word line driving circuit area, in which there are a plurality of word line driving devices extending and arranged along the first direction, and the word line driving devices are connected to the word line .
  • the semiconductor structure further includes:
  • the peripheral circuit area is located outside the core circuit area, the circuits or devices in the peripheral circuit area are connected to the circuits or devices in the core circuit area, and the peripheral circuit area has an edge A profile extending in the first direction and in the second direction.
  • a second aspect of the present disclosure provides a method for fabricating a semiconductor structure, the fabricating method comprising:
  • the substrate performing second etching on the substrate to form a plurality of second grooves extending along a second direction and arranged at intervals along a direction perpendicular to the second direction, the first direction and the second direction form a predetermined included angle, and the predetermined included angle is an acute angle or an obtuse angle;
  • the first groove and the second groove are interspersed to form a plurality of discrete active pillars, and the distance between adjacent active pillars in the first direction and the distance in the second direction equal.
  • the groove depth of the first groove is greater than the groove depth of the second groove.
  • the manufacturing method further includes:
  • bit line is formed in the first trench, the bit line extends along the first direction, and a top surface of the bit line is lower than a bottom surface of the second trench;
  • a first isolation layer is formed, the first isolation layer covers the bit lines and fills gaps between adjacent bit lines, part of the first trench and part of the second trench.
  • the manufacturing method further includes:
  • a word line is formed, the word line extends along the extension direction of the second trench, the word line covers part of the gate oxide layer and fills the first active column between two adjacent active columns.
  • a second isolation layer is formed, and the second isolation layer fills the gaps between adjacent word lines, the unfilled regions of the first trench and the second trench.
  • the manufacturing method further includes:
  • a contact layer is formed covering the top surface of the active pillar.
  • the manufacturing method further includes:
  • a plurality of capacitive structures are formed on top of the active pillars, and the projections of the capacitive structures on the substrate cover the projections of the active pillars on the substrate.
  • the active column is prism-shaped
  • the manufacturing method further includes:
  • the active pillar is oxidized, and the active pillar is formed from a prism to a cylinder or an ellipse.
  • the manufacturing method further includes:
  • the core circuit area includes a sense amplifier circuit area and a word line driver circuit area;
  • sense amplifier devices There are a plurality of sense amplifier devices extending and arranged along the second direction in the sense amplifier circuit area, and the sense amplifier devices are connected to the bit lines;
  • word line driving devices There are a plurality of word line driving devices extending along the first direction in the word line driving circuit area, and the word line driving devices are connected to the word lines.
  • the manufacturing method further includes:
  • peripheral circuit outside the core circuit area, the peripheral circuit having an outline extending in the first direction and the second direction;
  • the circuits or devices in the peripheral circuit area are electrically connected to the circuits or devices in the core circuit area.
  • FIG. 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a top view of a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a top view of an array region of a semiconductor structure according to an exemplary embodiment.
  • Fig. 4 is a top view of an array region of a semiconductor structure according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram of a semiconductor structure according to an exemplary embodiment.
  • Fig. 6 is a top view of a semiconductor structure according to an exemplary embodiment.
  • Fig. 7 is a schematic diagram of a semiconductor structure according to an exemplary embodiment.
  • Fig. 8 is a flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 9 is a flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 10 is a flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 11 is a schematic diagram showing forming a first trench in a substrate according to an exemplary embodiment.
  • Fig. 12 is a schematic diagram of forming a second trench in a substrate according to an exemplary embodiment.
  • FIG. 13 is a top view of FIG. 12 .
  • Fig. 14 is a schematic diagram of an oxidation-treated active pillar according to an exemplary embodiment.
  • Fig. 15 is a schematic diagram showing filling isolation material in the first trench and the second trench according to an exemplary embodiment.
  • Fig. 16 is a sectional view of the A-A section of Fig. 15 .
  • Fig. 17 is a schematic diagram of removing part of the isolation material in the first trench on the section A-A in Fig. 15 according to an exemplary embodiment.
  • Fig. 18 is a schematic diagram of forming an initial bit line layer on section A-A in Fig. 15 according to an exemplary embodiment.
  • Fig. 19 is a schematic diagram of forming a first gap in section A-A in Fig. 15 according to an exemplary embodiment.
  • Fig. 20 is a schematic diagram illustrating filling and isolating material to isolate adjacent bit lines according to an exemplary embodiment.
  • Fig. 21 is a schematic diagram of forming a first isolation layer according to an exemplary embodiment.
  • Fig. 22 is a top view of forming a gate oxide layer according to an exemplary embodiment.
  • Fig. 23 is a schematic diagram of forming an initial word line layer according to an exemplary embodiment.
  • Fig. 24 is a schematic diagram of forming a second gap according to an exemplary embodiment.
  • Fig. 25 is a schematic diagram of forming a second isolation layer according to an exemplary embodiment.
  • Second trench; 20 Active column; 200. Second structure; 211. Second gap; 40, bit line; 40a, bit line layer; 41, bit line initial layer; 50, word line; 50a, initial word line layer; 51, gate oxide layer; 60, isolation structure; 61, first isolation layer; 62, second isolation layer; 70, capacitor structure; 71, contact layer; 80, core circuit area; 81, sense amplifier circuit area; 810, sense amplifier device; 82, word line drive circuit area; 820, word line drive device; 90, peripheral circuit area; 910, peripheral circuit; 920, peripheral electrical components; D1, first direction; D2, second direction; D3, third direction; D4, fourth direction.
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be introduced below as an example of Dynamic Random Access Memory (DRAM), but this embodiment is not limited thereto.
  • DRAM Dynamic Random Access Memory
  • the semiconductor structure in this embodiment is also Other configurations are possible.
  • An exemplary embodiment of the present disclosure provides a semiconductor structure, as shown in FIG. 1, FIG. 2, and FIG. Two word lines 50 extending in the direction D2.
  • the array area 01 has a plurality of active pillars 20, a plurality of bit lines 40 are located at the bottom of the active pillars 20, any one word line 50 covers the sidewall of a column of active pillars 20 arranged along the second direction D2, and a plurality of word lines
  • the wires 50 respectively cover sidewalls of multiple rows of active pillars 20 arranged along the second direction D2 .
  • the first direction D1 and the second direction D2 form a predetermined included angle
  • the predetermined included angle is an acute angle or an obtuse angle.
  • the first direction D1 intersects the second direction D2 at an acute angle or an obtuse angle
  • a plurality of active pillars 20 are arranged in a parallelogram array along a non-orthogonal direction, and a plurality of active pillars 20 are arranged in a parallelogram array along the first direction D1 a plurality of rows; a plurality of active pillars 20 are arranged in a column along the second direction D2 and have a plurality of columns.
  • the arrangement of the active pillars 20 in this embodiment increases the arrangement density of the active pillars 20 per unit area.
  • the included angle between the first direction D1 and the second direction D2 may be 30°-70°, in one example, the included angle between the first direction D1 and the second direction D2 may be 30°, 35°, 45° °, 55°, 65° or 70°; the first direction D1 and the second direction D2 can also be 110° ⁇ 150°, for example, the angle between the first direction D1 and the second direction D2 can be 110°, 120°, 130°, 140° or 150°.
  • the predetermined included angle is 60° or 120°
  • the arrangement number of the plurality of active columns 20 in the array area 01 is the largest, and the arrangement density is the highest.
  • the active pillar 20 is in the shape of a prism, and as shown in FIG. 4 , the active pillar 20 may also be in the shape of a cylinder or an ellipse.
  • the semiconductor structure further includes a capacitive structure 70 , and the capacitive structure 70 is correspondingly disposed above each active pillar 20 , and the capacitive structure 70 is formed on the active pillar 20 The projection covers the top surface of the active pillar 20 .
  • any bit line 40 is connected to a row of active pillars 20 arranged along the first direction D1, and any word line 50 covers the sidewall of a row of active pillars 20 arranged along the second direction D2.
  • the word lines 50 respectively cover sidewalls of multiple columns of active pillars 20 arranged along the second direction D2 .
  • the bit lines 40 and the word lines 50 intersect at the active pillars 20 , and the capacitor structure 70 is correspondingly arranged at intersections of the bit lines 40 , the word lines 50 and the active pillars 20 .
  • the capacitor structures 70 are arranged in a parallelogram array according to the active pillars 20, so as to improve the space utilization rate of the semiconductor structure, and more capacitor structures 70 are arranged per unit area. Moreover, in this embodiment, the More capacitive structures 70 also increase the charge storage capability of the semiconductor structure.
  • the semiconductor structure further includes: a contact layer 71 covering the top surface of the active pillar 20, the contact layer 71 is disposed between the active pillar 20 and the capacitor structure 70, The contact layer 20 is used to fix the capacitive structure 70 on the active pillar 20 .
  • the semiconductor structure further includes: an isolation structure 60, and the isolation structure 60 is filled between adjacent active pillars 20, between adjacent word lines 50, In gaps between adjacent bit lines 40 , between word lines 50 and bit lines 40 , and between word lines 50 and capacitor structures 70 .
  • the isolation structure 60 multiple elements in the semiconductor structure are isolated by the isolation structure 60, so that each element in the semiconductor structure remains independent, avoiding conductive interference between adjacent elements, and avoiding leakage of the semiconductor structure, ensuring Electrical properties of semiconductor structures.
  • the top surface of the word line 50 is lower than the top surface of the active pillar 20 , and the top surface of the word line 50 is covered by the isolation structure 60 .
  • the word line 50 is integrally arranged in the semiconductor structure. Since adjacent word lines 50 are separated by the isolation structure 60, when the semiconductor structure is connected to other semiconductor devices, other semiconductor devices will not be directly connected to the word line 50, avoiding other The direct connection of the semiconductor device to the word line 50 causes the word line 50 to be shorted.
  • the semiconductor structure of this embodiment further includes: a core circuit area 80 located on the periphery of the array area 01 .
  • the core circuit area 80 has a sense amplifier circuit area 81 and a word line drive circuit area 82, the sense amplifier circuit area 81 has a plurality of sense amplifier devices 810 extending along the second direction D2, the sense amplifier devices 810 are connected to the bit line
  • the word line driving circuit area 82 has a plurality of word line driving devices 820 extending along the first direction D1, and the word line driving devices 820 are connected to the word line 50.
  • the arrangement directions of the sense amplifier circuit area 81 and the word line driver circuit area 82 of the core circuit area 80 are consistent with the extension directions of the bit line 40 and the word line 50, so as to prevent the core circuit area 80 from damaging the array area.
  • the active pillar 20 in 01 ensures the integrity of the semiconductor structure.
  • the semiconductor structure further includes a peripheral circuit region 90 having a profile extending along the first direction D1 and the second direction D2 .
  • the peripheral circuit area 90 is located outside the core circuit area 80 , and the peripheral circuits 910 and peripheral electrical components 920 in the peripheral circuit area 90 are connected to the circuits and electrical components in the core circuit area 80 .
  • the peripheral circuit area of the semiconductor structure in this embodiment has the same parallelogram outer contour as the array area, which is convenient for circuit design and wiring, ensures the structural integrity of each internal device in the semiconductor structure, and realizes the complete application of the array area.
  • the semiconductor structure in this embodiment may be a memory chip, and the memory chip may be used in a dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • flash memory flash EPROM
  • ferroelectric memory Feroelectric Random-Access Memory
  • MRAM magnetic random access memory
  • Phase change random access memory Phase change Random-Access Memory
  • FIG. 8 shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 11-FIG. 14 are schematic diagrams of various stages of the manufacturing method of the semiconductor structure. The manufacturing method of the semiconductor structure will be introduced below in conjunction with FIG. 11-FIG. 14.
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM), but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S110 providing a substrate.
  • the substrate 10 can be made of a semiconductor material, wherein the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds; the semiconductor material can include intrinsic semiconductor materials or a small amount of doped A semiconductor doped material doped with dopant ions.
  • the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds; the semiconductor material can include intrinsic semiconductor materials or a small amount of doped A semiconductor doped material doped with dopant ions.
  • Step S120 performing a first etching on the substrate to form a plurality of first grooves extending along a first direction and arranged at intervals along a direction perpendicular to the first direction.
  • part of the substrate 10 is removed by the first etching, that is, the first etching process is performed on the substrate 10, and a plurality of first grooves 11 are formed in the substrate, and each first groove 11 Extending along the first direction D1, and the plurality of first grooves 11 are arranged at intervals along a third direction D3 perpendicular to the first direction D1.
  • Step S130 performing a second etching on the substrate to form a plurality of second grooves extending along the second direction and arranged at intervals along a direction perpendicular to the second direction, the first direction and the second direction form a predetermined angle , the predetermined included angle is an acute angle or an obtuse angle.
  • the second etching is performed on the substrate 10, that is, the second etching is performed on the substrate 10, which specifically includes: removing part of the substrate 10 through the second etching to form a plurality of first strips.
  • Two grooves 12 each second groove 12 extends along the second direction D2 , and a plurality of second grooves 12 are arranged at intervals along a fourth direction D4 perpendicular to the second direction D2 .
  • a plurality of first grooves 11 are arranged side by side along the first direction D1, and a plurality of second grooves 12 are arranged side by side along the second direction D2, and the plurality of first grooves 11 and the plurality of second grooves 11 form a predetermined angle
  • the remaining structures on the substrate 10 are divided into a plurality of independent active pillars 20 by intersecting each other.
  • the plurality of active pillars 20 form a quadrilateral array along the first direction D1 and the second direction D2.
  • the active column 20 is in the shape of a prism.
  • the angle between the first direction D1 and the second direction D2 can be 30°, 35°, 45°, 55°, 65° or 70°; the angle between the first direction D1 and the second direction D2 can also be 110° ⁇ 150°, for example, the included angle between the first direction D1 and the second direction D2 may be 110°, 120°, 130°, 140° or 150°.
  • the included angle between the first direction D1 and the second direction D2 is 60° or 120°.
  • the first trenches 11 and the second trenches 12 are arranged crosswise to divide the substrate 10
  • the number of active pillars 20 is larger, and the plurality of active pillars 20 are arranged in a hexagonal closest-packed arrangement.
  • the number of active pillars 20 formed per unit area is the largest, and the arrangement density is the highest.
  • the widths of the first trenches 11 and the second trenches 12 are equal, and the distance between adjacent active pillars 20 in the first direction D1 and the distance in the second direction D2 is equal.
  • the active column 20 formed in this embodiment is a diamond-shaped column with four sides of equal length, so that the space occupied by the active column 20 on the semiconductor structure can be minimized, and the space utilization rate of the semiconductor structure can be further improved. The largest number and the highest arrangement density.
  • the distance between two adjacent active pillars 20 in the first direction D1 may be greater than the distance between two adjacent active pillars 20 in the second direction D2;
  • the distance between the active pillars 20 in the first direction D1 may also be smaller than the distance between two adjacent active pillars 20 in the second direction D2.
  • the groove depth of the first groove 11 can be greater than or smaller than the groove depth of the second groove 12.
  • the depth of the first groove 11 and the second groove 12 are selected.
  • Bit lines 40 are formed in one of the larger trenches, and word lines 50 are formed in the other trench.
  • the first trench 11 is deeper than the second trench 12 , so the bit line 40 is formed in the first trench 11 , and the word line 50 is formed in the second trench 12 .
  • the substrate is divided into a plurality of active pillars arranged independently, so that the arrangement of the active pillars More compact, improving the space utilization of the semiconductor structure.
  • the method for forming a semiconductor structure in this embodiment further includes the following steps
  • Step S140 Oxidize the active column, the active column is formed from a prism to a column or an ellipse.
  • the active column 20 when the active column 20 is oxidized, the oxidation rate of the four corners of the prism of the active column 20 is relatively fast, and the oxidation rate of the middle part between any two corners is relatively slow, so that The four corners of the active column 20 are oxidized into rounded corners (refer to FIG. 13 and FIG. 14 ), and the active column is formed from a prismatic column to a cylindrical or elliptical column.
  • an oxide layer is formed on the sidewall of the active pillar 20.
  • the active pillar 20 is removed by dry or wet etching. The oxide layer on the sidewall ensures that the active pillar 20 has good electrical performance.
  • the active column 20 can be oxidized by using a thermal oxidation process (Thermal oxidizer), the semiconductor structure is placed in a reaction chamber with a temperature of 600° C. to 1000° C., and oxygen is introduced into the reaction chamber.
  • the treatment time is 60 ⁇ 300 seconds.
  • the active pillar 20 is cleaned with an acid solution to remove the oxide layer on the surface of the active pillar 20 .
  • a plurality of independently arranged active pillars 20 are formed on the substrate 10.
  • the plurality of active pillars 20 are independently arranged, and the plurality of active pillars 20 are arranged along the first
  • the direction D1 and the second direction D2 are arranged in a parallelogram array, and any two adjacent active pillars 20 among the plurality of active pillars 20 are separated by the first trench 11 or the second trench 12 .
  • the semiconductor structure formed in this embodiment is referred to as the first structure 100 .
  • the oxidation treatment of the active pillar can repair the defects formed on the surface of the active pillar during the first etching and the second etching, that is, the surface of the first trench and the second trench is reduced. defects, and reduce the stress between the subsequently formed isolation structure and the active pillar, so that the subsequently formed isolation structure has a better isolation effect, and prevents leakage of devices in the semiconductor structure.
  • FIG. 9 shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 12 - FIG. 25 is a schematic diagram of various stages of the manufacturing method of the semiconductor structure. The manufacturing method of the semiconductor structure will be introduced below in conjunction with FIGS. 12-25 .
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM), but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a method for fabricating a semiconductor structure includes the following steps:
  • S210 Provide a first structure.
  • the first structure 100 of the present embodiment is formed from the above-described embodiments. As shown in FIG. 12 , the first structure 100 includes a plurality of active pillars 20, and any two adjacent active pillars 20 in the plurality of active pillars 20 are separated by the first trench 11 or the second trench 12. , the first grooves 11 and the second grooves 12 are arranged crosswise at a predetermined angle, the predetermined angle is an acute angle or an obtuse angle, and a plurality of active pillars 20 are arranged in a parallelogram array.
  • S220 Form a bit line in the first trench, the bit line extends along a first direction, and the top surface of the bit line is lower than the bottom surface of the second trench.
  • a bit line 40 is formed in the first trench 11 .
  • the bit line 40 extends along the first direction D1 and is disposed under a row of active pillars 20 arranged along the first direction D1 .
  • forming the bit line 10 in the first trench 11 includes the following process:
  • a conductive material is deposited to form a bit line initial layer 41 in the first trench 11 , and the top surface of the bit line initial layer is lower than the bottom surface of the second trench 12 . As shown in FIG. 18 , referring to FIG. 12 , a conductive material is deposited to form a bit line initial layer 41 in the first trench 11 , and the top surface of the bit line initial layer is lower than the bottom surface of the second trench 12 . As shown in FIG.
  • the initial bit line layer 41 is removed by etching, and a first gap 111 extending along the first direction 11 is formed in the first trench 11, and the retained bit line initial layer 41 is separated by the first gap 111 into A plurality of bit lines 40, wherein the bit line initial layer 41 located in each first trench 11 is divided by the first gap 111 into bit line layers 40a arranged on both sides of the first trench 11, each The bit lines 40 are connected to a row of active pillars 20 extending along the first direction D1, each bit line 40 includes two bit line layers 40a arranged on both sides of each row of active pillars 20, and the two bit line layers 40a of each bit line 40 The bit line layer 40 a is disposed in two adjacent first trenches 11 .
  • S230 forming a first isolation layer, the first isolation layer covers the bit lines and fills the gap between adjacent bit lines, part of the first trench and part of the second trench.
  • an isolation material is deposited to fill the gap between two adjacent bit lines 40 .
  • the isolation material in the first trench 11 and the second trench 12 is etched back, the depth of the etching back is not greater than the depth of the second trench 12, and the remaining isolation material forms the first trench 12. Isolation layer 61.
  • the gate oxide layer 51 can be formed by depositing an atomic layer deposition process (Atomic Layer Deposition, ALD) or a chemical vapor deposition process (Chemical Vapor Deposition, CVD), and the gate oxide layer 51 covers The sidewalls of the active pillar 20 are exposed by the first trench 11 and the second trench 12 .
  • the dielectric material of the gate oxide layer 51 includes silicon oxide or silicon oxynitride.
  • S250 forming a word line, the word line extends along the extension direction of the second trench, the word line covers part of the gate oxide layer and fills part of the structure of the first trench between two adjacent active pillars.
  • the process of forming word line 50 includes:
  • the word line material is deposited by atomic layer deposition (Atomic Layer Deposition, ALD) or chemical vapor deposition (Chemical Vapor Deposition, CVD), and the word line material fills the first trench 11 and the second trench 12 to form the initial word line layer 50 a , etching back the initial word line layer 50 a until the top surface is lower than the top surface of the active pillar 20 .
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • an isolation material is deposited to cover the initial word line layer 50a.
  • Provide a mask, as shown in FIG. 24 remove part of the isolation material covering the initial word line layer 50a and part of the initial word line layer 50a according to the mask, and form a second trench 12 extending along the second direction D2.
  • the reserved initial word line layer 50a is separated by the second gap 211 to form a plurality of independently arranged word lines 50 .
  • each word line 50 covers part of the sidewall of a column of active pillars 20 arranged along the second direction D2, and multiple word lines 50 respectively cover multiple columns arranged along the second direction D2.
  • the sidewall of the active pillar 20 .
  • the material of the word line 50 includes one or more of conductive metal, conductive metal nitride, and conductive alloy.
  • the material of the conductive metal can be titanium (Titanium), tantalum (tantalum) or tungsten (Tungsten).
  • the initial word line layer 50a is first etched back to be lower than the active pillar 20, and then an isolation material is deposited to cover the top surface of the initial word line layer 50a, which can prevent the material forming the word line 50 from being oxidized by air and promote the formation of the word line layer 50a.
  • the electrical properties of the word line 50 are first etched back to be lower than the active pillar 20, and then an isolation material is deposited to cover the top surface of the initial word line layer 50a, which can prevent the material forming the word line 50 from being oxidized by air and promote the formation of the word line layer 50a.
  • S260 forming a second isolation layer, the second isolation layer filling the gap between adjacent word lines, the first trench and the unfilled area of the second trench.
  • an isolation material is deposited to fill the second gap 211 .
  • the isolation material in the second gap 211 and the isolation material covering the top surface of the word line 50 form a second isolation layer 62 , and the first isolation layer 61 and the second isolation layer 62 form an isolation structure 60 .
  • a plurality of contact layers 71 are correspondingly arranged on the active pillar 20, and each contact layer 71 is correspondingly arranged on the top surface of an active pillar 20, and the contact layer 71 is used for subsequent processes to form capacitors.
  • Structure 70 a plurality of contact layers 71 are correspondingly arranged on the active pillar 20, and each contact layer 71 is correspondingly arranged on the top surface of an active pillar 20, and the contact layer 71 is used for subsequent processes to form capacitors.
  • Structure 70 is shown in FIG. 5, referring to FIG. 25, a plurality of contact layers 71 are correspondingly arranged on the active pillar 20, and each contact layer 71 is correspondingly arranged on the top surface of an active pillar 20, and the contact layer 71 is used for subsequent processes to form capacitors. Structure 70.
  • Step S280 forming a plurality of capacitive structures on top of the active pillars, and the projections of the capacitive structures on the substrate cover the projections of the active pillars on the substrate.
  • a capacitive structure 70 is correspondingly formed on each contact layer 71 , and each capacitive structure 70 is correspondingly disposed on one active pillar 20 , and the capacitive structure 70 and the active pillar 20 are contact-connected through the contact layer 71 .
  • a silicon-germanium compound is deposited to fill the gaps between the capacitor structures 70 .
  • a plurality of bit lines 40 extending along the first direction D1 As shown in FIG. 5, after the processing steps of this embodiment, on the first structure 100, a plurality of bit lines 40 extending along the first direction D1, a plurality of word lines 50 extending along the second direction D2, and isolation structures 60 , a contact layer 71 and a plurality of capacitive structures 70 respectively corresponding to the plurality of active pillars 20 .
  • the semiconductor structure formed in this embodiment is used as the second structure 200 .
  • the capacitor structure forms a parallelogram array arranged in the same arrangement as the active pillars, which improves the packing density of the capacitor structure per unit area, improves the storage capacity of the semiconductor structure, and can further meet the needs of the integrated development of the semiconductor structure. It is especially helpful to realize the size reduction of the semiconductor structure that fully surrounds the gate structure.
  • the included angle between the first direction D1 and the second direction D2 is 60° or 120°
  • the number of capacitive structures 70 per unit area of the semiconductor structure formed in this embodiment is more, and the capacitive structure 70 are arranged in hexagonal closest packing, and the arrangement density of capacitor structure 70 is the highest.
  • FIG. 10 shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure. The following combines 5-7 introduce the fabrication method of the semiconductor structure.
  • This embodiment does not limit the semiconductor structure, and the following will introduce the semiconductor structure as an example of a memory chip, but this embodiment is not limited thereto, and the semiconductor structure in this embodiment may also be other structures.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S310 providing a second structure.
  • the second structure 200 of this embodiment is formed by the above-mentioned embodiments.
  • the second structure 20 has a parallelogram outer contour.
  • Step S320 forming a core circuit area, the core circuit area includes a sense amplifier circuit area and a word line driver circuit area.
  • the sense amplifier circuit area 81 extending along the second direction D2 is firstly formed, and the sense amplifier circuit area 81 has a plurality of sense amplifier circuits extending along the second direction D2.
  • the amplifier device 810 , the sense amplifier device 810 is connected to the bit line 40 .
  • forming the core circuit area 80 also includes forming a word line driver circuit area 82 extending along the first direction D1, and the word line driver circuit area 82 has a plurality of word line driver circuits extending along the first direction D1.
  • Device 820 the word line driver device 820 is connected to the word line 50 .
  • the core circuit area 80 is arranged according to the arrangement direction of the bit lines 40 and the word lines 50 , which can prevent the arrangement of the core circuit area 80 from damaging the active pillars 20 inside the second structure 200 .
  • Step S330 forming a peripheral circuit area outside the core circuit area, the peripheral circuit has an outline extending along the first direction and the second direction.
  • the peripheral circuits 910 or peripheral devices 920 in the peripheral circuit area 90 are electrically connected to the circuits or devices in the core circuit area 80 .
  • the peripheral circuit region 90 is disposed along the outer contour of the second structure 200 , and the outer contour of the semiconductor structure formed in this embodiment is a parallelogram that is the same shape as the second structure 200 .
  • the semiconductor structure formed in this embodiment can be a memory chip, and the memory chip can be used in a dynamic random access memory (Dynamic Random Access Memory, DRAM). However, it can also be applied to static random access memory (Static Random-Access Memory, SRAM), flash memory (flash EPROM), ferroelectric memory (Ferroelectric Random-Access Memory, FRAM), magnetic random access memory (Magnetic Random -Access Memory, MRAM), phase change random access memory (Phase change Random-Access Memory, PRAM), etc.
  • SRAM static random access memory
  • flash memory flash memory
  • FRAM ferroelectric Memory
  • MRAM magnetic random access memory
  • Phase change random access memory Phase change random access memory
  • the peripheral circuit region is formed along the contour edge of the second structure, and the outer contour of the formed semiconductor structure is a parallelogram, which omits the step of cutting the semiconductor structure into regular squares or rectangles, saving the production process , each active pillar and each capacitor structure in the semiconductor structure is not damaged by cutting, and the complete application of the array area is realized.
  • a plurality of active pillars of the semiconductor structure are arranged in a parallelogram array, which increases the arrangement density of the active pillars per unit area and improves the space utilization ratio of the semiconductor structure.

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Abstract

本公开提供一种半导体结构及其制作方法，半导体结构的制作方法包括，阵列区，阵列区具有多个有源柱；多条沿第一方向延伸的位线，位线位于有源柱的底部；多条沿第二方向延伸的字线，任意一条字线包覆沿第二方向排列的一列有源柱的侧壁；其中，第一方向与第二方向呈一预定夹角，预定夹角为锐角或钝角。

Description

半导体结构及其制作方法
本公开基于申请号为202111440983.7，申请日为2021年11月30日，申请名称为“半导体结构及其制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及其制作方法。
背景技术
电容器作为集成电路中的重要元件之一，广泛运用于存储器芯片中。当前，集成电路向着微型化方向发展，要求相应的集成电路具有更高的集成密度和更小的特征尺寸，即要求在更小尺寸的集成电路区域内设置尽可能多的器件，以获得较高的性能。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种了半导体结构及其制作方法。
本公开的第一方面提供了一种半导体结构，包括：
阵列区，所述阵列区具有多个有源柱；
多条沿第一方向延伸的位线，所述位线位于所述有源柱的底部；
多条沿第二方向延伸的字线，任意一条所述字线包覆沿所述第二方向排列的一列所述有源柱的侧壁；
其中，所述第一方向与所述第二方向呈一预定夹角，所述预定夹角为锐角或钝角。
根据本公开的一些实施例，所述有源柱呈棱柱状、圆柱状或椭圆柱状。
根据本公开的一些实施例，所述预定夹角为60°或120°。
根据本公开的一些实施例，所述半导体结构还包括电容结构，所述电容结构对应设置在每个所述有源柱的上方，所述电容结构在所述有源柱上形成的投影覆盖所述有源柱的顶面。
根据本公开的一些实施例，所述半导体结构还包括：
隔离结构，所述隔离结构填充相邻所述有源柱之间、相邻所述字线之间、相邻所述位线之间、所述字线与所述位线之间、所述字线与所述电容结构之间的间隙；
接触层，所述接触层覆盖所述有源柱的顶面，所述接触层设置在所述有源柱和所述电容结构之间。
根据本公开的一些实施例，所述半导体结构还包括：
核心电路区，所述核心电路区位于所述阵列区外围；
所述核心电路区具有感测放大电路区，所述感测放大电路区内具有沿所述第二方向延伸排列的多个感测放大器件，所述感测放大器件与所述位线连接；
所述核心电路区还具有字线驱动电路区，所述字线驱动电路区内具有沿所述第一方向延伸排列的多个字线驱动器件，所述字线驱动器件与所述字线连接。
根据本公开的一些实施例，所述半导体结构还包括：
外围电路区，所述外围电路区位于所述核心电路区之外，所述外围电路区内的电路或器件与所述核心电路区内的电路或器件相连接，所述外围电路区的具有沿所述第一方向和所述第二方向延伸的轮廓。
本公开的第二方面提供了一种半导体结构的制作方法，所述制作方法包括：
提供衬底；
对所述衬底进行第一刻蚀，以形成多条沿第一方向延伸且沿垂直于所述第一方向的方向间隔设置的第一沟槽；
对所述衬底进行第二刻蚀，以形成多条沿第二方向延伸且沿垂直于所述第二方向的方向间隔设置的第二沟槽，所述第一方向和所述第二方向呈一预定夹角，所述预定夹角为锐角或钝角；
所述第一沟槽与所述第二沟槽穿插间隔形成多个分立的有源柱，相邻所述有源柱在所述第一方向上的间距和在所述第二方向上的间距相等。
根据本公开的一些实施例，所述第一沟槽的槽深大于所述第二沟槽的槽深。
根据本公开的一些实施例，所述制作方法，还包括：
在所述第一沟槽中形成位线，所述位线沿着所述第一方向延伸，所述位线的顶面低于所述第二沟槽的底面；
形成第一隔离层，所述第一隔离层覆盖所述位线并填充相邻所述位线之间的间隙、部分所述第一沟槽以及部分所述第二沟槽。
根据本公开的一些实施例，所述制作方法，还包括：
形成栅氧化层，所述栅氧化层覆盖所述有源柱的暴露的侧壁；
形成字线，所述字线沿所述第二沟槽的延伸方向延伸，所述字线覆盖部分所述栅氧化层并填充位于相邻的两个所述有源柱之间的所述第一沟槽的部分结构；
形成第二隔离层，所述第二隔离层填充相邻所述字线之间的间隙、所述第一沟槽以及第二沟槽未被填充的区域。
根据本公开的一些实施例，所述制作方法，还包括：
形成接触层，所述接触层覆盖所述有源柱的顶面。
根据本公开的一些实施例，所述制作方法，还包括：
形成多个电容结构于所述有源柱的顶部，所述电容结构在所述衬底上形成的投影覆盖所述有源柱在所述衬底上形成的投影。
根据本公开的一些实施例，所述有源柱为棱柱状，所述制作方法还包括：
氧化处理所述有源柱，所述有源柱由棱柱状形成为圆柱状或椭圆柱状。
根据本公开的一些实施例，所述制作方法，还包括：
形成核心电路区，所述核心电路区包括感测放大电路区和字线驱动电路区；
所述感测放大电路区内具有沿所述第二方向延伸排列的多个感测放大器件，所述感测放大器件与所述位线连接；
所述字线驱动电路区内具有沿所述第一方向延伸排列的多个字线驱动器件，所述字线驱动器件与所述字线连接。
根据本公开的一些实施例，所述制作方法，还包括：
在所述核心电路区之外形成外围电路区，所述外围电路具有沿所述第一方向和所述第二方向延伸的轮廓；
所述外围电路区内的电路或器件与所述核心电路区内的电路或器件电连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的示意图。
图2是根据一示例性实施例示出的半导体结构的俯视图。
图3是根据一示例性实施例示出的半导体结构的阵列区的俯视图。
图4是根据一示例性实施例示出的半导体结构的阵列区的俯视图。
图5是根据一示例性实施例示出的半导体结构的示意图。
图6是根据一示例性实施例示出的半导体结构的俯视图。
图7是根据一示例性实施例示出的半导体结构的示意图。
图8是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图9是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图10是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图11是根据一示例性实施例示出的在衬底中形成第一沟槽的示意图。
图12是根据一示例性实施例示出的在衬底中形成第二沟槽的示意图。
图13是图12的俯视图。
图14是根据一示例性实施例示出的经过氧化处理的有源柱的示意图。
图15是根据一示例性实施例示出的在第一沟槽和第二沟槽中填充隔离材料的示意图。
图16是图15的A-A截面的剖面图。
图17是根据一示例性实施例示出的图15中A-A截面去除第一沟槽中的部分隔离材料的示意图。
图18是根据一示例性实施例示出的图15中A-A截面形成初始位线层的示意图。
图19是根据一示例性实施例示出的图15中A-A截面中形成第一间隙的示意图。
图20是根据一示例性实施例示出的填充隔离材料隔离相邻位线的示意图。
图21是根据一示例性实施例示出的形成第一隔离层的示意图。
图22是根据一示例性实施例示出的形成栅氧化层的俯视图。
图23是根据一示例性实施例示出的形成初始字线层的示意图。
图24是根据一示例性实施例示出的形成第二间隙的示意图。
图25是根据一示例性实施例示出的形成第二隔离层的示意图。
附图标记：
01、阵列区；10、衬底；11、第一沟槽；100、第一结构；111、第一间隙；12、第二沟槽；20、有源柱；200、第二结构；211、第二间隙；40、位线；40a、位线层；41、位线初始层；50、字线；50a、初始字线层；51、栅氧化层；60、隔离结构；61、第一隔离层；62、第二隔离层；70、电容结构；71、接触层；80、核心电路区；81、感测放大电路区；810、感测放大器件；82、字线驱动电路区；820、字线驱动器件；90、外围电路区；910、外围电路；920、外围电元器件；D1、第一方向；D2、第二方向；D3、第三方向；D4、第四方向。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(Dynamic Random Access Memory，DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中 的半导体结构还可以为其他的结构。
本公开示例性的实施例中提供了一种半导体结构，如图1、图2、图3所示，包括：阵列区01、多条沿第一方向D1延伸的位线40以及多条沿第二方向D2延伸的字线50。阵列区01具有多个有源柱20，多条位线40位于有源柱20的底部，任意一条字线50包覆沿第二方向D2排列的一列有源柱20的侧壁，多条字线50分别对应包覆沿第二方向D2排列的多列有源柱20的侧壁。其中，第一方向D1与第二方向D2呈一预定夹角，预定夹角为锐角或钝角。
本实施例的半导体结构，第一方向D1与第二方向D2呈锐角或钝角相交，多个有源柱20沿非正交方向排列成平行四边形阵列，多个有源柱20沿第一方向D1排成行，并且具有多行；多个有源柱20沿第二方向D2排成列，并且具有多列。本实施例中有源柱20的排布方式，提高了单位面积下有源柱20的排列密度。
示例性的，第一方向D1与第二方向D2的夹角可以为30°～70°，在一个示例中，第一方向D1和第二方向D2的夹角可以为30°、35°、45°、55°、65°或70°；第一方向D1第二方向D2还可以为110°～150°，例如，第一方向D1和第二方向D2的夹角可以为110°、120°、130°、140°或150°。其中，预定夹角为60°或120°时，阵列区01的多个有源柱20的排布数量最多，排列密度最高。
根据一个示例性实施例，如图3所示，有源柱20呈棱柱状，如图4所示有源柱20还可以为圆柱状或椭圆柱状。
根据一个示例性实施例，如图5、图6所示，半导体结构还包括电容结构70，电容结构70对应设置在每个有源柱20的上方，电容结构70在有源柱20上形成的投影覆盖有源柱20的顶面。
如图6所示，任意一条位线40与沿第一方向D1排列的一行有源柱20连接，任意一条字线50包覆沿第二方向D2排列的一列有源柱20的侧壁，多条字线50分别对应包覆沿第二方向D2排列的多列有源柱20的侧壁。位线40和字线50在有源柱20处交错，电容结构70对应设置在位线40、字线50和有源柱20的交点处。
本实施例的半导体结构，电容结构70根据有源柱20排布成平行四边形阵列，提高半导体结构的空间利用率，在单位面积下设置更多的电容结构70，而且，本实施例中，设置更多的电容结构70还提高了半导体结构的电荷存储能力。
根据一个示例性实施例，如图5所示，半导体结构还包括：接触层71，接触层71覆盖有源柱20的顶面，接触层71设置在有源柱20和电容结构70之间，接触层20用于将电容结构70固定设置在有源柱20上。
根据一个示例性实施例，如图1或如图5所示，半导体结构还包括：隔离结构60，隔离结构60填充于相邻的有源柱20之间、相邻的字线50之间、相邻的位线40之间和字线50与位线40之间，以及字线50与电容结构70之间的间隙中。
本实施例的半导体结构，通过隔离结构60隔离半导体结构中的多个元件，以使半导体结构中的各个元件保持独立，避免相邻元件之间发生导电干扰，并避免半导体结构发生漏电，保证了半导体结构的电性能。
根据一个示例性实施例，如图1或如图5所示，字线50的顶面低于有源柱20的顶面，字线50的顶面被隔离结构60覆盖。字线50整体设置在半导体结构中，由于相邻的字线50被隔离结构60隔开，半导体结构与其它的半导体器件连接时，其它的半导体器件不会与字线50直接连接，避免其它的半导体器件与字线50直接连接导致字线50短路。
根据一个示例性实施例，如图7所示，本实施例的半导体结构还包括：位于阵列区01外围的核心电路区80。核心电路区80具有感测放大电路区81和字线驱动电路区82，感测放大电路区81内具有沿第二方向D2延伸排列的多个感测放大器件810，感测放大器件810与位线40连接；字线驱动电路区82内具有沿第一方向D1延伸排列的多个字线驱 动器件820，字线驱动器件820与字线50连接。
在本实施例中，核心电路区80的感测放大电路区81和字线驱动电路区82的布置方向分别和位线40、字线50的延伸方向保持一致，以免核心电路区80破坏阵列区01中的有源柱20，保证了半导体结构的完整性。
根据本公开的一些实施例，如图7所示，半导体结构还包括外围电路区90，外围电路区90的具有沿第一方向D1和第二方向D2延伸的轮廓。外围电路区90位于核心电路区80之外，外围电路区90内的外围电路910和外围电元器件920与核心电路区80内的电路和电元器件相连接。
本实施例的半导体结构的外围电路区具有和阵列区相同的平行四边形的外轮廓，方便进行电路设计布线，保证半导体结构中的每个内部器件的结构完整，实现了对阵列区的完全应用。
本实施例的半导体结构可以为存储芯片，存储芯片可以用在动态随机存储器(Dynamic Random Access Memory，DRAM)中。然而，也可以应用于静态随机存取存储器(Static Random-Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电存储器(Ferroelectric Random-Access Memory，FRAM)、磁性随机存取存储器(Magnetic Random-Access Memory，MRAM)、相变随机存储器(Phase change Random-Access Memory，PRAM)等。
本公开示例性的实施例中提供了一种半导体结构的制作方法，如图8所示，图8示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图11-图14为半导体结构的制作方法的各个阶段的示意图，下面结合图11-图14对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图8所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S110：提供衬底。
参照图11，衬底10可以由半导体材料制成，其中，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种；半导体材料可以包括本征半导体材料或少量掺杂有掺杂离子的半导体掺杂材料。
步骤S120：对衬底进行第一刻蚀，以形成多条沿第一方向延伸且沿垂直于第一方向的方向间隔设置的第一沟槽。
如图11所示，通过第一刻蚀去除部分衬底10，即对衬底10进行第一次刻蚀处理，在衬底中形成多条第一沟槽11，每条第一沟槽11沿第一方向D1延伸，且多条第一沟槽11沿垂直于第一方向D1的第三方向D3间隔设置。
步骤S130：对衬底进行第二刻蚀，以形成多条沿第二方向延伸且沿垂直于第二方向的方向间隔设置的第二沟槽，第一方向和第二方向呈一预定夹角，预定夹角为锐角或钝角。
如图12所示，参照图11，对衬底10进行第二刻蚀，即对衬底10进行第二次刻蚀，具体包括：通过第二刻蚀去除部分衬底10，形成多条第二沟槽12，每条第二沟槽12沿第二方向D2延伸，且多条第二沟槽12沿垂直于第二方向D2的第四方向D4间隔设置。多个第一沟槽11沿第一方向D1并列设置，多个第二沟槽12沿第二方向D2并列设置，多个第一沟槽11与多个第二沟槽11呈一预定夹角相互交叉，将衬底10上其余的结构划分为相互独立的多个有源柱20。多个有源柱20沿第一方向D1和第二方向D2形成四边形阵列。
在本实施例中，如图12所示、图13所示，有源柱20为棱柱状。
示例性的，第一方向D1和第二方向D2的夹角可以为30°、35°、45°、55°、65° 或70°；第一方向D1第二方向D2还可以为110°～150°，例如，第一方向D1和第二方向D2的夹角可以为110°、120°、130°、140°或150°。
在本实施例中，第一方向D1和第二方向D2之间的夹角为60°或120°，本实施例中第一沟槽11和第二沟槽12交叉排布将衬底10划分出有源柱20的数量更多，多个有源柱20呈六方最密堆积排布，在单位面积下形成的有源柱20数量最多，排列密度最高。
在一实施例中，第一沟槽11与第二沟槽12的槽宽相等，相邻有源柱20在第一方向D1上的间距和在第二方向D2上的间距相等。本实施例形成的有源柱20为四边等长的菱形柱，使得有源柱20在半导体结构上占用的空间最小，能够进一步提高半导体结构的空间利用率，本实施例在半导体结构上设置的数量最多，排列密度最大。
在其它实施例中，相邻的两个有源柱20在第一方向D1上的间距可以大于相邻的两个有源柱20在第二方向D2上的间距；或者，相邻的两个有源柱20在第一方向D1上的间距还可以小于相邻的两个有源柱20在第二方向D2上的间距。
在本实施例中，参照图12，第一沟槽11的槽深可以大于或小于第二沟槽12的槽深，在后续制程中，选择第一沟槽11和第二沟槽12中深度较大的一个沟槽中形成位线40，在另一沟槽中形成字线50。在本实施例中，第一沟槽11的槽深大于第二沟槽12的槽深，则在第一沟槽11中形成位线40，在第二沟槽12中形成字线50。
本实施例的制作方法，通过形成非正交排布的多条第一沟槽和多条第二沟槽，将衬底划分出独立设置的多个有源柱，以使有源柱排列的更加紧密，提高了了半导体结构的空间利用率。
根据一个示例性实施例，本实施例的半导体结构的形成方法，还包括以下步骤
步骤S140：氧化处理有源柱，有源柱由棱柱状形成为圆柱状或椭圆柱状。
在本步骤中，氧化处理有源柱20时，有源柱20的棱柱状的四个边角的部分的氧化速率比较快，任意两个边角之间的中间部分的氧化速率比较慢，从而将有源柱20的四个边角氧化成圆角部(参照图13、图14)，有源柱由棱柱状形成为圆柱状或椭圆柱状。经过氧化处理，有源柱20的侧壁形成了氧化物层，为了避免氧化物层影响有源柱20的导电性能，在氧化处理后，再通过干法或湿法刻蚀去除有源柱20侧壁上的氧化物层，确保有源柱20具有良好的电性能。
本实施例中，可以采用热氧化工艺(Thermal oxidizer)氧化处理有源柱20，将半导体结构置于温度为600℃～1000℃的反应腔中，向反应腔中通入氧气，处理时间为60～300秒。热氧化处理后通过酸液清洗有源柱20，去除有源柱20表面的氧化物层。
如图12所示，经过本实施例的加工步骤后，在衬底10上形成了多个独立设置的有源柱20，多个有源柱20独立设置，多个有源柱20沿第一方向D1、第二方向D2排布成平行四边形阵列，多个有源柱20中的任意相邻的两个有源柱20被第一沟槽11或第二沟槽12隔开。将本实施例形成的半导体结构作为第一结构100。
本实施例的制作方法，氧化处理有源柱能够修复第一刻蚀和第二刻蚀过程中在有源柱表面形成的缺陷，也即减小了第一沟槽和第二沟槽的表面缺陷，减小后续形成的隔离结构和有源柱之间的应力，以使后续形成的隔离结构具有更好的隔离效果，以防止半导体结构中的器件发生漏电。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图9所示，图9示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图12-图25为半导体结构的制作方法的各个阶段的示意图，下面结合图12-图25对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图9所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下 的步骤：
S210：提供第一结构。
本实施例的第一结构100由上述实施例形成。如图12所示，第一结构100包括多个有源柱20，多个有源柱20中的任意相邻的两个有源柱20被第一沟槽11或第二沟槽12隔开，第一沟槽11和第二沟槽12呈预定夹角交叉排布，预定夹角为锐角或钝角，多个有源柱20排布成平行四边形阵列。
S220：在第一沟槽中形成位线，位线沿着第一方向延伸，位线的顶面低于第二沟槽的底面。
如图20所示，参照图12，在第一沟槽11中形成位线40，位线40沿第一方向D1延伸且设置在沿第一方向D1排列的一行有源柱20的下方。
在一示例中，如图15、图16所示，在第一沟槽11中形成位线10包括以下过程：
沉积隔离材料填充第一沟槽11和第二沟槽12，如图17所示，回刻第一沟槽11中的隔离材料至预定深度，预定深度大于第二沟槽12的深度且小于第一沟槽11的深度。如图18所示，参照图12，沉积导电材料在第一沟槽11中形成位线初始层41，位线初始层的顶面低于第二沟槽12的底面。如图19所示，刻蚀去除位线初始层41，在第一沟槽11中形成沿第一方向11延伸的第一间隙111，被保留的位线初始层41被第一间隙111分隔成多条位线40，其中，位于每个第一沟槽11中的位线初始层41被第一间隙111划分成设置在第一沟槽11的两侧侧壁的位线层40a，每条位线40与沿第一方向D1延伸的一行有源柱20连接，每条位线40包括设置在每行有源柱20两侧的两条位线层40a，每条位线40的两条位线层40a设置在相邻的两个第一沟槽11中。
S230：形成第一隔离层，第一隔离层覆盖位线并填充相邻位线之间的间隙、部分第一沟槽以及部分第二沟槽。
如图20所示，参照图19，沉积隔离材料，填充相邻的两个位线40之间的间隙。如图21所示，参照图20，回刻第一沟槽11和第二沟槽12中的隔离材料，回刻深度不大于第二沟槽12的槽深，被保留的隔离材料形成第一隔离层61。
S240：形成栅氧化层，栅氧化层覆盖有源柱的暴露的侧壁。
如图22所示，参照图13、图21，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)或化学气相沉积工艺(Chemical Vapor Deposition，CVD)沉积形成栅氧化层51，栅氧化层51覆盖有源柱20被第一沟槽11和第二沟槽12暴露出的侧壁。其中，栅氧化层51的介质材料包括氧化硅或氮氧化硅。
S250：形成字线，字线沿第二沟槽的延伸方向延伸，字线覆盖部分栅氧化层并填充位于相邻的两个有源柱之间的第一沟槽的部分结构。
如图23所示，参照图21、图22，形成字线50的过程包括：
采用原子层沉积工艺(Atomic Layer Deposition，ALD)或化学气相沉积工艺(Chemical Vapor Deposition，CVD)沉积字线材料，字线材料填充第一沟槽11和第二沟槽12，形成初始字线层50a，将初始字线层50a回刻至顶面低于有源柱20的顶面。接着，沉积隔离材料覆盖在初始字线层50a上。提供掩膜版，如图24所示，根据掩膜版去除覆盖在初始字线层50a上的部分隔离材料和部分初始字线层50a，在第二沟槽12中形成沿第二方向D2延伸的第二间隙211，被保留的初始字线层50a被第二间隙211隔开形成多条独立设置的字线50。如图24，参照图2，每条字线50包覆沿第二方向D2排列的一列有源柱20的部分侧壁，多条字线50分别对应包覆沿第二方向D2排列的多列有源柱20的侧壁。
其中，字线50的材料包括导电金属、导电金属氮化物、导电合金中的一种或二种以上，例如，导电金属的材料可以为钛(Titanium)、钽(tantalum)或钨(Tungsten)。
本实施例中，先将初始字线层50a回刻至低于有源柱20，然后再沉积隔离材料覆盖初 始字线层50a顶面，能够避免形成字线50的材料被空气氧化，提升形成的字线50的电性能。
S260：形成第二隔离层，第二隔离层填充相邻字线之间的间隙、第一沟槽以及第二沟槽未被填充的区域。
如图25所示，参照图24，沉积隔离材料填充第二间隙211。第二间隙211中隔离材料和覆盖在字线50顶面上的隔离材料形成第二隔离层62，第一隔离层61和第二隔离层62形成隔离结构60。
S270：形成接触层，接触层覆盖有源柱的顶面。
如图5所示，参照图25，在有源柱20上对应设置多个接触层71，每个接触层71对应设置在一个有源柱20的顶面，接触层71用于后续制程形成电容结构70。
步骤S280：形成多个电容结构于有源柱的顶部，电容结构在衬底上形成的投影覆盖有源柱在衬底上形成的投影。
如图5所示，在每个接触层71上对应形成电容结构70，每个电容结构70对应设置在一个有源柱20上，电容结构70和有源柱20通过接触层71接触连接。在本实施例中，形成电容结构70后，沉积硅锗化合物填充电容结构70之间缝隙。
如图5所示，经过本实施例的加工步骤后，在第一结构100上多条沿第一方向D1延伸的位线40、多条沿第二方向D2延伸的字线50、隔离结构60、接触层71以及分别与多个有源柱20对应设置的多个电容结构70。将本实施例形成的半导体结构作为第二结构200。
本实施例形成的半导体结构，电容结构形成和有源柱相同排布的平行四边形阵列，提高了单位面积的电容结构的堆积密度，提高了半导体结构的存储能力能够进一步满足半导体结构集成化发展，尤其有助于实现全包围栅极结构的半导体结构的尺寸微缩。
根据一示例性实施例，在第一方向D1和第二方向D2之间的夹角为60°或120°时，本实施例形成半导体结构在单位面积下电容结构70的数量更多，电容结构70以六方最密堆积排布，电容结构70的排列密度最大。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图10所示，图10示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，下面结合图5-图7对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为存储芯片为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图10所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S310：提供第二结构。
如图5、图6所示，本实施例的第二结构200由上述实施例形成。第二结构20具有平行四边形的外轮廓。
步骤S320：形成核心电路区，核心电路区包括感测放大电路区和字线驱动电路区。
在本实施例中，在形成核心电路区80时，首先形成沿第二方向D2延伸的感测放大电路区81，感测放大电路81区内具有沿第二方向D2延伸排列的多个感测放大器件810，感测放大器件810与位线40连接。
如图7所示，形成核心电路区80还包括，形成沿第一方向D1延伸的字线驱动电路区82，字线驱动电路区82内具有沿第一方向D1延伸排列的多个字线驱动器件820，字线驱动器件820与字线50连接。
在本实施例中，核心电路区80根据位线40和字线50的排列方向设置，可避免核心电路区80的设置破坏第二结构200内部的有源柱20。
步骤S330：在核心电路区之外形成外围电路区，外围电路具有沿第一方向和第二方 向延伸的轮廓。
如图7所示，外围电路区90内的外围电路910或外围器件920与核心电路区80内的电路或器件电连接。外围电路区90沿着第二结构200的外轮廓设置，本实施例形成的半导体结构的外部轮廓为与第二结构200的形状相同的平行四边形。
本实施例形成的半导体结构可以为存储芯片，存储芯片可以用在动态随机存储器(Dynamic Random Access Memory，DRAM)中。然而，也可以应用于静态随机存取存储器(Static Random-Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电存储器(Ferroelectric Random-Access Memory，FRAM)、磁性随机存取存储器(Magnetic Random-Access Memory，MRAM)、相变随机存储器(Phase change Random-Access Memory，PRAM)等。
本实施例的制作方法，沿着第二结构的轮廓边缘形成外围电路区，形成的半导体结构的外轮廓为平行四边形，省略了将半导体结构切割成规则的正方形或长方形的步骤，节约了生产工序，半导体结构中的每个有源柱、每个电容结构没有被切割破坏，实现了对阵列区的完全应用。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及其制作方法中，半导体结构的多个有源柱排布成平行四边形阵列，提高了单位面积有源柱的排列密度，提高了半导体结构的空间利用率。

Claims (16)

  1. 一种半导体结构，其中，所述半导体结构包括：
    阵列区，所述阵列区具有多个有源柱；
    多条沿第一方向延伸的位线，所述位线位于所述有源柱的底部；
    多条沿第二方向延伸的字线，任意一条所述字线包覆沿所述第二方向排列的一列所述有源柱的侧壁；
    其中，所述第一方向与所述第二方向呈一预定夹角，所述预定夹角为锐角或钝角。
  2. 根据权利要求1所述的半导体结构，其中，所述有源柱呈棱柱状、圆柱状或椭圆柱状。
  3. 根据权利要求1所述的半导体结构，其中，所述预定夹角为60°或120°。
  4. 根据权利要求1所述的半导体结构，所述半导体结构还包括：
    电容结构，所述电容结构对应设置在每个所述有源柱的上方，所述电容结构在所述有源柱上形成的投影覆盖所述有源柱的顶面。
  5. 根据权利要求4所述的半导体结构，所述半导体结构还包括：
    隔离结构，所述隔离结构填充相邻所述有源柱之间、相邻所述字线之间、相邻所述位线之间、所述字线与所述位线之间、所述字线与所述电容结构之间的间隙；
    接触层，所述接触层覆盖所述有源柱的顶面，所述接触层设置在所述有源柱和所述电容结构之间。
  6. 根据权利要求1所述的半导体结构，所述半导体结构还包括：
    核心电路区，所述核心电路区位于所述阵列区外围；
    所述核心电路区具有感测放大电路区，所述感测放大电路区内具有沿所述第二方向延伸排列的多个感测放大器件，所述感测放大器件与所述位线连接；
    所述核心电路区还具有字线驱动电路区，所述字线驱动电路区内具有沿所述第一方向延伸排列的多个字线驱动器件，所述字线驱动器件与所述字线连接。
  7. 根据权利要求6所述的半导体结构，其中，所述半导体结构还包括：
    外围电路区，所述外围电路区位于所述核心电路区之外，所述外围电路区内的电路或器件与所述核心电路区内的电路或器件相连接，所述外围电路区的具有沿所述第一方向和所述第二方向延伸的轮廓。
  8. 一种半导体结构的制作方法，其中，所述制作方法包括：
    提供衬底；
    对所述衬底进行第一刻蚀，以形成多条沿第一方向延伸且沿垂直于所述第一方向的方向间隔设置的第一沟槽；
    对所述衬底进行第二刻蚀，以形成多条沿第二方向延伸且沿垂直于所述第二方向的方向间隔设置的第二沟槽，所述第一方向和所述第二方向呈一预定夹角，所述预定夹角为锐角或钝角；
    所述第一沟槽与所述第二沟槽穿插间隔形成多个分立的有源柱，相邻所述有源柱在所述第一方向上的间距和在所述第二方向上的间距相等。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述第一沟槽的槽深大于所述第二沟槽的槽深。
  10. 根据权利要求9所述的半导体结构的制作方法，所述制作方法，还包括：
    在所述第一沟槽中形成位线，所述位线沿着所述第一方向延伸，所述位线的顶面低于所述第二沟槽的底面；
    形成第一隔离层，所述第一隔离层覆盖所述位线并填充相邻所述位线之间的间隙、部分所述第一沟槽以及部分所述第二沟槽。
  11. 根据权利要求10所述的半导体结构的制作方法，所述制作方法，还包括：
    形成栅氧化层，所述栅氧化层覆盖所述有源柱的暴露的侧壁；
    形成字线，所述字线沿所述第二沟槽的延伸方向延伸，所述字线覆盖部分所述栅氧化层并填充位于相邻的两个所述有源柱之间的所述第一沟槽的部分结构；
    形成第二隔离层，所述第二隔离层填充相邻所述字线之间的间隙、所述第一沟槽以及第二沟槽未被填充的区域。
  12. 根据权利要求8所述的半导体结构的制作方法，所述制作方法，还包括：
    形成接触层，所述接触层覆盖所述有源柱的顶面。
  13. 根据权利要求8所述的半导体结构的制作方法，所述制作方法，还包括：
    形成多个电容结构于所述有源柱的顶部，所述电容结构在所述衬底上形成的投影覆盖所述有源柱在所述衬底上形成的投影。
  14. 根据权利要求8所述的半导体结构的制作方法，其中，所述有源柱为棱柱状，所述制作方法还包括：
    氧化处理所述有源柱，所述有源柱由棱柱状形成为圆柱状或椭圆柱状。
  15. 根据权利要求11所述的半导体结构的制作方法，所述制作方法，还包括：
    形成核心电路区，所述核心电路区包括感测放大电路区和字线驱动电路区；
    所述感测放大电路区内具有沿所述第二方向延伸排列的多个感测放大器件，所述感测放大器件与所述位线连接；
    所述字线驱动电路区内具有沿所述第一方向延伸排列的多个字线驱动器件，所述字线驱动器件与所述字线连接。
  16. 根据权利要求15所述的半导体结构的制作方法，所述制作方法，还包括：
    在所述核心电路区之外形成外围电路区，所述外围电路具有沿所述第一方向和所述第二方向延伸的轮廓；
    所述外围电路区内的电路或器件与所述核心电路区内的电路或器件电连接。
PCT/CN2022/077658 2021-11-30 2022-02-24 半导体结构及其制作方法 WO2023097901A1 (zh)

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