WO2023206803A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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Publication number
WO2023206803A1
WO2023206803A1 PCT/CN2022/102988 CN2022102988W WO2023206803A1 WO 2023206803 A1 WO2023206803 A1 WO 2023206803A1 CN 2022102988 W CN2022102988 W CN 2022102988W WO 2023206803 A1 WO2023206803 A1 WO 2023206803A1
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Prior art keywords
substrate
active
trench
semiconductor structure
stacked
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PCT/CN2022/102988
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English (en)
French (fr)
Inventor
邵光速
杨蒙蒙
郁梦康
尤康
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长鑫存储技术有限公司
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Publication of WO2023206803A1 publication Critical patent/WO2023206803A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of manufacturing the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure.
  • a first aspect of the present disclosure provides a semiconductor structure, the semiconductor structure including a substrate and at least one memory unit disposed on the substrate, each of the memory units including:
  • a plurality of active strips a plurality of active strip arrays arranged above the substrate, each active strip extending along a first direction, any adjacent ones on a plane parallel to the substrate Two of the active strips are separated by a first trench, and any two adjacent active strips are separated by a second trench on a plane perpendicular to the substrate;
  • At least one group of stacked capacitors Two adjacent groups of stacked capacitors are arranged at intervals.
  • Each group of stacked capacitors includes a lower electrode, a dielectric layer covering the sidewall of the lower electrode, and an upper electrode.
  • the lower electrode includes a through hole.
  • the upper electrode covers the dielectric layer and fills the first trench and the second trench between the lower electrodes. .
  • the semiconductor structure includes a plurality of memory cells, and the plurality of memory cells are cyclically arranged on the substrate along the first direction.
  • the semiconductor structure further includes:
  • a support structure is provided on the substrate, the support structure is provided between adjacent memory cells, and the support structure connects two stacked capacitors of adjacent memory cells.
  • the material of the support structure includes an insulating material.
  • the stacked capacitor further includes:
  • a plurality of recessed portions are provided at one end of the stacked capacitor close to the support structure, and each recessed portion is provided between two adjacent active strips. The recessed portion is disposed toward the support structure.
  • the support structure further includes:
  • a raised portion is provided on the side wall of the support structure, each of the raised portions is provided corresponding to the recessed portion, and each of the raised portions is embedded in the recessed portion.
  • each of the memory cells further includes:
  • An array area is provided between two adjacent groups of stacked capacitors, and the array area is connected to the stacked capacitors through a plurality of active strips.
  • the array area includes:
  • a plurality of word lines each of which is vertically arranged on the substrate. On a plane parallel to the substrate, any two adjacent word lines are arranged at intervals. Each of the word lines intersects with a portion of the active strips among the plurality of active stripes, and each of the word lines covers a portion of a sidewall of a portion of the active strips;
  • a plurality of bit lines each of the bit lines extends along a second direction, the second direction is located parallel to a plane of the substrate, and the second direction is perpendicular to the first direction, and the second direction is perpendicular to the first direction.
  • any two adjacent bit lines are arranged at intervals, each of the bit lines intersects some of the active strips among the plurality of active strips, and each of the bit lines The line covers part of a side wall of part of the active strip;
  • the plurality of word lines and the plurality of bit lines are separated by isolation structures.
  • each of the memory cells includes two groups of stacked capacitors symmetrically disposed on both sides of the array area.
  • a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the method for manufacturing a semiconductor structure includes:
  • a first structure includes a capacitive region, the first structure includes a substrate and a plurality of active strips, a plurality of active strip arrays are arranged above the substrate, each of the The active strips extend along the first direction.
  • the capacitive region on a plane parallel to the substrate, any two adjacent active strips are separated by a first trench.
  • any two adjacent active strips are separated by a second trench.
  • the second trench is connected to the first trench and exposes the capacitor region. side walls of active strips;
  • each active strip located in the capacitance region is used as a lower electrode, and the upper electrode, the dielectric layer and the lower electrode form a stacked capacitor vertically stacked on the substrate.
  • a first structure including:
  • a substrate is provided, and a stacked structure is formed on the substrate, the stacked structure including active layers and sacrificial layers stacked alternately in sequence;
  • a plurality of first trenches are formed in the stacked structure, each of the first trenches extends along the first direction, and in a direction perpendicular to the substrate, each of the first trenches Throughout the stacked structure, the retained active layer is divided into a plurality of active strips by the first trench;
  • Part of the sacrificial layer is removed, and the second trench is formed in the capacitor area.
  • the first trench and the second trench are connected, exposing the side of the active strip located in the capacitor area. wall.
  • the first structure further includes a first region
  • the capacitive region is located in the first region
  • the manufacturing method further includes:
  • a support structure is formed in the first region, the support structure extends along a second direction and penetrates the first structure, the second direction is located parallel to a plane of the substrate, and the second direction and the The first direction is vertical, and the support structure divides the first area into two independently arranged capacitance areas.
  • a support structure including:
  • Depositing insulating material fills the trench to form the support structure.
  • the etching speed of the sacrificial layer is greater than the etching speed of etching the active strip, forming a groove wall on the channel groove.
  • Part of the insulating material is filled into the recessed portion to form a plurality of protrusions on the side walls of the support structure.
  • the first structure further includes an array region
  • the providing the first structure further includes:
  • a plurality of word lines are formed in the array area, each of the word lines is vertically arranged on the substrate, and any two adjacent word lines are arranged at intervals on a plane parallel to the substrate, Each of the word lines intersects a portion of the active bars among the plurality of active bars, and each of the word lines covers a portion of a sidewall of a portion of the active bars;
  • a plurality of bit lines are formed in the array area, each of the bit lines extends along a second direction, the second direction is located on a plane parallel to the substrate, and the second direction and the first direction Vertically, on a plane perpendicular to the substrate, any two adjacent bit lines are arranged at intervals, and each bit line intersects some of the active strips among the plurality of active strips, And each bit line covers part of a sidewall of the active strip.
  • providing the first structure further includes:
  • An isolation structure is formed in the array area, and the isolation structure fills gaps between a plurality of word lines and a plurality of bit lines.
  • FIG. 1 is a side view of a semiconductor structure according to an exemplary embodiment.
  • FIG. 2 is a top view of area A in FIG. 1 according to an exemplary embodiment.
  • FIG. 3 is a cross-sectional view along the line a-a in FIG. 2 .
  • Fig. 4 is a cross-sectional view of the plane b-b in Fig. 2 .
  • FIG. 5 is a cross-sectional view along the c-c plane in FIG. 2 .
  • FIG. 6 is a cross-sectional view along the d-d plane in FIG. 2 .
  • FIG. 7 is a flowchart of a method of manufacturing a semiconductor structure according to an exemplary embodiment.
  • FIG. 8 is a top view of a stacked structure formed according to an exemplary embodiment.
  • FIG. 9 is a cross-sectional view along a-a, b-b, c-c, and d-d in FIG. 8 .
  • FIG. 10 is a top view of forming a first trench according to an exemplary embodiment.
  • FIG. 11 is a cross-sectional view along a-a, b-b, c-c, and d-d in FIG. 10 .
  • FIG. 12 is a top view of forming a third trench according to an exemplary embodiment.
  • FIG. 13 is a cross-sectional view along a-a, b-b, and d-d of FIG. 12 .
  • FIG. 14 is a top view illustrating the formation of an initial gate oxide layer according to an exemplary embodiment.
  • FIG. 15 is a cross-sectional view along a-a, b-b, and d-d in FIG. 14 .
  • Figure 16 is a top view illustrating the formation of an initial high-K dielectric layer according to an exemplary embodiment.
  • FIG. 17 is a cross-sectional view along a-a, b-b, and d-d of FIG. 16 .
  • FIG. 18 is a top view of forming a word line according to an exemplary embodiment.
  • FIG. 19 is a cross-sectional view along a-a, b-b, and d-d in FIG. 18 .
  • FIG. 20 is a top view of a portion of the active strip with the array region removed according to an exemplary embodiment.
  • FIG. 21 is a cross-sectional view along a-a, b-b, and d-d in FIG. 20 .
  • FIG. 22 is a top view illustrating formation of a source layer and a drain layer according to an exemplary embodiment.
  • Fig. 23 is a cross-sectional view taken along a-a, b-b, and d-d in Fig. 22 .
  • FIG. 24 illustrates a top view of forming a first isolation layer according to an exemplary embodiment.
  • FIG. 25 is a cross-sectional view along a-a, b-b, and d-d in FIG. 24 .
  • 26 illustrates a top view of forming bit line trenches according to an exemplary embodiment.
  • FIG. 27 is a cross-sectional view along a-a, b-b, and d-d in FIG. 26 .
  • FIG. 28 illustrates a top view of forming bit lines according to an exemplary embodiment.
  • FIG. 29 is a cross-sectional view along a-a, b-b, and d-d of FIG. 28 .
  • Figure 30 illustrates a top view of forming an isolation structure according to an exemplary embodiment.
  • FIG. 31 is a cross-sectional view along a-a, b-b, and d-d in FIG. 30 .
  • Figure 32 is a top view of a first region according to an exemplary embodiment.
  • Fig. 33 is a cross-sectional view taken along line a-a of Fig. 32.
  • Fig. 34 is a cross-sectional view taken along line b-b of Fig. 32.
  • Fig. 35 is a cross-sectional view taken along line c-c in Fig. 32.
  • FIG. 36 shows a top view of forming a channel trench in the first region according to an exemplary embodiment.
  • FIG. 37 is a cross-sectional view taken along line a-a in FIG. 36 .
  • Fig. 38 is a cross-sectional view taken along line b-b of Fig. 36.
  • Figure 39 illustrates a top view of forming a support structure according to an exemplary embodiment.
  • Fig. 40 is a cross-sectional view taken along line a-a of Fig. 39.
  • Fig. 41 is a cross-sectional view taken along line b-b of Fig. 39.
  • FIG. 42 is a top view of a sacrificial layer with a capacitive region removed, according to an exemplary embodiment.
  • Fig. 43 is a cross-sectional view taken along line a-a of Fig. 42.
  • Fig. 44 is a cross-sectional view taken along line b-b of Fig. 42.
  • Fig. 45 is a cross-sectional view taken along line c-c in Fig. 42.
  • Figure 46 illustrates a top view of forming a dielectric layer according to an exemplary embodiment.
  • Fig. 47 is a cross-sectional view taken along line a-a in Fig. 46.
  • Fig. 48 is a cross-sectional view taken along line b-b of Fig. 46.
  • Fig. 49 is a cross-sectional view taken along line c-c in Fig. 46.
  • Figure 50 shows a top view of forming an upper electrode according to an exemplary embodiment.
  • FIG. 51 is a cross-sectional view taken along line a-a in FIG. 50 .
  • Fig. 52 is a cross-sectional view taken along line b-b of Fig. 50.
  • FIG. 53 is a cross-sectional view taken along line c-c in FIG. 50 .
  • First structure 101. First region; 1011. Capacitance region; 102. Array area; 110. Substrate; 120. Stacked structure; 121. Sacrificial layer; 122. Active layer; 123. Dielectric layer; 130. Active strip; 140, first trench; 150, second trench; 160, third trench; 200, support structure; 210, channel groove; 211, recessed portion; 220, raised portion; 300, stacking Capacitor; 310, lower electrode; 320, dielectric layer; 330, upper electrode; 400, word line; 401, initial gate oxide layer; 402, initial high-K dielectric layer; 410, gate oxide layer; 420, high-K dielectric layer ; 430. Word line layer; 440. Source layer; 450. Drain layer; 500. Bit line; 510. Bit line trench; 600. Isolation structure; 610. First isolation layer; 620. Second isolation layer; 700. Memory unit;
  • D1 first direction
  • D2 second direction
  • Exemplary embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure.
  • the semiconductor structure includes stacked capacitors stacked in a vertical direction, increasing the storage density of the semiconductor structure, and the stacked capacitor has an increaseable stacking layer. Therefore, the semiconductor structure has a continuously increasing storage density, which overcomes the problem that the storage density of dynamic random access memory is difficult to continue to increase due to size shrinkage, and provides a new direction for the development of dynamic random access memory.
  • Exemplary embodiments of the present disclosure provide a semiconductor structure. This embodiment does not limit the semiconductor structure.
  • the semiconductor structure is a dynamic random access memory (DRAM) as an example for introduction below, but this embodiment is not limited to this.
  • DRAM dynamic random access memory
  • the semiconductor structure in this embodiment can also be other structures.
  • the semiconductor structure of this embodiment includes a substrate 110 and at least one memory unit 700 disposed on the substrate 110 .
  • Each memory unit 700 includes a plurality of active strips 130 , the plurality of active strips 130 are arranged in an array above the substrate 110 , and each active strip 130 extends along the first direction D1 on a plane parallel to the substrate 110 , any two adjacent active strips 130 are separated by the first trench 140 (see FIGS. 42-45 ), and on a plane perpendicular to the substrate 110 , any two adjacent active strips 130 are separated by the first trench 140 (refer to FIGS. 42-45 ). Two grooves 150 (refer to Figures 42-45) are separated.
  • Each memory unit 700 also includes at least one group of stacked capacitors 300. When there are multiple stacked capacitors 300, adjacent two groups of stacked capacitors 300 are arranged at intervals.
  • Each group of stacked capacitors 300 includes a lower electrode 310, a bottom electrode covering the lower electrode 310.
  • the dielectric layer 320 of the sidewalls and the upper electrode 330 wherein the lower electrode 310 includes a partial structure passing through each active strip 130 of the stacked capacitor 300 , and the upper electrode 330 covers the dielectric layer 320 and fills between the lower electrodes 310
  • the first groove 140 and the second groove 150 (refer to Figures 42-45).
  • the semiconductor structure of this embodiment breaks through the inherent single-layer structure of the current dynamic random access memory and adds stacked capacitors stacked in the vertical direction, so that the dynamic random access memory has a multi-layer stacked 3D structure and increases the storage density of the semiconductor structure.
  • the stacked capacitor 300 has an increaseable number of stacked layers, so the semiconductor structure of this embodiment has an ever-increasing storage density, overcoming the problem that the storage density of dynamic random access memory is difficult to continue to increase due to size shrinkage, and is a dynamic random access memory. Provides new directions for device development.
  • the semiconductor structure includes multiple memory cells 700 , and the multiple memory cells 700 are cyclically arranged on the substrate 110 along the first direction D1 , that is, the multiple memory cells 700 are repeatedly arranged. on substrate 110.
  • the semiconductor structure further includes a support structure 200 disposed on the substrate 110 , and the support structure 200 is disposed between two adjacent memory cells 700 .
  • the structure 200 connects two stacked capacitors 300 of adjacent memory cells 700 to improve the stability of the semiconductor structure and prevent the semiconductor structure from tipping or collapsing.
  • the material of the support structure 200 includes insulating material.
  • the stacked capacitor 300 further includes a plurality of recessed portions 211 , and the plurality of recessed portions 211 are disposed at one end of the stacked capacitor 300 close to the support structure 200 , each recessed portion 211 is disposed between two adjacent active strips 130 , and each recessed portion 211 is disposed toward the support structure 200 .
  • the support structure 200 further includes a protruding portion 220 , the protruding portion 220 is disposed on the side wall of the support structure 200 , and each protruding portion 220 corresponds to the recessed portion 211 It is provided that each protruding portion 220 is embedded into the recessed portion 211 .
  • the protruding portion 220 of the supporting structure 200 is embedded into the recessed portion 211 of the stacked capacitor 300, which increases the contact area between the supporting structure 200 and the stacked capacitor 300, improves the effect of the supporting structure 200 in supporting the semiconductor structure, and can effectively prevent the semiconductor structure from tipping or Collapse.
  • each memory cell 700 further includes an array area 102 , which is disposed between two adjacent groups of stacked capacitors 300 .
  • the array area 102 is connected to the array area 102 through a plurality of active strips 130 .
  • Stacked capacitor 300 is connected.
  • each memory unit 700 in the first direction D1 , includes two groups of stacked capacitors 300 , and the two groups of stacked capacitors 300 are symmetrically disposed on both sides of the array area 102 , further improving the performance of the memory unit. 700 degree of integration.
  • the array area 102 includes a plurality of word lines 400 and a plurality of bit lines 500 .
  • Each word line 400 is arranged vertically on the substrate 110. On a plane parallel to the substrate 110, any two adjacent word lines 400 are arranged at intervals.
  • Each word line 400 and a portion of the plurality of active bars 130 The active bars 130 intersect, and each word line 400 covers part of a sidewall of the active bar 130 .
  • Each bit line 500 extends along the second direction D2.
  • the second direction D2 is located on a plane parallel to the substrate 110, and the second direction D2 and the first direction D1 are perpendicular to each other.
  • any phase angle is Two adjacent bit lines 500 are arranged at intervals, each bit line 500 intersects part of the active strips 130 of the plurality of active strips 130 , and each bit line 500 covers part of the sidewalls of part of the active strips 130 .
  • the plurality of word lines 400 and the plurality of bit lines 500 are separated by isolation structures 600 .
  • FIG. 7 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 8 - Figure 53 is a schematic diagram of each stage of the manufacturing method of the semiconductor structure. The manufacturing method of the semiconductor structure will be introduced below with reference to Figures 8-53.
  • the semiconductor structure is a dynamic random access memory (DRAM) as an example for introduction below.
  • DRAM dynamic random access memory
  • this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps:
  • Step S110 Provide a first structure.
  • the first structure includes a capacitor region.
  • the first structure includes a substrate and a plurality of active strips.
  • the plurality of active strip arrays are arranged above the substrate, and each active strip is along a first direction. Extended, in the capacitor region, on a plane parallel to the substrate, any two adjacent active strips are separated by the first trench, on a plane perpendicular to the substrate, any two adjacent active strips Separated by a second trench, the second trench is connected to the first trench and exposes the sidewalls of the active strip located in the capacitor region.
  • the first structure 100 may include one or more capacitive regions 1011 .
  • the multiple capacitive regions 1011 are in the first direction D1 Independent setting.
  • the plurality of active strips 130 are arranged in multiple rows along the second direction D2.
  • the plurality of active strips 130 are arranged in multiple columns, arbitrarily adjacent. The two active strips 130 are arranged independently, and the first trench 140 and the second trench 150 expose the sidewalls of the active strips 130 located in the capacitive region 1011.
  • the first structure 100 includes first regions 101 and array regions 102 alternately arranged along the first direction D1.
  • the capacitance area 1011 is located in the first area 101.
  • Each first area 101 includes two independently arranged capacitance areas 1011.
  • a support structure 200 is formed in the first area 101. The two capacitance areas 1011 of the first area 101 are supported by the support structure. 200 separated.
  • a first structure 100 including the following steps:
  • Step S111 Provide a substrate, and form a stack structure on the substrate.
  • the stack structure includes active layers and sacrificial layers stacked alternately in sequence.
  • the following implementation method can be used: using the substrate 110 as a seed crystal, place the substrate 110 in the reaction chamber, and The gas source for forming the sacrificial layer 121 and the gas source for forming the active layer 122 are alternately introduced into the reaction chamber, and a chemical vapor deposition process (Chemical Vapor Deposition, CVD) is used to alternately epitaxially grow the sacrificial layer 121 and the active layer on the substrate 110.
  • CVD Chemical Vapor Deposition
  • the sacrificial layer 121 and the active layer 122 of the stacked structure 120 may be alternately stacked with 2 to 1024 or more layers. For example, 48 layers, 64 layers, 128 layers, 256 layers or 512 layers may be alternately stacked.
  • the top structure of the stacked structure 120 is the sacrificial layer 121 .
  • any one of chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering is used.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • sputtering is used.
  • the sacrificial layer 121 and the active layer 122 are sequentially deposited on the substrate 110 .
  • the substrate 110 may be a semiconductor substrate, and the semiconductor substrate may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, or SOI (Silicon-on-insulator). Silicon) substrate or GOI (Germanium-on-Insulator, germanium on insulator) substrate, etc.
  • the semiconductor substrate can be doped with ions.
  • the semiconductor substrate can be a P-type doped substrate or an N-type doped substrate.
  • the material of the sacrificial layer 121 may include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.
  • the material of the active layer 122 may include silicon, for example, may include one or more of monocrystalline silicon, polycrystalline silicon or amorphous silicon.
  • the active layer 122 may be doped with N-type conductive doping ions or P-type conductive doping. Miscellaneous ions.
  • the substrate 110 is a silicon crystal substrate
  • the material of the sacrificial layer 121 is silicon germanium
  • the material of the active layer 122 is polysilicon.
  • line a-a passes through the first region 101 and the array region 102
  • line b-b passes through the first region 101 and the array region 102
  • line c-c is located in the capacitor region 1011
  • line d-d is located in the array region 102 .
  • the a-a cross-sectional view along the a-a line and the b-b cross-sectional view along the b-b line involved in this embodiment are not complete cross-sectional views of the semiconductor structure along the a-a line or b-b line, but are the complete cross-sectional views of the semiconductor structure along the a-a line.
  • Step S112 Form a plurality of first trenches in the stacked structure, each first trench extends along the first direction, and in the direction perpendicular to the substrate, each first trench penetrates the stacked structure and is retained.
  • the active layer is divided into a plurality of active strips by the first trench.
  • part of the sacrificial layer 121 and part of the active layer 122 are sequentially etched and removed until part of the top surface of the substrate 110 is exposed and the etching is stopped.
  • a plurality of first grooves 140 are formed. Each first trench 140 extends along the first direction D1, and the remaining active layer 122 is divided into a plurality of active strips 130 by the first trench 140.
  • the active strips 130 and the first trenches 140 in the capacitor region 1011 are spaced apart, and adjacent active strips 130 are separated by the first trenches 140 .
  • the stacked structures 120 at both ends of the first trench 140 are not etched, and the stacked structures 120 at both ends of the first trench 140 are retained.
  • the formed semiconductor structure is stable and has good stability.
  • Step S113 Form a dielectric layer, which at least fills the first trench located in the first region.
  • the dielectric layer 123 fills the first trench 140 located in the first region 101 so that the first region 101 can be processed in subsequent steps.
  • the material of the dielectric layer 123 may include one of silicon nitride, silicon oxide, or silicon oxynitride.
  • Step S114 Form a support structure in the first area.
  • the support structure extends along a second direction and penetrates the first structure.
  • the second direction is located on a plane parallel to the substrate, and the second direction is perpendicular to the first direction.
  • the support structure extends the first direction.
  • the area is divided into two independently set capacitance areas.
  • forming the support structure 200 in the first region 101 includes: as shown in FIGS. 36 to 38 , referring to FIGS. 32 to 35 , etching the first region 101 and removing part of the dielectric layer 123 and part of the sacrificial layer. 121 and part of the active strip 130, a channel groove 210 is formed in the first region 101.
  • the channel groove 210 extends along the second direction D2 and penetrates the first structure 100, and the channel groove 210 exposes part of the substrate 110.
  • the groove 210 divides the first area 101 into two independently provided capacitance areas 1011 . Then, as shown in FIGS. 39 to 41 , with reference to FIGS.
  • an insulating material is deposited to fill the trench 210 to form the support structure 200 .
  • the support structure 200 is used to connect two subsequently formed stacked capacitors 300 located in the same first region 101.
  • the support structure 200 provides good support for the stacked capacitor 300, so that the stacked capacitor 300 has a stable structure, and the stacked capacitor 300 can have a higher number of stacking layers.
  • the etching ratio of the active strip 130 and the sacrificial layer 121 is controlled so that when the first region 101 is etched, the etching ratio of the sacrificial layer 121 is reduced.
  • the etching speed is equal to the etching speed of the dielectric layer 123.
  • the etching speed of the sacrificial layer 121 is greater than the etching speed of the active strip 130.
  • a plurality of recessed portions 211 are formed on the groove wall of the channel groove 210. Each recessed portion 211 is laterally recessed between two adjacent active strips 130 .
  • the stacked capacitor 300 provides better support to ensure the stability of the semiconductor structure and avoid the risk of the semiconductor structure tipping or breaking.
  • Step S115 Remove part of the sacrificial layer, and form a second trench in the capacitor area.
  • the first trench and the second trench are connected, exposing the sidewalls of the active strip located in the capacitor area.
  • the capacitor region 1011 can be removed by dry or wet etching, and the conditions are controlled to make the etching process effective.
  • the material of the source bar 130 has a high etching selectivity. All the sacrificial layer 121 and the dielectric layer 123 in the capacitor region 1011 are removed by etching.
  • the second trench 150 is formed at the position where the sacrificial layer 121 is removed in the capacitor region 1011.
  • the groove 150 communicates with the first groove 140 .
  • the active strips 130 and the second trenches 150 in the capacitor area 1011 are alternately arranged, and adjacent active strips 130 are separated by the second trenches 150 .
  • Step S120 Form a dielectric layer in the capacitor area, and the dielectric layer covers the exposed sidewalls of the active strip.
  • dielectric material can be deposited through an atomic layer deposition process (Atomic Layer Deposition, ALD), and the dielectric material covers the capacitor region 1011
  • ALD atomic layer deposition
  • the sidewalls of the active strip 130 form a dielectric layer 320 .
  • the material of the dielectric layer 320 may include at least one of strontium titanate (SrTiO 3 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), or hafnium oxide (HfO 2 ).
  • Step S130 Form an upper electrode in the capacitor area.
  • the upper electrode covers the dielectric layer and fills the first trench and the second trench located in the capacitor area.
  • deposition is performed through any one of the chemical vapor deposition process, physical vapor deposition process (Physical Vapor Deposition, PVD), atomic layer deposition process or sputtering (sputtering)
  • the process deposits an upper electrode material, and the upper electrode material covers the dielectric layer 320 and fills the first trench 140 and the second trench 150 in the capacitor area 1011 to form the upper electrode 330, so that each active strip 130 is located in the capacitor area 1011.
  • Part of the structure serves as the lower electrode 310 , and the upper electrode 330 , the dielectric layer 320 and the lower electrode 310 together form the stacked capacitor 300 vertically stacked on the substrate 110 .
  • the upper electrode fills the first trench and the second trench located in the capacitor area, increasing the proportion of the upper electrode in the stacked capacitor. , increasing the storage space of stacked capacitors and reducing the process challenges and yield issues of semiconductor structures caused by size shrinkage.
  • This embodiment is a further explanation of a possible implementation manner of the above embodiment. Compared with the above embodiment, this embodiment adds the following steps: injecting doping ions into the active strip located in the capacitor region through ion implantation. This step is performed after step S110 provides the first structure, and this step is performed before step S120 forms a dielectric layer in the capacitor region.
  • doping ions are injected into the active strip 130 located in the capacitance region 1011 to increase the concentration of doping ions in the material of the active strip 130 located in the capacitance region 1011, and adjust the active strip 130 located in the capacitance region 1011.
  • the resistance of the source strip 130 is such that the formed stacked capacitor 300 has better electrical performance.
  • this embodiment is a further explanation of a possible implementation of step S110 of the above embodiment.
  • the first structure is provided, and also includes a process of the array area 102.
  • the process of the array area 102 is performed after forming a plurality of first trenches in the stacked structure in step S112, and the process of the array area is performed in step S114.
  • the process of the array area includes the following steps:
  • Step S101 Form multiple word lines in the array area.
  • Each word line is vertically arranged on the substrate.
  • any two adjacent word lines are arranged at intervals.
  • Each word line and multiple word lines are arranged at intervals. Some of the active strips intersect, and each word line covers part of the sidewalls of some of the active strips.
  • multiple word lines 400 are formed in the array area 102 in the following manner:
  • the sacrificial layer 121 located in the array area 102 is removed, and a third trench 160 is formed in the array area 102 where the sacrificial layer 121 is removed.
  • the groove 160 is connected with the first trench 140 to expose the sidewalls of the active strip 130 located in the array area 102 .
  • an initial gate oxide layer 401 is deposited and formed through any one of the atomic layer deposition process, the chemical vapor deposition process, or the physical vapor deposition process.
  • the gate oxide layer 401 covers the sidewalls of the active strips 130 located in the array area 102 .
  • the material of the initial gate oxide layer 401 may include at least one of silicon oxide or silicon oxynitride.
  • an initial high-K dielectric layer 402 is deposited through any of the above deposition processes, and the initial high-K dielectric layer 402 covers the initial gate oxide layer 401 .
  • the material of the initial high-K dielectric layer 402 may include metal silicates or metal silicon oxides.
  • the material of the initial high-K dielectric layer 402 may include tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium silicon oxide (HfSiO) 2 ) or at least one of hafnium oxide (HfO 2 ).
  • an initial word line layer (not shown in the figure) is deposited and formed through any of the above deposition processes.
  • the initial word line layer covers the initial high-K dielectric layer 402 and fills the first trench 140 and the third trench 160 .
  • the material of the initial word line layer may include conductive metal, doped semiconductor material or metal-semiconductor compound material.
  • the material of the initial word line layer may include one of metal titanium (Titanium), metal tantalum (Tantalum), metal tungsten (Tungsten) or alloys thereof, or the material of the initial word line layer may include doped single crystal.
  • each word line 400 is arranged vertically on the substrate 110. On a plane parallel to the substrate 110, any two adjacent word lines 400 are arranged at intervals. Each word line 400 and a portion of the plurality of active bars 130 The active bars 130 intersect, and each word line 400 covers part of a sidewall of the active bar 130 .
  • Each word line 400 includes a gate oxide layer 410, a high-K dielectric layer 420 and a word line layer 430 covering the active strip in sequence.
  • a plurality of word lines 400 are arranged in two rows along the second direction D2, and each active strip 130 intersects two word lines 400.
  • Step S102 Form a source layer and a drain layer.
  • the source layer 440 and the drain layer 450 may be formed in the following manner:
  • the active strip 130 in the array area 102 can be etched based on the first trench 140 and the third trench 160. After the etching process, in the array area 102 , the thickness of the active strip 130 exposed by the first trench 140 and the third trench 160 is thinner than the thickness of the active strip 130 covered by the word line 400 .
  • the active strips 130 exposed in the array area 102 are used as seed crystals, and source electrodes are formed on the active strips 130 on both sides of the word line 400 through epitaxial growth.
  • layer 440 and drain layer 450 may cover part of the sidewalls of the gate oxide layer 410, but the source layer 440, the drain layer 450, the high-K dielectric layer 420 and the word line layer 430 do not contact to avoid adjacent word lines. 400 short circuit occurred.
  • two word lines 400 connected to the same active strip 130 share a source layer 440 .
  • two word lines 400 connected to the same active strip 130 may share the drain layer 450 .
  • source regions and drain regions may be respectively formed in the active strips 130 on both sides of each word line 400 through an ion implantation process.
  • Step S103 Form a first isolation layer.
  • a low-K dielectric material can be deposited through a chemical vapor deposition process or a physical vapor deposition process.
  • the low-K dielectric material at least fills the first trench 140 located in the array area 102 and The unfilled area in the third trench 160 forms the first isolation layer 610 .
  • the material of the first isolation layer 610 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the low-K dielectric material may also fill the first trench 140 located in the first region 101 to form the dielectric layer 123 in the first region 101 .
  • Step S104 Form a plurality of bit lines in the array area, each bit line extends along a second direction, the second direction is located on a plane parallel to the substrate, and the second direction is perpendicular to the first direction, and on a plane perpendicular to the substrate , any two adjacent bit lines are arranged at intervals, each bit line intersects part of the active strips among the plurality of active strips, and each bit line covers part of the sidewalls of part of the active strips.
  • multiple bit lines 500 are formed in the array area 102 in the following manner:
  • the array area 102 is etched, part of the first isolation layer 610 , part of the source layer 440 and part of the active strip 130 are removed, and a bit line trench 510 is formed.
  • the bit line trench 510 extends along the second direction D2, and the bit line trench 510 exposes part of the top surface of the substrate 110 .
  • bit lines 500 are alternately formed in the bit line trenches 510 , on a plane perpendicular to the top surface of the substrate 110 , The second isolation layers 620 and the bit lines 500 are alternately arranged.
  • Each bit line 500 extends along the second direction D2 and covers the sidewalls of the active strip 130 on both sides thereof.
  • the first isolation layer 610 and the second isolation layer 620 in the array area 102 together form an isolation structure 600.
  • the isolation structure 600 fills the gap between the word line 400 and the bit line 500.
  • the gaps between the plurality of word lines 400 and the plurality of bit lines 500 are to prevent the devices in the array area 102 from short-circuiting and causing leakage of the semiconductor structure, and ensure that the semiconductor structure has good electrical properties.
  • the semiconductor structure formed in this embodiment forms word lines arranged vertically on the substrate.
  • the word lines surround part of the sidewalls of the active strips to form a GAA (Gate All Around) structure, reducing the size of the shrink band. coming process challenges and yield issues.
  • GAA Gate All Around
  • the semiconductor structure by adding stacked capacitors stacked in the vertical direction, the semiconductor structure has a multi-layer stacked 3D structure, thereby increasing the efficiency of the semiconductor structure.
  • Storage density, and stacked capacitors have an increaseable number of stacked layers. Therefore, the semiconductor structure provided by the present disclosure has an ever-increasing storage density, which greatly improves the electrical performance of the semiconductor structure.

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Abstract

本公开提供一种半导体结构及半导体结构的制作方法，涉及半导体技术领域，半导体结构包括衬底和至少一个存储器单元，每个存储器单元包括多个有源条和至少一组堆叠电容器，多个有源条阵列排布在衬底上方且平行于衬底，任意相邻的两个有源条被第一沟槽隔开；在垂直于衬底的平面上，任意相邻的两个有源条被第二沟槽隔开；相邻的两组堆叠电容器间隔设置，每组堆叠电容器包括下电极、介电层及上电极，下电极包括穿过堆叠电容器的每个有源条的部分结构，上电极覆盖介电层并填充位于下电极之间的第一沟槽和第二沟槽。

Description

半导体结构及半导体结构的制作方法
本公开基于申请号为202210435693.1、申请日为2022年04月24日、申请名称为“半导体结构及半导体结构的制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及半导体结构的制作方法。
背景技术
在集成电路领域，根据摩尔定律，集成电路中的半导体器件每增加一倍，集成电路的性能也会随之翻一番，因此为了提高集成电路的电性能，集成电路的尺寸不断微缩、集成度不断提高。
目前，动态随机存取存储器(Dynamic Random Access Memory，DRAM)通常为单层结构，单层结构的动态随机存取存储器的尺寸已经减小到极限，难以继续微缩延续摩尔定律的有效性。并且，动态随机存取存储器的特征尺寸的不断微缩增加了制程难度，特征尺寸越小，动态随机存取存储器的良率越低。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构及半导体结构的制作方法。
本公开的第一方面提供了一种半导体结构，所述半导体结构包括衬底和设置于所述衬底上的至少一个存储器单元，每个所述存储器单元包括：
多个有源条，多个所述有源条阵列排布在所述衬底上方，每个所述有源条沿第一方向延伸，在平行于所述衬底的平面上，任意相邻的两个所述有源条被第一沟槽隔开，在垂直于所述衬底的平面上，任意相邻的两个所述有源条被第二沟槽隔开；
至少一组堆叠电容器，相邻的两组所述堆叠电容器间隔设置，每组所述堆叠电容器包括下电极、覆盖所述下电极的侧壁的介电层以及上电极，所述下电极包括穿过所述堆叠电容器的每个所述有源条的部分结构，所述上电极覆盖所述介电层并填充位于所述下电极之间的所述第一沟槽和所述第二沟槽。
根据本公开的一些实施例，所述半导体结构包括多个存储器单元，多个所述存储器单元沿所述第一方向循环排布在所述衬底上。
根据本公开的一些实施例，所述半导体结构还包括：
支撑结构，所述支撑结构设置在所述衬底上，所述支撑结构设置在相邻的所述存储器单元之间，所述支撑结构连接相邻的存储器单元的两个堆叠电容器。
根据本公开的一些实施例，所述支撑结构的材料包括绝缘材料。
根据本公开的一些实施例，所述堆叠电容器还包括：
多个凹陷部，多个所述凹陷部设置在所述堆叠电容器的靠近所述支撑结构的一端，每个所述凹陷部设置于相邻的两个所述有源条之间，每个所述凹陷部朝向所述支撑结构设置。
根据本公开的一些实施例，所述支撑结构还包括：
凸起部，所述凸起部设置于所述支撑结构的侧壁，每个所述凸起部与所述凹陷部对应设置，每个所述凸起部嵌入至所述凹陷部中。
根据本公开的一些实施例，每个所述存储器单元还包括：
阵列区，所述阵列区设置于相邻的两组所述堆叠电容器之间，所述阵列区通过多个所述有源条与所述堆叠电容器连接。
根据本公开的一些实施例，所述阵列区包括：
多条字线，每条所述字线垂直设置在所述衬底上，在平行于所述衬底的平面上，任意相邻的两条所述字线间隔设置，每条所述字线和多个所述有源条中的部分所述有源条相交，并且每条所述字线覆盖部分所述有源条的部分侧壁；
多条位线，每条所述位线沿第二方向延伸，所述第二方向位于平行于所述衬底的平面，且所述第二方向和所述第一方向垂直，在垂直于所述衬底的平面上，任意相邻的两条所述位线间隔设置，每条所述位线和多个所述有源条中的部分所述有源条相交，并且每条所述位线覆盖部分所述有源条的部分侧壁；
多条所述字线和多条所述位线通过隔离结构隔开。
根据本公开的一些实施例，在所述第一方向上，每个所述存储器单元包括对称设置在所述阵列区两侧的两组所述堆叠电容器。
本公开的第二方面提供了一种半导体结构的制作方法，所述半导体结构的制作方法包括：
提供第一结构，所述第一结构包括电容区域，所述第一结构包括衬底以及多个有源条，多个所述有源条阵列排布在所述衬底上方，每个所述有源条沿第一方向延伸，所述电容区域中，在平行于所述衬底的平面上，任意相邻的两个所述有源条被第一沟槽隔开，在垂直于所述衬底的平面上，任意相邻的两个所述有源条被第二沟槽隔开，所述第二沟槽和所述第一沟槽连通并暴露出位于所述电容区域的所述有源条的侧壁；
于所述电容区域形成介电层，所述介电层覆盖所述有源条暴露的侧壁；
于所述电容区域形成上电极，所述上电极覆盖所述介电层并填充位于所述电容区域中的所述第一沟槽和所述第二沟槽；
以每个所述有源条位于所述电容区域的部分结构作为下电极，所述上电极、所述介电层和所述下电极形成垂直堆叠在所述衬底上的堆叠电容器。
根据本公开的一些实施例，提供第一结构，包括：
提供衬底，在所述衬底上形成堆叠结构，所述堆叠结构包括依次交替堆叠的有源层和牺牲层；
于所述堆叠结构中形成多条第一沟槽，每条所述第一沟槽沿所述第一方向延伸，且在垂直于所述衬底的方向上，每条所述第一沟槽贯穿所述堆叠结构，被保留的所述有源层被所述第一沟槽划分成多个所述有源条；
去除部分所述牺牲层，于所述电容区域形成所述第二沟槽，所述第一沟槽和所述第二沟槽连通，暴露出位于所述电容区域的所述有源条的侧壁。
根据本公开的一些实施例，所述第一结构还包括第一区域，所述电容区域位于所述第一区域中，所述制作方法还包括：
于所述第一区域形成支撑结构，所述支撑结构沿第二方向延伸并贯穿所述第一结构，所述第二方向位于平行于所述衬底的平面，且所述第二方向和所述第一方向垂直，所述支撑结构将所述第一区域划分成两个独立设置的所述电容区域。
根据本公开的一些实施例，形成支撑结构，包括：
刻蚀所述第一区域，于所述第一区域形成沟道槽，所述沟道槽沿所述第二方向延伸并贯穿所述第一结构，且所述沟道槽暴露出部分所述衬底；
沉积绝缘材料填充所述沟道槽，形成所述支撑结构。
根据本公开的一些实施例，刻蚀所述第一区域时，刻蚀所述牺牲层的刻蚀速度大于刻蚀所述有源条的刻蚀速度，于所述沟道槽的槽壁形成多个凹陷部，每个所述凹陷部沿横向凹入到相邻的两个所述有源条之间；
部分所述绝缘材料填充到所述凹陷部中，在所述支撑结构的侧壁形成多个凸起部。
根据本公开的一些实施例，所述第一结构还包括阵列区，所述提供第一结构，还包括：
去除位于所述阵列区的所述牺牲层；
于所述阵列区形成多条字线，每条所述字线垂直设置在所述衬底上，在平行于所述衬底的平面上，任意相邻的两条所述字线间隔设置，每条所述字线和多个所述有源条中的部分所述有源条相交，并且每条所述字线覆盖部分所述有源条的部分侧壁；
于所述阵列区形成多条位线，每条所述位线沿第二方向延伸，所述第二方向位于平行于所述衬底的平面，且所述第二方向和所述第一方向垂直，在垂直于所述衬底的平面上，任意相邻的两条所述位线间隔设置，每条所述位线和多个所述有源条中的部分所述有源条相交，并且每条所述位线覆盖部分所述有源条的部分侧壁。
根据本公开的一些实施例，所述提供第一结构，还包括：
于所述阵列区形成隔离结构，所述隔离结构填充多条所述字线和多条所述位线之间的间隙。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种半导体结构的侧视图。
图2是根据一示例性实施例示出的图1中A区域的俯视图。
图3是图2的a-a面的截面图。
图4是图2的b-b面的截面图。
图5是图2的c-c面的截面图。
图6是图2的d-d面的截面图。
图7是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图8是根据一示例性实施例示出的形成的堆叠结构的俯视图。
图9是图8的a-a、b-b、c-c、d-d的截面图。
图10是根据一示例性实施例示出的形成第一沟槽的俯视图。
图11是图10的a-a、b-b、c-c、d-d的截面图。
图12是根据一示例性实施例示出的形成第三沟槽的俯视图。
图13是图12的a-a、b-b、d-d的截面图。
图14是根据一示例性实施例示出的形成初始栅氧层的俯视图。
图15是图14的a-a、b-b、d-d的截面图。
图16是根据一示例性实施例示出的形成初始高K介质层的俯视图。
图17是图16的a-a、b-b、d-d的截面图。
图18是根据一示例性实施例示出的形成字线的俯视图。
图19是图18的a-a、b-b、d-d的截面图。
图20是根据一示例性实施例示出的去除阵列区的部分有源条的俯视图。
图21是图20的a-a、b-b、d-d的截面图。
图22是根据一示例性实施例示出的形成源极层和漏极层的俯视图。
图23是图22的a-a、b-b、d-d的截面图。
图24根据一示例性实施例示出的形成第一隔离层的俯视图。
图25是图24的a-a、b-b、d-d的截面图。
图26根据一示例性实施例示出的形成位线沟槽的俯视图。
图27是图26的a-a、b-b、d-d的截面图。
图28根据一示例性实施例示出的形成位线的俯视图。
图29是图28的a-a、b-b、d-d的截面图。
图30根据一示例性实施例示出的形成隔离结构的俯视图。
图31是图30的a-a、b-b、d-d的截面图。
图32根据一示例性实施例示出的第一区域的俯视图。
图33是图32的a-a截面图。
图34是图32的b-b截面图。
图35是图32的c-c截面图。
图36根据一示例性实施例示出的在第一区域形成沟道槽的俯视图。
图37是图36的a-a截面图。
图38是图36的b-b截面图。
图39根据一示例性实施例示出的形成支撑结构的俯视图。
图40是图39的a-a截面图。
图41是图39的b-b截面图。
图42根据一示例性实施例示出的去除电容区域的牺牲层的俯视图。
图43是图42的a-a截面图。
图44是图42的b-b截面图。
图45是图42的c-c截面图。
图46根据一示例性实施例示出的形成介电层的俯视图。
图47是图46的a-a截面图。
图48是图46的b-b截面图。
图49是图46的c-c截面图。
图50根据一示例性实施例示出的形成上电极的俯视图。
图51是图50的a-a截面图。
图52是图50的b-b截面图。
图53是图50的c-c截面图。
附图标记：
100、第一结构；101、第一区域；1011、电容区域；102、阵列区；110、衬底；120、堆叠结构；121、牺牲层；122、有源层；123、介质层；130、有源条；140、第一沟槽；150、第二沟槽；160、第三沟槽；200、支撑结构；210、沟道槽；211、凹陷部；220、凸起部；300、堆叠电容器；310、下电极；320、介电层；330、上电极；400、字线；401、初始栅氧层；402、初始高K介质层；410、栅氧层；420、高K介质层；430、字线层；440、源极层；450、漏极层；500、位线；510、位线沟槽；600、隔离结构；610、第一隔离层；620、第二隔离层；700、存储器单元；
D1、第一方向；D2、第二方向。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性实施例提供了一种半导体结构及半导体结构的制作方法，半导体结构包括在垂直方向上堆叠设置的堆叠电容器，增加了半导体结构的存储密度，并且，堆叠电容器具有可增加的堆叠层数，因此半导体结构具有可不断增加的存储密度，克服了动态随机存储器因尺寸微缩导致存储密度难以继续增加的问题，为动态随机储存器的发展提供了新的方向。
本公开示例性实施例提供了一种半导体结构，本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1-图6所示，本实施例的半导体结构包括衬底110和设置于衬底110上的至少一个存储器单元700。每个存储器单元700包括多个有源条130，多个有源条130阵列排布在衬底110上方，每个有源条130沿第一方向D1延伸，在平行于衬底110的平面上，任意相邻的两个有源条130被第一沟槽140(参照图42-图45)隔开，在垂直于衬底110的平面上，任意相邻的两个有源条130被第二沟槽150(参照图42-图45)隔开。
每个存储器单元700还包括至少一组堆叠电容器300，当堆叠电容器300设置有多个时，相邻的两组堆叠电容器300间隔设置，每组堆叠电容器300包括下电极310、覆盖下电极310的侧壁的介电层320以及上电极330，其中，下电极310包括穿过堆叠电容器300的每个有源条130的部分结构，上电极330覆盖介电层320并填充位于下电极310之间的第一沟槽140和第二沟槽150(参照图42-图45)。
本实施例的半导体结构突破了当前动态随机存储器固有的单层构架，增加了在垂直方向上堆叠设置的堆叠电容器，以使动态随机存储器具有多层堆叠的3D构架，增加了半导体结构的存储密度，并且，堆叠电容器300具有可增加的堆叠层数，因此本实施例的半导体结构具有可不断增加的存储密度，克服了动态随机存储器因尺寸微缩导致存储密度难以继续增加的问题，为动态随机储存器的发展提供了新的方向。
在一些实施例中，如图1所示，半导体结构包括多个存储器单元700，多个存储器单元700沿第一方向D1循环排布在衬底110上，也即多个存储器单元700重复排布在衬底110上。
在一些实施例中，如图1-图6所示，半导体结构还包括支撑结构200，支撑结构200设置在衬底110上，支撑结构200设置在相邻的两个存储器单元700之间，支撑结构200连接相邻的存储器单元700的两个堆叠电容器300，以提高半导体结构的稳定性，避免半导体结构的倾倒或坍塌。其中，支撑结构200的材料包括绝缘材料。
在一些实施例中，如图1-图6所示，参照图36-图41，堆叠电容器300还包括多个凹陷部211，多个凹陷部211设置在堆叠电容器300的靠近支撑结构200的一端，每个凹陷部211设置于相邻的两个有源条130之间，每个凹陷部211朝向支撑结构200设置。
如图1-图4所示，参照图36-图41，支撑结构200还包括凸起部220，凸起部220设置于支撑结构200的侧壁，每个凸起部220与凹陷部211对应设置，每个凸起部220嵌入至凹陷部211中。支撑结构200的凸起部220嵌入至堆叠电容器300的凹陷部211中，增加了支撑结构200和堆叠电容器300的接触面积，提高了支撑结构200支撑半导体结构的效果，能够有效避免半导体结构倾倒或坍塌。
在一些实施例中，如图1所示，每个存储器单元700还包括阵列区102，阵列区102设置于相邻的两组堆叠电容器300之间，阵列区102通过多个有源条130与堆叠电容器300连接。
在一些实施例中，如图1所示，在第一方向D1上，每个存储器单元700包括两组堆叠电容器300，两组堆叠电容器300对称设置在阵列区102两侧，进一步提高了存储器单元700的集成度。
在一些实施例中，如图1-图6所示，阵列区102包括多条字线400和多条位线500。每条字线400垂直设置在衬底110上，在平行于衬底110的平面上，任意相邻的两条字线400间隔设置，每条字线400和多个有源条130中的部分有源条130相交，并且每条字线400覆盖部分有源条130的部分侧壁。每条位线500沿第二方向D2延伸，第二方向D2位于平行于衬底110的平面，且第二方向D2和第一方向D1相互垂直，在垂直于衬底110的平面上，任意相邻的两条位线500间隔设置，每条位线500和多个有源条130中的部分有源条130相交，并且每条位线500覆盖部分有源条130的部分侧壁。多条字线400和多条位线500通过隔离结构600隔开。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图7所示，图7示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图8-图53为半导体结构的制作方法的各个阶段的示意图，下面结合图8-图53对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图7所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S110：提供第一结构，第一结构包括电容区域，第一结构包括衬底以及多个有源条，多个有源条阵列排布在衬底上方，每个有源条沿第一方向延伸，电容区域中，在平行于衬底的平面上，任意相邻的两个有源条被第一沟槽隔开，在垂直于衬底的平面上，任意相邻的两个有源条被第二沟槽隔开，第二沟槽和第一沟槽连通并暴露出位于电容区域的有源条的侧壁。
如图42-图45所示，第一结构100可以包括一个或多个电容区域1011，在第一结构100包括多个电容区域1011的实施例中，多个电容区域1011在第一方向D1上独立设置。在平行于衬底110的平面上，多个有源条130沿第二方向D2排成多排，在垂直于衬底110的平面上，多个有源条130排成多列，任意相邻的两个有源条130独立设置，第一沟槽140和第二沟槽150暴露出位于电容区域1011中有源条130的侧壁。
在本实施例中，如图42-图45所示，第一结构100包括沿第一方向D1交替设置的第一区域101和阵列区102。电容区域1011位于第一区域101中，每个第一区域101包括独立设置的两个电容区域1011，第一区域101中形成有支撑结构200，第一区域101的两个电容区域1011被支撑结构200隔开。
在实施过程中，提供第一结构100，包括以下步骤：
步骤S111：提供衬底，在衬底上形成堆叠结构，堆叠结构包括依次交替堆叠的有源层和牺牲层。
在本实施例中，如图8、图9所示，在衬底110上形成堆叠结构120，可以采用以下实施方式：以衬底110作为籽晶，将衬底110置于反应腔中，向反应腔中交替通入形成牺牲层121的气体源以及形成有源层122的气体源，采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)在衬底110上交替外延生长形成牺牲层121和有源层122，牺牲层121和有源层122共同形成堆叠结构120。其中，堆叠结构120的牺牲层121和有源层122可以交替叠置2层～1024层或更多层，例如，可以交替层叠48层、64层、128层、256层或512层等。在本实施例中，堆叠结构120的顶层结构为牺牲层121。
在其它实施例中，选用化学气相沉积工艺、物理气相沉积工艺(Physical Vapor Deposition，PVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)或溅射(sputtering)中的任一种沉积工艺，在衬底110上依次沉积形成牺牲层121和有源层122。
在本实施例中，衬底110可以为半导体衬底，半导体衬底可以包括硅衬底、锗(Ge)衬底、锗化硅(SiGe)衬底、SOI(Silicon-on-insulator，绝缘体上硅)衬底或GOI(Germanium-on-Insulator，绝缘体上锗)衬底等。半导体衬底中可以掺杂离子，例如，半导体衬底可以为P型掺杂衬底，也可以为N型掺杂衬底。
牺牲层121的材料可以包括锗、锗化硅、碳化硅、砷化镓或镓化铟。
有源层122的材料可以包括硅，例如可以包括单晶硅、多晶硅或非晶硅中的一种或多种，有源层122中可以掺杂有N型导电掺杂离子或P型导电掺杂离子。
在本实施例中，衬底110为硅晶衬底，牺牲层121的材料为锗化硅，有源层122的材料为多晶硅。
需要说明的是，在图8中，a-a线贯穿第一区域101和阵列区102，b-b线贯穿第一区域101和阵列区102，c-c线位于电容区域1011，d-d线位于阵列区102。可以理解的是，在本实施例中涉及到的沿a-a线的a-a截面图以及沿b-b线的b-b截面图并非半导体结构沿a-a线或b-b线完整的截面图，而是半导体结构沿a-a线的局部截面图或半导体结构沿b-b线的局部截面图。
步骤S112：于堆叠结构中形成多条第一沟槽，每条第一沟槽沿第一方向延伸，且在垂直于衬底的 方向上，每条第一沟槽贯穿堆叠结构，被保留的有源层被第一沟槽划分成多个有源条。
如图10、图11所示，参照图8、图9，依次刻蚀去除部分牺牲层121以及部分有源层122，直至暴露出衬底110的部分顶面停止刻蚀，在堆叠结构120中形成多条第一沟槽140。每条第一沟槽140沿第一方向D1延伸，被保留的有源层122被第一沟槽140划分成多个有源条130。在平行于衬底110的平面上，电容区域1011中的有源条130和第一沟槽140间隔设置，相邻的有源条130被第一沟槽140隔开。
在本实施例中，如图10、图11所示，在第一方向D1上，位于第一沟槽140两端的堆叠结构120未被刻蚀，第一沟槽140两端的堆叠结构120被保留作为半导体结构的支撑构架，以使形成的半导体结构稳固、具有良好的稳定性。
步骤S113：形成介质层，介质层至少填充位于第一区域的第一沟槽。
如图32-图35所示，参照图10、图11，介质层123填充位于第一区域101的第一沟槽140，以便后续步骤对第一区域101进行加工制程。其中，介质层123的材料可以包括氮化硅、氧化硅或氮氧化硅中的一种。
步骤S114：于第一区域形成支撑结构，支撑结构沿第二方向延伸并贯穿第一结构，第二方向位于平行于衬底的平面，且第二方向和第一方向垂直，支撑结构将第一区域划分成两个独立设置的电容区域。
在本实施例中，于第一区域101形成支撑结构200，包括：如图36-图38所示，参照图32-图35，刻蚀第一区域101，去除部分介质层123、部分牺牲层121以及部分有源条130，于第一区域101形成沟道槽210，沟道槽210沿第二方向D2延伸并贯穿第一结构100，且沟道槽210暴露出部分衬底110，沟道槽210将第一区域101划分成两个独立设置的电容区域1011。然后，如图39-图41所示，参照图36-图38，沉积绝缘材料填充沟道槽210，形成支撑结构200。支撑结构200用于连接后续形成的位于同一第一区域101的两个堆叠电容器300，支撑结构200为堆叠电容器300提供良好的支撑力，以使堆叠电容器300结构稳固，堆叠电容器300可以具有更高的堆叠层数。
在本实施例中，如图36-图38所示，通过控制刻蚀有源条130和牺牲层121的刻蚀比，以使刻蚀第一区域101时，刻蚀牺牲层121的刻蚀速度和刻蚀介质层123的刻蚀速度相等，刻蚀牺牲层121的刻蚀速度大于刻蚀有源条130的刻蚀速度，于沟道槽210的槽壁形成多个凹陷部211，每个凹陷部211沿横向凹入到相邻的两个有源条130之间。如图39-图41所示，沉积绝缘材料的过程中，部分绝缘材料填充到凹陷部211中，在支撑结构200的侧壁形成多个凸起部220，以使支撑结构200能够为后续形成的堆叠电容器300提供更好的支撑，确保半导体结构的稳定性，避免半导体结构发生倾倒或断裂的风险。
步骤S115：去除部分牺牲层，于电容区域形成第二沟槽，第一沟槽和第二沟槽连通，暴露出位于电容区域的有源条的侧壁。
本实施例中，如图42-图45所示，参照图39-图41以及图35，可以通过干法或湿法刻蚀去除位于电容区域1011，通过控制条件，以使刻蚀工艺对有源条130的材料具有高刻蚀选择比，刻蚀去除电容区域1011中全部的牺牲层121以及介质层123，在电容区域1011中牺牲层121被去除的位置形成第二沟槽150，第二沟槽150和第一沟槽140连通。在垂直于衬底110的平面上，电容区域1011中的有源条130和第二沟槽150交替设置，相邻的有源条130被第二沟槽150隔开。
步骤S120：于电容区域形成介电层，介电层覆盖有源条暴露的侧壁。
在本实施例中，如图46-图49所示，参照图42-图45，可以通过原子层沉积工艺(Atomic Layer Deposition，ALD)沉积介电材料，介电材料覆盖位于电容区域1011中的有源条130的侧壁，形成介电层320。介电层320的材料可以包括钛酸锶(SrTiO 3)、氧化铝(Al 2O 3)、氧化锆(ZrO)或氧化铪(HfO 2)中的至少一种。
步骤S130：于电容区域形成上电极，上电极覆盖介电层并填充位于电容区域中的第一沟槽和第二沟槽。
如图50-图53所示，参照图46-图49，通过化学气相沉积工艺、物理气相沉积工艺(Physical Vapor Deposition，PVD)、原子层沉积工艺或溅射(sputtering)中的任一种沉积工艺沉积上电极材料，上电极材料覆盖介电层320并填充电容区域1011中的第一沟槽140和第二沟槽150，形成上电极330，以每个有源条130位于电容区域1011的部分结构作为下电极310，上电极330、介电层320和下电极310共同形成垂直堆叠在衬底110上的堆叠电容器300。
如图50-图53所示，本实施例的制作方法形成的堆叠电容器，上电极填满了位于电容区域中的第一沟槽和第二沟槽，增加了堆叠电容器中上电极的占比，增加了堆叠电容器的存储空间，减小了尺寸 微缩对半导体结构的工艺挑战和良率问题。
本实施例是对上述实施例的一种可能的实施方式的进一步说明。本实施例和上述实施例相比，增加了以下步骤：通过离子注入向位于电容区域中的有源条注入掺杂离子。本步骤在步骤S110提供第一结构之后执行，且本步骤在步骤S120于电容区域形成介电层之前执行。
本实施例中，向位于电容区域1011中的有源条130中注入掺杂离子，提高位于电容区域1011中的有源条130的材料中掺杂离子的浓度，调节位于电容区域1011中的有源条130的电阻，以使形成的堆叠电容器300具有更好的电性能。
根据一个示例性实施例，本实施例是对上述实施例的步骤S110的一种可能的实施方式的进一步说明。
在实施过程中，提供第一结构，还包括阵列区102的制程，阵列区102的制程在步骤S112于堆叠结构中形成多条第一沟槽之后执行，且阵列区的制程在步骤S114于第一区域形成支撑结构之前执行，阵列区的制程包括以下步骤：
步骤S101：于阵列区形成多条字线，每条字线垂直设置在衬底上，在平行于衬底的平面上，任意相邻的两条字线间隔设置，每条字线和多个有源条中的部分有源条相交，并且每条字线覆盖部分有源条的部分侧壁。
在本实施例中，于阵列区102形成多条字线400，可以采用以下方式：
首先，如图12、图13所示，参照图9、图10，去除位于阵列区102的牺牲层121，在阵列区102中牺牲层121被去除的位置形成第三沟槽160，第三沟槽160和第一沟槽140连通，暴露出位于阵列区102的有源条130的侧壁。
然后，如图14、图15所示，参照图12、图13，通过原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺中的任一种沉积工艺，沉积形成初始栅氧层401，初始栅氧层401覆盖位于阵列区102中的有源条130的侧壁。其中，初始栅氧层401的材料可以包括氧化硅或氮氧化硅中的至少一种。
如图16、图17所示，参照图14、图15，通过上述任一种沉积工艺沉积形成初始高K介质层402，初始高K介质层402覆盖初始栅氧层401。初始高K介质层402的材料可以包括金属硅酸盐或金属氧化硅。示例性的，初始高K介质层402的材料可以包括氧化钽(Ta 2O 5)、氧化钛(TiO 2)、氧化锆(ZrO 2)、氧化铝(Al 2O 3)氧化铪硅(HfSiO 2)或氧化铪(HfO 2)中的至少一种。
接着，通过上述任一种沉积工艺沉积形成初始字线层(图中未示出)，初始字线层覆盖初始高K介质层402并填充第一沟槽140以及第三沟槽160。初始字线层的材料可以包括导电金属、掺杂半导体材料或金属-半导体化合物材料。示例性的，初始字线层的材料可以包括金属钛(Titanium)、金属钽(Tantalum)、金属钨(Tungsten)或其合金中的一种，或者初始字线层的材料可以包括掺杂单晶硅或多晶硅中的一种。
然后，如图18、图19所示，参照图16、图17，刻蚀去除部分初始字线层、初始高K介质层402以及初始栅氧层401，形成多条独立设置的字线400，每条字线400垂直设置在衬底110上，在平行于衬底110的平面上，任意相邻的两条字线400间隔设置，每条字线400和多个有源条130中的部分有源条130相交，并且每条字线400覆盖部分有源条130的部分侧壁。每条字线400包括依次覆盖有源条的栅氧层410、高K介质层420以及字线层430。
本实施例中，多条字线400沿第二方向D2排成两排，每个有源条130和两条字线400相交。
步骤S102：形成源极层和漏极层。
在本实施例中，形成源极层440和漏极层450，可以采用以下方式：
如图20、图21所示，参照图18、图19，可以基于第一沟槽140和第三沟槽160刻蚀阵列区102中的有源条130，刻蚀处理后，在阵列区102中，被第一沟槽140和第三沟槽160暴露的有源条130的厚度比被字线400覆盖的有源条130的厚度薄。
然后，如图22、图23所示，参照图20、图21，阵列区102中暴露的有源条130作为籽晶，通过外延生长在字线400两侧的有源条130上形成源极层440和漏极层450。源极层440和漏极层450可以覆盖部分栅氧层410的侧壁，但源极层440、漏极层450和高K介质层420以及字线层430不接触，避免相邻的字线400发生短路。
如图22、图23所示，在本示例中，和同一有源条130连接的两条字线400共用源极层440。在其它示例中，和同一有源条130连接的两条字线400可以共用漏极层450。
在其它实施例中，可以通过离子注入工艺在每个字线400两侧的有源条130中分别形成源区和漏区。
步骤S103：形成第一隔离层。
如图24、图25所示，参照图22、图23，可以通过化学气相沉积工艺或物理气相沉积工艺沉积低K介质材料，低K介质材料至少填充位于阵列区102的第一沟槽140以及第三沟槽160中未被填充的区域，形成第一隔离层610。第一隔离层610的材料可以包括氧化硅、氮化硅或氮氧化硅中的至少一种。在一些实施例中，低K介质材料还可以填充位于第一区域101中的第一沟槽140，在第一区域101形成介质层123。
步骤S104：于阵列区形成多条位线，每条位线沿第二方向延伸，第二方向位于平行于衬底的平面，且第二方向和第一方向垂直，在垂直于衬底的平面上，任意相邻的两条位线间隔设置，每条位线和多个有源条中的部分有源条相交，并且每条位线覆盖部分有源条的部分侧壁。
在本实施例中，于阵列区102形成多条位线500，可以采用以下方式：
首先，如图26、图27所示，参照图24、图25，刻蚀阵列区102，去除部分第一隔离层610、部分源极层440以及部分有源条130，形成位线沟槽510，位线沟槽510沿第二方向D2延伸，且位线沟槽510暴露出衬底110的部分顶面。
然后，如图28-图30所示，参照图26、图27，于位线沟槽510中交替形成第二隔离层620和位线500，在垂直于衬底110的顶面的平面上，第二隔离层620和位线500交替排列。其中，每条位线500沿第二方向D2延伸并覆盖位于其两侧的有源条130的侧壁。
如图28-图30所示，阵列区102中的第一隔离层610和第二隔离层620共同形成隔离结构600，隔离结构600填充字线400和字线400之间的间隙、位线500和位线500之间的间隙以及多条字线400和多条位线500之间的间隙，以免阵列区102中的器件发生短路造成半导体结构漏电，确保半导体结构具有良好的电性能。
本实施例形成的半导体结构，形成了垂直设置在衬底上的字线，字线环绕有源条的部分侧壁形成了GAA(Gate All Around，环绕式栅极)结构，减少了尺寸微缩带来的工艺挑战和良率问题。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的半导体结构及半导体结构的制作方法中，通过增加在垂直方向上堆叠设置的堆叠电容器，以使半导体结构具有多层堆叠的3D构架，从而增加了半导体结构的存储密度，并且，堆叠电容器具有可增加的堆叠层数，因此本公开所提供的半导体结构具有可不断增加的存储密度，极大地提升了半导体结构的电性能。

Claims (16)

  1. 一种半导体结构，所述半导体结构包括衬底和设置于所述衬底上的至少一个存储器单元，每个所述存储器单元包括：
    多个有源条，多个所述有源条阵列排布在所述衬底上方，每个所述有源条沿第一方向延伸，在平行于所述衬底的平面上，任意相邻的两个所述有源条被第一沟槽隔开，在垂直于所述衬底的平面上，任意相邻的两个所述有源条被第二沟槽隔开；
    至少一组堆叠电容器，相邻的两组所述堆叠电容器间隔设置，每组所述堆叠电容器包括下电极、覆盖所述下电极的侧壁的介电层以及上电极，所述下电极包括穿过所述堆叠电容器的每个所述有源条的部分结构，所述上电极覆盖所述介电层并填充位于所述下电极之间的所述第一沟槽和所述第二沟槽。
  2. 根据权利要求1所述的半导体结构，其中，所述半导体结构包括多个存储器单元，多个所述存储器单元沿所述第一方向循环排布在所述衬底上。
  3. 根据权利要求2所述的半导体结构，所述半导体结构还包括：
    支撑结构，所述支撑结构设置在所述衬底上，所述支撑结构设置在相邻的所述存储器单元之间，所述支撑结构连接相邻的存储器单元的两个堆叠电容器。
  4. 根据权利要求3所述的半导体结构，其中，所述支撑结构的材料包括绝缘材料。
  5. 根据权利要求3所述的半导体结构，其中，所述堆叠电容器还包括：
    多个凹陷部，多个所述凹陷部设置在所述堆叠电容器的靠近所述支撑结构的一端，每个所述凹陷部设置于相邻的两个所述有源条之间，每个所述凹陷部朝向所述支撑结构设置。
  6. 根据权利要求5所述的半导体结构，其中，所述支撑结构还包括：
    凸起部，所述凸起部设置于所述支撑结构的侧壁，每个所述凸起部与所述凹陷部对应设置，每个所述凸起部嵌入至所述凹陷部中。
  7. 根据权利要求1所述的半导体结构，其中，每个所述存储器单元还包括：
    阵列区，所述阵列区设置于相邻的两组所述堆叠电容器之间，所述阵列区通过多个所述有源条与所述堆叠电容器连接。
  8. 根据权利要求7所述的半导体结构，其中，所述阵列区包括：
    多条字线，每条所述字线垂直设置在所述衬底上，在平行于所述衬底的平面上，任意相邻的两条所述字线间隔设置，每条所述字线和多个所述有源条中的部分所述有源条相交，并且每条所述字线覆盖部分所述有源条的部分侧壁；
    多条位线，每条所述位线沿第二方向延伸，所述第二方向位于平行于所述衬底的平面，且所述第二方向和所述第一方向垂直，在垂直于所述衬底的平面上，任意相邻的两条所述位线间隔设置，每条所述位线和多个所述有源条中的部分所述有源条相交，并且每条所述位线覆盖部分所述有源条的部分侧壁；
    多条所述字线和多条所述位线通过隔离结构隔开。
  9. 根据权利要求7所述的半导体结构，其中，在所述第一方向上，每个所述存储器单元包括对称设置在所述阵列区两侧的两组所述堆叠电容器。
  10. 一种半导体结构的制作方法，所述半导体结构的制作方法包括：
    提供第一结构，所述第一结构包括电容区域，所述第一结构包括衬底以及多个有源条，多个所述有源条阵列排布在所述衬底上方，每个所述有源条沿第一方向延伸，所述电容区域中，在平行于所述衬底的平面上，任意相邻的两个所述有源条被第一沟槽隔开，在垂直于所述衬底的平面上，任意相邻的两个所述有源条被第二沟槽隔开，所述第二沟槽和所述第一沟槽连通并暴露出位 于所述电容区域的所述有源条的侧壁；
    于所述电容区域形成介电层，所述介电层覆盖所述有源条暴露的侧壁；
    于所述电容区域形成上电极，所述上电极覆盖所述介电层并填充位于所述电容区域中的所述第一沟槽和所述第二沟槽；
    以每个所述有源条位于所述电容区域的部分结构作为下电极，所述上电极、所述介电层和所述下电极形成垂直堆叠在所述衬底上的堆叠电容器。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，提供第一结构，包括：
    提供衬底，在所述衬底上形成堆叠结构，所述堆叠结构包括依次交替堆叠的有源层和牺牲层；
    于所述堆叠结构中形成多条第一沟槽，每条所述第一沟槽沿所述第一方向延伸，且在垂直于所述衬底的方向上，每条所述第一沟槽贯穿所述堆叠结构，被保留的所述有源层被所述第一沟槽划分成多个所述有源条；
    去除部分所述牺牲层，于所述电容区域形成所述第二沟槽，所述第一沟槽和所述第二沟槽连通，暴露出位于所述电容区域的所述有源条的侧壁。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，所述第一结构还包括第一区域，所述电容区域位于所述第一区域中，所述制作方法还包括：
    于所述第一区域形成支撑结构，所述支撑结构沿第二方向延伸并贯穿所述第一结构，所述第二方向位于平行于所述衬底的平面，且所述第二方向和所述第一方向垂直，所述支撑结构将所述第一区域划分成两个独立设置的所述电容区域。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，形成支撑结构，包括：
    刻蚀所述第一区域，于所述第一区域形成沟道槽，所述沟道槽沿所述第二方向延伸并贯穿所述第一结构，且所述沟道槽暴露出部分所述衬底；
    沉积绝缘材料填充所述沟道槽，形成所述支撑结构。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，刻蚀所述第一区域时，刻蚀所述牺牲层的刻蚀速度大于刻蚀所述有源条的刻蚀速度，于所述沟道槽的槽壁形成多个凹陷部，每个所述凹陷部沿横向凹入到相邻的两个所述有源条之间；
    部分所述绝缘材料填充到所述凹陷部中，在所述支撑结构的侧壁形成多个凸起部。
  15. 根据权利要求11所述的半导体结构的制作方法，其中，所述第一结构还包括阵列区，所述提供第一结构，还包括：
    去除位于所述阵列区的所述牺牲层；
    于所述阵列区形成多条字线，每条所述字线垂直设置在所述衬底上，在平行于所述衬底的平面上，任意相邻的两条所述字线间隔设置，每条所述字线和多个所述有源条中的部分所述有源条相交，并且每条所述字线覆盖部分所述有源条的部分侧壁；
    于所述阵列区形成多条位线，每条所述位线沿第二方向延伸，所述第二方向位于平行于所述衬底的平面，且所述第二方向和所述第一方向垂直，在垂直于所述衬底的平面上，任意相邻的两条所述位线间隔设置，每条所述位线和多个所述有源条中的部分所述有源条相交，并且每条所述位线覆盖部分所述有源条的部分侧壁。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，所述提供第一结构，还包括：
    于所述阵列区形成隔离结构，所述隔离结构填充多条所述字线和多条所述位线之间的间隙。
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