WO2023206669A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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Publication number
WO2023206669A1
WO2023206669A1 PCT/CN2022/094233 CN2022094233W WO2023206669A1 WO 2023206669 A1 WO2023206669 A1 WO 2023206669A1 CN 2022094233 W CN2022094233 W CN 2022094233W WO 2023206669 A1 WO2023206669 A1 WO 2023206669A1
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Prior art keywords
layer
support
capacitor
substrate
semiconductor structure
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PCT/CN2022/094233
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English (en)
French (fr)
Inventor
邵光速
肖德元
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长鑫存储技术有限公司
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Priority to JP2022562336A priority Critical patent/JP2024521595A/ja
Priority to EP22786872.6A priority patent/EP4294145A4/en
Priority to KR1020227032918A priority patent/KR20220137772A/ko
Priority to US17/940,952 priority patent/US20230005920A1/en
Publication of WO2023206669A1 publication Critical patent/WO2023206669A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a manufacturing method of the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line.
  • Capacitors usually include a stacked upper electrode layer, a dielectric layer and a lower electrode layer. However, there is still a problem in the related art that the capacitor capacity is small.
  • a first aspect of an embodiment of the present disclosure provides a semiconductor structure, including: a first capacitor structure and a first support pillar located on a substrate. A plurality of the first support pillars are arranged parallel to each other and spaced apart on the substrate. The first support pillars are located in the same plane parallel to the substrate.
  • the first capacitor structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer. The first lower electrode layer Covering the sidewall surface of the first support pillar and the substrate, the first dielectric layer covers the first lower electrode layer, and the first upper electrode layer covers the first dielectric layer. on layer;
  • the first capacitor structure is divided into a plurality of capacitors, a first insulating layer is provided between the first lower electrode layers corresponding to the adjacent capacitors, and the first insulating layer covers the first divided channel corresponding to the first insulating layer.
  • the sidewall surface of the first support pillar and the substrate are electrically connected to the first upper electrode layer corresponding to the adjacent capacitor.
  • a second aspect of the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • first support columns Forming a plurality of first support columns, the plurality of first support columns are arranged on the base parallel to each other and at intervals, and the plurality of first support columns are located in the same plane parallel to the base;
  • a first capacitor structure is formed.
  • the first capacitor structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer.
  • the first lower electrode layer covers the sidewall surface of the first support pillar and The substrate, the first dielectric layer covers the first lower electrode layer, and the first upper electrode layer covers the first dielectric layer;
  • a plurality of first divided channels are formed, and the plurality of first divided channels are arranged on the substrate in parallel and at intervals, and the extending direction of the first divided channels is perpendicular to the first support column, so
  • the first dividing channel divides the first capacitor structure into a plurality of capacitors
  • a first insulating layer is formed in the first divided channel, the first insulating layer is located between the first lower electrode layers adjacent to the capacitor, and the first insulating layer covers the first divided channel.
  • Conductive material is filled in the first divided trench to electrically connect the first upper electrode layers corresponding to adjacent capacitors.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, including a first capacitor structure and a first support pillar located on a substrate.
  • a plurality of first support pillars are spaced and arranged on the substrate in parallel.
  • a plurality of first support pillars are arranged on the substrate.
  • the support pillars are located in the same plane parallel to the base.
  • the first capacitor structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer.
  • the first lower electrode layer covers the sidewall surface of the first support pillar and the base.
  • the first dielectric layer covers the first lower electrode layer, and the first upper electrode layer covers the first dielectric layer; it also includes a plurality of first divided channels spaced apart and arranged parallel to the substrate, the first divided channels The extending direction of the channel is perpendicular to the first support pillar.
  • the first dividing channel divides the first capacitor structure into multiple capacitors.
  • a first insulating layer is provided between the first lower electrode layers corresponding to adjacent capacitors.
  • the first insulating layer The layer covers the sidewall surface and the base of the first support pillar corresponding to the first divided channel, and is electrically connected between the first upper electrode layers corresponding to adjacent capacitors.
  • Adjacent capacitors are isolated by the first insulating layer, the first lower electrode layers corresponding to the adjacent capacitors are electrically connected together through the first support pillar, and the first upper electrode layers corresponding to the adjacent capacitors are electrically connected so that the adjacent capacitors are electrically connected together.
  • the parallel connection of adjacent capacitors is beneficial to increasing the capacitance and thereby improving the performance of the semiconductor structure.
  • Figure 1a is a schematic structural diagram 1 of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 1b is a second structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 1c is a cross-sectional view of Figure 1a at A1-A1;
  • Figure 1d is a partial enlarged view of Figure 1c at B;
  • Figure 2 is a step flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of forming a sacrificial layer on a substrate in a method of manufacturing a semiconductor structure
  • Figure 4a is a schematic structural diagram of forming a first trench in a method of manufacturing a semiconductor structure
  • Figure 4b is a structural schematic diagram 2 of forming the first trench in the manufacturing method of a semiconductor structure
  • Figure 4c is a cross-sectional view at A2-A2 of Figure 4a;
  • Figure 5a is a structural schematic diagram 1 of forming a filling layer in the manufacturing method of a semiconductor structure
  • Figure 5b is a schematic diagram 2 of the structure of forming a filling layer in the manufacturing method of a semiconductor structure
  • Figure 5c is a cross-sectional view at A3-A3 of Figure 5a;
  • Figure 6a is a structural schematic diagram 1 of forming a second trench in the manufacturing method of a semiconductor structure
  • Figure 6b is a second structural schematic diagram of forming a second trench in a method of manufacturing a semiconductor structure
  • Figure 7a is a structural schematic diagram 1 of forming a filled trench in a method of manufacturing a semiconductor structure
  • Figure 7b is a schematic diagram 2 of the structure of forming a filled trench in the manufacturing method of a semiconductor structure
  • Figure 7c is a cross-sectional view at A4-A4 of Figure 7a;
  • Figure 8a is a structural schematic diagram 1 of forming the first support pillar in the manufacturing method of a semiconductor structure
  • Figure 8b is a structural schematic diagram 2 of forming the first support pillar in the manufacturing method of a semiconductor structure
  • Figure 8c is a cross-sectional view at A5-A5 of Figure 8a;
  • Figure 9a is a structural schematic diagram 1 of forming a third trench in the manufacturing method of a semiconductor structure
  • Figure 9b is a schematic diagram 2 of the structure of forming the third trench in the manufacturing method of a semiconductor structure
  • Figure 10a is a structural schematic diagram 1 of forming filled sidewalls in the manufacturing method of a semiconductor structure
  • Figure 10b is a structural schematic diagram 2 of forming filled sidewalls in the manufacturing method of a semiconductor structure
  • Figure 11a is a structural schematic diagram 1 of forming the first support layer in the manufacturing method of a semiconductor structure
  • Figure 11b is a structural schematic diagram 2 of forming the first support layer in the manufacturing method of a semiconductor structure
  • Figure 12a is a structural schematic diagram 1 of removing part of the sacrificial layer and the filling layer in the manufacturing method of a semiconductor structure;
  • Figure 12b is a schematic diagram 2 of the structure in which part of the sacrificial layer and the filling layer are removed in the manufacturing method of the semiconductor structure;
  • Figure 12c is a cross-sectional view at A6-A6 of Figure 12a;
  • Figure 13a is a schematic diagram 1 of the structure of forming the first lower electrode layer in the manufacturing method of a semiconductor structure
  • Figure 13b is a schematic diagram 2 of the structure of forming the first lower electrode layer in the manufacturing method of a semiconductor structure
  • Figure 14a is a structural schematic diagram 1 of forming the first dielectric layer and the first upper electrode layer in the manufacturing method of a semiconductor structure
  • Figure 14b is a schematic diagram 2 of the structure of forming the first dielectric layer and the first upper electrode layer in the manufacturing method of a semiconductor structure;
  • Figure 15a is a structural schematic diagram 1 of removing part of the intermediate support layer in the manufacturing method of a semiconductor structure
  • Figure 15b is a schematic diagram 2 of the structure in which part of the intermediate support layer is removed in the manufacturing method of the semiconductor structure;
  • Figure 16a is a structural schematic diagram 1 of forming a second support layer in a method of manufacturing a semiconductor structure
  • Figure 16b is a schematic diagram 2 of the structure of forming the second support layer in the manufacturing method of a semiconductor structure
  • Figure 17a is a structural schematic diagram 1 of forming a first divided channel in a method of manufacturing a semiconductor structure
  • Figure 17b is a structural schematic diagram 2 of forming the first divided channel in the manufacturing method of a semiconductor structure
  • Figure 18a is a schematic diagram 1 of the structure of forming the first insulating layer in the manufacturing method of a semiconductor structure
  • Figure 18b is a schematic diagram 2 of the structure of forming the first insulating layer in the manufacturing method of a semiconductor structure
  • Figure 19a is a schematic diagram 1 of a structure filled with conductive material in the manufacturing method of a semiconductor structure
  • Figure 19b is a schematic diagram 2 of a structure filled with conductive material in the manufacturing method of a semiconductor structure
  • Figure 19c is a cross-sectional view of Figure 19a at A1-A1;
  • Figure 19d is a partial enlarged view of Figure 19c at B.
  • embodiments of the present disclosure provide a semiconductor structure, including a first capacitor structure 41 and a first support pillar 331 located on a substrate 10 .
  • a plurality of first support columns 331 are arranged on the base 10 in parallel and spaced apart from each other, and the plurality of first support columns 331 are located in the same plane parallel to the base 10 .
  • the first capacitor structure 41 can be supported to prevent the capacitor structure from collapsing.
  • the material of the first support pillar 331 includes single crystal silicon, single crystal germanium, single crystal silicon germanium, or IGZO, thereby ensuring that the first support pillar 331 supports the first capacitor structure 41 .
  • IGZO indium gallium zinc oxide
  • the material of the first support pillar 331 may be IGZO, which is beneficial to improving the performance of the first capacitor structure 41 .
  • the first capacitor structure 41 includes a first lower electrode layer 411, a first dielectric layer 412 and a first upper electrode layer 413.
  • the first lower electrode layer 411 covers the sidewall surface of the first support pillar 331 and the substrate 10
  • the first dielectric layer 412 covers the first lower electrode layer 411 . 1a and 1c, it can be seen that in the first capacitor structure 41, a part of the first lower electrode layer 411 is arranged around the first support pillar 331, a part of the first dielectric layer 412 is arranged around the first lower electrode layer 411, and a part of the first lower electrode layer 411 is arranged around the first support pillar 331.
  • the lower electrode layer 411 and part of the first dielectric layer 412 also cover the substrate 10; in the first capacitor structure 41, the first upper electrode layer 413 covers the first dielectric layer 412.
  • the plurality of first support pillars 331 and the first capacitor structure 41 together constitute the first capacitor component 61 .
  • a plurality of stacked first capacitor components 61 are provided on the substrate 10 .
  • three stacked first capacitor components 61 may be provided on the substrate 10 .
  • the corresponding first upper electrode layers 413 of adjacent first capacitor components 61 are electrically connected.
  • the first upper electrode layers 413 corresponding to adjacent first capacitor components 61 may be connected through a conductive layer, and the material of the conductive layer may include, for example, metal or metal alloy.
  • the first upper electrode layers 413 corresponding to the adjacent first capacitor components 61 can also be directly joined together, so that the phases Adjacent first capacitor components 61 share the same first upper electrode layer 413 .
  • first dividing channels 51 may be provided.
  • the extending direction of the first dividing channels 51 is perpendicular to the extending direction of the first support column 331 , and the extending direction of the first dividing channels 51 is also perpendicular to the extending direction of the first supporting pillar 331 .
  • Base 10 is vertical.
  • the two first dividing channels 51 can divide the first capacitor structure 41 into three capacitors, and the three capacitors are arranged along the X-axis direction.
  • the first dividing channel 51 can also divide the plurality of first capacitor components 61 into a plurality of capacitors. For example, in this embodiment, there are three stacked first capacitor components 61, and each first capacitor component 61 is divided into three capacitors by two first dividing channels 51. That is, in this embodiment, the substrate There are a total of nine capacitors on the 10.
  • a first insulating layer 511 is provided between the first lower electrode layers 411 corresponding to adjacent capacitors.
  • the first insulating layer 511 The sidewall surface of the first support pillar 331 corresponding to the first divided channel 51 and the substrate 10 are covered, so that the first lower electrode layer 411 corresponding to adjacent capacitors is isolated by the first insulating layer 511 .
  • the first insulating layer 511 is located in the area where the first divided trench 51 is located, and part of the first insulating layer 511 is arranged around the first support pillar 331 , and part of the first insulating layer 511 also covers the substrate 10 .
  • the first upper electrode layers 413 corresponding to adjacent capacitors are electrically connected.
  • the first upper electrode layers 413 corresponding to adjacent capacitors may be connected through a conductive layer, and the material of the conductive layer may include, for example, metal or metal alloy.
  • the first upper electrode layers 413 corresponding to adjacent capacitors can also be directly joined together. That is, the first upper electrode layers 413 corresponding to adjacent capacitors also cover the first insulating layer 511. So that adjacent capacitors share the same first upper electrode layer 413.
  • the first lower electrode layers 411 corresponding to adjacent capacitors can be electrically connected together through the first support pillar 331, and the first upper electrode layers 413 corresponding to adjacent capacitors are electrically connected to each other, so that the adjacent capacitors can Achieving parallel connection is beneficial to increasing the capacitance of the first capacitor component 61, thereby improving the performance of the semiconductor structure.
  • the embodiment of the present disclosure provides a semiconductor structure, including a first capacitor structure 41 and a first support pillar 331 located on a substrate 10.
  • a plurality of first support pillars 331 are arranged parallel to each other and spaced apart on the substrate 10.
  • a plurality of first support pillars 331 are arranged on the substrate 10.
  • the support pillar 331 is located in the same plane parallel to the substrate 10.
  • the first capacitor structure 41 includes a first lower electrode layer 411, a first dielectric layer 412 and a first upper electrode layer 413.
  • the first lower electrode layer 411 covers the first support On the sidewall surface of the pillar 331 and the substrate 10, the first dielectric layer 412 covers the first lower electrode layer 411, and the first upper electrode layer 413 covers the first dielectric layer 412; it also includes a plurality of mutually parallel and The first divided channels 51 are arranged at intervals on the substrate 10. The extending direction of the first divided channels 51 is perpendicular to the first support pillar 331. The first divided channels 51 divide the first capacitor structure 41 into a plurality of capacitors. A first insulating layer 511 is disposed between the first lower electrode layer 411 corresponding to the adjacent capacitor.
  • the first insulating layer 511 covers the sidewall surface of the first support pillar 331 corresponding to the first divided channel 51 and the substrate 10, adjacent to The first upper electrode layers 413 corresponding to the capacitors are electrically connected. Adjacent capacitors are isolated by the first insulating layer 511. The first lower electrode layers 411 corresponding to the adjacent capacitors are electrically connected together through the first support pillar 331. The first upper electrode layers 413 corresponding to the adjacent capacitors are electrically connected. Connection enables adjacent capacitors to be connected in parallel, which is beneficial to increasing capacitance and thereby improving the performance of the semiconductor structure.
  • the material of the first insulating layer 511 may include a high dielectric constant material, silicon oxide, silicon nitride or silicon oxynitride to improve the insulation effect between the first lower electrode layers 411 corresponding to adjacent capacitors.
  • the material of the first insulating layer 511 may be a high dielectric constant material.
  • high dielectric constant materials refer to materials whose dielectric constant is higher than silicon dioxide and have good insulation properties.
  • they may include ferroelectric materials, metal oxides, etc.
  • the material of the first insulating layer 511 can be a high dielectric constant material, thereby further improving the insulation performance between the first lower electrode layers 411 corresponding to adjacent capacitors and realizing parallel connection between adjacent capacitors.
  • the thickness H3 of the first insulating layer 511 is greater than the thickness H1 of the first lower electrode layer 411 and less than the sum H2 of the thicknesses of the first lower electrode layer 411 and the first dielectric layer 412 .
  • the thickness H3 of the first insulating layer 511 is greater than the thickness H1 of the first lower electrode layer 411, which is beneficial to ensuring the insulation performance between the first lower electrode layers 411 corresponding to adjacent capacitors.
  • the thickness H3 of the first insulating layer 511 is less than The sum H2 of the thickness of the first lower electrode layer 411 and the first dielectric layer 412 , that is, the plane of the first insulating layer 511 is located between the first dielectric layer 412 and the first lower electrode layer 411 , which can also facilitate communication.
  • the first upper electrode layers 413 corresponding to adjacent capacitors are electrically connected, thereby ensuring parallel connection between adjacent capacitors.
  • the semiconductor structure further includes a first support layer 351 and a second support layer 322 covering the substrate 10 .
  • the first support layer 351 may be disposed on the right side of the first capacitor component 61
  • the second support layer 322 may be disposed on the left side of the first capacitor component 61, so that the first capacitor component 61 is located on the first support between layer 351 and second support layer 322.
  • the first support layer 351 and the second support layer 322 surround the side wall surface of the first support pillar 331 , so that the first support pillar 331 is disposed on the substrate 10 through the first support layer 351 and the second support layer 322 .
  • the materials of the first support layer 351 and the second support layer 322 may include silicon nitride, silicon oxynitride, silicon oxide, etc.
  • the first dielectric layer 412 also covers the side walls of the first support layer 351 and the second support layer 322, which is beneficial to ensuring that the first upper electrode layer 413 is connected to the first support layer 351 and the second support layer 351, respectively. The insulation performance between the two support layers 322.
  • the semiconductor structure also includes an isolation portion 70 and a plurality of second capacitor components 62 located on the substrate 10.
  • the substrate 10 In the direction perpendicular to the substrate 10 (that is, along the Y-axis direction), the substrate 10 is provided with a plurality of second capacitor components 62.
  • the isolation part 70 is located between the first capacitor component 61 and the second capacitor component 62
  • the second capacitor component 62 and the first capacitor component 61 are arranged symmetrically with respect to the isolation part 70 .
  • the first capacitor component 61 is located on the left side of the isolation part 70
  • the second capacitor structure 42 is located on the right side of the isolation part 70
  • the second capacitor component 62 has the same structure as the first capacitor component 61 .
  • first capacitor component 61 and the second capacitor component 62 are the same, so that the first capacitor component 61 and the second capacitor component 62 can be formed simultaneously.
  • a plurality of second capacitor components 62 are arranged in a stack on the substrate 10 . Between adjacent second capacitor components 62 connection between.
  • the second capacitor component 62 includes a plurality of second support pillars 332 and a second capacitor structure 42 , wherein the plurality of second support pillars 332 are arranged parallel to each other and spaced apart on the substrate 10 , and each second support pillar 332 is connected to a second capacitor structure 42 .
  • the corresponding first support pillars 331 are connected.
  • the second capacitor structure 42 includes a second lower electrode layer 421, a second dielectric layer 422 and a second upper electrode layer 423.
  • the second lower electrode layer 421 covers the side of the second support pillar 332.
  • the second dielectric layer 422 covers the second lower electrode layer 421, and the second upper electrode layer 423 covers the second dielectric layer 422.
  • the second upper electrode layers 423 corresponding to the adjacent second capacitor components 62 are electrically connected.
  • the second upper electrode layers 423 corresponding to adjacent capacitors can also be directly joined together. That is, the second upper electrode layers 423 corresponding to adjacent capacitors also cover the second insulating layer 521. So that the second upper electrode layers 423 corresponding to adjacent capacitors are electrically connected.
  • the second lower electrode layers 421 corresponding to adjacent capacitors can be electrically connected together through the second support pillar 332, and the second upper electrode layers 423 corresponding to adjacent capacitors are electrically connected, so that the adjacent capacitors Achieving parallel connection is beneficial to increasing the capacitance of the second capacitor component 62, thereby improving the performance of the semiconductor structure.
  • the plurality of second capacitor components 62 also include a plurality of second divided trenches 52 arranged parallel to each other and spaced apart on the substrate 10 .
  • the extending direction of the second divided trenches 52 is perpendicular to the second support pillar 332 .
  • the second divided trenches Tracks 52 divide the second capacitor structure 42 in any layer into multiple capacitors.
  • a second insulating layer 521 is provided between the second lower electrode layers 421 of adjacent capacitors.
  • the layer 521 covers the sidewall surface of the second support pillar 332 corresponding to the second split channel 52 and the substrate 10, and the second upper electrode layer 423 corresponding to the adjacent capacitor is connected, so that the second lower electrode layer corresponding to the adjacent capacitor is connected. 421 are isolated by the second insulating layer 521 .
  • the third support layer 352 is provided on the left side of the second capacitor component 62
  • the fourth support layer 323 is provided on the right side of the second capacitor component 62 , so that the second capacitor component 62 is located between the third support layer 352 and the third support layer 352 . between four support layers 323.
  • the third support layer 352 and the fourth support layer 323 surround the side wall surface of the second support column 332, and the third support layer 352 and the fourth support layer 323 surround the side wall surface of the second support column 332, so that the second support column 332 is disposed on the substrate 10 through the third support layer 352 and the fourth support layer 323 .
  • the second dielectric layer 422 also covers the side walls of the third support layer 352 and the fourth support layer 323, which is beneficial to ensuring the insulation between the second upper electrode layer 423 and the third support layer 352 and the fourth support layer 323 respectively. performance.
  • the isolation part 70 is also located between the first support layer 351 and the third support layer 352 , and the isolation part 70 is also disposed around the side walls of the first support column 331 and the second support column 332 .
  • the isolation part 70 also includes an intermediate support layer 321. One side of the intermediate support layer 321 is connected to the first support column 331, and the other side of the intermediate support layer 321 is connected to the second support column 332, so that the first support column 331 and the second support column 332 are connected.
  • the two support pillars 332 are electrically connected together through the middle support layer 321 .
  • the middle support layer 321, the first support pillar 331 and the second support pillar 332 are made of the same material so that they can be formed simultaneously through the same deposition process, thereby improving the production efficiency of the semiconductor structure.
  • the isolation part 70 also includes a sacrificial layer 20. Part of the sacrificial layer 20 is located between the middle support layer 321 and the first support layer 351, and part of the sacrificial layer 20 is arranged around the side wall of the first support column 331; part of the sacrificial layer 20 is also located in the middle. Between the support layer 321 and the second support layer 322 , part of the sacrificial layer 20 is arranged around the side wall of the second support column 332 .
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure. Referring to FIG. 2 , the process from step S101 to step S105 is as follows:
  • Step S101 Provide a substrate.
  • the substrate may be a semiconductor substrate, such as single crystal silicon, polycrystalline silicon, amorphous silicon or silicon germanium (SiGe), or a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, Indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof.
  • a semiconductor substrate such as single crystal silicon, polycrystalline silicon, amorphous silicon or silicon germanium (SiGe)
  • a mixed semiconductor structure such as silicon carbide, indium antimonide, lead telluride, Indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof. This embodiment does not limit it here.
  • the substrate 10 also includes:
  • Step S102 Form a plurality of first support columns.
  • the plurality of first support columns are arranged on the base in parallel and spaced apart from each other.
  • the plurality of first support columns are located in the same plane parallel to the base.
  • the step of forming a plurality of first support pillars 331 includes: forming a sacrificial layer 20 covering the substrate 10 .
  • the sacrificial layer 20 includes first sacrificial layers 21 and second sacrificial layers 22 that are alternately stacked.
  • this embodiment may include multiple first sacrificial layers 21 and multiple second sacrificial layers 22, wherein the second sacrificial layer 22 is sandwiched between two adjacent first sacrificial layers 21, and part of the first sacrificial layer 22 is sandwiched between two adjacent first sacrificial layers 21.
  • the sacrificial layer 21 also covers the substrate 10 , so that the first sacrificial layer 21 and the second sacrificial layer 22 are alternately stacked on the substrate 10 .
  • the material of the first sacrificial layer 21 may include oxide
  • the material of the second sacrificial layer 22 may include nitride, so that the materials of the first sacrificial layer 21 and the second sacrificial layer 22 are distinguished for convenience. Subsequently, a portion of the sacrificial layer 20 is selectively etched.
  • the sacrificial layer 20 may also include only a first sacrificial layer 21 and a second sacrificial layer 22 , with the first sacrificial layer 21 being located between the second sacrificial layer 22 and the substrate 10 .
  • the step of forming a plurality of first support pillars 331 further includes: removing part of the sacrificial layer 20 to form a plurality of first trenches 31 , along the Z-axis direction, a plurality of first grooves 31 are arranged on the substrate 10 at intervals and parallel to each other, and the extension direction of the first grooves 31 is parallel to the Y-axis direction.
  • a portion of the sacrificial layer 20 may be etched until the substrate 10 is exposed to form a plurality of first trenches 31 .
  • the step of forming a plurality of first support pillars 331 further includes: forming a filling layer 311 in the first trench 31 .
  • the plurality of filling layers 311 are arranged parallel to each other and spaced apart on the substrate 10 along the Z-axis direction, and The extending direction of the filling layer 311 is parallel to the Y-axis direction.
  • the filling material may include polycrystalline silicon, monocrystalline silicon, etc.
  • the step of forming a plurality of first support pillars 331 further includes: removing part of the sacrificial layer 20 and part of the filling layer 311 to form a plurality of second trenches.
  • Grooves 32 along the X-axis direction, a plurality of second grooves 32 are arranged on the substrate 10 parallel to each other and spaced apart, and the extension direction of the second grooves 32 is perpendicular to the first groove 31 .
  • part of the sacrificial layer 20 and part of the filling layer 311 may be etched until the substrate 10 is exposed to form a plurality of second trenches 32 .
  • three second trenches 32 may be formed, and the three second trenches 32 divide the sacrificial layer 20 into a first area 81 and a second area 82, so that subsequent operations in the first area 81 and the second area 82 can be performed respectively.
  • a capacitive structure is further formed in region 82 .
  • the step of forming a plurality of first support pillars 331 further includes: removing part of the sacrificial layer 20 to form a plurality of filled trenches. 33.
  • a plurality of filling trenches 33 are spaced apart and arranged parallel to the first trench 31.
  • a plurality of filling channels 33 are located in the same plane parallel to the substrate 10 along the Z-axis direction. . Since the sidewalls of the second trench 32 are the sacrificial layer 20 , the sacrificial layer 20 can be exposed by providing the second trench 32 .
  • the etching selectivity of the second sacrificial layer 22 is higher than that of the first sacrificial layer 21, so that the second sacrificial layer 22 in the sacrificial layer 20 is removed, and the first sacrificial layer 21 is retained, thereby forming
  • There are a plurality of filling trenches 33 and the plurality of filling trenches 33 are located between adjacent second trenches 32 and connected with the second trenches 32 .
  • a plurality of filling trenches 33 located in the same plane parallel to the substrate 10 constitute a filling structure.
  • the sacrificial layer 20 includes first sacrificial layers 21 and second sacrificial layers 22 that are alternately stacked
  • removing the second sacrificial layer 22 in the sacrificial layer 20 and retaining the first sacrificial layer 21 also includes: vertically In the direction of the substrate 10 (that is, along the Y-axis direction), a stacked filling structure is formed on the substrate 10.
  • Each layer of the filling structure includes a plurality of filling channels 33 that are parallel to each other and arranged at intervals.
  • the step of forming a plurality of first support pillars 331 further includes: forming the first support pillars 331 in the filling trench 33 .
  • a deposition process may be used to form the first support pillar 331 in the filling trench 33 .
  • the material of the first support pillar 331 includes single crystal silicon, single crystal germanium, single crystal silicon germanium or IGZO, thereby ensuring the supporting effect of the first support pillar 331 on the first capacitor structure 41 .
  • IGZO indium gallium zinc oxide
  • the material of the first support pillar 331 may be IGZO, which is beneficial to improving the performance of the first capacitor structure 41 .
  • the first support pillars 331 in the filling trench 33 while forming the first support pillars 331 in the filling trench 33 , it also includes forming an intermediate support layer 321 in the second trench 32 . Since the filling trench 33 is connected to the second trench 32, while the first support pillar 331 is formed, a deposition process can be used to simultaneously form the intermediate support layer 321 in the second trench 32. In this embodiment, the material of the middle support layer 321 is the same as that of the first support pillar 331 , and the middle support layer 321 is joined to the first support pillar 331 .
  • the method further includes: removing part of the filling layer 311 to form a plurality of third trenches 34.
  • the plurality of third trenches 34 are mutually exclusive.
  • the third grooves 34 are arranged parallel and spaced apart on the substrate 10 , and the extending direction of the third grooves 34 is perpendicular to the first grooves 31 .
  • a portion of the filling layer 311 may be etched until the substrate 10 is exposed to form a plurality of third trenches 34 .
  • the third trench 34 further divides the sacrificial layer 20 in the first region 81 into multiple regions, so that multiple capacitors can be subsequently formed in the multiple regions.
  • the third trench 34 after forming the third trench 34, it also includes: removing the sacrificial layer 20 corresponding to the sidewall of the third trench 34, and retaining the first support pillar 331 to form a filling sidewall. 35.
  • the sacrificial layer 20 corresponding to the sidewall of the third trench 34 is removed, that is, the first sacrificial layer 21 corresponding to the sidewall of the third trench 34 is removed, and the first support pillar 331 is retained.
  • the etching selectivity of the first sacrificial layer 21 is made higher than the etching selectivity of the first support pillar 331 , the first sacrificial layer 21 is removed through an etching process, and the first support pillar 331 is retained.
  • the filling sidewall 35 after forming the filling sidewall 35, it also includes: forming a first support layer 351 in the partially filled sidewall 35, and the first support layer 351 surrounds the side of the first support column 331. wall surface.
  • the first support layer 351 may be formed in the filling sidewall 35 through a deposition process, and the material of the first support layer 351 may include, for example, nitride.
  • first support layer 351 After forming the first support layer 351, it also includes:
  • Step S103 Form a first capacitor structure.
  • the first capacitor structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer.
  • the first lower electrode layer covers the sidewall surface and base of the first support pillar.
  • a dielectric layer covers the first lower electrode layer, and the first upper electrode layer covers the first dielectric layer.
  • the step of forming the first capacitor structure 41 includes: removing part of the sacrificial layer 20 and the filling layer 311 to retain the first support pillars 331 and the first support layer 351 .
  • part of the first sacrificial layer 21 and the filling layer 311 located in the first region 81 are removed to retain the first supporting pillars 331 and the first supporting layer 351, thereby forming a filling space for subsequent filling in the filling space. Capacitance is formed within.
  • the etching selectivity ratios of the first sacrificial layer 21 and the filling layer 311 are both higher than the etching selectivity ratios of the first support pillar 331 and the first support layer 351 , and the sacrificial layer 20 and the first support layer 351 are removed through an etching process.
  • the layer 311 is filled to retain the first support pillar 331 and the first support layer 351 .
  • the method further includes: forming a first bottom layer on the first support pillar 331 and the substrate 10 located in the filling space through a selective growth process.
  • Electrode layer 411 can selectively deposit on the desired material surface.
  • the material of the first lower electrode layer 411 may include metal materials such as tungsten and titanium.
  • the first lower electrode layer is selectively deposited on the side walls of the first support pillar 331 and the surface of the substrate 10 without deposited on the sidewalls of the first support layer 351.
  • subsequent removal of the first lower electrode layer 411 on the sidewall of the first support layer 351 is avoided, thereby improving the manufacturing efficiency.
  • the first lower electrode layer 411 since the material of the middle support layer 321 is the same as the material of the first support pillar 331, the first lower electrode layer 411 also covers the middle support layer 321 located on one side of the filling space. .
  • the method further includes: forming a first dielectric layer 412 and a first upper electrode layer 413 in sequence.
  • a deposition process may be used to sequentially form the first dielectric layer 412 and the first upper electrode layer 413.
  • the material of the first dielectric layer 412 may include a high dielectric constant material, silicon oxide, silicon nitride or silicon oxynitride to achieve an insulation effect between the first upper electrode layer 413 and the first lower electrode layer 411 .
  • the material of the first upper electrode layer 413 may include metal materials such as tungsten and titanium. In this embodiment, the material of the first upper electrode layer 413 is the same as the material of the first lower electrode layer 411 .
  • a first capacitor structure 41 is formed, and further includes: the first capacitor structure 41 and a second sacrificial layer 22 .
  • a support column 331 constitutes the first capacitor component 61, and a plurality of stacked first capacitor components 61 are formed in a direction perpendicular to the substrate 10 (that is, along the Y-axis direction).
  • the corresponding first upper electrode layers 413 of adjacent first capacitor components 61 are electrically connected.
  • the first upper electrode layers 413 corresponding to adjacent first capacitor components 61 may be connected through a conductive layer, and the material of the conductive layer may include, for example, metal or metal alloy.
  • the first upper electrode layers 413 corresponding to the adjacent first capacitor components 61 can also be directly joined together, so that the phases Adjacent first capacitor components 61 share the same first upper electrode layer 413 .
  • forming a plurality of first capacitor structures 41 also includes: after sequentially forming the first dielectric layer 412 and the first upper electrode layer 413: removing part of the intermediate support layer 321; refer to Figures 16a and 16b , after removing part of the middle support layer 321, a second support layer 322 is formed in part of the second trench 32.
  • the middle support layer 321 located on the left side of the first capacitor structure 41 can be removed to form the second trench 32, and the second support layer 322 is formed in the second trench 32, and the second support layer 322 is provided.
  • the material of the second support layer 322 may include nitride.
  • the material of the second support layer 322 may be the same as the material of the first support layer 351 .
  • Step S104 Form a plurality of first divided channels.
  • the plurality of first divided channels are arranged on the substrate in parallel and at intervals.
  • the extension direction of the first divided channels is perpendicular to the first support pillar.
  • the first divided channels will be
  • the first capacitor structure is divided into multiple capacitors.
  • a portion of the first support layer 351 is removed to form the first dividing channel 51 .
  • the first support layer 351 between adjacent capacitors can be removed, so that the corresponding first support pillars 331 and the substrate 10 in the first divided trench 51 are exposed.
  • the etching selectivity ratio of the first support layer 351 is made higher than the etching selectivity ratio of the first support pillar 331 , and the first support layer 351 is removed through an etching process to retain the first support pillar 331 .
  • the first capacitor structure 41 distributed along the X-axis direction is divided into a plurality of capacitors.
  • Step S105 Form a first insulating layer in the first divided channel.
  • the first insulating layer is located between the first lower electrode layers of adjacent capacitors.
  • the first insulating layer covers the first supporting pillar corresponding to the first divided channel. on the side wall surface and the base.
  • the material of the first insulating layer 511 may include a high dielectric constant material, silicon oxide, silicon nitride, or silicon oxynitride to achieve an insulation effect between the first lower electrode layers 411 corresponding to adjacent capacitors.
  • the material of the first insulating layer 511 may be a high dielectric constant material, thereby further improving the insulation performance between the first lower electrode layers 411 corresponding to adjacent capacitors.
  • step S106 filling the first divided trench with conductive material so that adjacent The first upper electrode layers corresponding to the capacitors are electrically connected.
  • the conductive material may be metal or metal alloy, etc., in the first capacitor structure 41 in the same horizontal plane along the X-axis direction, between the first upper electrode layers 413 corresponding to adjacent capacitors. Electrically connected through conductive materials.
  • the conductive material can be the same as the material of the first upper electrode layer 413, so that in the X-axis direction, the first capacitor structures 41 in the same horizontal plane share the same first upper electrode layer 413, so that adjacent The first upper electrode layers 413 corresponding to the capacitors are electrically connected.
  • the first lower electrode layers 411 corresponding to adjacent capacitors can be electrically connected together through the first support pillar 331, and the first upper electrode layers 413 corresponding to adjacent capacitors are electrically connected, so that adjacent capacitors can be connected in parallel, which is beneficial to The capacitance of the first capacitor component 61 is increased, thereby improving the performance of the semiconductor structure.
  • the thickness H3 of the first insulating layer 511 is greater than the thickness H1 of the first lower electrode layer 411, which is beneficial to ensuring the insulation performance between the first lower electrode layers 411 corresponding to adjacent capacitors.
  • the thickness H3 of the first insulating layer 511 is less than the sum H2 of the thicknesses of the first lower electrode layer 411 and the first dielectric layer 412, and can also facilitate electrical connection between the first upper electrode layers 413 corresponding to adjacent capacitors, thereby Ensure that adjacent capacitors are connected in parallel.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which includes: providing a substrate 10; forming a plurality of first support pillars 331, the plurality of first support pillars 331 being arranged parallel to each other and spaced apart on the substrate 10, and a plurality of first support pillars 331.
  • a support pillar 331 is located in the same plane parallel to the substrate 10; a first capacitor structure 41 is formed.
  • the first capacitor structure 41 includes a first lower electrode layer 411, a first dielectric layer 412 and a first upper electrode layer 413.
  • the lower electrode layer 411 covers the sidewall surface of the first support pillar 331 and the substrate 10, the first dielectric layer 412 covers the first lower electrode layer 411, and the first upper electrode layer 413 covers the first dielectric layer 412;
  • a plurality of first divided trenches 51 are formed.
  • the plurality of first divided trenches 51 are arranged parallel to each other and spaced apart on the substrate 10 .
  • the extending direction of the first divided trenches 51 is perpendicular to the first support pillar 331 .
  • the channel 51 divides the first capacitor structure 41 into a plurality of capacitors; a first insulating layer 511 is formed in the first divided channel 51, and the first insulating layer 511 is located between the first lower electrode layers 411 of adjacent capacitors.
  • the insulating layer 511 covers the sidewall surface of the first support pillar 331 corresponding to the first divided channel 51 and the substrate 10; conductive material is filled in the first divided channel 51 to make the first upper electrode corresponding to the adjacent capacitor
  • the layers 413 are electrically connected. Adjacent capacitors are isolated by the first insulating layer 511.
  • the first lower electrode layers 411 corresponding to the adjacent capacitors are electrically connected together through the first support pillar 331.
  • the first upper electrode layers 413 corresponding to the adjacent capacitors are electrically connected. Connection enables adjacent capacitors to be connected in parallel, which is beneficial to increasing capacitance and thereby improving the performance of the semiconductor structure.
  • the second trench 32 divides the sacrificial layer 20 into a first region 81 and a second region 82, wherein the first region 81 is used to form a plurality of stacked first regions.
  • Capacitor component 61 Referring to Figures 6a to 8c, while the first support pillar 331 is formed in the first area 81, the second support pillar 332 is also formed in the second area 82, and the second support pillar 332 and the first support pillar 331 Arranged symmetrically, the structure and material of the second support column 332 will not be described again here.
  • forming the first support column 331 also includes forming the isolation portion 70 .
  • the third trench 34 further divides the sacrificial layer 20 in the second region 82 into multiple regions, so that multiple capacitors can be subsequently formed in the multiple regions.
  • the isolation portion 70 is located between adjacent third trenches 34 for isolating the capacitance subsequently formed in the first region 81 from the capacitance subsequently formed in the second region 82 .
  • the isolation part 70 also includes an intermediate support layer 321.
  • the isolation part 70 also includes a sacrificial layer 20.
  • Part of the sacrificial layer 20 is located between the middle support layer 321 and the first support layer 351, and part of the sacrificial layer 20 is arranged around the side wall of the first support column 331; part of the sacrificial layer 20 is also located in the middle. Between the support layer 321 and the second support layer 322 , part of the sacrificial layer 20 is arranged around the side wall of the second support column 332 .
  • the second region 82 also includes a plurality of filling side walls 35.
  • a third support layer 352 is also formed.
  • the third support layer 352 is located in the second region 82, and the third support layer 352 is connected to the third support layer 352.
  • the first support layer 351 is arranged symmetrically, and the structure and material of the third support layer 352 will not be described again here.
  • removing part of the sacrificial layer 20 and the filling layer 311 to retain the first support pillar 331 and the first support layer 351 also includes: removing part of the sacrificial layer 20 and the filling layer in the second region 82 311, and retain the second support column 332 and the third support layer 352 to form a filling space.
  • first capacitor components 61 while forming a plurality of stacked first capacitor components 61 in the first region 811, it also includes: in the direction perpendicular to the substrate 10 (that is, along the Y-axis direction), A plurality of second capacitor components 62 are formed in a stack, and the isolation part 70 is located between the first capacitor component 61 and the second capacitor component 62 .
  • the second capacitor component 62 and the first capacitor component 61 are arranged symmetrically with respect to the isolation part 70 .
  • the second capacitor component 62 is located in the second first region 821, and the second capacitor structure 42 includes a second lower electrode layer 421, a second dielectric layer, and a second upper electrode layer 423. The structure and material thereof will not be described again here.
  • removing part of the middle support layer 321 also includes removing the middle support layer 321 located on the right side of the second capacitor structure 42 to form the second trench 32 .
  • a fourth support layer 323 is also formed.
  • the fourth support layer 323 is located on the side of the second capacitor structure 42 away from the isolation portion 70, and the fourth support layer 323 is arranged symmetrically with the second support layer 322. The structure and material of the fourth support layer 323 will not be described again here.
  • the first divided channel 51 while forming the first divided channel 51 , it also includes: removing the third support layer 352 to form the second divided channel 52 .
  • a plurality of second split channels 52 are provided through the second split channel 52 , so that the second capacitor structure 42 located in the same plane along the X-axis direction is split into multiple capacitors.
  • the second insulating layer 521 in the second divided channel 52 while forming the second insulating layer 521 in the second divided channel 52, it also includes: forming the second insulating layer 521 in the second divided channel 52, and the second insulating layer 521 is located adjacent to Between the second lower electrode layer 421 of the capacitor, the second insulating layer 521 covers the sidewall surface of the second support pillar 332 corresponding to the second divided channel 52 and the substrate 10 .
  • the structure and material of the second insulating layer 521 will not be described again here.
  • the thickness of the second insulating layer 521 is greater than the thickness of the second lower electrode layer 421, which is beneficial to ensuring the insulation performance between the second lower electrode layers 421 corresponding to adjacent capacitors, and the thickness of the second insulating layer 521 is less than the thickness of the second lower electrode layer 421.
  • the sum of the thicknesses of the two lower electrode layers 421 and the second dielectric layer 422 can also facilitate the electrical connection between the second upper electrode layers 423 corresponding to adjacent capacitors, thereby ensuring parallel connection between adjacent capacitors.
  • the first divided trench 51 while filling the first divided trench 51 with conductive material, it also includes: filling the second divided trench 52 with conductive material, so that there is a gap between the second upper electrode layers 423 corresponding to adjacent capacitors. Electrical connection.
  • the conductive material can be the same as the second upper electrode layer 423, so that in the X-axis direction, the second capacitor structures 42 in the same horizontal plane share the same second upper electrode layer 423, so that adjacent The second upper electrode layers 423 corresponding to the capacitors are electrically connected.
  • the second lower electrode layers 421 corresponding to adjacent capacitors can be electrically connected together through the second support pillar 332, and the second upper electrode layers 423 corresponding to adjacent capacitors are electrically connected, so that adjacent capacitors can be connected in parallel, which is beneficial to The capacitance of the second capacitor component 62 is increased, thereby further improving the performance of the semiconductor structure.

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Abstract

本公开实施例属于半导体制造技术领域，具体涉及一种半导体结构及半导体结构的制作方法。半导体结构包括位于基底上的第一电容结构和第一支撑柱，多个第一支撑柱相互平行且间隔地设置在基底上，且位于平行于基底的同一平面内，第一电容结构包括第一下电极层、第一介电层以及第一上电极层；半导体结构还包括多个第一分割沟道，第一分割沟道将第一电容结构分割成多个电容，相邻电容对应的第一下电极层之间设置有第一绝缘层，相邻电容对应的第一上电极层之间电性连接。通过第一绝缘层将相邻电容隔离，相邻电容对应的第一下电极层之间电性连接，相邻电容对应的第一上电极层之间电性连接，使得相邻电容实现并联，有利于提高电容容量。

Description

半导体结构及半导体结构的制作方法
本公开要求于2022年04月26日提交中国专利局、申请号为202210446041.8、申请名称为“半导体结构及半导体结构的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及半导体制造技术领域，尤其涉及一种半导体结构及半导体结构的制作方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。电容器通常包括层叠设置的上电极层、介电层和下电极层，然而，相关技术中还存在电容器容量较小的问题。
发明内容
本公开实施例第一方面提供一种半导体结构，包括：位于基底上的第一电容结构和第一支撑柱，多个所述第一支撑柱相互平行且间隔地设置在所述基底上，多个所述第一支撑柱位于平行于所述基底的同一平面内，所述第一电容结构包括第一下电极层、第一介电层以及第一上电极层，所述第一下电极层覆盖所述第一支撑柱的侧壁表面和所述基底上，所述第一介电层覆盖在所述第一下电极层上，所述第一上电极层覆盖在所述第一介电层上；
还包括多个相互平行且间隔地设置在所述基底上的第一分割沟道，所述第一分割沟道的延伸方向与所述第一支撑柱垂直，所述第一分割沟道将所述第一电容结构分割成多个电容，相邻所述电容对应的所述第一下电极层之间设置有第一绝缘层，所述第一绝缘层覆盖在所述第一分割沟道对应的所述第一支撑柱的侧壁表面和所述基底，相邻所述电容对应的所述第一上电极层之间电性连接。
本公开实施例第二方面提供一种半导体结构的制作方法，包括：
提供基底；
形成多个第一支撑柱，多个所述第一支撑柱相互平行且间隔地设置在所述基底上，多个所述第一支撑柱位于平行于所述基底的同一平面内；
形成第一电容结构，所述第一电容结构包括第一下电极层、第一介电层以及第一上电极层，所述第一下电极层覆盖所述第一支撑柱的侧壁表面和所述基底，所述第一介电层覆盖在所述第一下电极层上，所述第一上电极层覆盖在所述第一介电层上；
形成多个第一分割沟道，多个所述第一分割沟道相互平行且间隔地设置于所述基底上，所述第一分割沟道的延伸方向与所述第一支撑柱垂直，所述第一分割沟道将所述第一电容结构分割成多个电容；
在所述第一分割沟道内形成第一绝缘层，所述第一绝缘层位于相邻所述电容的所述第一下电极层之间，所述第一绝缘层覆盖在所述第一分割沟道对应的所述第一支撑柱的侧壁表面和所述基底上；
在所述第一分割沟道内填充导电材料，以使相邻所述电容对应的所述第一上电极层之间电性 连接。
本公开实施例提供一种半导体结构及半导体结构的制作方法，包括位于基底上的第一电容结构和第一支撑柱，多个第一支撑柱间隔且平行地设置在基底上，多个第一支撑柱位于平行于基底的同一平面内，第一电容结构包括第一下电极层、第一介电层以及第一上电极层，第一下电极层覆盖第一支撑柱的侧壁表面和基底上，第一介电层覆盖在第一下电极层上，第一上电极层覆盖在第一介电层上；还包括多个间隔且平行于基底设置的第一分割沟道，第一分割沟道的延伸方向与第一支撑柱垂直，第一分割沟道将第一电容结构分割成多个电容，相邻电容对应的第一下电极层之间设置有第一绝缘层，第一绝缘层覆盖在第一分割沟道对应的第一支撑柱的侧壁表面和基底，相邻电容对应的第一上电极层之间电性连接。通过第一绝缘层将相邻电容隔离，相邻电容对应的第一下电极层通过第一支撑柱电性连接在一起，相邻电容对应的第一上电极层之间电性连接，使得相邻电容实现并联，有利于提高电容容量，进而提高半导体结构的性能。
附图说明
图1a为本公开实施例提供的一种半导体结构的结构示意图一；
图1b为本公开实施例提供的一种半导体结构的结构示意图二；
图1c为图1a在A1-A1处的剖面图；
图1d为图1c在B处的局部放大图；
图2为本公开实施例提供的一种半导体结构的制作方法的步骤流程图；
图3为半导体结构的制作方法中在基底上形成牺牲层的结构示意图；
图4a为半导体结构的制作方法中形成第一沟槽的结构示意图一；
图4b为半导体结构的制作方法中形成第一沟槽的结构示意图二；
图4c为图4a在A2-A2处的剖面图；
图5a为半导体结构的制作方法中形成填充层的结构示意图一；
图5b为半导体结构的制作方法中形成填充层的结构示意图二；
图5c为图5a在A3-A3处的剖面图；
图6a为半导体结构的制作方法中形成第二沟槽的结构示意图一；
图6b为半导体结构的制作方法中形成第二沟槽的结构示意图二；
图7a为半导体结构的制作方法中形成填充沟道的结构示意图一；
图7b为半导体结构的制作方法中形成填充沟道的结构示意图二；
图7c为图7a在A4-A4处的剖面图；
图8a为半导体结构的制作方法中形成第一支撑柱的结构示意图一；
图8b为半导体结构的制作方法中形成第一支撑柱的结构示意图二；
图8c为图8a在A5-A5处的剖面图；
图9a为半导体结构的制作方法中形成第三沟槽的结构示意图一；
图9b为半导体结构的制作方法中形成第三沟槽的结构示意图二；
图10a为半导体结构的制作方法中形成填充侧壁的结构示意图一；
图10b为半导体结构的制作方法中形成填充侧壁的结构示意图二；
图11a为半导体结构的制作方法中形成第一支撑层的结构示意图一；
图11b为半导体结构的制作方法中形成第一支撑层的结构示意图二；
图12a为半导体结构的制作方法中去除部分牺牲层和填充层的结构示意图一；
图12b为半导体结构的制作方法中去除部分牺牲层和填充层的结构示意图二；
图12c为图12a在A6-A6处的剖面图；
图13a为半导体结构的制作方法中形成第一下电极层的结构示意图一；
图13b为半导体结构的制作方法中形成第一下电极层的结构示意图二；
图14a为半导体结构的制作方法中形成第一介质层和第一上电极层的结构示意图一；
图14b为半导体结构的制作方法中形成第一介质层和第一上电极层的结构示意图二；
图15a为半导体结构的制作方法中去除部分中间支撑层的结构示意图一；
图15b为半导体结构的制作方法中去除部分中间支撑层的结构示意图二；
图16a为半导体结构的制作方法中形成第二支撑层的结构示意图一；
图16b为半导体结构的制作方法中形成第二支撑层的结构示意图二；
图17a为半导体结构的制作方法中形成第一分割沟道的结构示意图一；
图17b为半导体结构的制作方法中形成第一分割沟道的结构示意图二；
图18a为半导体结构的制作方法中形成第一绝缘层的结构示意图一；
图18b为半导体结构的制作方法中形成第一绝缘层的结构示意图二；
图19a为半导体结构的制作方法中填充导电材料的结构示意图一；
图19b为半导体结构的制作方法中填充导电材料的结构示意图二；
图19c为图19a在A1-A1处的剖面图；
图19d为图19c在B处的局部放大图。
具体实施方式
为了使本发明实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本发明保护的范围。
请参照图1a、图1b以及图1c，本公开实施例提供一种半导体结构，包括位于基底10上的第一电容结构41和第一支撑柱331。
如图1c所示，在沿Z轴方向上，多个第一支撑柱331相互平行且间隔地设置在基底10上，多个第一支撑柱331位于平行于基底10的同一平面内。通过设置多个第一支撑柱331，可以对第一电容结构41起到支撑作用，防止电容结构坍塌。在一些实施例中，第一支撑柱331的材质包括单晶硅、单晶锗、单晶硅锗或者IGZO，从而保证第一支撑柱331对第一电容结构41的支撑作用。其中，IGZO(indium gallium zinc oxide，铟镓锌氧化物)是一种含有铟、镓和锌的非晶氧化物，其具有良好的载流子迁移性能。本实施例中，第一支撑柱331的材质可以为IGZO，有利于提高第一电容结构41的性能。
第一电容结构41包括第一下电极层411、第一介电层412以及第一上电极层413。第一下电极层411覆盖第一支撑柱331的侧壁表面和基底10上，第一介电层412覆盖在第一下电极层411上。参照图1a和图1c可以看出，第一电容结构41中，部分第一下电极层411环绕第一支撑柱331设置，部分第一介电层412环绕第一下电极层411设置，部分第一下电极层411和部分第一介电层412还覆盖在基底10上；第一电容结构41中，第一上电极层413覆盖在第一介电层412上。
如图1a和图1c所示，本实施例中，多个第一支撑柱331和第一电容结构41共同构成了第一电容组件61，在垂直于基底10的方向上(也即沿Y轴方向上)，基底10上设置有多个层叠设置的第一电容组件61。例如，基底10上可以设置有三个层叠设置的第一电容组件61。相邻的第一电容组件61对应的第一上电极层413之间电性连接。例如，在相邻的第一电容组件61所对应的第一上电极层413之间可以通过导电层连接，导电层的材质例如可以包括金属或者金属合金等。如图1c所示，在垂直于基底10的方向上(也即沿Y轴方向上)，相邻的第一电容组件61对应的第一上电极层413还可以直接接合在一起，以使相邻的第一电容组件61共用同一第一上电极层413。
如图1a和图1b所示，在沿X轴方向上，半导体结构还包括多个相互平行且间隔设置在基底10上的第一分割沟道51，第一分割沟道51将第一电容结构41分割成多个电容。例如，本实施例中可以设置有两个第一分割沟道51，第一分割沟道51的延伸方向与第一支撑柱331的延伸方向垂直，且第一分割沟道51的延伸方向还与基底10垂直。两个第一分割沟道51可以将第一电容结构41分割成三个电容，这三个电容沿X轴方向排布。在基底10上设置有多个层叠设置的第一电容组件61的实施例中，第一分割沟道51还可以将多个第一电容组件61分割成多个电容。例如，本实施例中具有三个层叠设置的第一电容组件61，且每个第一电容组件61都被两个第一分割沟道51分割成三个电容，也即，本实施例中基底10上共设置有九个电容。
继续参照图1a和图1b,在任一第一电容组件61内，在沿X轴方向上，相邻电容对应的第一下电极层411之间设置有第一绝缘层511，第一绝缘层511覆盖在第一分割沟道51对应的第一支撑柱331的侧壁表面和基底10，以使相邻电容对应的第一下电极层411之间通过第一绝缘层511隔离开来。本实施例中，第一绝缘层511位于第一分割沟道51所在的区域内，且部分第一绝缘层511环绕第一支撑柱331设置，部分第一绝缘层511还覆盖在基底10上。在平行于基底10的方向上，相邻电容对应的第一上电极层413之间电性连接。例如，在相邻电容对应的第一上电极层413之间可以通过导电层连接，导电层的材质例如可以包括金属或者金属合金等。如图1a所示，相邻电容对应的第一上电极层413之间还可以直接接合在一起，也即，相邻电容对应的第一上电极层413还覆盖在第一绝缘层511上，以使相邻电容之间共用同一第一上电极层413。通过设置上述结构，相邻电容对应的第一下电极层411可以通过第一支撑柱331电性连接在一起，相邻电容对应的第一上电极层413之间电性连接，使得相邻电容实现并联，有利于提高第一电容组件61的电容容量，进而提高半导体结构的性能。
本公开实施例提供一种半导体结构，包括位于基底10上的第一电容结构41和第一支撑柱331，多个第一支撑柱331相互平行且间隔地设置在基底10上，多个第一支撑柱331位于平行于基底10的同一平面内，第一电容结构41包括第一下电极层411、第一介电层412以及第一上电极层413，第一下电极层411覆盖第一支撑柱331的侧壁表面和基底10上，第一介电层412覆盖在第一下电极层411上，第一上电极层413覆盖在第一介电层412上；还包括多个相互平行且间隔设置在基底10上的第一分割沟道51，第一分割沟道51的延伸方向与第一支撑柱331垂直，第一分割沟道51将第一电容结构41分割成多个电容，相邻电容对应的第一下电极层411之间设置有第一绝缘层511，第一绝缘层511覆盖在第一分割沟道51对应的第一支撑柱331的侧壁表面和基底10，相邻电容对应的第一上电极层413之间电性连接。通过第一绝缘层511将相邻电容隔离，相邻电容对应的第一下电极层411通过第一支撑柱331电性连接在一起，相邻电容对应的第一上电极层413之间电性连接，使得相邻电容实现并联，有利于提高电容容量，进而提高半导体结构的性能。
在一些实施例中，第一绝缘层511的材质可以包括高介电常数材料、氧化硅、氮化硅或者氮氧化硅，以提高相邻电容对应的第一下电极层411之间的绝缘效果。本实施例中，第一绝缘层511的材质可以为高介电常数材料。其中，高介电常数材料是指介电常数高于二氧化硅的材料，具有良好的绝缘性，例如可以包括铁电材料、金属氧化物等等。本实施例中，第一绝缘层511的材质可以为高介电常数材料，从而进一步提升相邻电容对应的第一下电极层411之间的绝缘性能，实现相邻电容之间并联。
参照图1d，第一绝缘层511的厚度H3大于第一下电极层411的厚度H1，且小于第一下电极层411与第一介电层412的厚度之和H2。第一绝缘层511的厚度H3大于第一下电极层411的厚度H1，有利于保证相邻电容对应的第一下电极层411之间的绝缘性能，同时，第一绝缘层511的厚度H3小于第一下电极层411与第一介电层412的厚度之和H2，也即，第一绝缘层511的平面位于第一介电层412和第一下电极层411之间，还能够便于相邻电容对应的第一上电极层413之间电性连接，从而保证相邻电容之间进行并联。
参照图1a和图1b，半导体结构还包括覆盖基底10上的第一支撑层351和第二支撑层322。本实施例中，第一支撑层351可以设置在第一电容组件61的右侧，第二支撑层322可以设置在第一电容组件61的左侧，以使第一电容组件61位于第一支撑层351和第二支撑层322之间。第一支撑层351和第二支撑层322环绕第一支撑柱331的侧壁表面，从而使得第一支撑柱331通过第一支撑层351和第二支撑层322设置在基底10上。在一些实施例中，第一支撑层351和第二支撑层322的材质可以包括氮化硅、氮氧化硅或者氧化硅等。继续参照图1a和图1b，第一介电层412还覆盖在第一支撑层351和第二支撑层322的侧壁，有利于保证第一上电极层413分别与第一支撑层351和第二支撑层322之间的绝缘性能。
本实施例中，半导体结构还包括位于基底10上的隔离部70和多个第二电容组件62，在垂直于基底10的方向上(也即沿Y轴方向上)，基底10上设置有多个层叠设置的第二电容组件62，隔离部70位于第一电容组件61和第二电容组件62之间，第二电容组件62与第一电容组件61关于隔离部70对称设置。如图1a所示，第一电容组件61位于隔离部70的左侧，第二电容结构42位于隔离部70的右侧，且第二电容组件62与第一电容组件61的结构相同。
值得说明的是，第一电容组件61与第二电容组件62所对应的同层结构的材质相同，以便第一电容组件61和第二电容组件62可以同步形成。
参照图1a和图1b，在垂直于基底10的方向上(也即沿Y轴方向上)，基底10上设置有多个层叠设置的第二电容组件62，相邻的第二电容组件62之间连接。第二电容组件62包括多个第二支撑柱332和第二电容结构42，其中，多个第二支撑柱332相互平行且间隔地设置在基底10上，且每个第二支撑柱332均与其对应的第一支撑柱331连接，第二电容结构42包括第二下电极层421、第二介电层422以及第二上电极层423，第二下电极层421覆盖第二支撑柱332的侧壁表面和基底10上，第二介电层422覆盖在第二下电极层421上，第二上电极层423覆盖在第二介电层422上。可见，相邻的第二电容组件62对应的第二上电极层423之间电性连接。如图1a所示，相邻电容对应的第二上电极层423之间还可以直接接合在一起，也即，相邻电容对应的第二上电极层423还覆盖在第二绝缘层521上，以使相邻电容对应的第二上电极层423之间电性连接。通过设置上述结构，相邻电容对应的第二下电极层421可以通过第二支撑柱332电性连接在一起，相邻电容对应的第二上电极层423之间电性连接，使得相邻电容实现并联，有利于提高第二电容组件62的电容容量，进而提高半导体结构的性能。
多个第二电容组件62还包括多个相互平行且间隔地设置在基底10上的第二分割沟道52，第二分割沟道52的延伸方向与第二支撑柱332垂直，第二分割沟道52将任一层中的第二电容结构42分割成多个电容。在任一第二电容组件62内，在平行于基底10的方向上(也即沿X轴方向上)，相邻电容的第二下电极层421之间设置有第二绝缘层521，第二绝缘层521覆盖在第二分割沟道52对应的第二支撑柱332的侧壁表面和基底10，相邻电容对应的第二上电极层423连接，以使相邻电容对应的第二下电极层421之间通过第二绝缘层521隔离开来。
相同地，第二电容组件62的左侧设置有第三支撑层352，第二电容组件62的右侧设置有第四支撑层323，以使第二电容组件62位于第三支撑层352和第四支撑层323之间。第三支撑层352和第四支撑层323环绕第二支撑柱332的侧壁表面，第三支撑层352和第四支撑层323环绕第二支撑柱332的侧壁表面，从而使得第二支撑柱332通过第三支撑层352和第四支撑层323设置在基底10上。第二介电层422还覆盖在第三支撑层352和第四支撑层323的侧壁，有利于保证第二上电极层423分别与第三支撑层352和第四支撑层323之间的绝缘性能。
参照图1a和图1b，隔离部70还位于第一支撑层351和第三支撑层352之间，且隔离部70还环绕第一支撑柱331和第二支撑柱332的侧壁设置。隔离部70还包括中间支撑层321，中间支撑层321的一侧与第一支撑柱331连接，中间支撑层321的另一侧与第二支撑柱332连接，以使第一支撑柱331和第二支撑柱332通过中间支撑层321电性连接在一起。本实施例中，中间支撑层321、第一支撑柱331和第二支撑柱332的材质相同，以便通过同一沉积制程同步形成，从而提高半导体结构的生产效率。 隔离部70还包括牺牲层20，部分牺牲层20位于中间支撑层321与第一支撑层351之间，且部分牺牲层20环绕第一支撑柱331的侧壁设置；部分牺牲层20还位于中间支撑层321与第二支撑层322之间，且部分牺牲层20环绕第二支撑柱332的侧壁设置。
本公开实施例还提供一种半导体结构的制作方法，参照图2，步骤S101至步骤S105的过程如下：
步骤S101、提供基底。
本实施例中，基底可以为半导体基底，例如单晶硅、多晶硅或非晶结构的硅或硅锗(SiGe)，也可以为混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合。本实施例在此不对其进行限制。
下面参照图3至图8c，在提供基底10以后，还包括：
步骤S102、形成多个第一支撑柱，多个第一支撑柱相互平行且间隔地设置在基底上，多个第一支撑柱位于平行于基底的同一平面内。
参照图3，本实施例中，形成多个第一支撑柱331的步骤包括：形成牺牲层20，其覆盖基底10。牺牲层20包括交替层叠设置的第一牺牲层21和第二牺牲层22。例如，本实施例中可以包括多个第一牺牲层21和多个第二牺牲层22，其中，第二牺牲层22夹设在相邻的两个第一牺牲层21之间，部分第一牺牲层21还覆盖在基底10上，以使第一牺牲层21和第二牺牲层22在基底10上交替层叠设置。在一些实施例中，第一牺牲层21的材质可以包括氧化物，第二牺牲层22的材质可以包括氮化物，以使第一牺牲层21和第二牺牲层22的材质有所区分，便于后续选择性的蚀刻部分牺牲层20。
当然，在一些其他实施例中，牺牲层20还可以只包括一层第一牺牲层21和一层第二牺牲层22，第一牺牲层21位于第二牺牲层22和基底10之间。
参照图4a、图4b以及图4c，本实施例中，在形成牺牲层20以后，形成多个第一支撑柱331的步骤还包括：去除部分牺牲层20，以形成多个第一沟槽31，在沿Z轴方向上，多个第一沟槽31相互平行且间隔地设置在基底10上，且第一沟槽31的延伸方向平行于Y轴方向。在一种具体的实现方式中，可以对部分牺牲层20进行蚀刻，并且蚀刻至暴露出基底10，以形成多个第一沟槽31。
参照图5a、图5b以及图5c，本实施例中，在形成第一沟槽31以后，形成多个第一支撑柱331的步骤还包括：在第一沟槽31内形成填充层311。在第一沟槽31内填充材料，以使在第一沟槽31内形成多个填充层311，在沿Z轴方向上，多个填充层311相互平行且间隔地设置在基底10上，且填充层311的延伸方向平行于Y轴方向。在一些实施例中，填充材料的材质可以包括多晶硅、单晶硅等。
参照图6a和图6b，本实施例中，在形成填充层311以后，形成多个第一支撑柱331的步骤还包括：去除部分牺牲层20以及部分填充层311，以形成多个第二沟槽32，在沿X轴方向上，多个第二沟槽32相互平行且间隔地设置在基底10上，且第二沟槽32的延伸方向垂直于第一沟槽31。在一种具体的实现方式中，可以对部分牺牲层20和部分填充层311进行蚀刻，并且蚀刻至暴露出基底10，以形成多个第二沟槽32。本实施例中，可以形成三个第二沟槽32，且三个第二沟槽32将牺牲层20分割成第一区域81和第二区域82，以便后续分别在第一区域81和第二区域82内进一步形成电容结构。
参照图7a、图7b以及图7c，本实施例中，在形成第二沟槽32以后，形成多个第一支撑柱331的步骤还包括：去除部分牺牲层20，以形成多个填充沟道33，多个填充沟道33间隔且平行于第一沟槽31设置。
在牺牲层20还可以只包括一层第一牺牲层21和一层第二牺牲层22的实施例中，在沿Z轴方向上，多个填充沟道33位于平行于基底10的同一平面内。由于第二沟槽32的侧壁即为牺牲层20，通过设置第二沟槽32，可使牺牲层20暴露出来。通过对牺牲层20进行蚀刻，第二牺牲层22的蚀刻选择比较第一牺牲层21的蚀刻选择比高，以去除牺牲层20中的第二牺牲层22，保 留第一牺牲层21，从而形成多个填充沟道33，且多个填充沟道33均位于相邻的第二沟槽32之间，并与第二沟槽32连通。
在沿Z轴方向上，位于平行于基底10的同一平面内的多个填充沟道33构成填充结构。在牺牲层20包括交替层叠设置的第一牺牲层21和第二牺牲层22的实施例中，去除牺牲层20中第二牺牲层22的，保留第一牺牲层21之后，还包括：在垂直于基底10的方向上(也即沿Y轴方向上)，形成在基底10上层叠设置的填充结构，每层填充结构包括多个相互平行且间隔设置的填充沟道33。
参照图8a、图8b以及图8c，本实施例中，在形成填充沟道33以后，形成多个第一支撑柱331的步骤还包括：在填充沟道33内形成第一支撑柱331。在一些实施例中，可以采用沉积的工艺在填充沟道33内形成第一支撑柱331。第一支撑柱331的材质包括单晶硅、单晶锗、单晶硅锗或者IGZO，从而保证第一支撑柱331对第一电容结构41的支撑作用。其中，IGZO(indium gallium zinc oxide，铟镓锌氧化物)是一种含有铟、镓和锌的非晶氧化物，其具有良好的载流子迁移性能。本实施例中，第一支撑柱331的材质可以为IGZO，有利于提高第一电容结构41的性能。
继续参照图8a和图8b，在填充沟道33内形成第一支撑柱331的同时，还包括：在第二沟槽32内形成中间支撑层321。由于填充沟道33与第二沟槽32连通，在形成第一支撑柱331的同时，可以采用沉积的工艺同步在第二沟槽32内形成中间支撑层321。本实施例中，中间支撑层321的材质与第一支撑柱331的材质相同，且中间支撑层321与第一支撑柱331接合。
下面参照图9a至图11a，在形成多个第一支撑柱331以后，还包括：
参照图9a和图9b，本实施例中，在形成多个第一支撑柱331以后，还包括：去除部分填充层311，以形成多个第三沟槽34，多个第三沟槽34相互平行且间隔设置在基底10上，第三沟槽34的延伸方向垂直于第一沟槽31。在一种具体的实现方式中，可以对部分填充层311进行蚀刻，并且蚀刻至暴露出基底10，以形成多个第三沟槽34。对比图6b和图9b，第三沟槽34将第一区域81内的牺牲层20进一步分割成多个区域，以便后续在多个区域内形成多个电容。
参照图10a和图10b，本实施例中，在形成第三沟槽34以后，还包括：去除第三沟槽34侧壁对应的牺牲层20，保留第一支撑柱331，以形成填充侧壁35。去除第三沟槽34侧壁对应的牺牲层20，也即，去除第三沟槽34侧壁对应的第一牺牲层21，并保留第一支撑柱331。在一种具体的实施方式中，使第一牺牲层21的蚀刻选择比较第一支撑柱331的蚀刻选择比高，通过蚀刻工艺去除第一牺牲层21，保留第一支撑柱331。
参照图11a和图11b，本实施例中，在形成填充侧壁35以后，还包括：在部分填充侧壁35内形成第一支撑层351，第一支撑层351环绕第一支撑柱331的侧壁表面。例如，可以通过沉积的工艺在填充侧壁35内形成第一支撑层351，第一支撑层351的材质例如可以包括氮化物。通过设置第一支撑层351，有利于进一步提升对第一支撑柱331的支撑效果。
下面参照图12a至图15b，在形成第一支撑层351以后，还包括：
步骤S103、形成第一电容结构，第一电容结构包括第一下电极层、第一介电层以及第一上电极层，第一下电极层覆盖第一支撑柱的侧壁表面和基底，第一介电层覆盖在第一下电极层上，第一上电极层覆盖在第一介电层上。
参照图12a、图12b以及图12c，本实施例中，形成第一电容结构41的步骤包括：去除部分牺牲层20和填充层311，以保留第一支撑柱331和第一支撑层351。本实施例中，去除位于第一区域81内的部分第一牺牲层21和填充层311，以保留第一支撑柱331和第一支撑层351，进而形成一填充空间，以便后续在该填充空间内形成电容。在一种具体的实现方式中，使第一牺牲层21和填充层311的蚀刻选择比均高于第一支撑柱331和第一支撑层351的蚀刻选择比，通过蚀刻工艺去除牺牲层20和填充层311，以保留第一支撑柱331和第一支撑层351。
参照图13a和图13b，本实施例中，去除部分牺牲层20和填充层311以后，还包括：通过选择性生长工艺在位于填充空间内的第一支撑柱331和基底10上形成第一下电极层411。值得说明 的是，选择性生长工艺可以选择性地沉积在所需的材料表面。例如，第一下电极层411的材质可以包括钨、钛等金属材料，在沉积的过程中，第一下电极层选择性的沉积在第一支撑柱331侧壁以及基底10的表面，而不沉积在第一支撑层351的侧壁上。通过上述选择性沉积工艺，避免后续去除第一支撑层351侧壁上的第一下电极层411，从而提高制作效率。
继续参照图13a和图13b，本实施例中，由于中间支撑层321的材质与第一支撑柱331的材质相同，第一下电极层411还覆盖在位于填充空间一侧的中间支撑层321上。
参照图14a和图14b，本实施例中，在形成第一下电极层411以后，还包括：依次形成第一介电层412和第一上电极层413。在一种具体的实现方式中，可以采用沉积的工艺依次形成第一介电层412和第一上电极层413。第一介电层412的材质可以包括高介电常数材料、氧化硅、氮化硅或者氮氧化硅，以实现第一上电极层413与第一下电极层411之间的绝缘效果。第一上电极层413的材质可以包括钨、钛等金属材料，本实施例中，第一上电极层413的材质与第一下电极层411的材质相同。
继续参照图14a和图14b，在牺牲层20包括交替层叠设置的第一牺牲层21和第二牺牲层22的实施例中，形成第一电容结构41，还包括：第一电容结构41和第一支撑柱331构成第一电容组件61，在垂直于基底10的方向上(也即沿Y轴方向上)，形成多个层叠设置的第一电容组件61。在依次沉积形成第一下电极层411、第一介电层412以及第一上电极层413时，多个第一电容组件61同步形成。
相邻的第一电容组件61对应的第一上电极层413之间电性连接。例如，在沿Y轴方向上，在相邻的第一电容组件61所对应的第一上电极层413之间可以通过导电层连接，导电层的材质例如可以包括金属或者金属合金等。如图14a所示，在垂直于基底10的方向上(也即沿Y轴方向上)，相邻的第一电容组件61对应的第一上电极层413还可以直接接合在一起，以使相邻的第一电容组件61共用同一第一上电极层413。
参照图15a和图15b，形成多个第一电容结构41，还包括：在依次形成第一介电层412和第一上电极层413以后：去除部分中间支撑层321；参照图16a和图16b，在去除部分中间支撑层321以后，在部分第二沟槽32内形成第二支撑层322。例如，可以去除位于第一电容结构41左侧的中间支撑层321，以形成第二沟槽32，并在该第二沟槽32内形成第二支撑层322，设置第二支撑层322，有利于进一步提升对第一支撑柱331的支撑效果。在一种具体的实现方式中，第二支撑层322的材质可以包括氮化物。本实施例中，第二支撑层322的材质可以与第一支撑层351的材质相同。
对比图14a和图15a，在去除部分中间支撑层321的同时，还去除覆盖在中间支撑层321侧壁上的第一下电极层411，从而在垂直于基底10的方向上(沿Y轴方向上)，将相邻的电容隔离开来。
下面参照图17a和图17b，在形成多个第一电容结构41以后，还包括：
步骤S104、形成多个第一分割沟道，多个第一分割沟道相互平行且间隔地设置于基底上，第一分割沟道的延伸方向与第一支撑柱垂直，第一分割沟道将第一电容结构分割成多个电容。
去除部分第一支撑层351，以形成第一分割沟道51。例如，可以去除相邻的电容之间的第一支撑层351，以使第一分割沟道51内对应的第一支撑柱331以及基底10暴漏出来。在一种具体的实现方式中，使第一支撑层351的蚀刻选择比高于第一支撑柱331的蚀刻选择比，通过蚀刻工艺去除第一支撑层351，以保留第一支撑柱331。
值得说明的是，通过设置多个第一分割沟道51，使沿X轴方向分布的第一电容结构41被分割成多个电容。
下面参照图18a和图18b，在形成多个第一分割沟道51以后，还包括：
步骤S105、在第一分割沟道内形成第一绝缘层，第一绝缘层位于相邻电容的第一下电极层之间，第一绝缘层覆盖在第一分割沟道对应的第一支撑柱的侧壁表面和基底上。
在一些实施例中，第一绝缘层511的材质可以包括高介电常数材料、氧化硅、氮化硅或者氮氧化 硅，以实现相邻电容对应的第一下电极层411之间的绝缘效果。本实施例中，第一绝缘层511的材质可以为高介电常数材料，从而进一步提升相邻电容对应的第一下电极层411之间的绝缘性能。
下面参照图19a、图19b、图19c以及图19d，在第一分割沟道51内形成第一绝缘层511以后，还包括：步骤S106、在第一分割沟道内填充导电材料，以使相邻电容对应的第一上电极层之间电性连接。
在一种具体的实现方式中，导电材料可以为金属或者金属合金等，在沿X轴方向上，同一水平面内的第一电容结构41中，相邻电容对应的第一上电极层413之间通过导电材料电性连接。本实施例中，导电材料可以与第一上电极层413的材质相同，以使在沿X轴方向上，同一水平面内的第一电容结构41共用同一第一上电极层413，从而使得相邻电容对应的第一上电极层413之间电性连接。相邻电容对应的第一下电极层411可以通过第一支撑柱331电性连接在一起，相邻电容对应的第一上电极层413之间电性连接，使得相邻电容实现并联，有利于提高第一电容组件61的电容容量，进而提高半导体结构的性能。例如，参照19d，第一绝缘层511的厚度H3大于第一下电极层411的厚度H1，有利于保证相邻电容对应的第一下电极层411之间的绝缘性能。第一绝缘层511的厚度H3小于第一下电极层411与第一介电层412的厚度之和H2，还能够便于相邻电容对应的第一上电极层413之间进行电性连接，从而保证相邻电容之间进行并联。
本公开实施例还提供一种半导体结构的制作方法，包括：提供基底10；形成多个第一支撑柱331，多个第一支撑柱331相互平行且间隔地设置在基底10上，多个第一支撑柱331位于平行于基底10的同一平面内；形成第一电容结构41，第一电容结构41包括第一下电极层411、第一介电层412以及第一上电极层413，第一下电极层411覆盖第一支撑柱331的侧壁表面和基底10，第一介电层412覆盖在第一下电极层411上，第一上电极层413覆盖在第一介电层412上；形成多个第一分割沟道51，多个第一分割沟道51相互平行且间隔地设置于基底10上，第一分割沟道51的延伸方向与第一支撑柱331垂直，第一分割沟道51将第一电容结构41分割成多个电容；在第一分割沟道51内形成第一绝缘层511，第一绝缘层511位于相邻电容的第一下电极层411之间，第一绝缘层511覆盖在第一分割沟道51对应的第一支撑柱331的侧壁表面和基底10上；在第一分割沟道51内填充导电材料，以使相邻电容对应的第一上电极层413之间电性连接。通过第一绝缘层511将相邻电容隔离，相邻电容对应的第一下电极层411通过第一支撑柱331电性连接在一起，相邻电容对应的第一上电极层413之间电性连接，使得相邻电容实现并联，有利于提高电容容量，进而提高半导体结构的性能。
参照图6a，在形成第二沟槽32以后，第二沟槽32将牺牲层20分割成第一区域81和第二区域82，其中，第一区域81用于形成多个层叠设置的第一电容组件61。参照图6a至图8c，在形成第一区域81内形成第一支撑柱331的同时，还在第二区域82内形成了第二支撑柱332，且第二支撑柱332与第一支撑柱331对称设置，第二支撑柱332的结构以及材质在此不再赘述。
参照图9a和图11b，形成第一支撑柱331的同时，还包括：形成隔离部70。第三沟槽34还将第二区域82内的牺牲层20进一步分割成多个区域，以便后续在多个区域内形成多个电容。参照图10a，隔离部70位于位于相邻的第三沟槽34之间，用于将后续在第一区域81内形成的电容与后续在第二区域82内形成的电容隔离开。隔离部70还包括中间支撑层321，中间支撑层321的一侧与第一支撑柱331连接，中间支撑层321的另一侧与第二支撑柱332连接，以使第一支撑柱331和第二支撑柱332通过中间支撑层321电性连接在一起。本实施例中，中间支撑层321、第一支撑柱331和第二支撑柱332的材质相同，以便通过同一沉积制程同步形成，从而提高半导体结构的生产效率。隔离部70还包括牺牲层20，部分牺牲层20位于中间支撑层321与第一支撑层351之间，且部分牺牲层20环绕第一支撑柱331的侧壁设置；部分牺牲层20还位于中间支撑层321与第二支撑层322之间，且部分牺牲层20环绕第二支撑柱332的侧壁设置。
参照图10a和图10b，第二区域82内还包括多个填充侧壁35。参照图11a和图11b，在填充侧壁35内形成第一支撑层351的同时，还形成第三支撑层352，第三支撑层352位于第二区域82内，且第三支撑层352与第一支撑层351对称设置，第三支撑层352的结构以及材质在此不再 赘述。
参照图12a和图12b，去除部分牺牲层20和填充层311，以保留第一支撑柱331和第一支撑层351的同时，还包括：去除第二区域82内的部分牺牲层20和填充层311，并保留第二支撑柱332和第三支撑层352，以形成填充空间。参照图13a至图14b，在第一一区域811内形成多个层叠设置的第一电容组件61的同时，还包括：在垂直于基底10的方向上(也即在沿Y轴方向上)，形成多个第二电容组件62层叠设置，隔离部70位于第一电容组件61和第二电容组件62之间，第二电容组件62与第一电容组件61关于隔离部70对称设置。第二电容组件62位于第二一区域821内，且第二电容结构42包括第二下电极层421、第二介质层以及第二上电极层423，其结构以及材质在此不再赘述。
参照图15a和图15b，去除部分中间支撑层321，还包括去除位于第二电容结构42右侧的中间支撑层321，以形成第二沟槽32。参照图16a和图16b，形成的第二支撑层322的同时，还形成第四支撑层323，第四支撑层323位于第二电容结构42的背离隔离部70的一侧，且第四支撑层323与第二支撑层322对称设置，第四支撑层323的结构以及材质在此不再赘述。
参照图17a和图17b，在形成第一分割沟道51的同时，还包括：去除第三支撑层352，以形成第二分割沟道52。第二分割沟道52的通过设置多个第二分割沟道52，以使在沿X轴方向上，位于同一平面内的第二电容结构42被分割成多个电容。参照图18a和图18b，在第二分割沟道52内形成第二绝缘层521的同时，还包括：在第二分割沟道52内形成第二绝缘层521，第二绝缘层521位于相邻电容的第二下电极层421之间，第二绝缘层521覆盖在第二分割沟道52对应的第二支撑柱332的侧壁表面和基底10上。第二绝缘层521的结构以及材质在此不再赘述。相同地，第二绝缘层521的厚度大于第二下电极层421的厚度，有利于保证相邻电容对应的第二下电极层421之间的绝缘性能，且第二绝缘层521的厚度小于第二下电极层421与第二介电层422的厚度之和，还能够便于相邻电容对应的第二上电极层423之间进行电性连接，从而保证相邻电容之间进行并联。
参照19a和图19b，在第一分割沟道51内填充导电材料的同时，还包括：在第二分割沟道52内填充导电材料，以使相邻电容对应的第二上电极层423之间电性连接。本实施例中，导电材料可以与第二上电极层423的材质相同，以使在沿X轴方向上，同一水平面内的第二电容结构42共用同一第二上电极层423，从而使得相邻电容对应的第二上电极层423之间电性连接。相邻电容对应的第二下电极层421可以通过第二支撑柱332电性连接在一起，相邻电容对应的第二上电极层423之间电性连接，使得相邻电容实现并联，有利于提高第二电容组件62的电容容量，进而进一步提高半导体结构的性能。
以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (18)

  1. 一种半导体结构，包括：
    位于基底上的第一电容结构和第一支撑柱，多个所述第一支撑柱相互平行且间隔地设置在所述基底上，所述第一电容结构包括第一下电极层、第一介电层以及第一上电极层，所述第一下电极层覆盖所述第一支撑柱的侧壁表面和所述基底上，所述第一介电层覆盖在所述第一下电极层上，所述第一上电极层覆盖在所述第一介电层上；
    还包括多个相互平行且间隔地设置在所述基底上的第一分割沟道，所述第一分割沟道的延伸方向与所述第一支撑柱垂直，所述第一分割沟道将所述第一电容结构分割成多个电容，相邻所述电容对应的所述第一下电极层之间设置有第一绝缘层，所述第一绝缘层覆盖在所述第一分割沟道对应的所述第一支撑柱的侧壁表面和所述基底，相邻所述电容对应的所述第一上电极层之间电性连接。
  2. 根据权利要求1所述的半导体结构，其中，所述第一绝缘层的材质包括高介电常数材料、氧化硅、氮化硅或者氮氧化硅。
  3. 根据权利要求2所述的半导体结构，其中，所述第一绝缘层的厚度大于所述第一下电极层的厚度，且小于所述第一下电极层与所述第一介电层的厚度之和。
  4. 根据权利要求1所述的半导体结构，其中，所述第一支撑柱的材质包括单晶硅、单晶锗、单晶硅锗或者氧化铟镓锌。
  5. 根据权利要求3所述的半导体结构，其中，所述第一电容结构和所述第一支撑柱构成第一电容组件，在垂直于基底的方向上，所述基底上设置有多个层叠设置的所述第一电容组件，相邻的所述第一电容组件对应的所述第一上电极层之间电性连接。
  6. 根据权利要求5所述的半导体结构，其中，还包括覆盖所述基底上的第一支撑层和第二支撑层，所述第一支撑层和第二支撑层环绕所述第一支撑柱的侧壁表面，所述第一电容组件位于所述第一支撑层和所述第二支撑层之间，所述第一介电层还覆盖在所述第一支撑层和所述第二支撑层的侧壁。
  7. 根据权利要求5所述的半导体结构，其中，还包括位于基底上的隔离部和多个第二电容组件，在垂直于基底的方向上，所述基底上设置有多个层叠设置的所述第二电容组件，所述隔离部位于所述第一电容组件和所述第二电容组件之间，所述第二电容组件与所述第一电容组件关于所述隔离部对称设置。
  8. 一种半导体结构的制作方法，包括：
    提供基底；
    形成多个第一支撑柱，多个所述第一支撑柱相互平行且间隔地设置在所述基底上；
    形成第一电容结构，所述第一电容结构包括第一下电极层、第一介电层以及第一上电极层，所述第一下电极层覆盖所述第一支撑柱的侧壁表面和所述基底，所述第一介电层覆盖在所述第一下电极层上，所述第一上电极层覆盖在所述第一介电层上；
    形成多个第一分割沟道，多个所述第一分割沟道相互平行且间隔地设置于所述基底上，所述第一分割沟道的延伸方向与所述第一支撑柱垂直，所述第一分割沟道将所述第一电容结构分割成多个电容；
    在所述第一分割沟道内形成第一绝缘层，所述第一绝缘层位于相邻所述电容的所述第一下电极层之间，所述第一绝缘层覆盖在所述第一分割沟道对应的所述第一支撑柱的侧壁表面和所述基底上；
    在所述第一分割沟道内填充导电材料，以使相邻所述电容对应的所述第一上电极层之间电性连接。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，所述第一绝缘层的材料包括高介电常 数材料、氧化硅、氮化硅或者氮氧化硅。
  10. 根据权利要求8所述的半导体结构的制作方法，其中，所述第一绝缘层的厚度大于所述第一下电极层的厚度，且小于所述第一下电极层与所述第一介电层的厚度之和。
  11. 根据权利要求9所述的半导体结构的制作方法，其中，所述第一支撑柱的材质包括单晶硅、单晶锗、单晶硅锗或者氧化铟镓锌。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，形成第一支撑柱，包括：
    形成牺牲层，其覆盖所述基底；
    去除部分所述牺牲层，以形成多个第一沟槽，多个所述第一沟槽相互平行且间隔地设置在所述基底上；
    在所述第一沟槽内形成填充层；
    去除部分所述牺牲层以及部分所述填充层，以形成多个第二沟槽，多个所述第二沟槽相互平行且间隔设置在所述基底上，所述第二沟槽的延伸方向垂直于所述第一沟槽；
    去除部分所述牺牲层，以形成多个填充沟道，多个所述填充沟道间隔且平行于所述第一沟槽设置；
    在所述填充沟道内形成所述第一支撑柱。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，所述牺牲层包括交替层叠设置的第一牺牲层和第二牺牲层，去除部分所述牺牲层，以形成填充沟道，包括：
    去除所述牺牲层中的所述第二牺牲层，保留所述第一牺牲层，以形成在所述基底上层叠设置的填充结构，在垂直于基底的方向上，每层所述填充结构包括多个相互平行且间隔设置的所述填充沟道；
    形成第一电容结构，还包括：所述第一电容结构和所述第一支撑柱构成第一电容组件，在垂直于基底的方向上，形成多个层叠设置的所述第一电容组件，相邻的所述第一电容组件对应的所述第一上电极层之间电性连接。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，在所述填充沟道内形成所述第一支撑柱的同时，还包括：
    在所述第二沟槽内形成中间支撑层；
    形成所述第一电容结构，还包括：
    去除部分所述中间支撑层；
    在部分所述第二沟槽内形成第二支撑层。
  15. 根据权利要求14所述的半导体结构的制作方法，其中，在所述填充沟道内形成所述第一支撑柱以后，还包括：
    去除部分填充层，以形成多个第三沟槽，多个所述第三沟槽相互平行且间隔设置在所述基底上，所述第三沟槽的延伸方向垂直于所述第一沟槽；
    去除所述第三沟槽侧壁对应的所述牺牲层，保留所述第一支撑柱，以形成填充侧壁；
    在部分所述填充侧壁内形成第一支撑层，所述第一支撑层环绕所述第一支撑柱的侧壁表面。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，形成第一电容结构，还包括：
    去除部分所述牺牲层和所述填充层，以保留所述第一支撑柱和所述第一支撑层；
    通过选择性生长工艺在所述第一支撑柱和所述基底上形成所述第一下电极层；
    依次形成所述第一介电层和所述第一上电极层。
  17. 根据权利要求15所述的半导体结构的制作方法，其中，形成第一分割沟道，包括：
    去除部分所述第一支撑层。
  18. 根据权利要求14所述的半导体结构的制作方法，其中，还包括：
    形成所述第一支撑柱的同时，还包括：形成隔离部；
    形成多个层叠设置的所述第一电容组件，还包括：在垂直于基底的方向上，形成多个层叠设置 的第二电容组件，所述隔离部位于所述第一电容组件和所述第二电容组件之间，所述第二电容组件与所述第一电容组件关于所述隔离部对称设置。
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