WO2023201849A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2023201849A1
WO2023201849A1 PCT/CN2022/095920 CN2022095920W WO2023201849A1 WO 2023201849 A1 WO2023201849 A1 WO 2023201849A1 CN 2022095920 W CN2022095920 W CN 2022095920W WO 2023201849 A1 WO2023201849 A1 WO 2023201849A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
layer
semiconductor
forming
substrate
Prior art date
Application number
PCT/CN2022/095920
Other languages
English (en)
French (fr)
Inventor
邵光速
肖德元
邱云松
苏星松
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/880,926 priority Critical patent/US20230345712A1/en
Publication of WO2023201849A1 publication Critical patent/WO2023201849A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • Some embodiments of the present disclosure provide semiconductor structures and methods for forming them to adapt to the continuous shrinkage of semiconductor structure sizes, simplify the manufacturing process of semiconductor structures, and improve the performance of semiconductor structures.
  • the present disclosure provides a semiconductor structure including:
  • the stacked structure includes a plurality of first semiconductor layers spaced apart in a direction perpendicular to the top surface of the substrate;
  • the first semiconductor layer includes a plurality of first semiconductor layers arranged along a first A plurality of channel regions arranged at intervals in one direction, and first doped regions and second doped regions distributed on opposite sides of each channel region along a second direction;
  • the first direction and the The second directions are all directions parallel to the top surface of the substrate, and the first direction intersects the second direction;
  • a word line structure includes a plurality of word lines extending along the first direction, and in the second direction, edges of the word lines are flush with edges of the channel region.
  • a spacing width between two adjacent channel regions along the first direction is smaller than a spacing width between two adjacent trenches along a direction perpendicular to the top surface of the substrate. The width of the gap between lane areas.
  • each word line continuously covers a plurality of channel regions arranged along the first direction, and a dielectric layer is further included between the channel region and the word line.
  • the dielectric layer covers the surface of the channel area, the word line covers the surface of the dielectric layer, and in a direction perpendicular to the top surface of the substrate, the edge of the dielectric layer is in contact with the The edges of the word lines are flush.
  • the stacked structure further includes a capacitor structure
  • the capacitor structure includes: a first electrode layer, a dielectric layer and a second electrode layer arranged around the surface of the first semiconductor layer in sequence; the capacitor structure Adjacent to the first doped region and electrically connected to the first doped region, the first semiconductor layer surrounded by the capacitor structure and the corresponding layer of the first doped region
  • the first semiconductor layer is doped with the same ions.
  • the stacked structure further includes a bit line structure adjacent to the second doped region, the bit line structure includes at least one bit line, and an extension of the bit line
  • the direction is perpendicular to the top surface of the substrate. In the direction perpendicular to the top surface of the substrate, one bit line is spaced apart from a plurality of bit lines arranged in a direction perpendicular to the top surface of the substrate.
  • the second doped region is electrically connected.
  • the stacked structure further includes: a first filling layer and a second filling layer, the first filling layer is located between adjacent word lines, and the second filling layer is located between adjacent word lines. between the first doped region and the adjacent second doped region.
  • a plurality of the word lines are spaced apart in a direction perpendicular to the top surface of the substrate; the semiconductor structure further includes:
  • An air gap is located in the first filling layer and at least between two adjacent word lines in a direction perpendicular to the top surface of the substrate.
  • it further includes: at least one support pillar, the support pillar is located on the substrate and on a side of the capacitor structure away from the first doped region, the support pillar is connected to at least The laminated structure.
  • the first semiconductor layer in the stacked structure extends to the inside of the support pillar along the second direction.
  • the support pillars extend in a direction perpendicular to the top surface of the substrate, and the top surface of the support pillars is flush with the top surface of the stacked structure.
  • the present disclosure also provides a method for forming a semiconductor structure, including the following steps:
  • the stacked layer including first semiconductor layers and second semiconductor layers alternately stacked in a direction perpendicular to a top surface of the substrate, the first semiconductor layer It includes a plurality of channel regions spaced apart along the first direction, and first doped regions and second doped regions distributed on opposite sides of each channel region along the second direction, the first The direction and the second direction are both directions parallel to the top surface of the substrate, and the first direction intersects the second direction;
  • a word line structure is directly formed in the first opening, and the word line structure includes a plurality of word lines extending along the first direction, and the word lines continuously cover a plurality of the channel regions arranged at intervals.
  • the thickness of the second semiconductor layer is greater than a spacing width between two adjacent first openings spaced apart along the first direction.
  • the support groove is filled to form a support pillar connected to the first semiconductor layer in the first region.
  • the specific steps of forming a support groove in the second area include:
  • a transistor region is defined in the first region, and capacitor regions and bit line regions distributed on opposite sides of the transistor region along the second direction, the channel region, the first doped region and the The second doped regions are located within the transistor region, the first doped region is adjacent to the capacitor region, and the second doped region is adjacent to the bit line region;
  • a third filling layer filling the second opening and the third opening is formed.
  • a second electrode layer covering the surface of the dielectric layer is formed.
  • the specific steps of forming a first electrode layer covering the surface of the first semiconductor layer in the capacitor region include:
  • a first electrode layer covering the surface of the first semiconductor layer is formed using a selective atomic layer deposition process.
  • the following steps are further included:
  • An in-situ oxidation process is used to oxidize the surface of the channel region, and form a dielectric layer on the surface of the channel region.
  • the specific steps of directly forming a word line structure in the first opening include:
  • an edge of the word line is flush with an edge of the channel region.
  • the following steps are also included:
  • a second filling layer is formed that fills the second opening and the third opening and covers the first doped region and the second doped region.
  • the specific steps of forming the first filling layer include: depositing an insulating material in a plurality of the first openings using an atomic layer deposition process to form the first filling layer covering the surface of the word line. , and an air gap located in the first filling layer, and the air gap is located at least between two adjacent word lines in a direction perpendicular to the top surface of the substrate.
  • the first doping ions are of the same type as the second doping ions.
  • the following steps are further included:
  • a bit line is formed in the bit line trench, and the bit line is electrically connected to the second doped region.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, by forming a word line structure above a substrate, and the word line structure includes a plurality of word lines extending in a direction parallel to the top surface of the substrate, This forms a horizontal word line structure, which can not only be used in semiconductor structures whose dimensions are constantly shrinking, but also help improve the performance of semiconductor structures. Moreover, since the horizontal word line in the present disclosure is directly deposited in the first opening exposing the channel region, so that the edge of the formed word line is flush with the edge of the channel region, no additional steps are required after deposition. The etching process simplifies the formation process of the semiconductor structure and reduces the manufacturing cost of the semiconductor structure.
  • FIG. 1 is a cross-sectional schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional view along the a-a’ position of Figure 1;
  • Figure 3 is a schematic cross-sectional view along the b-b' position of Figure 1;
  • FIG. 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • 5A-5U are schematic cross-sectional views of main processes in the process of forming a semiconductor structure according to specific embodiments of the present disclosure.
  • Figure 1 is a schematic cross-sectional view of the semiconductor structure in the specific embodiment of the present disclosure.
  • Figure 2 is a schematic cross-sectional view along the a-a' position in Figure 1.
  • Figure 3 is a schematic cross-sectional view of the semiconductor structure in the specific embodiment of the present disclosure.
  • Figure 1 is a schematic cross-sectional view along bb', and Figure 1 is a schematic cross-section along c-c' in Figures 2 and 3.
  • the semiconductor structure in this specific embodiment may be, but is not limited to, DRAM.
  • the semiconductor structure provided by this specific embodiment includes:
  • the stacked structure is located on the substrate 10 .
  • the stacked structure includes a plurality of first semiconductor layers spaced in a direction perpendicular to the top surface of the substrate 10 .
  • the first semiconductor layer includes a plurality of first semiconductor layers spaced in a direction perpendicular to the top surface of the substrate 10 .
  • the word line structure includes a plurality of word lines 13 extending along the first direction D1. In the second direction D2, the edge of the word line 13 is flush with the edge of the channel region 11.
  • the substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment will be described by taking the substrate 10 as a silicon substrate as an example.
  • the substrate 10 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the substrate 10 is used to support the stacked structure on its top surface.
  • the plurality of first semiconductor layers in the stacked structure are spaced apart along a direction perpendicular to the top surface of the substrate (for example, the third direction D3 in FIG. 1), and each first semiconductor layer includes a layer along the first direction D1.
  • the word line structure is located on the top surface of the substrate 10 and includes word lines 13 extending along the first direction D1.
  • Each word line 13 continuously covers a plurality of channel regions 11 spaced apart along the first direction D1 in a first semiconductor layer.
  • the channel region 11 is flush with the edge of the word line 13 located on the surface of the channel region 11.
  • This specific embodiment sets horizontal word lines, that is, multiple word lines 13 extending along the first direction D1, so that the multiple word lines 13 are at different horizontal heights, so that the word line structure no longer occupies the top surface of the substrate 10 , to adapt to the needs of semiconductor structures that continue to shrink in size.
  • the word line leads can be at different levels, which helps to reduce the capacitive coupling effect between adjacent word line leads and the resistance inside the semiconductor structure, thereby improving Properties of Semiconductor Structures.
  • the horizontal word line in this specific embodiment is formed through a one-step deposition process, so that the edge of the formed word line 13 is flush with the edge of the channel region 11, no additional etching process is required after the deposition process, thereby simplifying It improves the formation process of the semiconductor structure and reduces the manufacturing cost of the semiconductor structure.
  • the spacing width between two adjacent channel regions 11 along the first direction D1 is smaller than the spacing width between two adjacent channel regions 11 along the direction perpendicular to the top surface of the substrate 10 interval width.
  • the spacing width between two adjacent channel regions 11 along the first direction D1 is smaller than the spacing between two adjacent channel regions 11 along the direction perpendicular to the top surface of the substrate 10 width, so that when depositing conductive material to form the word line 13, the conductive material in the horizontal direction is first connected into a line along the first direction D1, so that the deposition parameters and other conditions can be controlled to directly form a line extending only along the first direction D1.
  • the word line 13 helps to further simplify the formation process of the word line 13.
  • each word line 13 continuously covers multiple channel regions 11 arranged along the first direction D1, and further includes between the channel region 11 and the word line 13:
  • the dielectric layer 12 covers the surface of the channel region 11
  • the word line 13 covers the surface of the dielectric layer 12
  • the edge of the dielectric layer 12 is in contact with the word line 13 The edges are flush.
  • the dielectric layer 12 is located between the channel region 11 and the word line 13 .
  • the material of the first semiconductor layer may be silicon
  • the material of the dielectric layer 12 may be silicon dioxide
  • the dielectric layer 12 may be formed by in-situ oxidation of the surface of the first semiconductor layer, thereby further simplifying the manufacturing of the semiconductor structure. Craftsmanship.
  • the stacked structure also includes a capacitor structure.
  • the capacitor structure includes: a first electrode layer 19, a dielectric layer 20 and a second electrode layer 21 disposed in sequence around the surface of the first semiconductor layer; the capacitor structure and the first doping layer
  • the region 17 is adjacent and electrically connected to the first doped region 17 , and the first semiconductor layer surrounded by the capacitor structure and the first semiconductor layer corresponding to the first doped region 17 are doped with the same ions.
  • the top surface of the substrate 10 further includes a capacitor structure adjacent to the first doped region 17 along the second direction D2.
  • the capacitor structure includes a plurality of capacitors spaced apart in a direction perpendicular to the top surface of the substrate 10 .
  • Each capacitor includes: a first electrode layer 19 disposed sequentially around the surface of the first semiconductor layer, covering the surface of the first electrode layer 19 The dielectric layer 20 and the second electrode layer 21 covering the surface of the dielectric layer 20 .
  • the first semiconductor layer is located between two adjacent capacitors, and the first semiconductor layer located between the adjacent capacitors and the first doped region 17 have the same doping ions, so that the first semiconductor layer surrounded by the capacitor structure
  • the semiconductor layer is conductive, and the contact resistance between the first semiconductor layer surrounded by the capacitor structure and the first doped region 17 is small, thereby further improving the electrical performance of the semiconductor structure.
  • the materials of the first electrode layer 19 and the second electrode layer 21 may be the same, for example, both are metal materials such as tungsten or both are TiN.
  • the material of the dielectric layer 20 may be a material with a higher dielectric constant.
  • the stacked structure further includes a bit line structure adjacent to the second doped region 18 , the bit line structure includes at least one bit line 16 , and the extending direction of the bit line 16 is perpendicular to the substrate 10 On the top surface, in a direction perpendicular to the top surface of the substrate 10 , a bit line 16 is electrically connected to a plurality of second doped regions 18 spaced apart in a direction perpendicular to the top surface of the substrate 10 .
  • the top surface of the substrate 10 further includes a bit line structure adjacent to the second doped region 18 along the second direction D2.
  • the bit line structure includes at least one bit line 16 extending in a direction perpendicular to the top surface of the substrate 10 .
  • a bit line is in direct contact and electrical connection with a plurality of second doped regions 18 spaced apart in a direction perpendicular to the top surface of the substrate 10 .
  • the stacked structure further includes: a first filling layer 14 and a second filling layer 15.
  • the first filling layer 14 is located between adjacent word lines 13, and the second filling layer 15 is located between adjacent first filling layers. between the doped region 17 and the adjacent second doped region 18 .
  • a plurality of word lines 13 are spaced apart in a direction perpendicular to the top surface of the substrate 10; the semiconductor structure further includes:
  • the air gap 141 is located in the first filling layer 14 and at least between two adjacent word lines 13 in a direction perpendicular to the top surface of the substrate 10 .
  • the first filling layer 14 is filled between adjacent word lines 13 and covers the top surface of the topmost word line 13 in the stacked structure
  • the second filling layer 15 is filled between adjacent first doped words. between regions 17 and between adjacent second doped regions 18, and the second filling layer 15 covers the top surface of the topmost first doped region 17 in the stacked structure and the top second doped region 17 in the stacked structure.
  • the material of the first filling layer 14 and the second filling layer 15 are the same (for example, silicon dioxide), and the top surface of the first filling layer 14 is planar with the top surface of the second filling layer 15 . to further simplify the manufacturing process of semiconductor structures.
  • the electrical isolation effect between adjacent word lines 13 is further enhanced.
  • the semiconductor structure further includes:
  • At least one support pillar 22 is located on the substrate 10 and on a side of the capacitor structure away from the first doped region 17.
  • the support pillar 22 at least connects the stacked structure.
  • the first semiconductor layer in the stacked structure extends to the inside of the support pillar 22 along the second direction D2.
  • the support pillars 22 extend in a direction perpendicular to the top surface of the substrate 10 , and the top surface of the support pillar 10 is flush with the top surface of the stacked structure.
  • At least one support pillar 22 is located on the top surface of the substrate 10 and extends in a direction perpendicular to the top surface of the substrate 10 and is connected to a side of the capacitor structure away from the first doped region 17 for Support the stacked structure, improve the stability of the stacked structure, and prevent the stacked structure from collapsing or toppling during the formation of the capacitor structure or other structures.
  • the top surface of the support column 22 is flush with the top surface of the stacked structure, so that the support column 22 can support the entire stacked structure, which helps to further improve the stability of the top of the stacked structure.
  • the top surface of the support column 22 may also be located above the top surface of the stacked structure.
  • Each first semiconductor layer in this specific embodiment may also include a plurality of channel regions 11 spaced apart along the second direction D2, and a third channel region 11 distributed on opposite sides of each channel region 11 along the second direction D2.
  • One bit line 16 is located between the second doped regions 18 adjacent along the second direction D2 and is electrically connected to the second doped regions 18 adjacent along the second direction D2.
  • the number of capacitor structures in the stacked structure is multiple, and the multiple capacitor structures are respectively adjacent to the multiple first doped regions 17 and are electrically connected to the multiple first doped regions 17 respectively.
  • the number of support pillars 22 may be multiple, and the multiple support pillars are in contact with multiple capacitive structures respectively.
  • a plurality of support columns can be symmetrically distributed around the periphery of the laminated structure to further improve the stability of the laminated structure.
  • the plurality in this specific embodiment may be two or more.
  • FIG. 4 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure.
  • Figures 5A-5U are a process of forming a semiconductor structure in a specific embodiment of the present disclosure. Schematic diagram of the main process cross-section. Schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in Figures 1 to 3.
  • Figures 5A to 5U show the semiconductor structure from four positions: c-c', a-a', b-b' and d-d'.
  • the semiconductor structure in this specific embodiment may be, but is not limited to, DRAM.
  • the method of forming a semiconductor structure includes the following steps:
  • Step S41 forming the substrate 10 and a stacked layer located on the substrate 10.
  • the stacked layer includes first semiconductor layers 51 and second semiconductor layers 52 alternately stacked in a direction perpendicular to the top surface of the substrate 10.
  • the first semiconductor layer 51 includes a plurality of channel regions 11 spaced apart along the first direction D1, and first doped regions 17 and second doped regions 18 distributed on opposite sides of each channel region 11 along the second direction D2.
  • the first direction D1 and the second direction D2 are both directions parallel to the top surface of the substrate 10
  • the first direction D1 and the second direction D2 intersect.
  • Step S42 forming a plurality of first openings 60 respectively exposing a plurality of channel regions 11, as shown in FIG. 5M.
  • Step S43 a word line structure is directly formed in the first opening 60.
  • the word line structure includes a plurality of word lines 13 extending along the first direction D1.
  • the word lines 13 continuously cover a plurality of spaced apart channel regions 11, as shown in FIG. As shown in 5O.
  • a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process may be used to alternately deposit the first semiconductor layer 51 and the second semiconductor layer 52 on the top of the substrate 10 in a direction perpendicular to the top surface of the substrate 10
  • stacked layers with a superlattice stack structure are formed to further improve the storage density of the semiconductor structure.
  • the specific number of alternately stacked first semiconductor layers 51 and second semiconductor layers 52 in the stacked layer can be selected by those skilled in the art according to actual needs. The greater the number of alternately stacked first semiconductor layers 51 and second semiconductor layers 52 . , the greater the storage capacity of the semiconductor structure.
  • the material of the first semiconductor layer 51 may be Si
  • the material of the second semiconductor layer 52 may be SiGe.
  • the support groove 56 is filled to form a support pillar 22 connected to the first semiconductor layer 51 in the first region, as shown in FIG. 5E .
  • the specific steps of forming the support groove in the second area include:
  • All the second semiconductor layer 52 and part of the first semiconductor layer 51 in the second region are removed to form a support groove 56 , and the remaining first semiconductor layer 51 extends from the first region into the support groove 56 , as shown in FIG. 5D .
  • a dry etching process may be used to etch the stacked layer in a direction perpendicular to the top surface of the substrate 10 to form an exposed liner.
  • the first groove 54 at the bottom is shown in Figure 5B.
  • the first trench 54 is filled with materials such as oxide (such as silicon dioxide) to form a first isolation structure 55, as shown in FIG. 5C.
  • the first area may be located in a middle area of the top surface of the substrate 10
  • the second area may be located at an edge area of the top surface of the substrate 10
  • the second area may be distributed around the periphery of the first area.
  • a dry etching process may be used to etch all of the second semiconductor layer 52 and part of the first semiconductor layer 51 in the second region in a direction perpendicular to the top surface of the substrate 10 to form support grooves 56 , leaving the remaining first semiconductor
  • the layer 51 extends from the first region into the support groove 56, as shown in Figure 5D.
  • a material such as nitride (eg, silicon nitride) may be deposited in the support groove 56 to form a support pillar 22 for supporting the stacked layer in the first region, as shown in FIG. 5E .
  • the first semiconductor layer 51 extends to the inside of the support pillar 22, thereby further improving the support ability of the support pillar 22 for the remaining stacked layers, thereby further improving the structural stability of the remaining stacked layers.
  • a transistor region is defined in the first region, as well as capacitor regions and bit line regions distributed on opposite sides of the transistor region along the second direction D2.
  • the channel region, the first doped region 17 and the second doped region 18 are all located in the transistor region.
  • the first doped region 17 is adjacent to the capacitor region
  • the second doped region 18 is adjacent to the bit line region;
  • a third filling layer 53 filling the second opening 57 and the third opening 58 is formed, as shown in FIG. 5H .
  • the first isolation structure 55 is etched to form the second trench 61 in the first isolation structure 55, as shown in FIG. 5F.
  • a wet etching process can be used to remove part of the second semiconductor layer 52 along the second trench 61 to form a second opening 57 exposing the first doped region 17 and exposing the second doped region in the transistor region of the stacked layer.
  • the third opening 58 of area 18 is shown in Figure 5G.
  • a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process can be used to deposit insulating materials such as nitride (such as silicon nitride) in the second opening 57 and the third opening 58 to form the third filling layer 53, as shown in FIG. Shown in 5H.
  • the third filling layer 53 is used to protect the first doped region 17 and the second doped region 18 to avoid damage to the first doped region 17 and the second doped region 18 in subsequent processes.
  • the number of transistor regions can be multiple, and the number of capacitor regions can also be multiple, and the multiple capacitor regions are adjacent to multiple transistor regions respectively, and the multiple transistor regions can be distributed in one bit line region. (for example, two transistor regions are distributed on opposite sides of a bit line region), thereby improving the internal space utilization of the semiconductor structure and further increasing the storage capacity of the semiconductor structure.
  • a second electrode layer 21 covering the surface of the dielectric layer 20 is formed, as shown in FIG. 5L.
  • the specific steps of forming the first electrode layer 19 covering the surface of the first semiconductor layer 51 in the capacitor region include:
  • the first electrode layer 19 covering the surface of the first semiconductor layer 51 is formed using a selective atomic layer deposition process.
  • the following steps are further included:
  • the first doping ions are implanted into the exposed first semiconductor layer 51 in the capacitor region, as shown in FIG. 5J.
  • a wet etching process can be used to remove the second semiconductor layer 52 located in the capacitor region and the first isolation structure 55 located in the capacitor region, thereby exposing the first semiconductor layer in the capacitor region. 51, forming a structure as shown in Figure 5I.
  • the first doping ions can be injected into the exposed first semiconductor layer 51 in the capacitor region using a vapor phase diffusion method, as shown in FIG. 5J , thereby enhancing the conductivity of the first semiconductor layer 51 in the capacitor region.
  • a selective atomic deposition process can be used to deposit conductive materials such as tungsten or TiN on the surface of the first semiconductor layer 51 doped with the first doping ions to form the first electrode layer 19, as shown in FIG. 5K.
  • the selective atomic layer deposition process can directly form the first electrode layer 19 on the top and bottom surfaces of the first semiconductor layer 51 without causing conductive material to be deposited on the sidewalls of the support pillars 22 and the sidewalls of the third filling layer 53. This helps further simplify the manufacturing process of semiconductor structures.
  • a dielectric layer 20 with a higher dielectric constant is deposited on the surface of the first electrode layer 19, and a second electrode layer 21 made of conductive material such as tungsten or TiN is deposited on the surface of the dielectric layer 20 to form a capacitor structure.
  • the capacitor structure includes A plurality of capacitors, each capacitor includes a first electrode layer 19, a dielectric layer 20 and a second electrode layer 21, as shown in FIG. 5L.
  • the thickness of the second semiconductor layer 52 is greater than the spacing width between two adjacent first openings 60 spaced apart along the first direction D1.
  • the following steps are also included:
  • the surface of the channel region 11 is oxidized using an in-situ oxidation process, and a dielectric layer 12 is formed on the surface of the channel region 11, as shown in FIG. 5N.
  • specific steps of directly forming the word line structure in the first opening 60 include:
  • An atomic layer deposition process is used to deposit conductive material in the plurality of first openings 60 to directly form a plurality of word lines 13 spaced apart in a direction perpendicular to the top surface of the substrate 10 .
  • Each word line 13 continuously covers the first openings 60 along the first opening 60 .
  • a plurality of channel regions 11 are arranged at intervals in one direction D1.
  • the edge of the word line 13 is flush with the edge of the channel region 11.
  • a wet etching process can be used to remove the second semiconductor layer 52 and part of the first isolation structure 55 covering the surface of the channel region 11 to form a first opening exposing the channel region 11 60, as shown in Figure 5M.
  • a thermal oxidation method is used to oxidize the surface of the channel region 11 to form a dielectric layer 12, as shown in FIG. 5N. Since the thickness of the second semiconductor layer 52 is greater than the spacing width between two adjacent first openings 60 spaced apart along the first direction D1, the conductive material is deposited on the plurality of first openings 60 using a selective atomic layer deposition process.
  • the conductive materials in the plurality of first openings 60 spaced apart along the first direction are first connected to form a line (namely, the word line 13 ) to directly form the conductive material including the space along the direction perpendicular to the top surface of the substrate 10
  • a line namely, the word line 13
  • a plurality of word lines 13 are arranged, and each word line 13 only continuously covers a plurality of channel regions 11 arranged at intervals along the first direction D1, as shown in FIG. 5O.
  • the thickness of the second semiconductor layer 52 refers to the width of the second semiconductor layer 52 in a direction perpendicular to the top surface of the substrate 10 .
  • the word line structure is formed through a one-step deposition process, no additional etching process is required, which not only helps to simplify the manufacturing process of the semiconductor structure, but also makes the edge of the word line 13 and the edge of the channel region 11 along the second direction D2 If the word lines 13 are flush, the morphological characteristics of the word lines 13 are better, and the size uniformity among the plurality of word lines 13 is better, thereby further improving the electrical performance of the semiconductor structure.
  • the following steps are also included:
  • a second filling layer 15 is formed that fills the second opening 57 and the third opening 58 and covers the first doped region 17 and the second doped region 18, as shown in FIG. 5S.
  • specific steps of forming the first filling layer 14 include:
  • An atomic layer deposition process is used to deposit insulating material in the plurality of first openings 60 to form a first filling layer 14 covering the surface of the word line 13 and an air gap 141 located in the first filling layer 14, and the air gap 141 is located at least along the edge. Between two adjacent word lines 13 in a direction perpendicular to the top surface of the substrate 10 .
  • a gas phase diffusion process may be used to inject second doping ions into the first doping region 17 and the second doping region 18 .
  • air gaps 141 can also be formed in the first filling layer 14 to increase the electrical conductivity between adjacent channel regions 11 that are spaced along the first direction D1.
  • sexual isolation effect In one embodiment, the air gap 141 is located between two adjacent word lines 13 in a direction perpendicular to the top surface of the substrate 10 , and between the word lines 13 and the substrate 10 between.
  • the first filling layer 14 and the second filling layer 15 may be made of the same material, for example, both are oxide materials (which may be but are not limited to silicon dioxide).
  • the type of the first doping ions and the type of the second doping ions are the same.
  • the following steps are also included:
  • a bit line 16 is formed in the bit line trench 50, and the bit line 16 is electrically connected to the second doped region 18, as shown in FIG. 5U.
  • a dry etching process may be used to etch away the stacked layers of the bit line region in a direction perpendicular to the top surface of the substrate 10 to form the bit line trench 50 that exposes the substrate 10 .
  • metal materials such as tungsten are deposited in the bit line trench 50 to form the bit line 16 that fills the bit line trench 50 .
  • One bit line 16 is electrically connected to a plurality of second doped regions 18 spaced apart in a direction perpendicular to the top surface of the substrate 10 .
  • the semiconductor structure and its formation method provided by some embodiments of this specific embodiment form a word line structure above the substrate, and the word line structure includes a plurality of word lines extending in a direction parallel to the top surface of the substrate, thereby forming
  • the horizontal word line structure can not only be used in semiconductor structures that are continuously shrinking in size, but also help improve the performance of semiconductor structures.
  • the horizontal word lines in this embodiment are directly deposited in the first opening exposing the channel region, so that the edges of the formed word lines are flush with the edges of the channel region, no additional etching is required after deposition. process, thereby simplifying the formation process of the semiconductor structure and reducing the manufacturing cost of the semiconductor structure.

Landscapes

  • Semiconductor Memories (AREA)

Abstract

本公开提供的半导体结构包括：衬底；叠层结构，位于所述衬底上，所述叠层结构包括沿垂直于所述衬底的顶面的方向间隔排布的多个第一半导体层，所述第一半导体层包括沿第一方向间隔排布的多个沟道区域、以及沿第二方向分布于每一所述沟道区域的相对两侧的第一掺杂区域和第二掺杂区域；所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；字线结构，所述字线结构包括多条沿所述第一方向延伸的字线，在沿所述第二方向上，所述字线的边缘与所述沟道区域的边缘平齐。本公开形成的水平字线结构能够应用于尺寸不断微缩的半导体结构中，还能改善半导体结构的性能，而且简化了制程工艺。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年04月21日递交的中国专利申请号202210419984.1、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着DRAM等存储器结构的不断微缩，给三维存储器的制造工艺、以及制造良率都带来了较大的挑战。例如，随着DRAM等存储器结构的尺寸微缩，竖直字线结构会导致存储器内部的电阻过高，影响存储器的电学性能。
因此，如何改善存储器的结构、以适应尺寸不断微缩的存储器，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用以适应半导体结构尺寸不断微缩的需求，在简化半导体结构的制造工艺的同时，改善半导体结构的性能。
根据一些实施例，本公开提供了一种半导体结构，包括：
衬底；
叠层结构，位于所述衬底上，所述叠层结构包括沿垂直于所述衬底的顶面的方向间隔排布的多个第一半导体层，所述第一半导体层包括沿第一方向间隔排布的多个沟道区域、以及沿第二方向分布于每一所述沟道区域的相对两侧的第一掺杂区域和第二掺杂区域；所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
字线结构，所述字线结构包括多条沿所述第一方向延伸的字线，在沿所述第二方向上，所述字线的边缘与所述沟道区域的边缘平齐。
在一些实施例中，沿所述第一方向上相邻的两个所述沟道区域之间的间隔宽度小于沿垂直于所述衬底的顶面的方向上相邻的两个所述沟道区域之间的间隔宽度。
在一些实施例中，每条所述字线连续覆盖沿所述第一方向排布的多个所述沟道区域，所述沟道区域与所述字线之间还包括：介质层，所述介质层覆盖于所述沟道区域的表面，所述字线覆盖于所述介质层表面，且在沿垂直于所述衬底的顶面的方向上，所述介质层的边缘与所述字线的边缘平齐。
在一些实施例中，所述叠层结构还包括电容结构，所述电容结构包括：依次围绕所述第一半导体层表面设置的第一电极层、电介质层和第二电极层；所述电容结构与所述第一掺杂区域相邻，且与所述第一掺杂区域电连接，对所述电容结构所包围的所述第一半导体层以及所述第一掺杂区域所对应的所述第一半导体层进行相同离子的掺杂。
在一些实施例中，所述叠层结构还包括位线结构，所述位线结构与所述第二掺杂区域相邻，所述位线结构包括至少一条位线，所述位线的延伸方向垂直于所述衬底的顶面，在垂直于所述衬底的顶面的方向上，一条所述位线与多个沿垂直于所述衬底的顶面的方向间隔排布的所述第二掺杂区域电连接。
在一些实施例中，所述叠层结构还包括：第一填充层和第二填充层，所述第一填充层位于相邻的所述字线之间，所述第二填充层位于相邻的所述第一掺杂区域以及相邻的所述第二掺杂区域之间。
在一些实施例中，多条所述字线沿垂直于所述衬底的顶面的方向间隔排布；所述半导体结构还包括：
空气隙，位于所述第一填充层内，且至少位于沿垂直于所述衬底的顶面的方向相邻的两条所述字线之间。
在一些实施例中，还包括：至少一个支撑柱，所述支撑柱位于所述衬底上、且位于所述电容结构背离所述第一掺杂区域的一侧，所述支撑柱至少连接所述叠层结构。
在一些实施例中，所述叠层结构中的所述第一半导体层沿所述第二方向延伸至所述支撑柱内部。
在一些实施例中，所述支撑柱沿垂直于所述衬底的顶面的方向延伸，且所述支撑柱的顶面与所述叠层结构的顶面平齐。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括如下步骤：
形成衬底、以及位于所述衬底上的堆叠层，所述堆叠层包括沿垂直于所述衬底的顶面方向交替堆叠的第一半导体层和 第二半导体层，所述第一半导体层包括沿第一方向间隔排布的多个沟道区域、以及沿第二方向分布于每一所述沟道区域的相对两侧的第一掺杂区域和第二掺杂区域，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
形成分别暴露多个所述沟道区域的多个第一开口；
在所述第一开口中直接形成字线结构，所述字线结构包括多条沿所述第一方向延伸的字线，所述字线连续覆盖间隔排布的多个所述沟道区域。
在一些实施例中，所述第二半导体层的厚度大于沿所述第一方向间隔排布的相邻的两个所述第一开口之间的间隔宽度。
在一些实施例中，在形成多个所述第一开口之前，还包括如下步骤：
于所述堆叠层中定义第一区域和位于所述第一区域外部的第二区域；
去除部分所述堆叠层，于所述第二区域形成支撑槽；
填充所述支撑槽，形成与所述第一区域的所述第一半导体层连接的支撑柱。
在一些实施例中，于所述第二区域形成支撑槽的具体步骤包括：
去除所述第二区域的全部的所述第二半导体层和部分的所述第一半导体层，形成支撑槽，残留的所述第一半导体层自所述第一区域延伸至所述支撑槽内。
在一些实施例中，在形成多个所述第一开口之前，还包括如下步骤：
于所述第一区域中定义晶体管区域、以及沿所述第二方向分布于所述晶体管区域相对两侧的电容区域和位线区域，所述沟道区域、所述第一掺杂区域和所述第二掺杂区域均位于所述晶体管区域内，且所述第一掺杂区域与所述电容区域相邻，所述第二掺杂区域与所述位线区域相邻；
形成暴露所述第一掺杂区域的第二开口、以及暴露所述第二掺杂区域的第三开口；
形成填充满所述第二开口和所述第三开口的第三填充层。
在一些实施例中，在形成多个所述第一开口之前，还包括如下步骤：
去除所述电容区域的所述第二半导体层，暴露位于所述电容区域的所述第一半导体层；
于所述电容区域中形成覆盖所述第一半导体层表面的第一电极层；
形成覆盖于所述第一电极层表面的电介质层；
形成覆盖于所述电介质层表面的第二电极层。
在一些实施例中，于所述电容区域中形成覆盖所述第一半导体层表面的第一电极层的具体步骤包括：
采用选择性原子层沉积工艺形成覆盖所述第一半导体层表面的第一电极层。
在一些实施例中，于所述电容区域中形成覆盖暴露的所述第一半导体层的表面的第一电极层之前，还包括如下步骤：
注入第一掺杂离子至所述电容区域中暴露的所述第一半导体层中。
在一些实施例中，在所述第一开口中直接形成字线结构之前，还包括如下步骤：
采用原位氧化工艺氧化所述沟道区域的表面，于所述沟道区域的表面形成介质层。
在一些实施例中，在所述第一开口中直接形成字线结构的具体步骤包括：
采用原子层沉积工艺沉积导电材料于多个所述第一开口中，直接形成包括沿垂直于所述衬底的顶面的方向间隔排布的多条所述字线，每条所述字线连续覆盖沿所述第一方向间隔排布的多个所述沟道区域。
在一些实施例中，在沿所述第二方向上，所述字线的边缘与所述沟道区域的边缘平齐。
在一些实施例中，在形成所述字线结构后，还包括如下步骤：
形成填充满所述第一开口且覆盖所述字线表面的第一填充层；
去除所述第三填充层，暴露所述第一掺杂区域和所述第二掺杂区域；
注入第二掺杂离子至所述第一掺杂区域和所述第二掺杂区域；
形成填充满所述第二开口和所述第三开口、并覆盖所述第一掺杂区域和所述第二掺杂区域的第二填充层。
在一些实施例中，形成所述第一填充层的具体步骤包括：采用原子层沉积工艺沉积绝缘材料于多个所述第一开口内，形成覆盖所述字线表面的所述第一填充层、以及位于所述第一填充层内的空气隙，且所述空气隙至少位于沿垂直于所述衬底的顶面的方向相邻的两条所述字线之间。
在一些实施例中，所述第一掺杂离子的种类与所述第二掺杂离子的种类相同。
在一些实施例中，形成所述第二填充层之后，还包括如下步骤：
去除所述位线区域的所述堆叠层，形成位线槽；
于所述位线槽中形成位线，所述位线与所述第二掺杂区域接触电连接。
本公开一些实施例提供的半导体结构及其形成方法，通过在衬底上方形成字线结构，且所述字线结构包括多条沿平行于所述衬底的顶面的方向延伸的字线，从而形成水平字线结构，不仅能够应用于尺寸不断微缩的半导体结构中，还有助于改善半导体结构的性能。而且，由于本公开中的水平字线是在暴露沟道区域的第一开口中直接沉积形成，使得形成的所述字线的边缘与所述沟道区域的边缘平齐，沉积之后无需额外的刻蚀工艺，从而简化了半导体结构的形成工艺，降低了半导体结构的制造成本。
附图说明
附图1是本公开具体实施方式中半导体结构的一截面示意图；
附图2是附图1沿a-a’位置的截面示意图；
附图3是附图1沿b-b’位置的截面示意图；
附图4是本公开具体实施方式中半导体结构的形成方法流程图；
附图5A-5U是本公开具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式中半导体结构的一截面示意图，附图2是附图1沿a-a’位置的截面示意图，附图3是附图1沿b-b’位置的截面示意图，附图1是附图2和附图3沿c-c’的截面示意图。本具体实施方式中的半导体结构可以是但不限于DRAM。如图1-图3所示，本具体实施方式提供的半导体结构，包括：
衬底10；
叠层结构，位于衬底10上，叠层结构包括沿垂直于衬底10的顶面的方向间隔排布的多个第一半导体层，第一半导体层包括沿第一方向D1间隔排布的多个沟道区域11、以及沿第二方向D2分布于每一沟道区域11的相对两侧的第一掺杂区域17和第二掺杂区域18；第一方向D1和第二方向D2均为平行于衬底10的顶面的方向，且第一方向D1与第二方向D2相交；
字线结构，字线结构包括多条沿第一方向D1延伸的字线13，在沿第二方向D2上，字线13的边缘与沟道区域11的边缘平齐。
具体来说，衬底10可以是但不限于硅衬底，本具体实施方式以衬底10为硅衬底为例进行说明。在其他示例中，衬底10可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。衬底10用于支撑在其顶面上的叠层结构。叠层结构中的多个第一半导体层沿垂直于衬底的顶面的方向(例如图1中的第三方向D3)间隔排布，每个第一半导体层中均包括沿第一方向D1间隔排布的多个沟道区域11、以及沿第二方向D2分布于每一沟道区域11的相对两侧的第一掺杂区域17和第二掺杂区域18。字线结构位于衬底10的顶面之上，包括条沿第一方向D1延伸的字线13。每条字线13连续覆盖一个第一半导体层中沿第一方向D1间隔排布的多个沟道区域11。在沿第二方向D2上，沟道区域11与位于沟道区域11表面的字线13的边缘平齐。
本具体实施方式通过设置水平字线，即多条沿第一方向D1延伸的字线13，使得多条字线13处于不同的水平高度，从而使得字线结构不再占用衬底10的顶面，以适应尺寸不断微缩的半导体结构的需求。在形成用于引出字线13的字线引线时，可以使得字线引线处于不同的水平高度，有助于减小相邻字线引线之间的电容耦合效应以及半导体结构内部的电阻，从而改善半导体结构的性能。而且，由于本具体实施方式中的水平字线是通过一步沉积工艺形成，从而使得形成的字线13的边缘与沟道区域11的边缘平齐，沉积工艺之后无需额外的刻蚀工艺，从而简化了半导体结构的形成工艺，降低了半导体结构的制造成本。
在一些实施例中，沿第一方向D1上相邻的两个沟道区域11之间的间隔宽度小于沿垂直于衬底10的顶面的方向上相邻的两个沟道区域11之间的间隔宽度。
具体来说，沿第一方向D1上相邻的两个沟道区域11之间的间隔宽度小于沿垂直于衬底10的顶面的方向上相邻的两个沟道区域11之间的间隔宽度，从而使得在沉积导电材料形成字线13时，沿水平方向上的导电材料先沿第一方向D1连成一条线，从而可以通过控制沉积参数等条件，直接形成仅沿第一方向D1延伸的字线13，有助于进一步简化字线13的形成工艺。
在一些实施例中，每条字线13连续覆盖沿第一方向D1排布的多个沟道区域11，沟道区域11与字线13之间还包括：
介质层12，介质层12覆盖于沟道区域11的表面，字线13覆盖于介质层12表面，且在沿垂直于衬底10的顶面的方 向上，介质层12的边缘与字线13的边缘平齐。
具体来说，介质层12位于沟道区域11与字线13之间。在一示例中，第一半导体层的材料可以是硅，介质层12的材料可以是二氧化硅，且介质层12可以是原位氧化第一半导体层的表面形成，从而进一步简化半导体结构的制造工艺。
在一些实施例中，叠层结构还包括电容结构，电容结构包括：依次围绕第一半导体层表面设置的第一电极层19、电介质层20和第二电极层21；电容结构与第一掺杂区域17相邻，且与第一掺杂区域17电连接，对电容结构所包围的第一半导体层以及第一掺杂区域17所对应的第一半导体层进行相同离子的掺杂。
具体来说，衬底10的顶面上还包括沿第二方向D2与第一掺杂区域17相邻的电容结构。电容结构包括沿垂直于衬底10的顶面的方向间隔排布的多个电容器，每个电容器包括：依次围绕第一半导体层表面设置的第一电极层19、覆盖于第一电极层19表面的电介质层20和覆盖于电介质层20表面的第二电极层21。第一半导体层位于相邻的两个电容器之间，且位于相邻的电容器之间的第一半导体层与第一掺杂区域17具有相同的掺杂离子，从而使得被电容结构包围的第一半导体层具有导电性，且被电容结构包围的第一半导体层与第一掺杂区域17之间的接触电阻较小，从而进一步改善半导体结构的电性能。其中，第一电极层19和第二电极层21的材料可以相同，例如均为钨等金属材料或者均为TiN。电介质层20的材料可以为具有较高介电常数的材料。
在一些实施例中，叠层结构还包括位线结构，位线结构与第二掺杂区域18相邻，位线结构包括至少一条位线16，位线16的延伸方向垂直于衬底10的顶面，在垂直于衬底10的顶面的方向上，一条位线16与多个沿垂直于衬底10的顶面的方向间隔排布的第二掺杂区域18电连接。
具体来说，衬底10的顶面上还包括沿第二方向D2与第二掺杂区域18相邻的位线结构。位线结构包括至少一条沿垂直于衬底10的顶面的方向延伸的位线16。在沿垂直于衬底10的顶面的方向上，一条位线与沿垂直于衬底10的顶面的方向间隔排布的多个第二掺杂区域18直接接触电连接。
在一些实施例中，叠层结构还包括：第一填充层14和第二填充层15，第一填充层14位于相邻的字线13之间，第二填充层15位于相邻的第一掺杂区域17以及相邻的第二掺杂区域18之间。
在一些实施例中，多条所述字线13沿垂直于所述衬底10的顶面的方向间隔排布；半导体结构还包括：
空气隙141，位于第一填充层14内，且至少位于沿垂直于所述衬底10的顶面的方向相邻的两条所述字线13之间。
具体来说，第一填充层14填充于相邻的字线13之间且覆盖位于叠层结构中最顶层的字线13的顶面，第二填充层15填充于相邻的第一掺杂区域17之间和相邻的第二掺杂区域18之间，且第二填充层15覆盖叠层结构中最顶层的第一掺杂区域17的顶面和叠层结构中最顶层的第二掺杂区域18的顶面。在一实施例中，第一填充层14的材料与第二填充层15的材料相同(例如均为二氧化硅)，且第一填充层14的顶面与第二填充层15的顶面平齐，以进一步简化半导体结构的制造工艺。另外，通过在第一填充层14内设置空气隙141，有助于进一步增强相邻所述字线13之间的电性隔离效果。
在一些实施例中，半导体结构还包括：
至少一个支撑柱22，支撑柱22位于衬底10上、且位于电容结构背离第一掺杂区域17的一侧，支撑柱22至少连接叠层结构。
在一些实施例中，叠层结构中的第一半导体层沿第二方向D2延伸至支撑柱22内部。
在一些实施例中，支撑柱22沿垂直于衬底10的顶面的方向延伸，且支撑柱10的顶面与叠层结构的顶面平齐。
具体来说，至少一个支撑柱22位于衬底10的顶面上，且沿垂直于衬底10的顶面的方向延伸，并与电容结构背离第一掺杂区域17的一侧连接，用于支撑叠层结构，提高叠层结构的稳定性，避免在形成电容结构或者其他结构的过程中叠层结构出现坍塌或者倾倒。支撑柱22的顶面与叠层结构的顶面平齐，使得支撑柱22能够对整个叠层结构进行支撑，有助于进一步提高叠层结构顶部的稳定性。在另一实施例中，支撑柱22的顶面还可以位于叠层结构的顶面之上。
本具体实施方式中的每个第一半导体层还可以包括多个沿第二方向D2间隔排布的沟道区域11、以及沿第二方向D2分布于每一个沟道区域11相对两侧的第一掺杂区域17和第二掺杂区域18。一条位线16位于沿第二方向D2相邻的第二掺杂区域18之间、且同时与沿第二方向D2相邻的第二掺杂区域18电连接。叠层结构中的电容结构的数量为多个，且多个电容结构分别与多个第一掺杂区域17相邻，且分别与多个第一掺杂区域17电连接。支撑柱22的数量可以为多个，且多个支撑柱分别与多个电容结构接触连接。多个支撑柱可以环绕叠层结构的外周对称分布，以进一步提高叠层结构的稳定性。本具体实施方式中的多个可以是两个以上。
本具体实施方式还提供了一种半导体结构的形成方法，附图4是本公开具体实施方式中半导体结构的形成方法流程图，附图5A-5U是本公开具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。本具体实施方式形成的半导体结构的示意图可以参见图1-图3，图5A-图5U从c-c’、a-a’、b-b’和d-d’四个位置示出了半导体结构在形成过程中的工 艺截面示意图，以清楚的表明半导体结构的形成方法。本具体实施方式中的半导体结构可以是但不限于DRAM。如图1-图4、图5A-图5U所示，半导体结构的形成方法，包括如下步骤：
步骤S41，形成衬底10、以及位于衬底10上的堆叠层，堆叠层包括沿垂直于衬底10的顶面方向交替堆叠的第一半导体层51和第二半导体层52，第一半导体层51包括沿第一方向D1间隔排布的多个沟道区域11、以及沿第二方向D2分布于每一沟道区域11的相对两侧的第一掺杂区域17和第二掺杂区域18，第一方向D1和第二方向D2均为平行于衬底10的顶面的方向，且第一方向D1与第二方向D2相交。
步骤S42，形成分别暴露多个沟道区域11的多个第一开口60，如图5M所示。
步骤S43，在第一开口60中直接形成字线结构，字线结构包括多条沿第一方向D1延伸的字线13，字线13连续覆盖间隔排布的多个沟道区域11，如图5O所示。
具体来说，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沿垂直于衬底10的顶面的方向交替沉积第一半导体层51和第二半导体层52于衬底10的顶面，如图5A所示，形成具有超晶格堆栈结构的堆叠层，以便于进一步提高半导体结构的存储密度。堆叠层中第一半导体层51与第二半导体层52交替堆叠的具体层数，本领域技术人员可以根据实际需要进行选择，第一半导体层51与第二半导体层52交替堆叠的层数越多，半导体结构的存储容量越大。第一半导体层51与第二半导体层52之间应具有较大的刻蚀选择比(例如刻蚀选择比大于3)，以便于后续通过选择性刻蚀去除第二半导体层52。在一示例中，第一半导体层51的材料可以是Si，第二半导体层52的材料可以是SiGe。
在一些实施例中，在形成多个第一开口60之前，还包括如下步骤：
于堆叠层中定义第一区域和位于第一区域外部的第二区域；
去除部分堆叠层，于第二区域形成支撑槽56，如图5D所示；
填充支撑槽56，形成与第一区域的第一半导体层51连接的支撑柱22，如图5E所示。
在一些实施例中，于第二区域形成支撑槽的具体步骤包括：
去除第二区域的全部的第二半导体层52和部分的第一半导体层51，形成支撑槽56，残留的第一半导体层51自第一区域延伸至支撑槽56内，如图5D所示。
具体来说，在形成第一半导体层51与第二半导体层52交替堆叠的堆叠层之后，可以采用干法刻蚀工艺沿垂直于衬底10的顶面的方向刻蚀堆叠层，形成暴露衬底的第一沟槽54，如图5B所示。采用氧化物(例如二氧化硅)等材料填充第一沟槽54，形成第一隔离结构55，如图5C所示。在一示例中，第一区域可以位于衬底10的顶面的中部区域，第二区域可以是位于衬底10的顶面的边缘区域，且第二区域可以环绕第一区域的外周分布。可以采用干法刻蚀工艺沿垂直于衬底10的顶面的方向刻蚀第二区域的全部的第二半导体层52和部分的第一半导体层51，形成支撑槽56，残留的第一半导体层51自第一区域延伸至支撑槽56内，如图5D所示。之后，可以沉积氮化物(例如氮化硅)等材料于支撑槽56内，形成用于支撑第一区域的堆叠层的支撑柱22，如图5E所示。第一半导体层51延伸至支撑柱22的内部，从而能够进一步提高支撑柱22对残留的堆叠层支撑能力，从而进一步提高残留的堆叠层的结构稳定性。
在一些实施例中，在形成多个第一开口60之前，还包括如下步骤：
于第一区域中定义晶体管区域、以及沿第二方向D2分布于晶体管区域相对两侧的电容区域和位线区域，沟道区域、第一掺杂区域17和第二掺杂区域18均位于晶体管区域内，且第一掺杂区域17与电容区域相邻，第二掺杂区域18与位线区域相邻；
形成暴露第一掺杂区域17的第二开口57、以及暴露第二掺杂区域18的第三开口58，如图5G所示；
形成填充满第二开口57和第三开口58的第三填充层53，如图5H所示。
具体来说，刻蚀第一隔离结构55，于第一隔离结构55中形成第二沟槽61，如图5F所示。之后，可以采用湿法刻蚀工艺沿第二沟槽61去除部分的第二半导体层52，于堆叠层的晶体管区域中形成暴露第一掺杂区域17的第二开口57和暴露第二掺杂区域18的第三开口58，如图5G所示。之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氮化物(例如氮化硅)等绝缘材料于第二开口57和第三开口58，形成第三填充层53，如图5H所示。第三填充层53用于保护第一掺杂区域17和第二掺杂区域18，避免后续工艺对第一掺杂区域17和第二掺杂区域18造成损伤。
在一实施例中，晶体管区域的数量可以为多个，电容区域的数量也可以为多个，且多个电容区域分别与多个晶体管区域相邻，多个晶体管区域可以分布于一个位线区域的外周(例如两个晶体管区域分布于一个位线区域的相对两侧)，从而在提高半导体结构内部空间利用率的同时，进一步增大半导体结构的存储容量。
在一些实施例中，在形成多个第一开口之前，还包括如下步骤：
去除电容区域的第二半导体层52，暴露位于电容区域的第一半导体层51，如图5I所示；
于电容区域中形成覆盖第一半导体层51表面的第一电极层19，如图5K所示；
形成覆盖于第一电极层19表面的电介质层20；
形成覆盖于电介质层20表面的第二电极层21，如图5L所示。
在一些实施例中，于电容区域中形成覆盖第一半导体层51表面的第一电极层19的具体步骤包括：
采用选择性原子层沉积工艺形成覆盖第一半导体层51表面的第一电极层19。
在一些实施例中，于电容区域中形成覆盖暴露的第一半导体层51的表面的第一电极层19之前，还包括如下步骤：
注入第一掺杂离子至电容区域中暴露的第一半导体层51中，如图5J所示。
具体来说，在形成第三填充层53之后，可以采用湿法刻蚀工艺去除位于电容区域的第二半导体层52和位于电容区域的第一隔离结构55，从而暴露电容区域的第一半导体层51，形成如图5I所示的结构。之后，可以采用气相扩散方式注入第一掺杂离子至电容区域暴露的第一半导体层51中，如图5J所示，从而增强电容区域的第一半导体层51的导电性。之后，可以采用选择性原子沉积工艺沉积钨或者TiN等导电材料于掺杂有第一掺杂离子的第一半导体层51的表面，形成第一电极层19，如图5K所示。选择性原子层沉积工艺可以直接于第一半导体层51的顶面和底面形成第一电极层19，而不会使得导电材料沉积在支撑柱22的侧壁和第三填充层53的侧壁，从而有助于进一步简化半导体结构的制造工艺。接着，沉积具有较高介电常数的电介质层20于第一电极层19表面，并沉积材料为钨或者TiN等导电材料的第二电极层21于电介质层20表面，形成电容结构，电容结构包括多个电容器，每个的电容器包括第一电极层19、电介质层20和第二电极层21，如图5L所示。
在一些实施例中，第二半导体层52的厚度大于沿第一方向D1间隔排布的相邻的两个第一开口60之间的间隔宽度。
在一些实施例中，在第一开口60中直接形成字线结构之前，还包括如下步骤：
采用原位氧化工艺氧化沟道区域11的表面，于沟道区域11的表面形成介质层12，如图5N所示。
在一些实施例中，在第一开口60中直接形成字线结构的具体步骤包括：
采用原子层沉积工艺沉积导电材料于多个第一开口60中，直接形成包括沿垂直于衬底10的顶面的方向间隔排布的多条字线13，每条字线13连续覆盖沿第一方向D1间隔排布的多个沟道区域11。
在一些实施例中，在沿第二方向D2上，字线13的边缘与沟道区域11的边缘平齐。
具体来说，在形成电容结构之后，可以采用湿法刻蚀工艺去除覆盖于沟道区域11表面的第二半导体层52和部分的第一隔离结构55，形成暴露沟道区域11的第一开口60，如图5M所示。之后，采用热氧化法氧化沟道区域11的表面，形成介质层12，如图5N所示。由于第二半导体层52的厚度大于沿第一方向D1间隔排布的相邻的两个第一开口60之间的间隔宽度，因而在采用选择性原子层沉积工艺沉积导电材料于多个第一开口60中，沿第一方向间隔排布的多个第一开口60内的导电材料先连接成一条线(即字线13)，以直接形成包括沿垂直于衬底10的顶面的方向间隔排布的多条字线13，且每条字线13仅连续覆盖沿第一方向D1间隔排布的多个沟道区域11，如图5O所示。其中，第二半导体层52的厚度是指第二半导体层52沿垂直于衬底10的顶面方向的宽度。由于字线结构是通过一步沉积工艺形成，无需额外的刻蚀工艺，不仅有助于简化半导体结构的制造工艺，而且在沿第二方向D2上，字线13的边缘与沟道区域11的边缘平齐，字线13的形貌特征较佳，多条字线13之间的尺寸均匀性较好，从而能够进一步改善半导体结构的电性能。
在一些实施例中，在形成字线结构后，还包括如下步骤：
形成填充满第一开口60且覆盖字线13表面的第一填充层14，如图5P所示；
去除第三填充层53，暴露第一掺杂区域17和第二掺杂区域18，如图5Q所示；
注入第二掺杂离子至第一掺杂区域17和第二掺杂区域18，如图5R所示；
形成填充满第二开口57和第三开口58、并覆盖第一掺杂区域17和第二掺杂区域18的第二填充层15，如图5S所示。
在一些实施例中，形成第一填充层14的具体步骤包括：
采用原子层沉积工艺沉积绝缘材料于多个第一开口60内，形成覆盖字线13表面的第一填充层14、以及位于第一填充层14内的空气隙141，且空气隙141至少位于沿垂直于所述衬底10的顶面的方向相邻的两条所述字线13之间。
具体来说，可以采用气相扩散工艺注入第二掺杂离子至第一掺杂区域17和第二掺杂区域18。在采用原子层沉积工艺形成第一填充层14时，还能够于第一填充层14中形成空气隙141，以增加沿第一方向D1间隔排布且相邻的沟道区域11之间的电性隔离效果。在一实施例中，所述空气隙141位于沿垂直于所述衬底10的顶面的方向相邻的两条所述字线13之间、以及所述字线13与所述衬底10之间。第一填充层14与第二填充层15的材料可以相同，例如均为氧化物材料(可以是但不限于二氧化硅)。
为了降低电容区域的第一半导体层51与第一掺杂区域17之间的接触电阻，在一些实施例中，第一掺杂离子的种类与 第二掺杂离子的种类相同。
在一些实施例中，形成第二填充层15之后，还包括如下步骤：
去除位线区域的堆叠层，形成位线槽50，如图5T所示；
于位线槽50中形成位线16，位线16与第二掺杂区域18接触电连接，如图5U所示。
具体来说，可以采用干法刻蚀工艺沿垂直于衬底10的顶面的方向刻蚀掉位线区域的堆叠层，形成暴露衬底10的位线槽50。之后，沉积钨等金属材料于位线槽50内，形成填充满位线槽50的位线16。一条位线16与沿垂直有衬底10的顶面的方向间隔排布的多个第二掺杂区域18电连接。
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过在衬底上方形成字线结构，且字线结构包括多条沿平行于衬底的顶面的方向延伸的字线，从而形成水平字线结构，不仅能够应用于尺寸不断微缩的半导体结构中，还有助于改善半导体结构的性能。而且，由于本具体实施方式中的水平字线是在暴露沟道区域的第一开口中直接沉积形成，使得形成的字线的边缘与沟道区域的边缘平齐，沉积之后无需额外的刻蚀工艺，从而简化了半导体结构的形成工艺，降低了半导体结构的制造成本。
以上仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种半导体结构，包括：
    衬底；
    叠层结构，位于所述衬底上，所述叠层结构包括沿垂直于所述衬底的顶面的方向间隔排布的多个第一半导体层，所述第一半导体层包括沿第一方向间隔排布的多个沟道区域、以及沿第二方向分布于每一所述沟道区域的相对两侧的第一掺杂区域和第二掺杂区域；所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
    字线结构，所述字线结构包括多条沿所述第一方向延伸的字线，在沿所述第二方向上，所述字线的边缘与所述沟道区域的边缘平齐。
  2. 根据权利要求1所述的半导体结构，其中，沿所述第一方向上相邻的两个所述沟道区域之间的间隔宽度小于沿垂直于所述衬底的顶面的方向上相邻的两个所述沟道区域之间的间隔宽度。
  3. 根据权利要求1所述的半导体结构，其中，每条所述字线连续覆盖沿所述第一方向排布的多个所述沟道区域，所述沟道区域与所述字线之间还包括：
    介质层，所述介质层覆盖于所述沟道区域的表面，所述字线覆盖于所述介质层表面，且在沿垂直于所述衬底的顶面的方向上，所述介质层的边缘与所述字线的边缘平齐。
  4. 根据权利要求1所述的半导体结构，其中，所述叠层结构还包括电容结构，所述电容结构包括：依次围绕所述第一半导体层表面设置的第一电极层、电介质层和第二电极层；所述电容结构与所述第一掺杂区域相邻，且与所述第一掺杂区域电连接，对所述电容结构所包围的所述第一半导体层以及所述第一掺杂区域所对应的所述第一半导体层进行相同离子的掺杂。
  5. 根据权利要求4所述的半导体结构，其中，所述叠层结构还包括位线结构，所述位线结构与所述第二掺杂区域相邻，所述位线结构包括至少一条位线，所述位线的延伸方向垂直于所述衬底的顶面，在垂直于所述衬底的顶面的方向上，一条所述位线与多个沿垂直于所述衬底的顶面的方向间隔排布的所述第二掺杂区域电连接。
  6. 根据权利要求1所述的半导体结构，其中，所述叠层结构还包括：第一填充层和第二填充层，所述第一填充层位于相邻的所述字线之间，所述第二填充层位于相邻的所述第一掺杂区域以及相邻的所述第二掺杂区域之间。
  7. 根据权利要求6所述的半导体结构，其中，多条所述字线沿垂直于所述衬底的顶面的方向间隔排布；所述半导体结构还包括：
    空气隙，位于所述第一填充层内，且至少位于沿垂直于所述衬底的顶面的方向相邻的两条所述字线之间。
  8. 根据权利要求5所述的半导体结构，还包括：
    至少一个支撑柱，所述支撑柱位于所述衬底上、且位于所述电容结构背离所述第一掺杂区域的一侧，所述支撑柱至少连接所述叠层结构。
  9. 根据权利要求8所述的半导体结构，其中，所述叠层结构中的所述第一半导体层沿所述第二方向延伸至所述支撑柱内部。
  10. 根据权利要求9所述的半导体结构，其中，所述支撑柱沿垂直于所述衬底的顶面的方向延伸，且所述支撑柱的顶面与所述叠层结构的顶面平齐。
  11. 一种半导体结构的形成方法，包括如下步骤：
    形成衬底、以及位于所述衬底上的堆叠层，所述堆叠层包括沿垂直于所述衬底的顶面方向交替堆叠的第一半导体层和第二半导体层，所述第一半导体层包括沿第一方向间隔排布的多个沟道区域、以及沿第二方向分布于每一所述沟道区域的相对两侧的第一掺杂区域和第二掺杂区域，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
    形成分别暴露多个所述沟道区域的多个第一开口；
    在所述第一开口中直接形成字线结构，所述字线结构包括多条沿所述第一方向延伸的字线，所述字线连续覆盖间隔排布的多个所述沟道区域。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，所述第二半导体层的厚度大于沿所述第一方向间隔排布的相邻的两个所述第一开口之间的间隔宽度。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，在形成多个所述第一开口之前，还包括如下步骤：
    于所述堆叠层中定义第一区域和位于所述第一区域外部的第二区域；
    去除部分所述堆叠层，于所述第二区域形成支撑槽；
    填充所述支撑槽，形成与所述第一区域的所述第一半导体层连接的支撑柱。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，于所述第二区域形成支撑槽的具体步骤包括：
    去除所述第二区域的全部的所述第二半导体层和部分的所述第一半导体层，形成支撑槽，残留的所述第一半导体层自所述第一区域延伸至所述支撑槽内。
  15. 根据权利要求13所述的半导体结构的形成方法，其中，在形成多个所述第一开口之前，还包括如下步骤：
    于所述第一区域中定义晶体管区域、以及沿所述第二方向分布于所述晶体管区域相对两侧的电容区域和位线区域，所述沟道区域、所述第一掺杂区域和所述第二掺杂区域均位于所述晶体管区域内，且所述第一掺杂区域与所述电容区域相邻，所述第二掺杂区域与所述位线区域相邻；
    形成暴露所述第一掺杂区域的第二开口、以及暴露所述第二掺杂区域的第三开口；
    形成填充满所述第二开口和所述第三开口的第三填充层。
  16. 根据权利要求15所述的半导体结构的形成方法，其中，在形成多个所述第一开口之前，还包括如下步骤：
    去除所述电容区域的所述第二半导体层，暴露位于所述电容区域的所述第一半导体层；
    于所述电容区域中形成覆盖所述第一半导体层表面的第一电极层；
    形成覆盖于所述第一电极层表面的电介质层；
    形成覆盖于所述电介质层表面的第二电极层。
  17. 根据权利要求16所述的半导体结构的形成方法，其中，于所述电容区域中形成覆盖所述第一半导体层表面的第一电极层的具体步骤包括：
    采用选择性原子层沉积工艺形成覆盖所述第一半导体层表面的第一电极层。
  18. 根据权利要求16所述的半导体结构的形成方法，其中，于所述电容区域中形成覆盖暴露的所述第一半导体层的表面的第一电极层之前，还包括如下步骤：
    注入第一掺杂离子至所述电容区域中暴露的所述第一半导体层中。
  19. 根据权利要求15所述的半导体结构的形成方法，其中，在所述第一开口中直接形成字线结构之前，还包括如下步骤：
    采用原位氧化工艺氧化所述沟道区域的表面，于所述沟道区域的表面形成介质层。
  20. 根据权利要求12所述的半导体结构的形成方法，其中，在所述第一开口中直接形成字线结构的具体步骤包括：
    采用原子层沉积工艺沉积导电材料于多个所述第一开口中，直接形成包括沿垂直于所述衬底的顶面的方向间隔排布的多条所述字线，每条所述字线连续覆盖沿所述第一方向间隔排布的多个所述沟道区域。
  21. 根据权利要求20所述的半导体结构的形成方法，其中，在沿所述第二方向上，所述字线的边缘与所述沟道区域的边缘平齐。
  22. 根据权利要求18所述的半导体结构的形成方法，其中，在形成所述字线结构后，还包括如下步骤：
    形成填充满所述第一开口且覆盖所述字线表面的第一填充层；
    去除所述第三填充层，暴露所述第一掺杂区域和所述第二掺杂区域；
    注入第二掺杂离子至所述第一掺杂区域和所述第二掺杂区域；
    形成填充满所述第二开口和所述第三开口、并覆盖所述第一掺杂区域和所述第二掺杂区域的第二填充层。
  23. 根据权利要求22所述的半导体结构的形成方法，其中，形成所述第一填充层的具体步骤包括：
    采用原子层沉积工艺沉积绝缘材料于多个所述第一开口内，形成覆盖所述字线表面的所述第一填充层、以及位于所述第一填充层内的空气隙，且所述空气隙至少位于沿垂直于所述衬底的顶面的方向相邻的两条所述字线之间。
  24. 根据权利要求22所述的半导体结构的形成方法，其中，所述第一掺杂离子的种类与所述第二掺杂离子的种类相同。
  25. 根据权利要求22所述的半导体结构的形成方法，其中，形成所述第二填充层之后，还包括如下步骤：
    去除所述位线区域的所述堆叠层，形成位线槽；
    于所述位线槽中形成位线，所述位线与所述第二掺杂区域接触电连接。
PCT/CN2022/095920 2022-04-21 2022-05-30 半导体结构及其形成方法 WO2023201849A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/880,926 US20230345712A1 (en) 2022-04-21 2022-08-04 Semiconductor structure and method for forming semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210419984.1A CN116997176A (zh) 2022-04-21 2022-04-21 半导体结构及其形成方法
CN202210419984.1 2022-04-21

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/880,926 Continuation US20230345712A1 (en) 2022-04-21 2022-08-04 Semiconductor structure and method for forming semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023201849A1 true WO2023201849A1 (zh) 2023-10-26

Family

ID=88418999

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/095920 WO2023201849A1 (zh) 2022-04-21 2022-05-30 半导体结构及其形成方法

Country Status (2)

Country Link
CN (1) CN116997176A (zh)
WO (1) WO2023201849A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108807401A (zh) * 2017-05-05 2018-11-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN110890371A (zh) * 2018-09-07 2020-03-17 英特尔公司 用于存储器单元的结构和方法
US20210013210A1 (en) * 2019-07-12 2021-01-14 SK Hynix Inc. Vertical memory device
CN113421884A (zh) * 2020-06-29 2021-09-21 台湾积体电路制造股份有限公司 存储器器件及其制造方法
CN114023744A (zh) * 2022-01-10 2022-02-08 长鑫存储技术有限公司 一种半导体结构、半导体结构的制备方法和半导体存储器
CN114068568A (zh) * 2020-08-05 2022-02-18 三星电子株式会社 半导体存储器装置
CN114121819A (zh) * 2021-11-19 2022-03-01 长鑫存储技术有限公司 半导体器件的形成方法及半导体器件
CN114373735A (zh) * 2020-10-16 2022-04-19 爱思开海力士有限公司 存储器件

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108807401A (zh) * 2017-05-05 2018-11-13 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN110890371A (zh) * 2018-09-07 2020-03-17 英特尔公司 用于存储器单元的结构和方法
US20210013210A1 (en) * 2019-07-12 2021-01-14 SK Hynix Inc. Vertical memory device
CN113421884A (zh) * 2020-06-29 2021-09-21 台湾积体电路制造股份有限公司 存储器器件及其制造方法
CN114068568A (zh) * 2020-08-05 2022-02-18 三星电子株式会社 半导体存储器装置
CN114373735A (zh) * 2020-10-16 2022-04-19 爱思开海力士有限公司 存储器件
CN114121819A (zh) * 2021-11-19 2022-03-01 长鑫存储技术有限公司 半导体器件的形成方法及半导体器件
CN114023744A (zh) * 2022-01-10 2022-02-08 长鑫存储技术有限公司 一种半导体结构、半导体结构的制备方法和半导体存储器

Also Published As

Publication number Publication date
CN116997176A (zh) 2023-11-03

Similar Documents

Publication Publication Date Title
US8120103B2 (en) Semiconductor device with vertical gate and method for fabricating the same
WO2023216360A1 (zh) 三维存储器及其形成方法
KR20150104337A (ko) 라인형 에어갭을 구비한 반도체장치 및 그 제조 방법
KR100609182B1 (ko) Ｄｒａｍ 셀 장치 및 그 제조 방법
US20210391332A1 (en) Semiconductor structure, method for forming semiconductor structure and memory
US20230171947A1 (en) Semiconductor structure and manufacturing method thereof
TWI802469B (zh) 記憶體裝置及其形成方法
JP3665614B2 (ja) Ｄｒａｍセル装置の製法
CN115188715A (zh) 存储器及其形成方法
US20230005919A1 (en) Semiconductor structure and method for forming semiconductor structure
WO2023245788A1 (zh) 半导体器件及其形成方法
WO2023201849A1 (zh) 半导体结构及其形成方法
US20230345712A1 (en) Semiconductor structure and method for forming semiconductor structure
US20230389265A1 (en) Semiconductor structure and method for forming semiconductor structure
WO2023231196A1 (zh) 半导体结构及其形成方法
US20230422466A1 (en) Semiconductor structure and formation method thereof
CN117529103B (zh) 半导体结构及其形成方法
CN117529105B (zh) 半导体结构及其形成方法
WO2023245799A1 (zh) 半导体结构及其形成方法
US20230013060A1 (en) Semiconductor device and method for forming same
WO2024146132A1 (zh) 半导体结构及其形成方法
WO2023221187A1 (zh) 半导体结构及其形成方法
WO2023168778A1 (zh) 存储器及其形成方法
US20230389261A1 (en) Semiconductor structure and method for forming semiconductor structure
WO2024045328A1 (zh) 半导体结构及其形成方法